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is a need for holding a large amount of data or instruction. The CPU has to depend on memory (main memory of the computer system) . Any instruction taken for execution is stored on the memory. The memories consist of Ic chip, which are plugged into the motherboard or on a small electronic circuit board connected to the motherboard. This memory helps CPU to store and retrieve data and instruction quickly as and when required. This memory is called as electronic memory or semiconductor memory. The electronic memory or simply memory is categorized into two types based on the nature of retention of data is it temporary memory is also called non-permanent memory. When it retains the data and instruction on power frailer. On the other hand a temporary memory loses it contents when the computer is swithed off. Therefore a temporary memory is called volatile memory and permanent memory is called non-volatile memory. MAR - Memory Address Register. MDR – Memory Data Register. MFC - Memory Function Computed. R / W - Read Write. CS-Chip Select. CAS-column address Strobe. RAS - Row Address strobe. Basic Concept:The maximum size of the memory that can be used in any computer is determined by the addressing Scheme. Ex:- A 16-bit Computer that generates 16-bit addresses is capable of addressing up to 2^16= 64K memory location. Similarly, machines whose instructions generate 32-bit address can utilize a memory that contains up to 2^32 = 4G(giga) memory locations. -Whereas machine with 40-bit addresses can access up to 240= 1T(tera) The memory is usually designed to store and retrieve is one memory access is the most common definition of the word length of a computer Consider for example a byte addressable Computer whose instructions generate 32-bit addresses. When a 32-bit address is sent from the processor to the memory unit, the high –order 30 bit determine which word will be accessed of a byte quantity is specified, the low- order 2 bits of the address specify which byte location is involved. In a Read operation, other bytes may be fetched from the memory. But the processor ignores them. From the system stand point; we can wave the memory unit as the block box. Data transfer between the memory and the processor takes place through the use of
And confirms this action by addressing the MFC Signal. MFC etc) Two-processor register. The read or write operation involve consecutive address location in a main memory. The Processor writes data into a memory location by loading the address of this location into MAR.Processor k-bit address bus MAR Memory n-bit address bus MDR Up to 2^k addressable locations Word length= n bits Control/lines (R/W. Then the memory unit may up to 2^k addressable location. It indicates that a write operation is involved by setting the (R/W) line to 0. then a block transfer operation can be performed in . Which has “K” Address lines and “n” data lines. The memory responds by placing the data from the addressed location on to the data lines. The bus also includes the control lines Read/Write (R/W) and memory function completed (MFC) for Co-coordinating data transfers The processor reads data from the memory by loading the address of the required memory location into the MAR register and the setting the (R/W) line to one. And Loading the data into MDR. During a memory Cycle ‘n’ bits of data or transferred between the memory and processor This transfer takes place over the processor bus. Usually called MAR (Memory Address Register) and MDR (Memory data register) • • • • • • • • • • If MAR is “K” bits long and MDR is ‘n’ bit long.
that identifies the first location. • Modern PC implement RAM both SRAM (Static Ram) and DRAM (Dynamic Ram) WORD: A memory unit stores binary information in groups called word. SEMICONDUCTOR RAM MEMORY A Semiconductor memory unit is of the volatile Category. they replaced because of rapid advance in VLSI technology. • We say that. • Rams are used where only temporary memory is needed. since it binary cells need external power to maintain the needed signals. Another important measure is the memory cycle time.The time between the read and the MFC Signal. • They were much more expensive than the magnetic core memories. Buffer memories.• • • • which the only address sent to the memory is the one. This is referred to as the memory access time. Cache memory and microcomputer user memory. The useful measure of the speed of memory units is the time that elapses between the initiation of an operation and the completion of the operation. we can write information (0s and 1s) into the memory and read out or recall information. The cycle time range from 100ns to less than 10ns • Semiconductor memories are first introduced in the late 1960s. • The RAM can’t be used for permanent memory because it looses its data when power off the IC s is turned off. . • In a Ram the registers may be through of f as being separated in space with each register occupying one particulars special location as in a magnetic core memory. • Rams are used for calculator memories. Memory access may be synchronized using a Clock or they may be controlled using special signals that controls transfers on the bus. * Semiconductor memories are available in wide range of speeds. Which is the minimum time delay required between initiations of the two successive memory operations. (RAM) • The Ram is a memory that you can “teach” • After the “teaching and learning” process (called writes) • Ram remembers the information for while and the Rams stored information can be recalled or remembered at any time. • The cost of semiconductor memories has dropped has dramatically • One type of semiconductor memory device used in digital electronics is the random accesses memory. Ex: . Memory read and write operation are controlled as input and output bus transfer respectively.
a group of alphanumeric character or any binary coded information’s. READ AND WRITE: The two control signals applied to the memory unit are called read and write Write: . high cost DRAM:. an instruction. read and write requires continuous power (volatile memory) • Low density.(dynamic random access memory) * Good access speed read or write * Volatile memory plus a need for refresh circuitry * High density.• • • Each word stored in a memory register A word is a memory is a entity of ‘n’ bits that moves in and out of the storage as a unit. lower cost • RAM type used in most modern PCs STATIC MEMORY: Memory that consist of circuit capable of retaining their state as long as power is applied are known as static memories • It is also called as SRAM b b T1 x y T2 word line bit line .a read signals specifies a transfer-out function SRAM: -(static random-access memory) • High access speed. A memory word may represent as operand.a write signals specifies a transfer in function Read: .
These forces the cell into the corresponding static .the transistor are turned off and the latch relations its state Ex: -let us assume that cell is in state ‘1’if the logic value at point ‘x’ is 1 and at point ‘y’is 0.thus ‘b’ and ‘b’ is complements of each other sense/write circuits at the end of the bit the output accordingly • • The SRAM will remember the gray code for us And then we can use the RAM to convert from binary to gray code WRITE OPERATION: The state of the cell is set by placing the appropriate value on bit ‘b’ and its complement ‘b ’ .if the cell is in static 1. These transistors act as switches that can be opened or closed under control of the word line • When the word line is at ground level .Two inverters are cross-connected to form a. the word line is activated to close switches T1 and T2.and then activating the word line.the signal on bit line ‘b’ is high and the signal on bit line ‘b’ is low The opposite is true if the cell is in static 0. latch The latch is connected to the two bit lines by transistors T1 and T2. .the required signals on the bit lines are generated by sense/write circuit. This static is maintained as long as the signal on the word line is at ground level • • • READ ORERATION: • We need some practice in using the 7489 read/write RAM In order to read the static of the SRAM cell.
Since the cell is required to store information for a much longer time. Let expression RAM can be implemented if simpler cell are used. after it is turned off.ASYNCHRONOUS DRAMs :Static RAM are fast but they come at a high cost because their cell require several transistors. A sense amplifier connected to the bit line detects whether the charge stored on the capacitor is above the threshold value. Cell array Refresh SYNCHRONIZE DRAMS: counter Read /write Circuit & latches . This voltage recharges the capacitor to the full sense amplifier detects that the charge on the capacitor is below the threshold value it palls the bit line to ground level. In order to store information’s in this cell. If so it drives the bit line too full voltage that represented logic value 1. Hence they are called DYNAMIC RAMs. This is caused by the capacitors own leakage resistance and by the fact that the transistor continues to conduct a tiny amount of current measured is microamperes. Transistor T is turned on and an appropriate voltage are applied to the bit line. After the transistor is turned off the capacitor begins to discharge. restoring the capacitor charge to its fill value must periodically refresh its contents.Thus reading the contents of the cell automatically refreshes its contents. EXPL:Bit line Word line T C A dynamic all that consist of a capacitor C and a transistor T as show in the above fig. However such do not retain their state indefinitely. which refreshed the contents of the entire row. Hence the information stored in cell can be retrieved correctly only if it is read before the charge on the capacitor drops below some threshold value during a read operation the transistor is a selected cell is turned on. All cells in a selected row are read at the same time. This causes a know amount of charge to be stored is the capacitor. Information is stored is a dynamic memory cell is the form of a charge on a capacitor and this charge can be maintained for only term of milliseconds. which ensures that the capacitor will have no charge representing logic value 0.
-The above figure shows that structure of an SDRAM. It will nearly refresh the contents of the cells. Such memories are known as synchronous DRAMs (SDRAMs). -The cell array is same as in asynchronous. . Clock RAS Data i/p register Mode register And Timing counter Data Data o/p register CAS R/W CS Recent development is memory technology have result is DRAMs whose operation is directly synchronized with a signal. . -The address and data connection are buffered by means of registers. -But if an access is made for refreshing purpose only it will not change the contents of these latches. -A read operation cause the contents of all cell is the selected row to be loaded into these latches. which can be selected by writing control information into a mode register. Column Address countr Row/ column Address Column decoder . -The output of each sense amplifier is connected to a latch. -Data held in the latches that correspond to the select column are transferred In to data out put register. SDRAMs have several different modes of operation. . thus becoming available on the data output pins.Row address latch Row decoder .
and size of the chip. The high order address provided first and latched into the memory chip order address bits. are provided on the same address pins and latched using the CAS signal. SDRAMs have built in refresh circuitry a part of this circuitry is a refresh counter. Static RAMs are generally used only when very fast operation is the primary requirement. which provides for refreshing. New data can be placed on the data lines in each clock cycle. which select a column. MEMORY CONTROLLER: To reduce the number of pins the dynamic memory chips use multiplexed address inputs. In typical SDRAMs a typical period is 64 ms. MEMORY SYSTEM CONSIDERATION: The choice of a RAM chip for a given application depends on several factors foremost among these factors are the cost speed power dissipations.In SDRAMs it is necessary to provide externally generated pulse on the CAS line to select successive columns. In typical SDRAMs each row must be refreshed at least every 64 ms. The address is decided into two parts. All action is triggered by the rising edge of the clock. The necessary signals are provided internally using a column counter and clock signal. Address R/W Memory controller Processor Request CS Clock Clock R /C address RAS CAS Memory . Note that the clock signal is needed is SDRAM chips. This cost and size are adversely affected by the complexity of the circuit that realizes the predominant choice for implementing computer main memories.
It is about 2V and logic values are represented by 0. The controller these to forwards the row and column portions of the address to the memory and generators the RAS and CAS signals. RAMBUS MEMORY: A very wide bus is expensive and requires a lot of space on a motherboard. Eight of the lines are intended for transferring a byte of data. The refreshing process occupies 0. These chips use cell arrays based on the std. to develop a proprietary design known as Ram bus.4% of the total time available for accessing the memory. Instead of using signals that have voltage levels of 0 or Vsupply to represents the logic values.3V.swings above and below Vref. This type of signaling is generally known as differential signaling. REFRESH OVERHEAD: All dynamic memories are hence to be refreshed. such chips are known as Ram bus DRAm’s (RDARM’s). This approach was used by Ram bus Inc. Data lines are connected directly between the processor and the memory.0038’ Which is less than 0. The original specification of ram bus providing for a channel consisting of ‘9’ data lines and number of control and power supply lines. The CS signal is usually action low. The key feature of ram bus technology is a fast signaling method used to transfer information between chips. The controller accepts a complete address and the R/w signal form the processor. The required multiplexing of address bit is usually performed by a memory controller circuit as show is the above figure. Multiple banks of cell arrays are used to access more than one word at a time. The ninth data line can be used for purposes such as purity . An alternative approach is to implement a narrow bus that is much faster.246ms is each ’64-ms’ time interval therefore the refresh overhead is ‘0. DRAM technology.246/64=0. Circuitry needed to interface to the ram bus channel is included on the chip. Which is interposed between the processor and the dynamic memory. Differential signaling and high transformation rate requires special technique for the design of wire connections that serves as a communication links. under the control of a request signal. the signal consist of much smaller voltage swings the around a reference voltage Vref.A typical processor issues all bit of address at the same time. Ram bus provides a complete specification for the design of wire connection called Ram bus channel Ram bus requires specially designed chips. It is also send the R/W and CS signals to the memory.
Another two important thing is that is. -Smaller ROMs can be used to solve combinational logical problems like decoding. -ROMs are classified as nonvolatile memory. -The ROM consists of a number of Ic pall ages and is used for storing programs and tables of constants that are not subject to change once the production of the microcomputer system is completed. RDRAMs is a proprietary design of ram bus Inc. It has ‘18’ data line intended to transfer two bytes of data at a time. -Computer system programs look up tables’ decoders and character generator is but a few uses of the ROM. A memory of this type is called read only memory. because they do not loose their data when power is turned off.checking. READ ONLY MEMORY: A special writing process is needed to place the information into this memory since its normal operation involves only reading of stored data. In ram bus there are three types of packets. The number of bits in a request packet excess the number of data lines. -This is also referred as the mask programmed. -it is used only high-volume production application because of the expensive initial setup costs. acknowledge. Many digital devices including microcomputer must store some information permanently. . for which the manufactures of chips have to pay a royalty. SDRAM technology each has certain advantage and disachatagy. Ram bus technology completed directly with the DDR. The ROM is high-density memory and It cannot be reprogrammed. Which means that several clock cycle are needed to transmit the entire packet RDRAMs chips can be assembled in to larger modules one such modules are RIMM can hold up 16 RDRAMs. also know as direct ‘RDRAM ‘. This is typically stored is a read only memory or ROM. -ROM is programmed by the manufacture to the users specifications. A computer program is typically referred to as software. they are request packet. data packets. -ROM can also be used for solving combinational logic programs. However when a computer programs is stored in a ROM it is called firmware because of the difficulty of making changes. There are three types in ROM these are. -ROM memories are used to store permanent data and programs.
-The collection of rules of matching the decision constitution the replacement algorithm. It issues red and write requests using addresses that refer to location in the memory. -This is a high-speed memory and is placed between the CPU and RAM. Thus the total execution time can be reduced significantly. -The cache memory can store a reasonable number of block at any given time. -We use the blocks term to refer to a set of contiguous address location if some size. 1. -The correspondence between the main memory block and in the cache is specified by a mapping function.first technique is called the write through protocol .PROM 2. Consider the above example when a read request is received from the processor the contents of a block of memory words containing the location specification are transferred into the cache one word at a time.EPROM 3. -The operation of cache memory is very simple. -The term is often used to refer to a cache block is cache line.the cache location and the main memory locations are updated simultaneously. -In the reds operation the main memory is not involved. .1. -In this case a read hit or write but is said to occurred. -Desired contents are read directly from the cache. -The effeteness of the cache mechanism is based on a property of computer program called locality of reference. but this number is small compared to the total number of block in the main memory. the cache control hardware must decide which block should be removed to create space for The new block that contains the referenced word. -If the requested word current exits in the cache the read and write operation is performed on the appropriate cache location. -Here the processor doest need to know explicitly absolute the existence of the cache. -The data a and instruction stored is it are accessed at a higher speed as compared to RAM. -When the cache is full and a memory word that is not in the cache is referenced. -The user can’t access this memory. -If the action segment of a program can be placed is fast cache memory. -For write operation the system can be proceed in two ways as below. -The cache control circuitry determines whether the requested word currently exit in the cache.EEPROM CACHE MEMORY: -The cache memory is used for which makes the main memory appear to the processor to faster than it really is.
2. Transfer of data between the disks and the main memory is performed using the DNA scheme. -Not that the write back on protocol may also result is unnecessary write operation because when a cache block is written back to the memory all word of the block are written back. -When the addressed word is a read operation is not in the cache a read miss occurs. -The binary addresses that the processor issues for either instruction or data are called virtual or logical addresses.second technique is called dirty or modified bit. -It is to update only the cache location and to mark if as updated with as associated flag bit. -If the referenced address is not in the main memory. . its contents must be brought into a suitable location is the memory before they can be used. In the case of the write block protocol the block containing the addressed word is first brought into the cache. -Then if the write through protocol in used the information is written directly into the main memory. If the data are not in the main memory the MMU causes the opening system the bring the data into the memory form the disk. -During a write operation if the addressed word is not in the cache a write miss occurs. -These addresses are translated into physical addresses by a combination of hardware and software components. -If a virtual address refers to a part of the programs or data space that is currently is the physical memory. Tran sate virtual addresses into physical addresses. The above figure shows a typical organization the implement virtual memory. VIRTUAL –MEMORIES: The techniques that automatically move program and data block into the physical main memory when they are required for execution are called virtual memory techniques. A special hardware unit called the memory management unit. and then the desired word is the cache is overwritten with the new information. then the contents of the appropriate location is the main memory are accessed immediately. When the desired data are the main memory. -The block of words that contains the requested word is copied from the main memory into the cache. view if only a single word has been changed which the block was in the cache. After the entire block is loaded into the cache the particular word requested is forward to the processor. these data are fetched as described is our presentation of the cache mechanism.
Semiconductor memories use either a read cycle or a write cycle depending on the type of request. or RAM. The read cycle is normally a shorter time period than the write cycle. In a nondestructive readout memory. as it is often referred to. the data stored in memory is not destroyed by the procedure used to read the data from the memory cells.Processor Virtual address Data cache Physical address Main memory MMU Physical address Disk storage MMU: -memory management unit SEMICONDUCTOR MEMORY Semiconductor random access memory. Semiconductor RAM refers to semiconductor IC memories that can be used in a read mode as well as a write mode. RAM is also called a read/write memory or a scratch-pad memory. is used in all types of computers. independent of each other. Volatile . Semiconductor memories are normally non.destructive readout and volatile memories.
the basic building block is the RAM chip This is true whether the memories are static or dynamic memories and are pcb’s in a memory module or a pcb or pcb’s mounted singularly. an uninterruptible power supply (UPS) and a battery backup system are used in many semiconductor memory applications to maintain constant power and prevent loss of information because of power fluctuations or failures. thus they are more expensive than DRAMS.memories require electrical power to maintain storage.sistently used for read/write devices. and variations of the two. The semiconductor RAM itself is made up of variable numbers of these RAM chips. literally thousands or hundreds of thousands of memory cell circuits can be placed on a single chip. The battery backup and a filter capacitor provide the required power when the microcomputer has been powered down. This is especially important in microcomputers where configuration data is maintained in special devices such as a complementary metal-oxide semiconductor (CMOS). For this reason. The RAM Chip In semiconductor memories. RAM means random addresses can be presented to the memory which means data can be written and read in any desired order from any location. Let’s explore the basic building block of semiconductor memories: the RAM chip. it is used and understood by most people to mean read/ write devices. Each chip contains large numbers of memory cells and the logic to support them. If the power goes away for some reason. Then we discuss the two main types of semiconductor RAM memories: static RAM (SRAM) and dynamic (DRAM). although a ROM can also be random access. With the advent of large and very large scale integration (LSI/VLSI). the data stored in the memory cells is lost. SRAMS are faster but require more logic than DRAMS. Note: The term RAM is not used for readonly memories (ROM). Although RAM only describes one characteristic of read/write devices. Computers that use an UPS system have an established time in which data will be retained for momentary power losses. . Each of the two-state memory cell circuits is capable of storing a single binary digit orbit (0 or 1). Each memory cell is an electronic circuit with at least two stable states. The term random access memory (RAM) is con.
Figure shows the general idea of how one-bit storage units (or cells) of any type are typically arranged so that stored information can be read out at random. Notice the row and column arrangement. Figure 6-26 shows the organization of a 64-bit memory. Notice that the 64 bits are organized into 16 groups called words. On RAM chips. notice the row-and-column arrangement. and each word is 4 bits long. The best it can do is the lower or upper half of the word. or written. it contains 16 words. the total number of memory cells is 64. that is why it is called random access. also called gate arrays. These chips are mounted on logic boards or circuit card assemblies pcb’s) in some sort of memory array. This 4K by 16 chip will not support a 32bit word for 4. we simply read the contents of word 3 using the read operation. This memory is said to be organized as a 16 × 4 memory. On the table afterword 3. There are many variations in the ways a 64-bit memory could be organized: 64 × 1. The 64 squares (mostly blank) in the figure represent the 64 positions that can be filled with data. Most memory logic chips are rated by these values.096 addresses. the number of memory words or addresses and the number of bits per word. The capabilities of individual chips determine the array organization for the memory capabilities desired. 32 × 2. To illustrate the random access nature of RAM. this is the same concept used by magnetic read/write memories. To support a 32-bit word. based on the memory capabilities required or desired by the equipment designer. . this is the write operation. we offer a simple illustration. For instance. the number of words or addresses. you’ll notice the contents of word 3 is (0110).096 addresses of 32 bits each. Each word contains four bits of information. It stores only 16 bits. The same arrangement works for writing data into a RAM. it would take two 4K by 16 chips to provide 4. as eight words of two bits each. and bits per word. That is. a word into the memory. look at the memory shown in figure 6-25. The total number and capabilities (16 by 4 and so forth) of these individual circuits will define the total memory capacities of the respective computer. As a simple explanation. The memory in figure 6-26 looks very much like a truth table on a scratch pad. or 8 × 8. What is also important about RAM memory is that we can read or write into any word on the table and in any order. To look-at the contents of word 3. We say we have stored. In our example. a 4K by 16 chip would provide 4.096 16-bit memory addresses. memory cells are organized based on two factors.
Figure illustrates .Static RAM (SRAM) Static random access memories (SRAMs) are semiconductor integrated circuits that use a flip-flop application for each storage cell.
is bipolar junction transistor (BJT) static RAM cell. The number of IC RAM chips needed for a computer’s RAM memory is determined by the requirements and memory size of the computer. RAM chips come in various configurations and sizes. Figure 6-30 is an illustration of an IC chip. is a diode-coupled Figure —Examples of SRAMs: A. As stated. Figure 6-28. The zero or one state in the cells can be held indefinitely as long as proper power supply levels are maintained. Similarly data is written through the column line only when the row-line is activated. D-type and R-S type flip-flops are commonly used for SRAMs. Information-is written into and read out of the cell through the column lines. figure 6-28.) SRAM cell. or store. so only one cell in each column is selected. MOS yields a higher density but lower access speed. and figure 6-29 is a static RAM MOS cell. A static RAM cell and its associated circuitry in block form Each memory cell can latch. Figure . A read/write control signal controls reading and writing operations.—SRAM MOS cell. or store. A read/write control signal controls reading and writing operations. data in a stable state. Figure 6-28. Many groups of 1K by 4 RAM chips can be grouped together with simple support logic to form larger memory systems.SRAM cell and associated circuitry a static RAM cell and its associated circuitry in block form Each memory cell can latch. and read/write cycles. Static RAM Organization and Operation Our example RAM uses a 1K by 4 configuration. The zero or one state in the cells can be held indefinitely as long as proper power supply levels are maintained. Bipolar RAMs have a higher access speed but take up more space. The characteristics of flip-flops keep the flip-flop in its present state and allow you to read the data out of the cell without changing its state when the row-line is activated. frame A. the RAM chip is mounted in a logic array on a pcb. The characteristics of flip-flops keep the flip-flop in its present state and allow you to read the data out of the cell without changing its state when the row-line is activated. with pin connections used in a static bipolar or MOS RAM. so only one cell in each column is selected. address selection. Let’s use an example IC to discuss the operation of a RAM chip. Similarly data is written through the column line only when the row-line is activated. Diode-coupled bipolar SRAM cell. frames A and B. D-type and R-S type . The flip-flops can be made of either bipolar or MOS transistors. bipolar static RAM cell. data in a stable state. and figure illustrate schematic diagrams of individual bipolar and MOS RAM cells. Bipolar junction transistor (BJT. frame B. B. Information-is written into and read out of the cell through the column lines. which includes the architecture. 1024 words that are 4 bits in length.
Static RAM Organization and Operation Our example RAM uses a 1K by 4 configuration. MOS yields a higher density but lower access speed. 1024 words that are 4 bits in length. Let’s use an example IC to discuss the operation of a RAM chip.flip-flops are commonly used for SRAMs. The number of IC RAM chips needed for a computer’s RAM memory is determined by the requirements and memory size of the computer. Figure 6-30 is an illustration of an IC chip. and figure 6-29 illustrate schematic diagrams of individual bipolar and MOS RAM cells. address selection. is bipolar junction transistor (BJT) static RAM cell. Many groups of 1K by 4 RAM chips can be grouped together with simple support logic to form larger memory systems.—SRAM MOS cell. frame A. frame B. frames A and B. : . B. Figure 6-28. Figure 6-28. RAM chips come in various configurations and sizes. figure 6-28. and figure 6-29 is a static RAM MOS cell.) SRAM cell. with pin connections used in a static bipolar or MOS RAM. bipolar static RAM cell.—Examples of SRAMs: A. The flip-flops can be made of either bipolar or MOS transistors. As stated. is a diode-coupled Figure 6-28. Figure 6-29. which includes the architecture. Bipolar junction transistor (BJT. Diode-coupled bipolar SRAM cell. the RAM chip is mounted in a logic array on a pcb. Bipolar RAMs have a higher access speed but take up more space. and read/write cycles.
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