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# ECEN 665 Edgar Sánchez-Sinencio

Low Noise Amplifier LNA

Part of the material here provided is based on Dr. Chunyu Xin’s dissertation

**Ideal characteristics of LNA in Receivers
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min F Large voltage gain to reduce Ftot Handling large signals without significant distortion must present 50 ohms to the input source

**Real characteristics of LNA in Receivers
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• F and power consumption trade-offs • Gain and input matching trade-offs F

G

P Zin

Analog and Mixed-Signal Center, TAMU

2

**Practical Requirements of LNA in Receivers
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Signal coming from antenna is very small: 100dBm(3.2uV)~-70dBm(0.1mV), amplification is needed for the following stage (mixer) to handle a reasonable signal magnitude. (Gain requirement) The received signal should have certain SNR to be reliable detected. Noise comes from the environment and the circuit itself. Noise floor is determined by thermal noise and system bandwidth (KTB). Noise added by the LNA circuit should be as small as possible. (Noise requirement). Large signal or blocker can occur at the input of LNA. Large signal performance of LNA should be good enough. (Linearity requirement) Reasonable ( or minimum) power consuming (Power constrain)

Analog and Mixed-Signal Center, TAMU 3

A Conceptual LNA Structure LNA consists of: Input/output match network Amplifier transistor (s) Power source Load Important terms: Source reflection coefficient: Γs Load reflection coefficient: Input reflection coefficient: Γin = s11 + s12 s21ΓL 1 − s22ΓL ΓL Amplifier S matrix: s s ⎜ ⎟ [S ] = ⎛ 11 21 ⎞ ⎜s ⎟ ⎝ 12 s22 ⎠ Output reflection coefficient: s s Γ Γout = s22 + 12 21 s 1 − s11Γs Analog and Mixed-Signal Center. TAMU 4 .

Remarks on LNAs: NFrec-front = (1/GLNA) (NF subsequent -1) + NFLNA Narrow band (NB) LNA are typically used in Wireless Commercial Communications. For NB the impedance matching and power gain are usually optimized at one frequency. GSM. TAMU 5 . Bluetooth. Wi-Fi. For wide band LNA the input matching stage and load are optimized for a frequency band.e. i. The output load stage and the input matching usually involve LC networks. thus the input matching and load impedance behave as low-Q ( wide bandwidth) filters Analog and Mixed-Signal Center.

e. Transducer power gain: Power delivered to the load divided by power available from source. Its output is not necessary matched if directly drive the on-chip block such as mixer. This is characterized by voltage gain or transducer power gain by knowing the load impedance level. TAMU 6 .LNA Metrics: Gain Gain is the ratio of output signal and input signal. S12~0 Analog and Mixed-Signal Center. LNA input is interfaced off-chip and usually matched to specific impedance (50ohm or 75ohm). It defines and small signal amplification capability of LNA. For IC implementation. GT = 1 − Γs 2 2 1 − s11Γs s21 2 1 − ΓL 2 2 1 − s22 ΓL For unilateral device i.

Analog and Mixed-Signal Center. Noise figure (F) is the dB form of noise factor. SNRi F= SNRo NF (dB) = 10 log F 2 Rn F = Fmin + Ys − Yopt Gs LNA noise matching: Rn is a fictitious resistance called optimum noise resistance The source impedance 1/Ys of the LNA can be transformed to an optimal value such that the noise figure is minimum. Noise figure shows the degradation of signal’s SNR due to the circuits that the signal passes.LNA Metrics: Two-Port Noise Figure Noise factor (NF) is defined by the ratio of output SNR and input SNR. TAMU 7 .

Notation for the Noise Figure Gs is the source conductance.e. TAMU 8 . Bs= -Bc = Bopt Analog and Mixed-Signal Center. Gu is the equivalent ( fictitious) uncorrelated noise conductance Thus one can write the noise factor as: F= 1+ (Gu/Gs) +(Rn/Gs)[ (Gs+Gc)2 +(Bs+Bc)2 ] Note that Gs and Bs can be changed independently. Rn is a fictitious noise resistance . i.

Analog and Mixed-Signal Center. TAMU 9 .Minimum Noise Figure BS = − Bc = Bopt Gu 2 GS = + GC = Gopt Gn Fmin = 1 + 2 Rn [Gopt + GC ] Detail NF expressions are given in the next pages.

LNA Metrics: Why are gain and low noise critical? Sensitivit y = Noisefloor ( dBm ) + SNR + NFtot -174dBm+10logBW System SNR is determined by BER requirement of a specific modulation scheme. TAMU 10 . LNA’s gain suppress the noise coming from following stages Analog and Mixed-Signal Center. for example: 1e-3 QPSK 16QAM 64QAM 7dB 12dB 17dB 1e-6 11dB 16dB 21dB Noise factor of cascaded system: Ftot = FLNA + FafterLNA − 1 G LNA LNA’s noise factor directly appears in the total noise factor of the system.

N o . Current Gain = Ai iout in N o .total 2 = i 2 + in + Ys vn ns 2 .source ins where in and vn are partially correlated in = ic + iu vn = vc + vu Analog and Mixed-Signal Center. ic = Yc vc .ELEN 665 (ESS) TWO-PORT NOISE COMPONENTS iin ins Ys vn Noiseless Network.source = i 2 ns 2 N i +Y v F = o . TAMU 11 .total = 1 + n 2 s n N o .

Then 2 2 2 2 2 2 2 i u + Yc + Ys vn iu + Yc + Ys vc + vu Ys F =1+ =1+ 2 2 ins ins 2 2 2 2 in vu 2 vc 2 Ys + Yc + Ys + 4kTB 4kTB F = 1 + 4kTB 2 ins 4kTB G + Yc + Ys Rc + Ru Ys G + Yc + Ys Rn F =1+ u =1+ u Gs Gs 2 2 2 where 2 2 iu vc Gu = . TAMU 12 . Rc = 4kTB 4kTB 2 2 vu ins Ru = . Gs = 4kTB 4kTB and 2 vn Rn = 4kTB Analog and Mixed-Signal Center.

s . then 2 Gu + (Gc + Gs ) + (Bc + Bs ) Rc + (Gs2 + BS )Ru F =1+ Gs 2 2 [ ] Optimal source admittance : Now if ∂F ∂F = 0 and =0 ∂Gs ∂Bs Bopt = − Bc = Bs Gopt = Gs = then Fmin = 1 + 2 Rn [Gopt 12 ⎡⎛ G ⎤ 2⎞ u + Gc ] = 1 + 2 Rn ⎢⎜ ⎜ R + Gc ⎟ + Gc ⎥ ⎟ ⎠ ⎥ ⎢⎝ n ⎣ ⎦ Gu + Gc2 Rn Analog and Mixed-Signal Center.s + jBc .s = Gc .Yc . TAMU 13 .

v nd = 2 i 2 nd 4kTγg do B 2 gm 5 g do . γ = 2 3 for saturation and long channels i ng = 4kTγg g B . g g = 2 ω2C gs Correlation coefficient c= [i * ing ind 2 ng ⋅ i nd 2 ] 12 2 vn γg do Rn = = 2 4kTB g m Analog and Mixed-Signal Center. we have to take into account two sources.F = Fmin + Rn (Gs − Gopt )2 + (Bs − Bopt )2 Gs [ ] For the MOSFET noise model. TAMU 14 . = 4kTγg do B .

ωT ≅ gm cgs Bopt = − Bc Yopt = Gopt + jBopt = Gopt − jBc Gopt = Gu δ 2 + Gc2 = αωC gs 1− c Rn 5γ 2ω 5ωT ( ) ( 2 Fmin = 1 + 2 Rn [G opt +Gc ] ≅ 1 + γδ 1 − c ) 15 Analog and Mixed-Signal Center. TAMU .Yc = jωC gs + g m ingc ind = jωC gs + δ gm ωC gs c g do 5γ ⎛ δ ⎞ ⎟ = jBc Yc ≅ jωC gs ⎜1 − α c ⎜ 5γ ⎟ ⎝ ⎠ Gc ~ 0 Rn = Gu = γg do γ 1 = 2 gm α gm 2 δω2C gs 1 − c ( 2 ) 5 g go .

2f2-f1 fall in band. It is measured by 1-dB compression point. TAMU 16 . Large in-band blocker can desensitize the circuit.LNA Metrics: Non-linearity model f1 f 2 f1 f 2 f2-f1 2f1-f2 2f2-f1 f1+f2 2f1 2f2 Output spectrum with two tone input Usually distortion term: 2f1-f2. This is characterized by 3rd order non-linearity. Wanted Signal -102dBm IM3 f=2f1-f2 f 1 f2 In-band blocker -23dBm Analog and Mixed-Signal Center.

LNA Metrics: Linearity measurement 1dB compression: Measure gain compression for large input signal IIP3/IIP2: Measure inter-modulation behavior Relationship between IIP3 and P1dB For one tone test: IIP3-P1dB=10dB For two tone test: IIP3-P1dB=15dB IIP3~ -10dBm~8dBm OIP2 OIP3 Pout (dB) P1dB@output 1dB Pin (dB) P1dB@input Pout (dBm) Fu nd am en ta l IM3 IIP3 IM2 IIP2 Pin(dBm) Analog and Mixed-Signal Center. TAMU 17 .

TAMU 18 .8dB Moderate < 2dB Analog and Mixed-Signal Center.CMOS LNA Topologies Resistive Termination VDD VDD Common Gate Shunt-series Feedback Source Degeneration VDD ZL OUTPUT ZL VBB OUTPUT M2 VDD Rf RL OUTPUT VBB INPUT M1 Rs VBB RL M1 INPUT Lg INPUT C1 Ls INPUT M1 OUTPUT R1 Z in = Rs F ≥ 2+ 4γ 1 α g m1 Rs Z in = 1 g m1 γ α F ≥ 1+ Rf Z in ≈ R 1+ L R1 Z in = jω (Lg + Ls ) + 1 g + m Ls jωC gs C gs NF: > 6dB 4.

LNA Topologies (cont’d) Narrowband LNA: inductive degenerated Broadband LNA: common-gate and series-shunt feedback Bipolar LNAs also have corresponding configurations Focusing on inductive degenerated LNA Input match Noise match Linearity Analog and Mixed-Signal Center. TAMU 19 .

A Popular Narrow Band LNA: Inductive Source Degenerated LNA Analog and Mixed-Signal Center. TAMU 20 .

5GHz Analog and Mixed-Signal Center.Source Degenerated LNA Input impedance VDD Z in = jω (Lg + Ls ) + g 1 + m Ls jωC gs C gs ZL OUTPUT VBB 1 ωo = (Lg + Ls )Cgs g ωT = m C gs INPUT Lg Z o = ωT Ls Cgs Ls Zo: 50Ohm. 75Ohm Wo: 900MHz. 1.9GHz. TAMU 21 . 2.4GHz.

TAMU LG+Ls Zin Cgs g m Ls C gs 22 .SOURCE DEGENERATED LNA ANALYSIS Lg s Ls Writing KCL and KVL I o = g mVgs = I in × 1 g g m = m I in sC gs sC gs (1) (2) Io Zin Vin Lg Cgs Iin Io gmVgs Ls ⎡ 1 ⎤ Vin = ⎢ s (Lg + Ls ) + ⎥ I in + I o sLs sC gs ⎦ ⎣ Solving (1) and (2) V g L 1 Z in = in = s( LG + LS ) + + m s I in sC gs C gs ⎡ 1 ⎤ g m LS Z in ( jω) = j ⎢(LG + LS )ω − ⎥+ ωC gs ⎦ C gs ⎣ Analog and Mixed-Signal Center.

ωo = 1 (LG + LS )Cgs which implies that : 1 − LS LG = 2 ωoC gs Analog and Mixed-Signal Center. Rs is the resistor associated in the input voltage source. TAMU 23 . That is (LG + LS )ωo = and Rs = g m LS C gs 1 ωoC gs 2 .Matching occurs when Z(jωo)=Rs .

NQS Inductance loss: RLg: offset Zin RLs: offset Zin and w0 Gate resistance Rg: offset Zin NQS gate resistance: Rnqs: offset Zin Rg = R poly . TAMU . NQS = 1 5g m 24 Analog and Mixed-Signal Center. NQS jωC gs jω 1 ωT RLs ⎞ ⎟ ⎟ ⎠ ωo = 1 ⎜ (Lg + Ls )⎛ C gs // ω 1 ⎜ T RLs ⎝ ωT = gm C gs Lg RLg Cgs Ls Z in = ωT Ls + RLg + Rg + RLs + Rg .Source Degenerated LNA (cont’d) Input impedance-non-idealities Z in = jω (Lg + Ls ) + 1 1 + + ωT Ls + RLg + Rg + RLs + Rg . shW 12n L 2 ZIN RLs Rg .

K.H.5GHz CMOS Low Noise Amplifier”. TAMU 25 . Shaeffer. “A 1. 5.5V 1. Vol. T. 32. No. Lee. IEEE JSSC. May 1997 Analog and Mixed-Signal Center.Source Degenerated LNA (cont’d) Noise factor RL Rg γ χ ⎛ ωo ⎞ ⎜ ⎟ F = 1+ + + Rs Rs α QL ⎜ ωT ⎟ ⎝ ⎠ QL = Lg RLg Cgs Ls ZIN RLs ωo (Ls + Lg ) Rs = 1 ωo Rs C gs χ = 1 + 2 c QL δα 2 δα 2 (1 + QL2 ) + 5γ 5γ There is a optimal QL to minimize F Is this F the minimum achievable one? D.

TAMU 26 . Analog and Mixed-Signal Center.Source Degenerated LNA (cont’d) Achieve minimum noise figure: trading input match F = Fmin + Rn Ys − Yopt Gs 2 Inductive Source degeneration: The degeneration inductance modifies the input reflection coefficient without affecting the optimal input reflection coefficient for minimum noise figure.

35um-0.7 0.4 0. TAMU 27 .5 0.s.9 1 ρ = θVeff 3 vsat Esat Po = VDD 2 ωo Rs VGS MOS transistor’s IIP3 v. gate drive voltage Esat ~ 1V/um L~0.Source Degenerated LNA (cont’d) Linearity V 2 IIP 3.8 0. MOS Different width of transistor IIP3 (dBm) 20 16 12 8 4 4 Veff (2 + θVeff )(1 + θVeff ) > 8 Veff = 3 θ 3 θ Veff = VGS − Vth θ= 1 Esat L IIP3 independent of W 2 IIP 3. strong .18um Analog and Mixed-Signal Center.6 0. LNA 2 16 PD ⎜ (2 + ρ )⎛1 + 1 ⎞ (V ) = 2 2 ⎜ ρ⎟ ⎟ 3 Po θ ⎝ ⎠ 2 3 V 0 -4 -8 0.

TAMU .Source Degenerated LNA (cont’d) Differential v.s. Single-ended Differential reject common mode noise and interferer double area and current shield the bond wire need balun at input common-mode stability linearity limited by bias current Single-ended compact layout size less power for same NF and linearity susceptive to bond wire and PCB trace drive single-balance mixer output balun drive double-balance mixer 28 Analog and Mixed-Signal Center.

com C2 2C2 Typical differential LNA Z in . TAMU 29 .Differential LNA Common-mode Stability Issue VBB VBB Lg M1 C1 Ls Ls M1 Lg C1 Lg M1 C1 Ls Zin.com = jω (Lg + Ls ) + Common-mode half circuit g C1 + C2 g m Ls − 2 m + jωC1C2 C1 ω C1C2 Analog and Mixed-Signal Center.

Differential LNA Common-mode Stability Issue (cont’d) Z in . When design differential LNA.com = jω (Lg + Ls ) + g C1 + C2 g m Ls − 2 m + jωC1C2 C1 ω C1C2 Real part: Rin . oscillation MAY occur. the real part of the source impedance will always be positive.com happens to be negative and cancel the real part of source impedance. TAMU 30 .com gm = C1 ⎛ 1 ⎞ ⎜ Ls − 2 ⎟ ⎜ ω C2 ⎟ ⎝ ⎠ For passive termination. not only pay attention to differential operation. but also check common-mode stability! Analog and Mixed-Signal Center. IF Rin.

10.” IEEE JSSC. TAMU 31 . “A 2-dB Noise Figure 900MHz Differential CMOS LNA.Variant of Inductive Degenerated LNA LSP LD Vo nMOS-pMOS shunt input Current reuse to save power Larger area due to two degeneration inductor if implemented on chip NF: 2dB. No. et al. Id: 8mA from 2. Power gain: 17. Sacchi. 1444-1452 Analog and Mixed-Signal Center. 2001 pp. Gatta. Vol.7V power supply VBB VIN LSN Single-ended version of currentreuse LNA (bias not shown) F.5dB. Oct. E. 36. IIP3: 6dBm.

TAMU 32 .Variant of Inductive Degenerated LNA (cont’d) LD Vo VBB Interstage Inductor VIN Inter-stage inductor with parasitic capacitance form impedance match network between input stage and cascoded stage boost gain lower noise figure. Input match condition will be affected LSN Inter-stage Inductor gain boost Analog and Mixed-Signal Center.

Design Procedure for Inductive Source Degenerated LNA Analog and Mixed-Signal Center. TAMU 33 .

TAMU 34 .Targeting Structure VDD RL Vo VB M2 Noise factor equations: ⎛ ω0 F = 1 + κ nf ⎜ ⎜ω ⎝ T κ nf = Q= ⎞ ⎟ ⎟ ⎠ γ 1 [1 − 2 c χ d + 4(Q 2 + 1)χ d2 ] α 2Q 1 Lg M1 Rs VIN Cgs Ls 2 Rsω0C gs δ χd = α 5γ Linearity: IIP3 ∝ Vgs − Vth Voltage Gain: ⎛ ωT AV = j ⎜ ⎜ω ⎝ 0 ⎞ RL ⎟ ⎟R ⎠ s Inductive degenerated CMOS LNA Analog and Mixed-Signal Center.

6 dB -8 dBm 20 dB < 10mA from 1.8V Analog and Mixed-Signal Center.Targeted Specifications Frequency Noise Figure IIP3 Voltage gain Power 2.4 GHz ISM Band 1. TAMU 35 .

1e-9 µm ε = 3. TAMU 36 .52 V α = gm/gdo δ/γ ~ 2 γ~3 Noise related c = -j0.18um CMOS Process: Process related tox = 4.85e-12)F/m µ = 3.274e-2 m^2/V.55 Important design guide plots obtained from simulation or measurements Analog and Mixed-Signal Center.9*(8.Step 1: Know your process A 0.s Vth = 0.

4 gm 1.4 0.2 300 360 420 480 0. TAMU 37 .8 1.8 0.2 1.0 0 60 120 180 240 W 1.8 W 0. current density plot 1. gdo.2 g do 1. Vgs-Vth vs.4 0.2 0. α.6 0.Step 2: Obtain design guide plots gm.4 Gate overdrive voltage (V) and α g do 2.0 1.6 0.0 Vgs − Vth gm 0.0 0.6 Analog and Mixed-Signal Center.0 540 600 Current density (µA/µm) gm/W and gdo/W (mS/µm) 1.

Step 2: Obtain design guide plots (cont’d) Insights: gdo increases all the way with current density Iden gm saturates when Iden larger than 120µA/µm Velocity saturation. TAMU 38 .short channel effects Low gm/current efficiency High linearity α deviates from long channel value (1) with large Iden Analog and Mixed-Signal Center. mobility degradation ---.

0 0.Step 2: Obtain design guide plots (cont’d) fT and Cgs vs.8 1.0 0.5 Analog and Mixed-Signal Center. gate overdrive voltage 50 Cut-off frequency (GHz) 45 40 35 30 25 20 15 10 0.4 1.8 0.9 0.2 1.6 0.2 Capacitance density (fF/µm) fT 1.3 C gs W 1.6 0.7 0. TAMU 39 .2 1.4 0.1 1.0 Gate overdrive voltage (V) 1.

2V fT begins to degrade when Vod > 0. TAMU 40 .3V --.Step 2: Obtain design guide plots (cont’d) Insights: fT increases with Vod when Vod is small and saturates after Vod > 0.short channel effects Cgs/W increases slowly after Vod > 0.8V gm saturates Cgs increases Analog and Mixed-Signal Center.

TAMU .Step 2: Obtain design guide plots (cont’d) κnf vs input Q and current density 15 14 13 Noise factor scaling coefficient 12 11 10 9 8 7 6 5 4 3 1 2 3 4 5 Quality factor 6 7 8 88µA/µm 135µA/µm 184µA/µm 300µA/µm Current density 47µA/µm 3-D plot for visual inspection ⎛ ω0 F = 1 + κ nf ⎜ ⎜ω ⎝ T ⎞ ⎟ ⎟ ⎠ Q= 1 2 Rsω0C gs 2-D plots for design reference 41 Analog and Mixed-Signal Center.

F↓ Q↑.F↑ For large Iden ( 300 µA/µm) there is an optimal value of Q --. increasing Q will reduce the size of transistor thus reduce total power ---. TAMU 42 .Step 2: Obtain design guide plots (cont’d) Insights: Iden↑.maybe too large for a practical design Design trade-offs For fixed Iden.noise figure will become larger Analog and Mixed-Signal Center.

5µm 30x2.1 0.3 0.4 0. gate overdrive and transistor size 20x2.Step 2: Obtain design guide plots (cont’d) Linearity plots :IIP3 vs.2 0.5µm 40x2.5 Gate overdrive voltage (V) IIP3 (dBm) Analog and Mixed-Signal Center.5µm 18 16 14 12 10 8 6 4 2 0 -2 0 0. TAMU 43 .

Step 2: Obtain design guide plots (cont’d) Insights: MOS transistor IIP3 only.1V overdrive Analog and Mixed-Signal Center. when embedded into actual circuit: Input Q will degrade IIP3 Non-linear memory effect will degrade IIP3 Output non-linearity will degrade IIP3 IIP3 is a very weak function of device size Generally. TAMU 44 . large overdrive means large IIP3 But the relationship between IIP3 and gate overdrive is not monotonic There is a local maxima around 0.

6 0.0 Gate overdrive voltage (V) 1.9 0.5 fT C gs W = 1.4 V fo = (F − 1) = 7.2 κ nf Small current budget ( < 10mA ) does not allow large gate over drive : 0.8 0.6 fo = 2.0 0.3 C gs W Capacitance density (fF/µm) fT 1.45 0.4 0.5 1.2 1.7 0.2 V ~ 0.3 fF / µm fT ~ 40 GHz Analog and Mixed-Signal Center.0 0.1 1.4 GHz F = 1.Step 3: Estimate fT and calculate κnf 50 Cut-off frequency (GHz) 45 40 35 30 25 20 15 10 0.4 1. TAMU 45 .8 1.2 1.

6 0.2 1.5µm 30x2.5µm 40x2.0 Vgs − Vth gm 0.8 1.2 300 360 420 480 0.5 Gate overdrive voltage (V) Current density (µA/µm) Select Iden = 70 µA/µm If Q = 4.0 20x2.4 0.0 540 600 IIP3 (dBm) 1. Q and Calculate Device Size 1.0 0.4 0.4 Gate overdrive voltage (V) and α g do 2.8 W 0.8 0.6 18 16 14 12 10 8 6 4 2 0 -2 0 0.1 0.5µm 1.3 0.0 0 60 120 180 240 W 1. TAMU 46 .4 0.2 0.2 0.2 gm/W and gdo/W (mS/µm) 1.4 gm g do 1.6 0.Step 4: Determine Iden. IIP3 will have enough margin: Estimated IIP3: IIP3( read from curve ) – 20log(Q)~ -4dBm Specs require: -8 dBm Analog and Mixed-Signal Center.

Q and Calculate Device Size (cont’d) 15 14 13 Noise factor scaling coefficient 12 11 10 9 8 7 6 5 4 3 1 2 3 4 5 Quality factor 6 7 8 88µA/µm 135µA/µm 184µA /µm 300µA /µm Current density 47µA /µm Now we can do calculations: 1 C gs = ~ 166 fF 2QRsωo W= Q=4 and Iden = 70µA/µm meet the noise factor requirement 166 fF = 128µm 1.9mA 47 Analog and Mixed-Signal Center.3 fF / µm I DS = 128µm × 70( µA / µm) = 8. TAMU .Step 4: Determine Iden.

Step 5: Calculate Lg. TAMU .Verified ! ⎛ ωT AV = j ⎜ ⎜ω ⎝ o ⎞ RL ⎟ ⎟R ⎠ s Ls = ωT Rs ≈ 0.2nH 1 Lg = 2 − Ls ≈ 26nH ωo C gs RL = ωo AV Rs ≈ 30Ω ωT 48 Analog and Mixed-Signal Center. LS and Required Load Verify cut-off frequency gm is about 50mA/V for the determined current density and device size fT = gm/(Cgs*2pi) = 48 GHz --.

9mA 50mA/V 166fF 0.Step 6: Simulation Verification Usually simulation-hand calculation iterations are necessary to obtain satisfactory design Parameters W Ids gm Cgs Ls Lg RL Calculation 128um 8.2nH 16nH 40 Ohm Deviate from hand-calculation most Possible reason: Cgd is not considered for hand calculation 49 Analog and Mixed-Signal Center.2nH 26nH 30 Ohm Simulation 127.7mA/V 151fF 0. TAMU .5um 8mA 50.

NF and S11 20 25.0 0.86 S11 and AV (dB) 15.78 2.88 P1dB=-20 dBm Output Voltage (dBV) 0 -20 -40 -60 -80 -100 -40 -35 -30 -25 -20 -15 -10 -5 0 20.30 2.40 2.Step 6: Simulation Verification (cont’d) Simulation plots for IIP3.0 AV Noise Figure (dB) 0. TAMU 50 .82 -5.84 5.0 IIP3=-6.0 -15.0 10.4 dBm 0.0 -20.0 -10.45 2.20 0.50 2.35 2. Av.55 Input Power (dBm) Input Frequency (GHz) Analog and Mixed-Signal Center.0 2.0 0.60 NF S11 0.0 0.80 2.25 2.

TAMU 51 .8V Simulated 0.8V Analog and Mixed-Signal Center.4 dBm -20dbm -17 dB 1.Step 6: Simulation Verification (cont’d) Comparison between targeted specs and simulation results Parameter Noise Figure Current drain Voltage gain IIP3 P1dB S11 Power Supply Target 1.6 dB < 10mA 20 dB -8 dBm ----1.8 dB 8 mA 21 dB -6.

Secondary effects such as gate poly resistance can be considered during simulation and can also be considered by add more margin in the design specifications.Summary for LNA Design Procedure Design mixed with simplified equations and simulation plots normalized to unity device size help to gain insights and consider all the important design specification at the same time. Several iterations is generally required from hand calculation to simulation to arrive at satisfactory or optimal design. TAMU 52 . Analog and Mixed-Signal Center.

TAMU 53 .LNA in BiCMOS Technology Analog and Mixed-Signal Center.

etc. Wider dynamic range operation for a given lithographic generation. highvalue MIM capacitors. Analog and Mixed-Signal Center.Advantages of BiCMOS Process Higher gm/DC current (Low Power) Translinear property Outstanding Vbe matching between adjacent devices Highly accurate low.and high-frequency equivalent circuit models based on physical device behavior Design flexibility due to availability of multiple device types Availability of higher quality passive devices (thick metal inductors. First-pass design success thanks to high-quality equivalent circuit models. Higher speed devices available in BiCMOS for a given lithographic generation. While pure CMOS process has higher level system integration and lower cost which in some cost-sensitive designs will out run BiCMOS process.) is more common in BiCMOS processes. TAMU 54 .

Variations of Bipolar LNAs Cascode LNA Increased Gain Potentially Unstable Lowered Headroom Matched LNA Increased Gain Potentially Very Unstable Lowered Headroom Complexity Analog and Mixed-Signal Center. TAMU Transformer Feedback Lower Gain Improved Linearity Excellent Headroom 55 .

determined by LNA specs 6 Re[Z1 (ω )]⋅ H (ω ) ⋅ A1 (ω ) ⋅ ε (∆ω . by tuning out-of-band termination impedance at 2ω and ∆ω.2ω ) 3 2 2g2 [2k (∆ω ) + k (2ω )] ε (∆ω .Principle of Out-of-band Termination Volterra Analysis gives: IIP3 = 1 In-band property. ε (∆ω . Analog and Mixed-Signal Center.2ω ) can be made small thus increase IIP3.2ω ) = g 3 − 3 Out-of-band parameters. can be modified w/o affecting inband property For BJT g3 is positive. TAMU 56 .

Input Termination Techniques IIP3 improves for a narrow range of ∆ω Slow gain switching Extra external components Stability issues High NF Lower gain Extra external component Extra pin Analog and Mixed-Signal Center. TAMU 57 .

Gazzerro. Jianjun.0dBm Power gain: 15.” 2002 IEEE International Solid-State Circuits Conference. C.4dB/3.7dBm/+23. Zeisel.234-5 Analog and Mixed-Signal Center. Aparin. S. P. C.1dB Noise figure: 1. Digest of Technical Papers.Example: Cellular-Band LNA Design Two gain modes Out-of-band termination improve linearity: IIP3=+11. Narathong.2dB Current: 5. S. Sridhara. R. Z. T. pp. Segoria. Szabo. E. Bo.4mA/0 V. “A highly-integrated tri-band/quadmode SiGe BiCMOS RF-to-baseband receiver for wireless CDMA/WCDMA/AMPS applications with GPS capability. Ciccarelli. S.7dB/-3. TAMU 58 . Persico.

TAMU 59 .Wide Band LNA Analog and Mixed-Signal Center.

Design considerations Resistive Termination VDD VDD Common Gate Shunt-series Feedback ZL VBB OUTPUT RL M2 VDD Rf OUTPUT INPUT M1 Rs VBB RL INPUT M1 INPUT M1 OUTPUT R1 Broadband impedance match: resistive termination. TAMU 60 . feedback Noise figure is usually high Broad gain flatness requires resistive load Analog and Mixed-Signal Center. common gate.

25um CMOS NF: 2. Klumperink. E. Nauta.Broad Band LNA: Noise Cancellation 0.6 Analog and Mixed-Signal Center. Bruccoleri.M.7dB F.A.4dB -3dB BW: 2M-1. “Noise Cancelling in Widband CMOS LNAs.6GHz IIP3: 0dBm Voltage Gain: 13. B. TAMU 61 .” ISSCC 2002 Session 24.

Ideally bandwidth should be infinity In practice bandwidth will be limited by the loading character of the transmission line. Analog and Mixed-Signal Center.Distributed Amplifier as LNA Why distributed? GBW Limits for traditional amplifier: gm/C In distributed circuits the parasitic cap C is absorbed into the distributed structure. TAMU 62 . So breaking the gainbandwidth relationship.

Distributed Amplifier as LNA (cont’d) Transmission line modeling on Silicon Coplanar Strip line Micro strip line Shrinking of feather size make dielectric material thicker. Top metal far away from lossy silicon substrate. Tline loss is reduced Analog and Mixed-Signal Center. TAMU 63 .

Distributed Amplifier as LNA (cont’d) Transmission line modeling on Silicon Characteristic Impedance of Coplanar Stripline 130 120 110 Zo (Ohms) 100 90 80 70 60 4 8 12 16 Line spacing (µ m) 20 24 28 5µ 8µ Characteristic Impedance of Micro Stripline 70 Z o (O h m s) 60 50 40 30 20 4 9 14 19 24 29 Width of signal line (M1) 11µ 14µ Loss: 0.8dB/mm at 30GHz Analog and Mixed-Signal Center. TAMU 64 .

**Distributed Amplifier as LNA (cont’d)
**

Artificial or real T-line?

Artificial line uses lumped inductors and capacitors: have good model from foundry. Real T-line uses metal lines to form energy transmission path: currently no models from foundry, has to be modeled by designers. The quality of lumped on-chip inductors limits the frequency operation: low Q and low self-resonate frequency. For higher and higher frequency, spiral inductor structure can not be modeled use lumped inductance any more.

Artificial line: low frequency operation ( <10GHz) Real transmission line: high frequency (>10GHz)

Analog and Mixed-Signal Center, TAMU

65

**Distributed Amplifier as LNA (cont’d)
**

Distributed LNA

0

xd

ld

ld 2

Output

ld 2

Z

T d

Z dL

Input

lg 2

0

Zs

xg

lg

lg 2

T Zg

Cgs and Cds absorbed into the T-line Under phase sync condition, maximum gain obtained : Optimal number of sections (loss line) :

N=

ln (α d ld ) − ln (α g l g )

2 N 2 g m Z cd Z cg G= 4

α d ld − α g l g

66

Analog and Mixed-Signal Center, TAMU

**Distributed Amplifier as LNA (cont’d)
**

Distributed LNA

15 10

17 15

S21

S21, S11, and S22 (dB)

5 0

Noise Figure (dB)

23 25 27

13 11 9 7 5

S11

-5 -10 -15 -20 -25 -30 1 3 5 7 9 11 13 15 17 19 21

S22

3 2 4 6 8 10 12 14 16 18 20 22 24 26

Frequency (GHz)

Frequency (GHz)

Extremely wide band and gain flatness (1 – 20 GHz) Good matching over wide band (1 – 15 GHz) High noise figure at lower portion of frequency

Analog and Mixed-Signal Center, TAMU 67

1 to 10. ISSCC 2004 Analog and Mixed-Signal Center. Bevilacqua and A. TAMU 68 .Wide-band LNA Using LC Lumped Matching Network In the literatures MOS Implementation [1] Bipolar Implementation [2] [1] A.6GHz Wireless Receivers”. Abidi. Niknejad. “An Ultra-Wideband CMOS LNA for 3. ISSCC 2004. “A 3 to 10GHz LNA using a Wideband LC-ladder Matching Network”. Ismail and A. M. [2] A.

Insight of LC Lumped Matching Network --An Alternative Implementation Method Impedance match based on LC ladder network An alternative method: using the well-known Smith Chart More straight forward and have well defined performance Required VSWR can be drawn on Smith Chart Visualize the matching goal Analog and Mixed-Signal Center. TAMU 69 .

L1 S11 C1 RB VB S11 RB VB Finish L2 Cc L1 C1 S11 VB M1 RB Cc M1 L2 Cc L1 S11 C1 M1 RB VB S11 RB VB Step3 Start Step2 Analog and Mixed-Signal Center. TAMU 70 .Wide-band Match Procedure Using Smith Chart TLine L2 Cc L2 Step1 Cc M1 M1 Step 1: Series inductance makes the conductance at the frequency edge has the same real part Step 2: Parallel inductor and capacitor brings the frequency edge S11 close together (forms a circle) Step 3: Series inductance again brings the circle center to pure resistance point Step4: A quarter-wave transmission line is used to rotate the circle to the center of the smith chart.

Implementation of Lumped Matched LNA VDD Rd Ld Quarter wave transmission line C2 Cc L3 M2 L2 Cc M1 RFOUT RFIN L1 C1 Bondwire RB VB Current drain: 5mA from 1. TAMU 71 .8V power supply Analog and Mixed-Signal Center.

TAMU 72 .Simulation Results of the Lumped Matched LNA Analog and Mixed-Signal Center.

Design Examples Analog and Mixed-Signal Center. TAMU 73 .

TAMU 74 .BT/WiFi Receiver Block Diagram 15dB φ LNA φ Q Mixer Attenuator(-15dB) Synthesizer & VCO LPF 0 18dB I Mixer LPF ADC φ φ 90 RF Filter Gain Control Signal Level Measurement ADC Bandwidth compatible (2.4GHz) Sharing Front-end is possible (save power) Multi-standard system delivers flexibility Pmin <-80dBm Pmax >-20dBm LNA switch gain at -40dBm Analog and Mixed-Signal Center.

Differential LNA using BJT cascode Proposed LNA Differential structure MOS transistor is more linear Inductor degeneration Cascoded BJT: better matching On-chip input matching Noise figure: 1.6dB Power/Voltage gain: 15dB Power consumption: 16mW Vin+ M6 VinRb Rb M1 M2 M8 LNA_bypass LNA bypass switches and attenuator Vbb i_tail LNA_rf_bias M3 M4 VDD Ld Cd Cd Ld Vo+ VoM5 Bond wire Cm M9 M7 LNA_cas_bias Q1 Q2 Rb Rb Ls Ls NMOS attenuator for low gain(-15dB) Analog and Mixed-Signal Center. TAMU 75 .

W.Differential LNA using BJT cascode (cont’d) LNA Layout Symmetrical layout Deep trench lattice under spiral inductor Inductors are placed far apart to avoid coupling (~200um) Differential inputs are decoupled by GSGSG pattern G S G S G 570um Analog and Mixed-Signal Center. Q2 M1. TAMU 76 Gain S. M2 1nH . 3nH 580um Q1.

TAMU 77 .Testing Setup Input matching (S11) S-parameter network analyzer (HP 8719ES) S11 better than -11dB High gain mode Testing board Low gain mode * LNA is tested together with mixer Analog and Mixed-Signal Center.

TAMU 78 .Testing Setup (cont’d) Gain of the front-end Signal generator RF IN Testing board Oscilloscope IF OUT I&Q Conversion gain: 33dB * LNA is tested together with mixer Analog and Mixed-Signal Center.

Testing Setup (cont’d) IIP3/IIP2 Testing board Spectrum Analyzer RF IN -80 -50 -45 -40 -35 -30 -25 -20 -15 -10 60 IIP3=-13dBm 40 Output (dBm) 20 0 -20 -40 -60 2-Tone Input Power (dBm) Signal generator Power combiner 80 60 IIP2=10dBm 40 Output (dBm) 20 0 IF OUT I&Q -20 -40 -60 -60 -50 -40 -30 -20 -10 0 10 20 2-Tone Input Power [dBm] * LNA is tested together with mixer Analog and Mixed-Signal Center. TAMU 79 .