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Analog-to-Digital Conversion

R. Jacob Baker and Vishal Saxena

R

Department of Electrical and Computer Engineering

Boise State University

jbaker@boisestate.edu

Abstract :

As CMOS technology shrinks, the transistor speed increases enabling higher speed

communications and more complex systems. These benefits come at the cost of decreasing

inherent device gain, increased transistor leakage currents, and additional mismatches due to

process variations. All of these drawbacks affect the design of high-resolution analog-to-

digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology

useful in these small processes the K-Delta-1-Sigma (KD1S) modulator-based ADC was

proposed. The KD1S topology employs inherent time-interleaving with a shared op-amp and

K-quantizing paths and can achieve significantly higher conversion bandwidths when

compared to the traditional delta-sigma ADCs. The 8-path KD1S modulator achieves an SNR

of 58 dB (or 9.4-bits resolution) when clocked at 100 MHz for a conversion bandwidth of 6.25

MHz and an effective sampling rate equal to 800 MHz. The KD1S modulator has been

fabricated in a 500 nm CMOS process and the experimental results are reported. Deficiencies

in the first test chip performance are discussed along with their alleviation to achieve

theoretical performance.

Outline

Introduction

Delta-Sigma

D l Si M d l i

Modulation

Interleaved Delta-Sigma Modulators

KD1S Modulator Topology

Test Chip and Results

Conclusion

CMOS Scaling Trends

9 Design headroom is shrinking.

Transistor open-loop gain is dropping ( ~10’s in nano-CMOS)

Random offsets due to device mismatches.

Analog to Digital Converter Trends

Different ADC architectures for the

signal bandwidth and bit resolution

requirements.

CMOS scaling enables higher sampling

speeds but at the cost of component

mismatches and reduced transistor gain.

New wireless

i l applications

li i require

i

higher bandwith (25 MHz) and over 10

bits of resolution.

Software defined radio (SDR) can

always utilize higher sampling rates for

high resolution.

Nyquist rate ADCs reaching 10 bits

@500 MHz.

9 Mismatch and reduced gain in nano-

CMOS

9 Digital calibration required.

required

Digital Calibration of ADCs

equalize ADC response

9 DAC runs at slower frequency

Calibration may break down at high

frequencies and takes time to converge.

DAC

modeling!

9 Promising but cumbersome.

Not robust with further CMOS scaling and

high speed operation.

9 Need topologies which are inherently robust

to mismatches.

Delta-Sigma (ΔΣ or DS) Modulation

ΔΣ Modulator

Qe

vin + vDSM vout

H(z) ADC Digital Filter

–

DAC

STF

NTF•Qe

|VDSM(f)| |Vout(f)|

vin vin

Qe

f f

fs/2•OSR fs/2 fs/2•OSR fs/2

signal band.

Digitally filter away the out-of band shaped (modulated) noise.

Trades-off SNR with oversampling ratio.

First-Order DSM Review

Y(z)= z−1Vin(z) + (1–z−1)Qe(z)

9 Quantization noise is differentiated and

pushed out of baseband.

Neff = N – 0.566 +1.5·log2(OSR)

9 N is the resolution of the quantizer

9 SNR = 6.02N+1.76–5.17+30·log10(OSR)

9 10 bits for OSR = 64 and N = 1.

Feedback structure desensitizes the

component mismatches and nonlinearity in

the forward path.

Op-amp can be lower gain (AOL > OSR) and

lo er fun.

lower

DSM for Wideband Data Conversion?

oversampling.

oversampling

9 Signal bandwith is a fraction of the sampling rate.

8 Not Nyquist-rate sampling as desired.

Use many DSM’s in parallel

9 Double Sampling

9 Time-Interleaved/Parallel

Time Interleaved/Parallel DSMs.

DSMs

Cascade of low-OSR DSMs with high sampling rates.

Double Sampling DSM

Sample input at both the clock phases

9 Integrator is utilized for both the clock phases.

9 Can

C alsol use a single

i l comparator clocked

l k d on both

b h the

h phases.

h

Two noise shaping loops exist, leading to two lobes in NTF.

8 Path mismatches lead to folding of noise into baseband.

Time-Interleaved DSM

φ1 φ1

ΔΣ

φ2

Use K parallel time-interleaved DS

φ2

ΔΣ Modulators.

Vin(z) φ3 Y(z) 9 Standard technique for Nyquist-rate

φ3

ΔΣ

ADCs.

K-sets of opamps and comparators

8 K-times power consumption

φ8 φ8

ΔΣ 8 Large area

8 Path mismatches will lower SNR and

cause spurious tones

tones.

Ts=1/fs

Does it really behave like a DSM with

φ1

K·OSR oversampling?

φ2 8 No!

φ3 Hadamard-modulation of input can be

used to achieve Nyquist rate sampling

φ8 9 Complex digital filters, large area and

Non-overlapping Clocks power.

Time-Interleaved DSM: Noise Shaping

8 Not true noise-shaping .

8 Only 00.5-bit

5 bit increase in resolution with doubling in number of paths.

paths

The feedback signal in the delta-sigma loop arrives back to the input only

after a delay of Ts (= 1/fs).

)

9 Noise shaping looks like a single DSM path.

True noise shaping only possible when the feedback delay is less than Ts/K.

9 DSMs

S ddon’t

’ quite

i stack

k up lik

like Flash

l h or pipelined

i li d ADCs

A C due

d to the

h feedback

f db k

structure.

K-Delta-1-Sigma Modulator (KD1S)

4CI

1-Sigma Share the op-amp across K-paths to

realize a K-Delta-1-Sigma (KD1S)

vint

φ1-1 φ2-1 φ2-1 Ts/K

VCM Ts=1/fs

CI VCM

Integrator

y0

φ1-1

topology

topology.

φ1-2 φ2-2 φ2-2

y1

φ2-1 Initially assume ideal components:

φ1-2

9 Comparators settle in time.

φ1-3 φ2-3 φ2-3 φ2-2

y2 φ1-3 9 Integrator

I

φ1-4 φ2-4 φ2-4

φ2-3

Thus the error signal

y3 φ1-4

vin φ2-4

is cycled through the integrator

φ2-1 φ1-1 φ1-1

y4

Non-overlapping Clocks within Ts/K duration.

9 True first order noise shaping.

φ2-2 φ1-2 φ1-2 y7

y6

y5

y5 b3

y4 K-Input

p

b2

y3 Wallace

b1

φ2-3 φ1-3 φ1-3 Tree Adder

y2 b0

y6 y1

y0

-K

φ2-4 φ1-4 φ1-4 Path Filter, 1-z-1

1-z

y7

Clock Generation

φ1_2

φ1_2

φ2_2

φ2_2

φ1_3

φ1_1

φ2_3

φ2_3

φ1_4

φ1_4

φ2_4

φ2_4

φ1_1

φ1_1

φ2_1

φ2_1

Ring oscillator is used to

generator the K clock phases and Delay Delay Delay Delay

their complements.

9 GHz sampling rates as the rate is

set by the clock edge spacing. φ1

in+

A DLL can also be used for low 5x 5x

φ1

(using an external reference in-

φ2

5x 5

5x

clock). φ2

K- Clock phases

KD1S Simulation

KD1S Output Spectrum KD1S Output Spectrum

0 0

-20 -20

-30 -30

-40 -40

-50 -50

+20dB/dec

dB

dB

-60 -60

-70 -70

-80 -80

-90 -90

-100 -100

0 1 2 3 4 5 6 7 8 5 6 7 8 9

10 10 10 10 10

F

Frequency 8

Frequency

x 10

9 Ideal first

first-order

order noise shaping

shaping.

KD1S with Non-ideal Components

Use a slow op-amp (fun≈3fs)

9 Each integrating path takes Ts/2

time to fully settle.

settle

9 Signal spreads into other paths

due to the clocking scheme.

Finite comparator speed.

speed

Effective sampling frequency

(fs,new) is only limited by the

comparator speed and not the op-

amp fun

9 Significant speed and power

benefits!

Note that, an equivalent single-

path DSM with require opamps

with

Charge Spreading

Q0 Q0 At any instance K/2 switch capacitors

Qp Q1

Q[K-1]/2 are connected to the integrator.

α0 n.Ts/K

t

9 Charge from path-i leaks into path-j.

α1

W[n] α[K-1]/2 The impulse response of the block is

0 1 2 [K-1]/2 K

convolved with the charge spreading

filter

φ2-1

Initial push

~α0•vin[n] ΔQ1

φ2-2

ΔQ where

ΔQ2

φ2-3

vint

i the

is th partial

ti l settling

ttli factor

f t (initial

(i iti l push)

h)

VCM of the integrator.

ΔQ3

Integrator

φ2-4

ΔQ4

KD1S with Non-Ideal Op-amp

4CI

1-Sigma

vint The theoretical result for the K-path

VCM

φ1-1

CI

φ2-1

VCM

φ2-1

y0

Integrator are plugged into the KD1S

Integrator Modulator:

φ1-2 φ2-2 φ2-2

y1

y2

y3

vin

φ2-1 φ1-1 φ1-1

y4 Worst case loss of ~1-bit resolution over

φ2-2 φ1-2 φ1-2

ideal KD1S

y5

y6

y7

K-Deltas

KD1S: Effect of Comparator Delay (Tcomp) KD1S Output Spectrum KD1S Output Spectrum

0 0

-10

-20

-20

-30

-40

-40

-60 -50

dB

dB

-60

-80

-70

-80

-100

-90

-120 -100

0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8

Frequency 8 Frequency 8

x 10 x 10

0 0

-10 -10

-20 -20

-30 -30

-40 -40

dB

dB

-50 -50

-60 -60

-70 -70

-80 -80

0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8

Frequency 8 Frequency 8

x 10 x 10

For true noise-shaping in a process the KD1S should be clocked such that

The resultingg bit resolution decreases with an increase in comparator

p delay.

y

9 Resolution drops from 9-bits to 6-bits as we increase Tcomp from Ts/2K to Ts/2.

KD1S Test Chip

nm CMOS process.

8-path outputs registered on a 100

MHz clock.

9 fs,new = 800 MHz.

MHz

Digital signal processing using

Matlab and Agilent MSO7104.

Test Results

PSD (dB)

SNR (dB)

Measured SNR for a 2 MHz, 4 Vp-p input tone, and BW = 6.25 MHz

9 SNR = 30 dB, Neff = 5 bits

9 Proof of Concept: First order wideband noise-shaping achieved.

Performance lower than expected:

9 Design mistake in connection of clock phases. Lower op-amp gain.

9 Rectified in subsequent designs.

KD1S vs. Single-path DSMs

KD1S topology

l ((and

d iits hi

higher

h order

d extensions)

i ) employl inherent

i h

interleaving to :

9 achieve comparable

p (or

( better)) performance

p than CT-DSMs.

9 have the desirable properties of DT-DSMs like frequency scalability

and clock jitter tolerance.

9 GHz sampling possible as Opamp gain gain-bandwidth

bandwidth limitations are

eliminated.

9 Modulator can be clocked as fast as the comparator can respond

without any stability concerns.

Comparison of KD1S with DT- and CT-DSMs

Discrete-time DSM Continuous-time DSM K-Delta-1-Sigma Modulator

where M = DSM order fs =1/(2Tcomp)

Opamp fun 2.5fs to 5fs ≥fs 3fs ≈fs,new/3

requirements

i (90% to 99% SC settling) (95% settling in Ts/2 interval)

fs,max limited by Opamp fun: ~fT/50 Excess loop delay and Only comparator

stability: fT/20 metastability: GHz sampling

Frequency

eque cy scalability

sc b y Yes

es No

o Yes

es

Process variation Ratio of C’s: <0.1% RC time constant: 30% Ratio of C’s: <0.1%

Delay Allocation Easy Complicated Easy

Parallel and Cross- Possible Not possible Possible

coupled Designs

Conclusion

nano CMOS

nano-CMOS.

K-Delta-1-Sigma Modulators combine the feedback

desensitization of mismatches and inherent interleavingg at low-

power.

A first-order noise shaping KD1S topology has been

demonstrated.

demonstrated

9 Easily extended to a second-order KD1S topology.

Test results for KD1S chipp are discussed alongg with suggested

gg

improvements.

References

1. Razavi, B., Aytur, T., Lam, C., Yang, F.-R., Yan, R.-H., Kang, H.-C., Hsu, C.-C.,

and Lee, C.-C. “Multiband UWB transceivers,” Proc. IEEE Custom Integrated

Circuits Conference, pp. 141-148, Sept 2005.

2

2. Fl d B

Floyd, B. ett al,

l “Sili

“Silicon Milli

Millimeter-Wave

t W Radio

R di CiCircuits

it att 60-100

60 100 GHz,”

GH ” IEEE

Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, pp.

213-218, Jan. 2007.

3. Malla, P. et al. “A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR

70dB SNDR DT ΔΣ ADC for 802

70dB-SNDR 802.11n/WiMAX

11n/WiMAX Receivers

Receivers,” International Solid

Solid-

State Circuits Conference, pp. 496-497, Feb. 2008.

4. Gustavsson, M., Wikner, J. J., and Tan, N. N., “CMOS Data Converters for

Communications,” 1st Ed., Kluwer, 2002.

5

5. Verma A

Verma, A., Razavi

Razavi, B.,

B “AA 10b 500MHz 55mW CMOS ADC, ADC ” International

Solid-State Circuits Conference, pp. 84-86, Feb. 2009.

6. Baker, R.J., “CMOS: Mixed-Signal Circuit Design,” 2nd Ed., Wiley Interscience,

2008. Website: http://CMOSedu.com

7

7. I Galton and H.

I. H T.T Jensen,

Jensen “Oversampling

Oversampling Parallel Delta

Delta-Sigma

Sigma Modulator A/D

Conversion,” IEEE Trans. on Circuits and Systems - II: Analog and Digital Signal

Processing, Vol. 43, No. 12, pp. 801-810, Dec. 1996.

References

8. R. Khoini-Poorfard, L. B. Lim, and D. A. Johns, “Time-Interleaved Oversampling

A/D Converters:Theory and Practice,” IEEE Trans. on Circuits and Systems - II:

Analog and Digital Signal Processing, Vol. 45, No. 8, pp. 634-645, August 1997.

9

9. E T King,

E.T. Ki A. A Eshraghi,

E h hi I.I Galton,

G lt T.

T S.

S Fiez,

Fi “A Nyquist-Rate

N i t R t Delta-Sigma

D lt Si A/D

Converter, ” IEEE Journal of Solid-State Circuits, vol. 33, no. 1, pp. 45-52, Jan.

1998.

10. Eshraghi, T. S. Fiez, “A Time-Interleaved Parallel ΔΣ A/D Converter,” IEEE

Transactions on Circuits and Systems-II:

Systems II: Analog and Digital Signal Processing,

Processing

vol. 50, no. 3, Mar. 2003.

11. Eshraghi, T. S. Fiez, “A Comparative Analysis of Parallel Delta-Sigma ADC

Architectures,” IEEE Transactions on Circuits and Systems-I: Regular Papers, vol.

51, no. 3, Mar 2004.

Questions ?

Backup Slides

KD1S – Timing and Charge Flow

Cf

In order to achieve true first order noise

shaping (K

(K-times),

times), the chain of noise

vint differentiation should not be broken:

VCM

φ1-1 φ2-1 φ2-1 9 Pick current integrator output (vint),

Ci VCM y1 quantize it with comp-1 to get y1.

9 This y1 must be used by path-1 and

φ1-2 φ2-2 φ2-2 subtracted from vin.

y2 9 The result (vin-y1) is integrated and its

vin result updates vint.

9 Now path-2 must pick this vint and

quantize with comp-2, and so on….

φ2-4 φ1-4 φ1-4

Al

Always fresh

f h Q(v

Q( int) information

i f i

yK

should fed back through the DAC

(important!)

Ideal KD1S- Circular Clock Phase Diagram (CCPD)

convenient tool to understand the

noise flow in a KD1S modulator.

The arcs represent the cycling of vint

info across a path and the integrator

forming a loop (Ts/K time):

9 vint→yi=Q(vint) t→Δ=vin–yi → vint

=Σ(Δ)

The arcs show an uninterrupted flow

of noise causing differentiation of

noise every Ts/K time period.

9 True first order noise shaping by K-

times.

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