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Microelectronic Circuit Analysis the various types of MOSFETs.

Sedra A. S., Microelectronic Circuits, 5th Edition, design techniques of MOSFET circuits.

Oxford University Press

Examine several applications of MOSFET circuits.

circuits.

Chapter 3

Jacob R Baker

Chapter 6

CMOS

Schematic of n-Channel

Enhancement Mode MOSFET

p-Channel Depletion- Cross-Section of nMOSFET and pMOSFET

Mode MOSFET

Symbols

Neamen Microelectronics Chapter 3-6

5/24/2006 McGraw-Hill

εox is oxide permittivity.

The physics of the MOS

structure can be explained

with the aid of a simple

parallel-plate capacitor.

Figure above shows how voltages, currents, and terminal

designations for a MOSFET are defined.

When the substrate is connected to ground and the well is

tied to VDD, the simplified model at the bottom is used.

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

MOS Capacitor Under Bias: MOS Capacitor Under Bias:

Electric Field and Charge Polarity of the applied voltage reversed

Parallel plate capacitor – p-type semiconductor substrate

because of the fixed acceptor impurity atoms.

Positive gate bias:

Holes attracted to gate

Electrons attracted to gate

Enhancement mode

n-type substrate

Parallel plate capacitor – n-type semiconductor substrate Means that a voltage must be applied to the

gate to create an inversion layer.

For the MOS capacitor with a p-type substrate,

a positive gate voltage must be applied to

create the electron inversion layer;

For the MOS capacitor with an n-type

substrate, a negative gate voltage must be

applied to create the hole inversion layer.

Negative gate bias:

Holes attracted to gate

In Smith & Sedra,

MOSFET Capacitance ε ox

Cox = .

– Case 1: Accumulation tox

Examine the cross-sectional view in the figure In R Jacob Baker,

below.

ε ox

With negative bias voltage, mobile holes from ′ =

Cox .

the substrate are attracted or accumulated tox

under the oxide, or dielectric. We follow Baker’s

book notation here.

Note that the capacitor is given by

′⎜ ⎟= = =

Cox

⎝ unit area ⎠ tox (µm ) (

A µm 2 )

t (separation of electrodes)

εr = 3.97 for relative dielectric constant of SiO2. MOSFET Capacitance

To calculate the value of a capacitor, we look at the area

where poly1 and poly2 intersect, A, or

– Case 2: Depletion

′ ⋅A

Cox = Cox Consider less negative voltage, which is not

enough to attract a large number of holes

under the oxide and not positive enough to

attract a large number of electrons.

Depletion capacitance

in series with oxide C.

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

MOSFET Capacitance – Case 2: Depletion MOSFET Capacitance – Case 2: Depletion

Under these conditions, the surface under the The MOSFET operated in this region is said to

gate is said to be nearly depleted (depleted of be in weak inversion or the subthreshold

free electrons and holes). region because the surface under the oxide is

We see that an additional capacitance exits. not heavily n+.

The new capacitance is the oxide capacitance

in series with the depletion capacitance.

The depletion layer is formed between the

substrate and the induced channel.

oxide.

Depletion capacitance

in series with oxide C.

MOSFET Capacitance bias voltage is varied, for an NMOS device.

This is the situation when an NMOS device source, drain,

– Case 3: Strong Inversion and bulk are grounded.

The attracted electrons under the gate oxide short the drain

If the bias voltage is sufficient large (the and source together forming a low-resistance bottom plate

threshold voltage of the NMOS device) so that for the capacitor.

a large number of electrons are attracted Capacitor is made in this fashion.

under the gate, the surface is said to be

inverted, that is, no longer p-type.

+++

–––

Example #1 - Capacitor

figure below is to be used as a capacitor. If

the width and length are both 100 µm,

estimate the capacitance between the gate

and the source/drain terminals. Are there any

restrictions on the voltages we can use across

the capacitor?

Given CMOS technology 1 µm (long channel),

oxide thickness, tox = 200 Å,

Capacitance per unit area, C’ox = 1.75 fF/µm2.

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Example #1 – Solution

operation in the strong inversion region, that is, VGS>>VTHN

(the gate potential at least a threshold voltage plus 5% of

VDD above the source/drain potentials).

The capacitance between the gate and the source/drain is

then Cox=C’ox×W×L, or

⎛ fF ⎞

Cox = ⎜⎜1.75 ⎟(100 µm )(100 µm ) = 17.5 pF

2 ⎟

⎝ µm ⎠

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

Below this channel, electrons fill the holes in the substrate

giving rise to a depletion region (depleted of free carriers).

The thickness of the depletion region is given from pn

junction theory by

than the threshold voltage VTHN. N A = no of acceptor atoms in substrate

Xd =

Under these conditions a channel of electrons is formed qN A Vs = electrostatic potential at oxide

under the gate oxide.

silicon interface (the channel)

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

As the temperature of the silicon crystal is increased it absorbs

heat. Some of the electrons in the valence band gain enough

energy to jump the bandgap energy of silicon, Eg, as seen in

the figure below.

The number of electrons in the conduction band and thus the

number of holes in the valence band at a given time is a

The electrostatic potential of the p-type substrate is given

random number and is an important parameter.

by

Ei − E fp These carriers are called intrinsic carriers, ni.

kT N A

V fp = − =− ln

q q ni

Note that this is a negative number.

One edge of the depletion region is the MOSFET’s gate

oxide, while the other edge is the p-substrate (holes).

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

The positive potential on the gate attracts electrons under If Vs = Vfp and then Q’b = 0, the MOSFET is operating in the

the gate oxide. This charge is equal and opposite to the accumulation mode, or the MOSFET is OFF in circuit terms.

charge in the polysilicon gate material. At this point the number of holes at the oxide-

The charge/unit area is given by semiconductor surface is NA, the same concentration as the

bulk.

Qb′ = qN A X d = 2ε si qN A Vs − V fp

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

As VGS is increased, the surface potential becomes more The threshold voltage of the n-channel MOSFET is

positive. defined as the applied gate voltage needed to

When Vs = 0, the surface under the oxide has become create an inversion charge in which the density is

depleted (the carrier concentration is ni).

equal to the concentration of majority carriers in

When Vs = –Vfp (a positive number), the channel is inverted

(electrons are pulled under the oxide forming a channel),

the semiconductor substrate.

and the electron concentration at the semiconductor-oxide In simple terms, we can think of the threshold

interface is equal to the substrate doping concentration. voltage as the gate voltage required to “turn on”

The value of VGS when Vs = –Vfp is arbitrarily defined as the the transistor.

threshold voltage, VTHN and the negative charge under the

gate oxide is given by

′ = 2qN Aε si − 2V fp

Qbo

with units of Coulombs/m2.

Note that the surface potential changed a total of 2|Vfp|

between the strong inversion and accumulation cases.

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

In a simplified cross section of a MOSFET, the

Schematic of n-Channel gate, oxide, and p-type substrate regions are the

Enhancement Mode MOSFET same as those of a MOS capacitor.

In addition, now there are two n-regions, called

the source terminal and the drain terminal.

The current flow in a MOSFET is the result of the

flow of charge in the inversion layer, also called

the channel region, adjacent to the oxide-

semiconductor interface.

The channel length L and channel width W are

defined in the figure above.

The channel length is typically less than 1 µm.

The oxide thickness on order of 400 Å or less.

A thick oxide, called the field oxide, is deposited Basic Transistor Operation

outside the area in which the metal interconnect

lines are formed.

the gate material is usually heavily doped

polysilicon.

inversion layer is inversion layer is

formed formed

A sufficiently large positive gate voltage is Since the gate terminal is separated from the

required to invert the p-type layer at the channel by an oxide or insulator, there is no

oxide-semiconductor interface to n-type layer gate current.

that connects the n-source to the n-drain. Similarly, since the channel and substrate are

A current can then be generated between the separated by a space-charge region, there is

source and drain terminals. The magnitude of essentially no current through the substrate.

the current is a function of the amount of

charge in the inversion layer, which in turn is

a function of the applied gate voltage.

This transistor is called an enhancement-mode

MOSFET.

Since the carriers in the inversion layer are

electrons, this device is called an n-channel

MOSFET (NMOS).

Enhancement-Mode nMOSFET

Lets derive the large-signal IV (current/voltage) characteristics

of the MOSFET, namely operation in the triode and the

saturation regions.

The derivation is sometimes referred to as the gradual-channel

approximation.

The electric field variation in the channel between the source

Gate-to-source > threshold

Gate-to-source < threshold and drain (the y-direction) doesn’t vary significantly when

Inversion layer is created. compared to the variation in the direction perpendicular to the

There is no electron inversion Drain-to-substrate pn-junction channel (the x-direction).

layer, drain-to-substrate pn is reverse-biased, so current

junction reverse biased. flows through channel region.

MOSFET Operation in the Triode (ohmic) • Conditions:

Region – When VGS>VTHN, the

surface under the

oxide is inverted, and

– VDS>0, causing a drift

current to flow from

the drain to source.

• Initial analysis,

– Assume VDS is

sufficiently small so

that the threshold

voltage and the

Triode region is a carryover from the days of vacuum- depletion layer width

tube devices whose operation a FET resembles. are approximately

constant.

– V(y) is the voltage with application of the threshold voltage VTHN

respect to the source – Application of the threshold voltage VTHN is necessary

of the MOSFET, of the for conduction between the drain and the source. As

channel a distance y a result, charge Q’b is present. This charge is given by

away from the source.

– The potential ′ ⋅ VTHN L (2 )

Qb′ = Cox

difference between the

– The total charge available in the inverted channel, for

gate electrode and the

conduction of a current between the drain and the

channel is then

source, is given by the difference in these two

VGS – V(y).

equations (1) & (2), or

– The charge/unit area

in the inversion layer is ′ ⋅ [VGS − V ( y ) − VTHN ]

QI′ ( y ) = Cox L (3)

given by

′ ⋅ [VGS − V ( y )]L (1)

′ = Cox

Qch

Derivation of the iD – vDS characteristic of the NMOS

Transistor Drift Velocity

• Let us now apply a small electric field to the

lattice. Note in the figure that the field-directed

motion is a small perturbation on the random

thermal velocity.

Modelling DiffusionFigures from CMOS Circuit Design, Layout, and Simulation, Copyright 2008, Wiley-IEEE,

CMOS d

• The time interval between collisions averaged • The net carrier velocity in an applied field is

over the entire electron population is τcn, the called the drift velocity, vd.

mean scattering time for electrons, is not • It can be found by equating the impulse (force

altered appreciably by the applied field. x time) applied to an electron during its free

flight between collisions with the momentum

gained by the electron in the same period.

• This equality is valid because steady state is

reached when all momentum gained between

collisions is lost to the lattice in the collisions.

Modelling DiffusionFigures from CMOS Circuit Design, Layout, and Simulation, Copyright 2008, Wiley-IEEE, Modelling DiffusionFigures from CMOS Circuit Design, Layout, and Simulation, Copyright 2008, Wiley-IEEE,

CMOS d CMOS d

• The force on an electron is –qE and the • The equation states that the electron drift

momentum gained is mn*vd. Thus, velocity vd is proportional to the field with a

proportionality factor that depends on the

− qEτ cn = mn*vd mean scattering time and the effective mass of

the nearly free electron.

or • The proportionality factor is an important

qEτ cn property of the electron called the mobility and

vd = − is designated by the symbol µn.

mn*

qτ cn

µn = L ( 3)

mn*

Modelling DiffusionFigures from CMOS Circuit Design, Layout, and Simulation, Copyright 2008, Wiley-IEEE, Modelling DiffusionFigures from CMOS Circuit Design, Layout, and Simulation, Copyright 2008, Wiley-IEEE,

CMOS d CMOS d

• Because vd = –µnE, the mobility describes how • Differential resistance of the channel region

– With a length dy and a width W, it is given by

easily an electron moves in response to an

applied field. 6474 8

eff. sheet Res.

dR = ⋅

• The hole mobility µp is defined as µnQI′ ( y ) W

µp = units of cm2/V·sec.

m*p – The mobility is simply a ratio of the electron (or hole)

velocity cm/sec to the electric field, V/cm.

Modelling DiffusionFigures from CMOS Circuit Design, Layout, and Simulation, Copyright 2008, Wiley-IEEE,

CMOS d

• Differential voltage drop across resistance • Transconductance parameter

– The differential voltage drop across this differential – The transconductance parameter, KP, for a n-channel

resistance is given by MOSFET is given by

ε ox

dV ( y ) = I D ⋅ dR =

ID In Smith’s book, this quantity is

⋅ dy ′ = µn ⋅

KPn = µ n ⋅ Cox

Wµ nQI′ ( y ) denoted as k’n. tox

I D ⋅ dy = Wµ nQI′ ⋅ dV ( y ) – For a p-channel MOSFET is given by

ε ox

– Substituting Eqn.(3) in this equation above, ′ = µp ⋅

KPp = µ p ⋅ Cox

tox

′ (VGS − V ( y ) − VTHN ) ⋅ dV ( y )

I D ⋅ dy = Wµ nCox L (4 ) where µp is the mobility of the holes in a PMOS

transistor.

ε ox A Cox ε ox

Cox = ′ =

Cox =

tox A tox

– KP in the long-channel process (with a minimum in the triode (linear or ohmic) region.

length of 1 µm) used in this course are 120 µA/V2 and – This is the case when the induced channel extends

40 µA/V2 for n- and p-channel transistors, from the source to the drain.

respectively. – Writing

• Expression for drain current flow W

β = KPn ⋅

– Can be obtained by integrating Eqn.(4) from the L

source to the drain, that is, from 0 to L on the left- ⎡ 2

⎤

I D = β ⋅ ⎢(VGS − VTHN )VDS −

VDS

hand side and the right side from 0 to VDS. ⎥

⎣ 2 ⎦

(VGS − V ( y ) − VTHN ) ⋅ dV ( y )

L VDS

I D ∫ dy = W ⋅ KPn ⋅ ∫

0 0

– For PMOS,

⎡ V ⎤ ⎧ for VGS ≥ VTHN

2

⋅ ⎢(VGS − VTHN )VDS −

W

I D = KPn ⋅ ⎥ L ⎨V ≤ V − V

DS

⎡ 2

⎤ ⎧ for VSG ≥ VTHP

⋅ ⎢(VSG − VTHP )VSD −

W VSD

L ⎣ 2 ⎦ ⎩ DS I D = KPp ⋅ ⎥ L⎨

2 ⎦ ⎩VSD ≤ VSG − VTHP

GS THN

L ⎣

L (5)

β KPn W

– Writing Kn = = ⋅ • MOSFET Operation in the Saturation Region

2 2 L (pinched off region)

– For NMOS,

[

I D = K n ⋅ 2(VGS − VTHN )VDS − VDS

2

]

– For PMOS,

[

I D = K p ⋅ 2(VSG − VTHP )VSD − VSD

2

]

– Kn and Kp are defined in Neamen’s textbook.

– β, KPn and KPp are defined in Baker’s textbook. We

use these notation here in this course.

(a) The relative charge density is essentially constant along the (c) As vDS reach the point vGS–vDS(sat)=VTHN across the oxide at

entire channel length. the drain terminal, the induced inversion charge density at the

drain terminal is zero. The incremental channel conductance at

(b) When vDS increases, the voltage drop near the drain terminal the drain is zero, which means the slope of iD versus vDS curves

decreases, which means that the induced inversion charge is zero.

density near the drain also decreases. The incremental

conductance of the channel at the drain then decreases, which (d) For vDS>vDS(sat), the point in the channel at which the

causes the slope of iD versus vDS curve to decrease. inversion charge is zero moves toward the source terminal.

Electrons enter the source, travel through the channel toward

the drain, and then…

(d) …at the point where the charge goes to zero, are injected into

the space-charge region, where they are swept by the E-field to

• MOSFET Operation in the Saturation Region

the drain contact. In the ideal MOSFET, the drain current is

– The voltage V(y) when y = L in Eqn.(3) is simply VDS.

constant for vDS>vDS(sat). This region is referred to as the

In the previous analysis, we said that VDS is always

saturation region. As the applied gate-to-source changes, the iD

less than VGS – VTHN so that at no point along the

versus vDS curve changes.

channel is the inversion charge zero.

– When VDS = VGS – VTHN the inversion charge under – Increase in VDS beyond VDS,sat attract the fixed

the gate at y = L (the drain-channel junction) is zero, channel charge to the drain terminal depleting the

Eqn.(3). charge in the channel directly adjacent to the drain

– This drain-source voltage is called VDS,sat(=VGS–VTHN), (again, pinching off the channel).

and indicates when the channel charge becomes – Further increases in VDS do not cause an increase in

pinched off at the drain-channel interface. the drain current.

– Figure 6.10 shows that the depletion region, with a – When a MOSFET is operated with its channel

thickness of Xdl, between the drain and substrate pinched off, that is, VDS≥VGS – VTHN and VGS≥VTHN, it

increases, causing the channel to pinch off. is operating in the saturation region. Substitution of

– If VDS is increased until the drain-substrate depletion VDS,sat into Eqn.(5) gives

region extends from the drain to the source, the

⎡ 2

⎤

⋅ ⎢(VGS − VTHN )VDS −

device is said to be punched through. W VDS

I D = KPn ⋅ ⎥

– Large currents can flow under these conditions,

causing device failure.

L ⎣ 2 ⎦

= KPn ⋅

W ⎡

⋅ ⎢(VGS − VTHN )(VGS − VTHN ) −

(VGS − VTHN ) ⎤

2

– The maximum voltage, for ⎥

near minimum-size channel L ⎣ 2 ⎦

lengths, that can be applied

β

⋅ ⋅ (VGS − VTHN ) = ⋅ (VGS − VTHN ) L (6 )

between the drain and KPn W

=

2 2

source of a MOSFET is set

by the “punchthrough” 2 L 2

voltage. → for VDS ≥ VGS − VTHN and VGS ≥ VTHN

– We can define an electrical channel length of the – Since the depletion layer width Xdl increases with

MOSFET as the difference between the drawn increasing VDS, the drain current increases as well.

channel length, neglecting laterial diffusion, and the

depletion layer width, Xdl, between the drain n+ and Lelec (↓ ) = Ldrawn − X dl (↑ )

the channel under the gate oxide by

I D (↑ ) = ⋅ (VGS − VTHN )

KPn W

Lelec = Ldrawn − X dl ⋅

2

2 Lelec (↓ )

– Substituting into Eqn.(6), we obtain a better

representation of the drain current – This effect is called channel length modulation (CLM).

– If Ldrawn is increased the effects of Xdl changing (CLM)

become negligible.

⋅ (VGS − VTHN ) L (7 )

KPn W

ID = ⋅

2

2 Lelec

– Taking the derivative of Eqn.(7) with respect to VDS, – Typical values for λ, called the channel length

∂Lelec ∂ (Ldrawn − X dl )

modulation parameter, range from greater than 0.1

= = −1 V–1 for short-channel devices to 0.01 V–1 for long-

∂X dl ∂X dl channel devices.

– Equation (6) can be rewritten for a device operating in

∂I D ∂I D ∂Lelec

= ⋅ the saturation region, taking into account channel

∂VDS ∂Lelec ∂VDS length modulation as

KPn W 2 dL

=−

⋅ ⋅ (VGS − VTHN ) [1 + λ (VDS − VDS , sat )]

KPn W

ID =

2

2 Lelec dVDS

2 L

=− ⋅ 2 ⋅ (VGS − VTHN ) ⋅ elec

KPn W 2 dL dX dl for VDS > VDS , sat = VGS − VTHN and VGS > VTHN

2 Lelec dX dl dVDS L (9 )

⎡ 1 dX dl ⎤

= ID ⋅ ⎢ ⎥ = ID ⋅λ L (8)

⎣ elec

L dVDS ⎦

– When VDS = VDS,sat or the drain current is at the • Characteristics of a long-channel NMOS device

triode/saturation region border, the drain current is – VGS = 5 V and VTHN = 1 V for an n-channel MOSFET.

sometime specified as

– Calculated VDS,sat = VGS – VTHN = 5 – 1 = 4 V.

– Typical curves for the NMOS in the simulation results:

I D , sat = I D when VDS = VDS , sat = VGS − VTHN

VDS.

– In short-channel MOSFET discussion, mobility does

indeed vary with VDS making characterizing ID

considerably more challenging.

– Notice that the device appears to go into saturation – Q’I(y) decreases as we move away from the source of

earlier than predicted by VDS,sat = VGS – VTHN. the MOSFET, causing Q’I(L) to become zero earlier,

– The bold line in the figure separates the actual triode as seen in Fig. 6.10.

and saturation regions (and also indicates ID,sat).

– From the curve, we see that VDS,sat is 1.4 V, not 4 V

as we calculate using VDS,sat = VGS – VTHN.

– The actual charge distribution in the channel is not

constant but rather a function of VDS.

– See page 145, CMOS Circuit Design, Layout and – The following SPICE model parameters are related to

Simulation. the calculation of VTHN.

Symbol Name Description Default Typ. Units

VTHN0 VTO Zero-bias threshold 1.0 0.8 Volts

voltage

γ GAMMA Body-effect parameter 0 0.4 V1/2

potential

NA NSUB Substrate doping 0 1E15 cm–3

Q’ss/q NSS Surface state density 0 1E10 cm–2

TPG Type of gate material 1 1

• TPG specifies the type of gate material: Long-channel MOSFET parameters used in this unit.

– 1 opposite to substrate, The VDD=5 V and the scale factor is 1 µm (1e-6)

– -1 same as substrate, and

– 0 for aluminum gate. Parameter NMOS PMOS Comments

• For Long-Channel MOSFET Models, refer to

textbook, pages 146-147. KPn and KPp 120 µA/V2 40 µA/V2 tox = 200 Å

• Table in the next slide shows a summary of the

device characteristics for the long-channel C’ox = εox/tox 1.75 fF/µm2 1.75 fF/µm2 Cox= C’oxWL(scale)2

CMOS process.

λn and λp 0.01 V–1 0.0125 V–1 at L = 2

Short-Channel MOSFETs

illustrating the fundamentals of MOSFET

operation.

– However, modern CMOS transistors are

short-channel devices.

• The electric field under the gate oxide can no

longer be treated in a single dimension.

• The average drift velocity, v, of an electron plotted

• In addition, the velocity of the carriers drifting against electric field, E, is shown in the figure above.

between the channel and the drain of the MOSFET When the electric field reaches a critical value, labeled

saturates. See figure on next slide. Ecrit, the velocity saturates at a value vsat, that is, the

velocity ceases to increase with increasing electric field.

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

• SPICE Models for Short-Channel CMOS

Process

slope – The BSIM4 models for the 50 nm process is used in

this unit with VDD = 1 V.

– The model listing is found on page 154-157.

• For Short-Channel MOSFET Models, refer to

textbook, pages 154-158.

• BSIM4 is a fourth generation MOSFET model

developed at the University of California,

• The ratio of electron drift velocity to applied Berkeley. The acronym stands for Berkeley

electric field is the electron mobility, or Short-channel IGFET (insulated gate FET)

Model. (http://www-device.eecs.berkeley.edu)

v

µn =

E

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

The VDD=1 V and scale factor is 50 nm (50e-9)

VTHN and VTHP 280 mV 280 mV Typical describes the DC behavior depends on

tpx 14 Å 14 Å See Table 6.4 which level of model is used.

p.158 of textbook

• For level 1 MOSFET model, the

C’ox = εox/tox 25 fF/µm2 25 fF/µm2 Cox= C’oxWL(scale)2

expression for drain current ID, assuming

λn and λp 0.6 V–1 0.3 V–1 at L = 2 that the drain is at a higher potential than

Ion,n & Ion,p 600 µA/µm 300 µA/µm On current the source, is described by

Ioff,n & Ioff,p 7.1 nA/µm 10 nA/µm See Table 6.4

p.158 of textbook

Summary

ID = Family of iD Versus vDS Curves:

⎧0 where VGS < VTHN Enhancement-Mode nMOSFET

⎪

[

⎨ K n 2(VGS − VTHN )VDS − VDS

2

] VGS ≥ VTHN and VDS ≤ VGS − VTHN

⎪ K (V − V )2 [1 + λ (V − V

⎩ n GS THN DS DS , sat )] VGS > VTHN & VDS ≥ VDS , sat = VDS − VTHN

process parameters and device geometry

according to vDS (sat) is a

β 1 ⎛W ⎞ KPn ⎛ W ⎞ W function of vGS.

Kn = = µ nCox ⎜ ⎟= ⋅ ⎜ ⎟ where β = KPn ⋅

2 2 ⎝L ⎠ 2 ⎝L⎠ L

VTN ≡VTHN

VTHN = VTHN 0 + γ ⎛⎜ 2V fp + VSB − 2V fp ⎞⎟

⎝ ⎠

channel device is given by

KPn W Wµ nCox

ideal drain current is independent

Kn = ⋅ =

2 L 2L

of the drain-to-source voltage,

the incremental or small-signal where C’ox is the oxide capacitance per unit area. The parameter

resistance is infinite. µn is the mobility of the electrons in the inversion layer. The

channel width W and channel length L were shown as follow.

∆vDS

r0 = =∞

∆iD vGS =const.

The electrical parameter of KPn is the oxide capacitance and Example #2 – Calculate the current in

carrier mobility, which are essentially constants for a given an n-channel MOSFET

fabrication technology.

The geometry, which is the width-to-length W/L ratio, is a variable See page 128 Example 3.1 (Neamen)

in the design of MOSFET that is used to produce specific current- Solution Example #2

voltage characteristics in MOSFET circuits. First, consider the units involved in the equation,

You can rewrite the conduction parameter in the form as follows:

KPn W

Kn = ⋅ , KPn = µ nCox is called the process conduction ⎛ cm 2 ⎞ ⎛ F ⎞

2 L W (cm ) ⋅ un ⎜⎜ ⎟⎟ ⋅ ε ox ⎜ ⎟

⎝ V − s ⎠ ⎝ cm ⎠ F

paremeter.

Kn = =

KPn is constant for a given fabrication technology 2 L(cm ) ⋅ tox (cm ) V −s

and W/L is the transistor design variable.

=

(C V ) = A

V −s V2

The value of the conductance parameter is For VGS = 2VTHN,

therefore

I D = K n (VGS − VTHN )

2

Wunε ox W ⋅ KPn β

Kn = = = = (0.249)(1.5 − 0.75)

2

2 Ltox 2L 2

= 0.140 mA

=

(40 ×10 )(650)(3.9)(8.854 ×10 )

−4 −14

−4 −8

Comment:

mA The current capability of a transistor can be

= 0.249 increased by increasing the conduction parameter.

V2 For a given fabrication technology, Kn is adjusted

by varying the transistor width W.

p-Channel Enhancement-Mode

MOSFET

P-channel

enhancement-mode

MOSFET is the

complementary

device of the n-

channel

enhancement-mode

MOSFET.

Figure above shows how voltages, currents, and terminal

designations for a MOSFET are defined.

When the substrate is connected to ground and the well is

tied to VDD, the simplified model at the bottom is used.

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Enhancement-Mode MOSFET

Note that all voltages and currents are positive using the

naming convention seen in the figure.

The devices are complementary.

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Symbols for p-Channel n-Channel Depletion-Mode MOSFET

Enhancement-Mode MOSFET

In addition to the n-channel enhancement-mode device and the p-

channel enhancement-mode device, there is the n-channel

depletion mode MOSFET and p-channel depletion-mode

MOSFET as well.

Depletion-Mode nMOSFET Mode MOSFET

Symbols

Symbols

Finite Output Resistance

Non-ideal Current-Voltage

Characteristics For vGS>vDS(sat), the actual

point in the channel at which

Five non-ideal effects in the current-voltage the inversion charge goes to

characteristics of MOS transistors are examined. There zero moves away from the

effects are: drain terminal. The effective

Finite output resistance in the saturation region. channel length decreases,

Body effect. producing the phenomenon

called channel length

Sub-threshold conduction. modulation.

Breakdown effects. An exaggerated view of the

Temperature effects. current-voltage characteristics

is shown in figure on the next

slide.

The output resistance due to the channel When the two transistors are conducting,

length modulation is defined as there is a nonzero drain-to-source voltage on

−1 M1, which means that the source of M2 is not

⎛ ∂i ⎞ 1 at the same potential as the substrate.

ro = ⎜⎜ D ⎟⎟ =

⎝ ∂vDS ⎠ λK n (VGSQ − VTHN )2

vGS =VGSQ

1

ro ≅

λI DQ

Body Effect Body Effect

For the bias condition that the substrate, or The body effect can cause a degradation in

body, is connected to the source as assumed circuit performance because of the changing

previously, the threshold voltage is constant. threshold voltage.

This is not case for M2 in the circuit below. However, we will neglect the body effect in our

circuit analyses, for simplicity.

Zero or reverse-bias voltage exists across the source-

substrate pn junction here

A change in the

source-bias junction

voltage changes the

threshold voltage.

This is called body

effect. The same

situation exists in p-

channel devices.

Consider the ideal current- Drain current of

voltage relationship for the experimental results

n-channel MOSFET biased shown on the plot is not

in the saturation region, zero as assumed.

This current is called the

iD = K n (vGS − VTHN )

2

subthreshold current.

iD = K n (vGS − VTHN )

The effect may not be

significant for single

device, but integrated

√iD is a linear function vGS. circuit with thousands or

A plot of this ideal millions of devices may

relationship is shown on the contribute to significant

right. power dissipation.

Subthreshold Conduction Breakdown Effects

down if the applied drain voltage is too high and

When a MOSFET in a

avalanche multiplication occurs (same as

circuit is to be turned off,

reversed-biased pn junction breakdown).

the “proper” design of the

circuit must involve Punch-through occurs when the drain voltage is

biasing the device at least large enough for the depletion region around the

a few tenths of a volt drain to extend completely through the channel

below the threshold to the source terminal. This effect also causes

voltage to achieve “true” the drain current to increase rapidly with only a

cutoff. small increase in drain voltage.

If the electric field in the oxide becomes large

Another breakdown mechanism is near- enough, breakdown can also occur in the oxide,

avalanche or snapback breakdown. This which can lead to catastrophic failure. In silicon

breakdown process is due to second-order dioxide, the electric field at breakdown is on the

effects within the MOSFET. The source- order of 6×106 V/cm, which to a first

substrate-drain structure is equivalent to that of approximation, is given by εox = VG/tox.

a bipolar transistor. As the device size shrinks,

The input impedance at the gate is very high,

we may begin to see a parasitic bipolar

and a small amount of static charge

transistor action with increases in the drain

accumulating on the gate can cause the

voltage. This parasitic action enhances the

breakdown voltage to be exceeded. To prevent

breakdown effect.

the accumulation of static charge on the gate

capacitance of a MOSFET, a gate protection

device, such as a reverse-biased diode, is

usually included at the input of a MOS IC.

Temperature Effects

VTHN and KPn are functions of temperature. VTHN

decreases with temperature. For a given VGS, MOSFET DC CIRCUIT ANALYSIS

the drain current increases with temperature.

KPn is direct function of the inversion carrier

mobility, which decreases as the temperature

increases. Jacob R Baker

Since temperature dependence of mobility is Chapter 6

larger than that of the threshold voltage, the net CMOS

effect of increasing temperature is a decrease in

drain current at a given VGS.

This particular result provides a negative

feedback conditions in power MOSFET and

provides stability for a power MOSFET.

Examine the current-voltage plot below: Examine the current-voltage plot below:

1V

=1 V

I = V/R, slope=1/R

The controlled parameter is the device output ¾ The resistance can be calculated by taking the

current, that is why current is on the y-axis, reciprocal of the IV plot slope.

Voltage is on the x-axis in an IV plot. ¾ So, the voltage source in this figure has zero

The voltage across voltage source doesn’t vary resistance.

with changes in current running through it. ¾ The current source has infinite resistance.

The voltage across resistor is linearly related to ¾ The x-axis corresponds to plotting the IV

current flowing (Ohm’s law). characteristics of open circuit (no current with

changes in voltage).

¾ The y-axis corresponds to a short (no change

in the voltage across a wire [a short], with

changing current).

¾ Slope of resistor is 200 nA/1 V.

Example ¾ Resistor value = reciprocal of slope = 5 MΩ

¾ The combined IV curve is

See Example 9.1 of recommended text.

Clearly, in the triode region (also known as the

linear or ohmic region), the MOSFET behaves like

Example a resistor.

In the saturation region, the MOSFET behaves

like a current source in parallel with a resistor.

See Example 9.2 of recommended text.

The resistive component, whether in the triode or

saturation regions, is often called the MOSFET’s

output resistance.

ID is related to VGS and VDS using For long channel MOSFET, this can be written as

VDS,sat = VGS – VTHN

⋅ ⋅ (VGS − VTHN ) [1 + λ (VDS − VDS , sat )]

KPn W

ID =

2

This term is very important when doing analogue

2 L

for VDS > VDS , sat = VGS − VTHN and VGS > VTHN design. It is only valid for long-channel MOSFETs.

The voltage VDS,sat simply indicates, for long- or

L (9 ) short-channel MOSFETs, the VDS at the boundary

between triode and saturation.

VDS,sat is the voltage where the MOSFET moves

from the triode region to the saturation region. When VDS = VDS,sat, the drain current is labeled

ID,sat or

KPn W KP W

I D , sat =

2 2

2 L 2 L

So, eqn.(9) can be written

Constant current source

123

1 ro

In parallel with a resistance with the value

Plot the IV characteristics for the circuit seen in Fig. 9.2.

1

ro = Figure 9.3a on next slide shows the IV curves for each

λI D , sat component of the circuit where a single quadrant is used

for the IV plotting plane.

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The slope of the resistor is 200 nA/1 V. what the MOSFET looks like in the triode and saturation

The resistance value is the reciprocal of this slope (5 MEG). regions.

The combined IV curve is seen in Fig. 9.3b.

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A gate-drain connected MOSFET (Fig. 9.5) is seen often in

analogue design.

Comment: Because drain and gate terminals are shorted together,

In the triode region, the MOSFET behaves like a resistor. VGS=VDS.

In the saturation region, the MOSFET behaves like a current If VGS>VTHN, current is flowing through the device. Then for

source in parallel with a resistor as seen before in Fig. 9.3b. the MOSFET to operate in the saturation region,

The resistive component, whether in the triode or VDS VDS

saturation regions, is often called the MOSFET’s output 67 8 67 8

resistance. VD − VS ≥ VG − VS − VTHN or VD ≥ VG − VTHN

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PMOS Square-Law Equations

The coupling capacitor CC acts as an open circuit

to dc but it allows the signal voltage to be

Equivalent of Eqn.(9) for PMOS is coupled to the gate of the MOSFET.

KPp W

ID =

2

2 L

and VSD , sat = VSG − VTHP

L (10 )

¾ Swap the subscripts of the symbols used in

the NMOS equations, the terminal currents

and voltages of the MOSFET are always

positive (both NMOS and PMOS).

NMOS Common-Source Circuit NMOS Common-Source Circuit

The DC equivalent circuit is shown here in (a). The drain-to-source voltage is

The gate-source junction is a capacitor, so dc

gate current is zero.

VDS = VDD − I D RD

R2

VG = VDD

R2 + R2

The gate current is zero, so the gate circuit does

not dissipate power. Example #3 – DC circuit analysis

Power is dissipate at the drain-to-source channel

given by See Example 3.3 of Neamen, pp. 141-142.

Drain current in

PT = I DVDS saturation

region is

iD = K n (VGS − VTHN )

2

= (0.1)(2 − 1)

2

= 0.1 mA

Example #3 – DC circuit analysis Exercise #3.3

Drain-to-source voltage is Solve the exercise problem on p. 142 of the

textbook by Neamen.

VDS = VDD − I D RD = 5 − (0.1)(20 ) = 3 V

Power dissipated

Comment:

VDS=3 V>VDS(sat)

=VGS-VTHN=2-1=1 V,

the transistor is

indeed biased in

saturation region

and our analysis is

valid.

Example #4 - PMOS

Example #4 - PMOS From circuit (b)

⎛ R2 ⎞ ⎛ 50 ⎞

See Neamen p.143 Example 3.4 VG = ⎜⎜ ⎟⎟(VDD ) = ⎜ ⎟(5) = 2.5 V

⎝ 1

R + R2 ⎠ ⎝ 50 + 50 ⎠

Example #4 - PMOS Example #4 - PMOS

Assume that the PMOS is not biased in the Solving this quadratic equation for ID,

saturation region. So, drain current is

[

I D = (0.2) 2(2.5 − 0.8)(5 − I D (7.5)) − (5 − I D (7.5))

2

]

[

I D = K p 2(VSG + VTHP )VSD − V 2

SD ] = (0.2)[3.4(5 − I (7.5)) − (5 − I D (7.5))2 ]

D

Source-to-drain voltage is

= −1.6 + 9.9 I D − I D2 (11.25)

VSD = VDD − I D RD 0 = 11.25I D2 − 8.9 I D + 1.6

Combining these two equations, 8.9 ± 79.21 − 4 ×11.25 ×1.6

ID =

[

I D = K p 2(VSG + VTHP )(VDD − I D RD ) − (VDD − I D RD )

2

] 2 ×11.25

[ ]

11.585 6.215

=

= (0.2 ) 2(2.5 − 0.8)(5 − I D (7.5)) − (5 − I D (7.5))

2 or

22.5 22.5

= 0.515 mA or 0.2762 mA

Also, the source-to-drain voltage is

As Example #4 illustrated, we may not know

VSD = VDD − I D RD = 5 − 0.515 × 7.5 = 1.14 V initially whether a transistor is biased in the

saturation or non-saturation region. The approach

or involves making an educated guess and then

VSD = VDD − I D RD = 5 − 0.276 × 7.5 = 2.93 V verifying that assumption. If the assumption

proves incorrect, we must then change it and re-

Therefore, for the first result, VSD<VSD(sat), which analyse the circuit.

verifies that the transistor is biased in the non- In linear amplifier containing MOSFET, the

saturation region. transistor are biased in the saturation region.

The second solution yields VSD>VSD(sat). So, it is

not a valid solution since we assumed that the

transistor is biased in the non-saturation region.

Load Line and Modes of Operation: Load Line and Modes of Operation:

NMOS Common-Source Circuit NMOS Common-Source Circuit

The load line is given by ID =

5 VDS

− (mA )

20 20

VDS = VDD − I D RD = 5 − I D (20 )

or

ID =

VDD VDS

− =

5 VDS

− (mA )

RD RD 20 20

NMOSFET DC Analysis source

1. Assume the transistor is in saturation. See Neamen Design Example 3.9

a. VGS > VTN, ID > 0, & VDS ≥ VDS(sat)

2. Analyze circuit using saturation I-V relations.

3. Evaluate resulting bias condition of transistor.

a. If VGS < VTN, transistor is likely in cutoff

b. If VDS < VDS(sat), transistor is likely in

nonsaturation region

4. If initial assumption is proven incorrect, make

new assumption and repeat Steps 2 and 3.

Example #6 – Constant current source Example #6 – Constant current source

Step 1 – Assume the transistor is in saturation. Step 3 – Evaluate the resulting bias conditions of

VGS > VTN, ID > 0, & VDS ≥ VDS(sat) the transistor.

¾ If the assumed parameter values in step 1

In dc analysis, vi = 0, there is no gate current through are valid, then the initial assumption is

RG. correct.

¾ If VGS<VTHN, then the transistor is probably

Step 2 – Analyze the circuit using the saturation cutoff, and if VDS<VDS(sat), the transistor is

current-voltage relations. likely biased in the non-saturation region.

⋅ (VGS − VTHN )

KPn W

ID =

2

The voltage at the source terminal is

2 L VS=–VGS=–2.24 V.

⎛ 80 ⎞

250 = ⎜ ⎟ ⋅ (3)(VGS − 0.8) ⇒ VGS = 2.24 V

2

⎝ 2⎠

The drain current can also be written as Step 4 – If the initial assumption is proved

5 − VD incorrect, then a new assumption must be

ID = made and the circuit reanalyzed. Step 3 must

RD then be repeated.

For VD=2.5 V, we have

5 − 2. 5

RD = = 10 kΩ

0.25

The drain-to-source voltage is

Since VDS=4.74 V > VDS(sat) =VGS–VTHN =2.24–0.8

=1.44 V, the transistor is biased in the saturation

region, as initially assumed.

Enhancement Load Device

Enhancement Load Device

An enhancement-mode MOSFET can

be used as a nonlinear resistor.

A transistor with this connection is

called an enhancement load device.

Since the transistor is an

enhancement device, VTHN>0.

Also, vDS=vGS>vDS(sat)=vGS–VTHN,

which means that the transistor is

Kn = 1mA/V2 always biased in the saturation

region.

VTHN = 1V

characteristics can then be written as In saturation mode,

iD = KPn (vGS − VTHN ) = KPn (vDS − VTHN ) I D = KPn (VGS − VTHN ) L (1)

2 2 2

Dc drain-to-source voltage is

Combining (1) and (2),

2

KPn = 1mA/V2

VTHN = 1V

Example #7 enhancement load device Example #7 enhancement load device

is conducting, the gate-to-source

VGS = 5 − (0.05)(10 )(VGS − 0.8)

2

voltage must be greater than the

threshold voltage. We therefore have

Which can be written as the following solution:

0.5VGS2 + 0.2VGS − 4.68 = 0 VGS = VDS = 2.87 V and I D = 0.213 mA

The two possible solutions are Comment: This particular circuit is

obviously not an amplifier. However,

VGS = −3.27 V and VGS = +2.87 V the transistor connected in this

configuration is extremely useful as

an effective load resistor.

3.9 )(8.854 × 10 −12 )

device dimension of 1µ, tox=8 nm, µn=450

cm2/V·s and VTHN=0.8 V. Cox =

ε ox

=

ε rε 0

=

(

a) Find Cox and KPn. tox tox 8 × 10 −9

b) For a MOSFET with W/L=8 µm/ 0.8 µm, = 4.32 × 10 −3 F m 2 = 4.32 fF µm 2

calculate the values of VGS and VDS,sat needed

to operate the transistor in the saturation ( )

KPn = µ nCox = 450 × 108 µm 2 V ⋅ s × 4.32 × 10 −15 F µm 2 ( )

region with a dc cufrrent ID=100 µA. = 194 × 10 −6 (F V ⋅ s ) = 194 µA V 2( )

c) For the device in b), find the value of VGS

required to cause the device to operate as a b) For operation in saturation region,

1kΩ resistor for very small vDS.

KPn ⋅ W

iD = (VGS − VTHN )2

2L

Example #4.1 Smith/Sedra Microelectronics- solution Example #4.1 Smith/Sedra Microelectronics- solution

KPn ⋅ W

iD = (VGS − VTHN )2 vDS 1

2L rDS ≅ =

KPn ⋅ W

194 × 8

iD (VGS − VTHN )

(VGS − 0.7 )2

small v DS

100 = L

2 × 0.8

1

VGS − 0.7 = 0.32 V 1000 =

194 × 10 ×10 × (VGS − 0.7 )

−6

VGS − 0.7 = 0.52 V

c) For the triode region, VGS = 1.22 V

KPn ⋅ W

iD ≅ (VGS − VTHN )VDS

L

Notation according to IEEE recommendation is used as

illustrated in the figure below.

Small-signal models are used to calculate AC gains.

It is impossible for the AC signal to generate a voltage

across the DC source.

component so that the DC voltage source is an AC short.

We adjust DC gate-source voltage, VGS, to DC drain current

ID.

At this bias point, we apply small AC signal where

|vgs|<<VGS and |id|<<ID.

These are conditions for small-signal operation.

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Summary of performing a small-signal analysis

equations.

2. Using the DC values from (1) to calculate the small-signal

parameters. Small-signal AC parameters are always a

function of the DC operating point.

3. Replacing the active elements (e.g., MOSFETs) with their

small-signal models. At the same time, the DC sources are

removed, that is, short out all DC voltages sources and

open up all DC current sources.

As a result, the change in drain current id with gate voltage

vgs is essentially linear.

An AC analysis doesn’t include any DC voltages or currents.

If AC signal amplitudes get comparable to the DC operating

(or bias) points, we get high nonlinearity, which makes

feedback necessary for any highly linear amplifier. (Recall

your study on feedback theory in Analogue Electronics.)

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device’s transconductance, gm. The gm of a device is an AC

small-signal parameter that relates the AC gate voltage to W

β n = KPn ⋅ and v gs << VGS

the AC drain current, that is, L

id = gm·vgs

Then we can write

VDS ,sat

⎜ ⎟

DC operating values VGS and ID. g m ≅ β n ⋅ ⎜VGS − VTHN ⎟ = 2 β n I D

From Fig. 9.16, to find the slope (gm) of the iD-vGS curve at ⎜ ⎟

the fixed bias points VGS and ID, we take the derivative of ⎝ ⎠

this equation with respect to the x-axis variable (vGS) gm goes up as the root of the drain current and linearly

with VDS,sat.

I D = constant

⎡ δi ⎤

= KPn ⋅ ⋅ (v gs + VGS − VTHN )

W

gm = ⎢ D ⎥

⎣ δvGS ⎦VGS =constant L

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Example 9.5 Long-channel MOSFET parameters used in this unit. The VDD=5 V

Problem statement: and the scale factor is 1 µm (1e-6)

¾ Calculate the DC and AC voltages and currents for the

circuit seen in Fig. 9.17. Use the long-channel MOSFET

parameters from Ch. 6, (shown on next slide). Parameter NMOS PMOS Comments

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1. Calculating the bias point of the circuit using the DC Rearranging algebraically,

equations.

2

The gates of M1 and M2 are 2.5 V. This is necessary to ⎛ 64 748 ⎞

VDS ,sat

⎜⎜ VGS − V THN ⎟⎟ = ⋅

Sources of M1 and M2 are physically tied together, KPn W

VGS1=VGS2 and ID1=ID2=20 µA. ⎝ ⎠

The square-law equation gives 647

V

48

DS ,sat

2I D L

VGS − VTHN = ⋅

⋅ ⋅ (VGS − VTHN ) [1 + λ (VDS − VDS , sat )]

KPn W

ID = KPn W

2

2 L

2I D L

Neglecting channel-length modulation results in VGS = ⋅ + VTHN

KPn W

2

⎛ VDS ,sat ⎞

KPn W ⎜ 64748 ⎟ Assuming both M1 and M2 are operating in the

ID = ⋅ ⋅ VGS − VTHN ⎟

2 L ⎜⎜ ⎟ saturation region (we’ll verify this in a moment), we get

⎝ ⎠

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STEP #1 (cont’d) STEP #1 (cont’d)

¾ To see if M1 is in saturation, we use

40 2 ?

VGS1 = VGS 2 = ⋅ + 0.8 = 1.058 V → VDS , sat ≈ 250 mV VD1 ≥ VG1 − VTHN

120 20

¾ The drain current of M3 is 20 µA. The source-to-gate → 3.842 ≥ (2.5 − 0.8 = 1.7 ) V (yes, M1 is in saturation )

voltage for M3 is ¾ Next we look at M4. M4’s source-to-gate voltage is 5 V.

¾ For PMOS to operate in saturation region,

2 ⋅ 20 2

VGS 3 = ⋅ + 0.9 = 1.158 V → VSD , sat ≈ 250 mV

40 30 VS −VD S −VG

} V}

¾ The drain potential of M1 and M3 is VSD ≥ VSG − VTHP → VD ≤ VG + VTHP

VD1 = VD 3 = VDD − VSG 3 = 3.842 V 5−VD

} } 5− 0

64SD7

V

48

3 ,sat VSD ≥ VSG − 0.9 → VD ≤ 0 + 0.9 = 0.9 V

VSG 3 − VTHP = (5 − 3.842) − 0.9 = 1.158 − 0.9 = 0.258 V

¾ So for M4 to be in saturation, VD ≤ 0.9 V. Gate of M2 is

¾ We know that M3 is in saturation. 2.5 V and VGS2=1.058 V, then its source is 1.442 V,

which makes it impossible for M4 to be saturated.

?

STEP #1 (cont’d)

VD1 ≥ VG1 − VTHN

¾ To estimate the drain-to-source voltage of M4, we use

→ 3.842 ≥ (2.5 − 0.8 = 1.7 ) V (yes, M1 is in saturation )

⎛ 2

⎞

⋅ ⎜⎜ (VSG − VTHP )VSD −

W VSD

I D = KPP ⎟⎟

L ⎝ 2 ⎠

¾ ID=20 µA and its gate-source voltage is 5 V

30 ⎛ 2

⎞

20 = 40 ⋅ ⎜⎜ (5 − 0.9)VSD −

VSD

⎟

2 ⎝ 2 ⎟⎠

2

VSD − 246VSD + 2 = 0

VSD = 8.13 mV

at VDD. Clearly M2 is operating in the saturation region.

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STEP #1 (cont’d) STEP #1 (cont’d)

¾ M4 can be thought of as a resistor with a value of LTSpice

Simulation

1 1

Rch ≈ = Spice directive

W

⋅ (VGS − VTHN ) ⎛ µA ⎞ 30

KPn ⎜ 40 ⎟ ⋅ (5 − 0.9) .op

L ⎝ V ⎠ 2

= 407 Ω

¾ Alternatively, the resistance can be estimated from

VSD 8.13 mV

= = 407 Ω

ID 20 µA

SPICE simulation.

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LTSpice ¾ The transconductance of M1 and M2 is

Simulation

Spice directive W 10

.op

g m1 = g m 2 = 2 ⋅ KPn ⋅ I D = 2 ⋅120µ ⋅ ⋅ 20µ ≈ 150 µA V

L 2

¾ The transocnductance of M3 is

W 30

g m 3 = 2 ⋅ KPp ⋅ I D = 2 ⋅ 40µ ⋅ ⋅ 20µ ≈ 150 µA V

L 2

¾ M4 is operating in the triode region and so we think of

it as a resistor (407 Ω).

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STEP #3 – Replace the active elements (e.g., MOSFETs) ¾ Notice how we can replace M3 with a resistor of 1/gm3.

with their small-signal models. The DC sources are

removed. That is, short out all DC voltage sources and

¾ This is because the AC voltage across M3 is vsg3 =vsd3 and

open up all DC current sources). the AC current through it is id or

¾ Fig. 9.18 shows the simplified AC schematic of Fig. 9.17. 1 vsd vsg

= =

g m id id

through it is always in saturation, and can be thought of as

a small-signal resistance of 1/gm (remember this).

¾ There is a significant difference between hand calculation

and simulation results about the potential calculated for the

sources of M1/M2. We didn’t include the body effect in

our calculations.

¾ To describe carrier concentration in a

semiconductor, Fermi energy level is often

used. The Fermi energy level is useful when

determining the contact potentials in materials.

E.g., the potential applied across a diode before

it turns on. It is set by the p-type and n-type

material contact potential difference. Also, the

threshold voltage is determined, in part, by

contact potentials.

¾ The Fermi energy level simply indicates the

Figure above shows that for intrinsic silicon the (intrinsic) Fermi

energy level where the probability of

level, Ei is close to the middle of the bandgap. In p-type silicon, the

occupation by a free electron is 50%. Fermi level, Ef, moves towards the valence band, since the number

of free electrons, n, is reduced with the abundance of holes.

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

The energy difference between the Ei and Ef is given by, for a

p-type semiconductor by

N

Ei − E fp = kT ⋅ ln A

ni

And for an n-type semiconductor by

N

E fn − Ei = kT ⋅ ln D

ni

The band diagram of a pn junction (a diode) is seen in the

figure below.

towards Ec with the abundance of electrons in the conduction

band.

diode. A variation in Ef would indicate a non-equilibrium

situation (the diode has an external voltage applied across it).

To get current to flow in a diode, we must apply an external

potential that approaches the diode’s contact potential (its

built-in potential, Vbi).

By applying a potential to forward bias the diode, the

conduction energy level in each side of the diode move closer

to the same level.

The voltage applied to the diode when the conduction energy

levels are exactly at the same level is given by

E fn − E fp kT N N

Vbi = = ⋅ ln A 2 D

q q ni

Figures from CMOS Circuit Design, Layout, and Simulation, Copyright Wiley-IEEE, CMOSedu.com

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