## Are you sure?

This action might not be possible to undo. Are you sure you want to continue?

Binary logic consists of binary variables and logical operations. The variables are designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1 and 0. There ar e thr ee basic logic operations: AND, OR, and NOT. 2) Write the names of basic logical operators. 1. NOT / INVERT 2. AND 3. OR 3) What are basic properties of Boolean algebra? The basic properties of Boolean algebra are commutative property, associative property and distributive property. 4) State the associative property of boolean algebra. The associative property of Boolean algebra states that the OR ing of sever al variables results in the same regardless of the grouping of the variables. The associative property is stated as follows: A+ (B+C) = (A+B) +C 5) State the commutat ive property of Boolean algebra. The commutative property states that the order in which the variables are OR ed makes no difference. The commutative property is: A+B=B+A 6) State the dist ributive property of Boolean algebra. The distributive property states that AND ing several variables and OR ing the result with a single var iable is equivalent to OR ing the single variable with each of the several variables and then AND ing the sums. The distributive property is: A+BC= (A+B) (A+C) 7) State the absorption law of Boolean algebra. The absorption law of Boolean algebra is given by X+XY=X, X(X+Y) =X. 8) Simplify the f ollowing using De Morgan's theorem [((AB) 'C)'' D]' [(( AB)'C)'' D]' = ((AB)'C)'' + D' [(AB)' = A' + B'] = (AB)' C + D' = (A' + B‟) C + D' 9) State De Morgan's theorem. De Morgan suggested two theorems that form important part of Boolean algebra. They are,

Powered By www.technoscriptz.com

1) The complement of a product is equal to the sum of the complements. (AB)' = A' + B' 2) The complement of a sum term is equal to the product of the complements. (A + B)' = A'B' 10) Reduce A.A'C A.A'C = 0.C [A.A' = 1] =0 11) Reduce A ( A + B) A (A + B) = AA + AB = A (1 + B) [1 + B = 1] = A. 12) Reduce A'B'C' + A'BC' + A'BC A'B'C' + A'BC' + A'BC = A'C'(B' + B) + A'B'C = A'C' + A'BC [A + A' = 1] = A'(C' + BC) = A'(C' + B) [A + A'B = A + B] 13) Reduce AB + (AC)' + AB’C (AB + C) AB + (AC)' + AB‟C (AB + C) = AB + (AC)' + AAB'BC + AB'CC = AB + (AC) ' + AB'CC [A.A' = 0] = AB + (AC) ' + AB'C [A.A = 1] = AB + A' + C' =AB'C [(AB)' = A' + B'] = A' + B + C' + AB'C [A + AB' = A + B] = A' + B'C + B + C' [A + A'B = A + B] = A' + B + C' + B'C =A' + B + C' + B' =A' + C' + 1 = 1 [A + 1 =1] 14) Simplify the following expression Y = (A + B)(A + C' )(B' + C' Y = (A + B)(A + C' )( B' + C' ) = (AA' + AC +A'B +BC) (B' + C') [A.A' = 0] = (AC + A'B + BC) (B' + C‟) = AB'C + ACC' + A'BB' + A'BC' + BB'C + BCC' = AB'C + A'BC' )

15) Show that (X + Y' + XY) (X + Y') (X'Y) = 0 (X + Y' + XY)(X + Y')(X'Y) = (X + Y' + X) (X + Y‟) (X' + Y) [A + A'B = A + B] = (X + Y‟) (X + Y‟) (X'Y) [A + A = 1] = (X + Y‟) (X'Y) [A.A = 1] = X.X' + Y'.X'.Y = 0 [A.A' = 0]

Powered By www.technoscriptz.com

16) Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC ABC + ABC' + AB'C + A'BC=AB( C + C') + AB'C + A'BC =AB + AB'C + A'BC =A (B + B'C) + A'BC =A (B + C) + A'BC =AB + AC + A'BC =B (A + C) + AC =AB + BC + AC =AB + AC +BC ...Proved 17) Convert the given expression in canonical SOP form Y = AC + AB + BC Y = AC + AB + BC =AC (B + B‟) + AB (C + C‟) + (A + A') BC =ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC =ABC + ABC' +AB'C + AB'C' [A + A =1] 18) Define duality property. Duality property states that every algebraic expression deducible from the postulates of Boolean algebra remains valid if the operators and identity elements are interchanged. If the dual of an algebraic expression is desired, we simply interchange OR and AND operators and replace 1's by 0's and 0's by 1's. 19) Find t he complement of the functions F1 = x'yz' + x'y'z and F2 = x (y'z' + yz). By applying De-Morgan's theorem. F1' = (x'yz' + x'y'z)' = (x'yz') '(x'y'z)' = (x + y' + z)(x + y +z') F2' = [x(y'z' + yz)]' = x' + (y'z' + yz)' = x' + (y'z')'(yz)' = x' + (y + z)(y' + z') 20) Simplify the following expression Y = (A + B) (A = C) (B + C) = (A A + A C + A B + B C) (B + C) = (A C + A B + B C) (B + C) =ABC+ACC+ABB+ABC+BBC+BCC =ABC Unit – II 1. What are the classifications of sequential circuit s? The sequential circuits are classified on the basis of timing of their signals into two types. They ar e, 1) Synchronous sequential circuit. 2) Asynchronous sequential circuit. . 2. Define Flip flop The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.

Powered By www.technoscriptz.com

3. What are the different types of flip-flop? There are various types of flip flops. Some of them are mentioned below they ar e, RS flip-flop SR flip-flop D flip-flop JK flip-flop T flip-flop 4. What is t he operat ion of RS f lip- flop? When R input is low and S input is high the Q output of flip-flop is set. When R input is high and S input is low the Q output of flip-flop is reset. When both the inputs R and S are low the output does not change When both the inputs R and S are high the output is unpredictable. What is t he operat ion of SR f lip- flop? When R input is low and S input is high the Q output of flip-flop is set. When R input is high and S input is low the Q output of flip-flop is reset. When both the inputs R and S are low the output does not change. When both the inputs R and S are high the output is unpredictable. What is t he operat ion of D flip-flop? In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.

5.

6.

7. What is the operation of JK flip-flop? When K input is low and J input is high the Q output of flip-flop is set. When K input is high and J input is low the Q output of flip-flop is reset. When both the inputs K and J are low the output does not change When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge. 8. What is the operation of T flip-flop? T flip-flop is also known as Toggle flip- flop. When T=0 there is no change in the output. When T=1 the output switch to the complement state (ie) the output toggles.

Powered By www.technoscriptz.com

9. Define race around condition. In JK flip-flop output is fed back to the input. Therefor e change in the output results change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called „race around condition‟. 10. What is edge-triggered f lip- flop? The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock. 11. What is a master-slave flip-flop? A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave. 12. Define rise time. The time required to change the voltage level from 10% to 90% is known as rise time(tr). 13. Define fall time. The time required to change the voltage level from 90% to 10% is known as fall time (tf) . 14. Define propagation delay. A propagation delay is the time required to change the output after the application of the input. 15. Explain the f lip- flop excitation tables for RS FF. In RS flip-flop there are four possible transitions fr om the present state to the next state. They are, 00 transition: This can happen either when R=S=0 or when R=1 and S=0. 01 transition: This can happen only when S=1 and R=0. 10 transition: This can happen only when S=0 and R=1. 11 transition: This can happen either when S=1 and R=0 or S=0 and R=0. 16. Explain the f lip- flop excitation tables for JK flip-flop In JK flip-flop also there are four possible transitions from present state to next state. They are, 00 transition: This can happen when J=0 and K=1 or K=0. 01 transition: This can happen either when J=1 and K=0 or when J=K=1. 10 transition: This can happen either when J=0 and K=1 or when J=K=1. 11 transition: This can happen when K=0 and J=0 or J=1.

Powered By www.technoscriptz.com

17. Explain the f lip- flop excitation tables for D flip-f lop In D flip-flop the next state is always equal to the D input and it is independent of the present state. Therefore D must be 0 if Qn+1 have to 0, and if Qn+1 has to be 1 regardless the value of Qn. 18. Explain the f lip- flop excitation tables for T flip-flop When input T=1 the state of the flip- flop is complemented; when T=0,the state of the flip-flop remains unchanged. Therefore, for 0_0 and 1_1 transitions T must be 0 and for 0 1 and 1 0 transitions must be 1. 19. Define sequential circuit? In sequential circuits the output variables dependent not only on the present input variables but they also depend up on the past history of these input variables. 20. Give the comparison between combinational circuits and sequential circuits. Combinational circuits Sequential circuits Memory unit is not required Memory unity is required Parallel adder is a combinational circuit Serial adder is a sequential circuit Unit III 1. What are secondary variables? Present state variables in asynchronous sequential circuits 2. What are excitation variables? Next state variables in asynchronous sequential circuits 3. What is fundamental mode sequential circuit? -input variables changes if the circuit is stable -inputs are levels, not pulses -only one input can change at a given time 4. What is pulse mode circuit? -inputs are pulses -widths of pulses are long for circuit to respond to the input -pulse width must not be so long that it is still pr esent after the new state is reached 5. What is the significance of state assignment? In synchronous circuits-state assignments are made with the objective of circuit reduction In Asynchronous circuits-its objective is to avoid critical r aces

Powered By www.technoscriptz.com

6. When does race condit ion occur? Two or more binary state variables change their value in r esponse to the change in i/p variable 7. What is non critical race? -final stable state does not depend on the order in which the state variable changes -race condition is not har mful 8. What is critical race? -final stable state depends on the order in which the state variable changes -race condition is harmful 9. When does a cycle occur? Asynchronous circuit makes a transition through a series of unstable state 10. What are the different techniques used in state assignment? -shared row state assignment -One hot state assignment 11. What are the steps for the design of asynchronous sequential circuit? -construction of primitive flow table -reduction of flow table -state assignment is made -realization of primitive flow table 12. What is flow t able? State table of a synchr onous sequential network 13. What is primitive flow chart? One stable state per row 14. What is combinational circuit? Output depends on the given input. It has no storage element. 15. What is state equivalence theorem? Two states SA and SB are equivalent if and only if for every possible input X sequence, the outputs are the same and the next states are equivalent i.e., if SA ( t + 1) = SB (t + 1) and ZA = ZB then SA = SB. 16. What do you mean by distinguishing sequences?

Powered By www.technoscriptz.com

Two states, SA and SB of sequential machine ar e distinguishable if and only if their exists at least one finite input sequence. Which, when applied to sequential machine causes different output sequences depending on whether SA or SB is the initial state. 17. Prove t hat the equivalence partit ion is unique Consider that ther e are two equivalence partitions exist: PA and PB, and PA) PB. This states that, there exist 2 states Si & Sj which are in the same block of one partition and not in the same block of the other. If Si & Sj are in different blocks of say PB, there exists atleast on input sequence which distinguishes Si & Sj and therefore, they cannot be in the same block of PA. 18. Define merger graph. The merger graph is defined as follows. It contains the same number of vertices as the state table contains states. A line drawn between the two state vertices indicates each compatible state pair. It two states are incompatible no connecting line is drawn. 19. Explain the procedure for state minimization. a. Partition the states into subsets such that all states in the same subsets are 1 -equivalent. b. Partition the states into subsets such that all states in the same subsets are 2 -equivalent. c. Partition the states into subsets such that all states in the same subsets are 3 -equivalent. 20. Define closed covering A Set of compatibles is said to be closed if, for every compatible contained in the set, all its implied compatibles are also contained in the set. A closed set of compatibles, which contains all the states of M, is called a closed covering. Unit – IV 1. What is a Logic gate? Logic gates are the basic elements that make up a digital system. The electr onic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function. 2. Give the classification of logic families 1. Bipolar Unipolar 2. Saturated Non Saturated PMOS 3. NMOS 4. CMOS 5. RTL Schottky TTL 6. ECL DTL

Powered By www.technoscriptz.com

7. TTL 8. I I C 3. What are the basic digital logic gates? The three basic logic gates are AND gate OR gate NOT gate 4. Classify the logic family by operation? The Bipolar logic family is classified into Saturated logic, Unsaturated logic. The RTL, DTL, TTL, I2L, HTL logic comes under the saturated logic family. The Schottky TTL, and ECL logic comes under the unsaturated logic family. 5. State the classifications of FET devices. FET is classified as Junction Field Effect Transistor (JFET) Metal oxide semiconductor family (MOS). 6. Mention the classification of saturated bipolar logic families. The bipolar logic family is classified as follows: 1. RTL- Resistor Transistor Logic 2. DTL- Diode Transistor logic 3. I2L- Integrated Injection Logic 4. TTL- Transistor Transistor Logic 5. ECL- Emitter Coupled Logic 7. Mention the important characteristics of digital IC’s? 1. Fan out 2. Power dissipation 3. Propagation Delay 4. Noise Margin 5. Fan In 6. Operating temperature 7. Power supply requirements 8. Def ine Fan-out? Fan out specifies the number of standard loads that the output of the gate can drive with out impairment of its normal operation. 9. Def ine power dissipation? Power dissipation is measur e of power consumed by the gate when fully driven by all its inputs.

Powered By www.technoscriptz.com

10. What is propagation delay? Propagation delay is the average transition delay time for the signal to propagate from input to output when the signals change in value. It is expressed in ns. 11. Def ine noise margin? It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts. 12. Def ine fan in? Fan in is the number of inputs connected to the gate without any degradation in the voltage level. 13. What is Operating temperature? All the gates or semiconductor devices are temperatur e sensitive in nature. The temperature in which the performance of the IC is effective is called as operating temperature. Operating temper ature of the IC vary from 00 C to 700 c. 14. What is High Threshold Logic? Some digital circuits operate in environments, which produce very high noise signals. For operation in such surroundings there is available a type of DTL gate which possesses a high threshold to noise immunity. This type of gate is called HTL logic or High Threshold Logic. 15. What are the t ypes of TTL logic? 1. Open collector output 2. Totem-Pole Output 3. Tri-state output. 16. What is depletion mode operation MOS? If the channel is initially doped lightly with p-type impurity a conducting channel exists at zero gate voltage and the device is said to operate in depletion mode. 17. What is enhancement mode operation of MOS? If the region beneath the gate is left initially uncharged the gate field must induce a channel before current can flow. Thus the gate voltage enhances the channel current and such a device is said to operate in the enhancement mode. 18. Mention the characteristics of MOS transist or? The n- channel MOS conducts when its gate- to- source voltage is positive.

Powered By www.technoscriptz.com

The p- channel MOS conducts when its gate- to- source voltage is negative Either type of device is turned of if its gate- to- source voltage is zero. 19. How Schottky transistors are formed and state its use? A schottky diode is formed by the combination of metal and semiconductor. The pr esence of Schottky diode between the base and the collector prevents the transistor fr om going into satur ation. The resulting transistor is called as schottky transistor. The use of schottky transistor in TTL decr eases the pr opagation delay without a sacrifice of power dissipation. 20. List the different versions of TTL 1. TTL (Std.TTL) 2.LTTL (Low Power TTL) 3. HTTL (High Speed TTL) 4.STTL (Schottky TTL) 5. LSTTL (Low power Schottky TTL) UNIT V 1. List basic types of programmable logic devices. a. Read only memor y b. Progr ammable logic Array c. Progr ammable Array Logic 2. Define ROM A read only memory is a device that includes both the decoder and the OR gates within a single IC package. 3. Define address and word: In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word. 4. What are the types of ROM a. Masked ROM. b. Progr ammable Read only Memory c. Erasable Programmable Read only memory. d. Electrically Erasable Programmable Read only Memory. 5. What is programmable logic array? How it differs f rom ROM? In some cases the number of don‟t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM

Powered By www.technoscriptz.com

6. What is mask - programmable? With a mask programmable PLA, the user must submit a PLA program table to the manufacturer. 7. What is field programmable gate array? The second type of PLA is called a field programmable gate array. The EPLA can be progr ammed by the user by means of certain recommended procedures. 8. Give the comparison between prom and PLA. PROM PLA 1.And array is fixed and OR Both AND and OR arrays are array is pr ogrammable. Programmable. 2. Cheaper and simple to use. Costliest and complex than PROMS 9. Define PROM. PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates connected to a decoder and a programmable OR array. 10. Define PLA PLA is Programmable Logic Array (PLA). The PLA is a PLD that consists of a programmable AND array and a programmable OR array. 11. Define PAL PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array with output logic. 12. Why was PAL developed? It is a PLD that was developed to overcome cer tain disadvantages of PLA, such as longer delays due to additional fusible links that result from using two programmable arrays and more circuit complexity. 13. Why the input variables to a PAL are buffered The input variables to a PAL are buffered to prevent loading by the large number of AND gate inputs to which available or its complement can be connected. 14. What does PAL 10L8 specify? PAL - Programmable Logic Array 10 - Ten inputs L - Active LOW Output 8 - Eight Outputs 15. Why totem pole outputs cannot be connected together.

Powered By www.technoscriptz.com

Totem pole outputs cannot be connected together because such a connection might produce excessive current and may result in damage to the devices. 16. State advantages and disadvantages of TTL Adv: Easily compatible with other ICs Low output impedance Disadv: Wired output capability is possible only with tristate and open collector types Special circuits in Circuit layout and system design are requir ed. 17. When does t he noise margin allow digital circuit s to function properly? When noise voltages ar e within the limits of VNA(High State Noise Margin) and VNK for a particular logic family. 18. Define state table. For the design of sequential counters we have to relate present states and next states. The table, which represents the relationship between present states and next states, is called state table. 19. Define total state The combination of level signals that appear at the inputs and the outputs of the delays define what is called the total state of the circuit. 20. What are the steps for the design of asynchronous sequential circuit? 1. Construction of a primitive flow table from the problem statement. 2. Primitive flow table is reduced by eliminating redundant states using the state reduction 3. State assignment is made 4. The primitive flow table is r ealized using appropriate logic elements.

Powered By www.technoscriptz.com

Part – B Unit-I 1) Construct a Truth Table for the Boolean equation and Draw the logic gate diagram for t he Boolean equation using AND, OR, and NOT gates. Identif y an appropriate choice of IC chips which may be used to make this logic circuit.

Q=(A · · · C) (A+C) C+B

inputs A B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

A*C 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1

output B*C (A*C)+(B*C) A+C Q 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1

A B C AC AC+BC Q BC A+C

Powered By www.technoscriptz.com

2) i)Write out the Boolean equation and construct the truth t able for the logic gate diagram shown below. A B C Solution: Q

Q=(A B·+B) ·

C

inputs A B 0 0 0 0 1 1 1 1

Q= C N(A*B) 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 N(A*B)+B N( N(A*B)+B)*C

Therefore: Q=0 ii) Using Boolean rules t o show the reduction:

Q=(A B·+B) ·

C “ Rule 20”

Q=((A +B)+B) · C Q=(A +(B+B)) ·C Q=(A +1) · C Q=(1) · C = 0 · C

Q=0

Q=((A +B)+B) · C “Rule 12” Q=(A +(B+B)) · C “Rule 4” Q=(A +1) · C “Rule 2” Q = 0 · C “Rule 6”

Powered By www.technoscriptz.com

**3) What is the logical expression shown by the following gate circuits? a) A B
**

X = A· B+B C D · ·

C D

X

b)

A B C D

Y Y = +A · · ·C) (C D) D · (B

()

c)

A B Z

Z = ( A · B) · (C · D ) · (C + A · B ) ·( D ) C D

Can you simplify any of these three cir cuits?

X:

X is simplified

Y:

Y can be simplified to Y = 1

Z:

Z can be simplified to Z = A ·B ·D

Powered By www.technoscriptz.com

4) Explain all the Logic Gates Digital Electronics use symbols to repr esent the digital logic or circuitry which are used to perform these logical operations. These logic gates form the basic construction tools for digital electronics: AND Gate: OR Gate: Inverter (NOT gate):

A 0 0 1 1

B 0 1 0 1

A·B 0 0 0 0 0 1 1 1

0 1 0 1

A B A+B 0 0 1 1 1 0 1 1

A

A

Other commonly used types of logical operations and electrical logic gates include: NAND gate: the combination of an AND gate followed by a NOT. A 0 0 1 1 B 0 1 0 1 A· B 1 1 1 0

NOR gate: a combination of an OR gate followed by a NOT gate. A B A+B 0 0 1 0 1 0 1 0 0 1 1 0 Exclusive OR gate also called XOR: a pair of ANDs with one inverted input into an OR gate. or A× B AB A A 0 0 1 1 B 0 1 0 1 0 0 1 0 0 1 0 0 A· B 0 1 1 0 A· B A·· B B+A B

Powered By www.technoscriptz.com

Rule 20 of the Boolean logic (DeMorgan Theorem) are statements that show relationships between NAND and NOR gate structures. NOR NAND

(X+Y =X Y and ) ·

(X · =X+Y )Y

=

Examine the Truth Table for each form of the NOR: A 0 0 1 1 B 0 1 0 1

=

A+B 1 0 0 0 A 1 0 1 0 1 0 0 0 B A· B

A B 0 0 1 0 1 1 1 0 0 1 1 0 A similar r elationship is also true for the NAND gate. Examine the Truth Table for each form of the NOR:

=

A B 0 0 1 0 1 1 1 0 1 1 1 0 A NOR may be created by either -- inverting the output of an OR gate AND gate or -- inverting all inputs of an AND gate gate. 1 1 0 0 1 0 1 0 AB 1 1 1 0 A B A+B

A NAND may be created by either --inverting the output of an or - - inverting all inputs of an OR

=

=

Powered By www.technoscriptz.com

There are NAND and NOR (as well as AND and OR) gates which have 3 or more inputs. Multiple input NAND gate:

Q = · · B C A+B+C A=

A B C Q

or

A B C

Q

**Multiple input NOR gate:
**

Q = A+B+C A B C =··

A B C Q Q

or

A B C

NANDs and NORs have a unique and robust ability. If you could only have a single kind of gate, you'd probably want to have either all NANDs or all NORs. To understand why, determine the logical results of the circuits below. A A· A 0 1 1 0

A ?

A B ?

A B 0 0 1 1 0 1 0 1 1 1 1 0 0 0 0 1

A· B

A· · · B

AB

A ?

A B

A· A

B· B

A· · · B B A

0 0 1 1 0 B 0 1 1 0 1 1 0 0 1 1 1 1 0 0 1 What do the results of the above Truth Tables tell you about the NAND gate Any other kind of logic gate may be set up using only NAND in the right number and configuration. It is possible to make any other type of common logic gate or logic gate circuit out of all NANDs. In other words, you could construct the complete logic circuit of a computer out of only one type of gate if you wanted to. This is not the most efficient use of the gates, and this won't produce the most efficient use of semiconductor density or power usage, but it could be done.

Powered By www.technoscriptz.com

In the same way, the NOR could also be used to create all other logic gates and logic circuitry. In the space below, can you create a logic gate structur e using only NORs which can be used to replace an AND gate. A B 5) State the postulates and theorems of Boolean algebra. X+0=X X·1=X X + X' = 1 X · X' = 0 X+X=X X·X=X X+1=1 X·0=0 (X')' = X X+Y=Y+X XY = YX X + (Y + Z) = ( X + Y) + Z X (YZ) = (XY) Z X(Y + Z) = XY + XZ X + YX = (X + Y) (X + Z) (X + Y)' = X'Y' (XY) ' = X' + Y' X + XY = X X( X + Y) = X

Unit-II 6) Examine the digit al circuit below and work through the output states given the Q values shown. Inputs Output S R Q 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1

Q

Powered By www.technoscriptz.com

1 0 1 0 1 1 - This circuit is known as an SR FlipFlop. (S for Set and R for Reset) The output toggles when the input states undergo certain transitions from low to high.

Time

R

Q

S

Q

Since this device is intended to have complimentary output Q and Q , the state when S=R=1 is called an illegal or invalid state. It also considered unstable. SR Flip- Flops are not intended be used with this input state. There are two common versions of the SR Flip- Flop: Low to High activated SR Flip- Flop. A flip flop (shown in the figure above) made from two NORs. The output will latch when an appr opriate Low to High transition is sent to an input. High to Low activated Flip-Flop: If a SR Flip-Flop is built out of NAND gates instead of NOR gates. The flip flops output is latched when a High to Low transition occurs at an input state. While the circuit is cor rectly shown using the NAND gates, the preferred gate diagram is to use ORs with inverted inputs indicating that Low levels activate the flip-flop. Tr y to fill in the table below: R Q S R Q Q 1 0 1 0 1 1 - Q 0 1 0 1 S Time 1 1 - R Q 1 0 1 0 1 1 - 0 1 0 1 0 0 0 1 Q S When working with digital IC chips, these flip flops are shown using the following alter nate diagrams: High-Level activated Low-Level Activated Flip Flop Flip Flop

S R

Q

Q

Powered By www.technoscriptz.com

S Q R

Q

Timing Char t: Since Flip-Flops are sequential devices, truth tables are not enough. The state levels are sometimes shown by use of timing charts. It's easier to keep track of the states using timing charts especially for devices which are triggered by edge transitions.

Set Input

Reset Input Set Output Q

Reset Output Q time

7) Explain D-Flip-Flop: D Flip- Flops are implemented with a Clock input instead of an Enable. These ar e devices which latch the output when a transition occurs on the clock input. The most common version of the D Flip-Flop uses a clock transition from Low to High as the enabling transition. Some versions of this flip-flop commonly have Set and Clear inputs that are primarily used as a way to preset the output to a known starting state. The symbol used to indicate a clock or edge trigger is the . Set Q D Q 1 1 0 1

Clock

Inputs Outputs Set Clear Clock D Q 0 1 0 1 1 1 0 0 1 1 X X X X X X 01 1 01 0 1 0 1 1 0 0

Q

Clear

Use the D Flip-Flop truth table above to complete the following behavior table for the D Flip-Flop. Observe that the output Q changes to agree with D whenever the Clock input undergoes a L H transition. Changing D at other times does not affect the output, Q

Powered By www.technoscriptz.com

The Set and Clear pins are used to initialize the original state of output and enable the device. Without these pins, you would not know what the or iginal output state of the device was. Complete the timing chart for this set of clock transitions. Assume that Set and Clear are both high (1) and that the output state Q starts low (0). D-Flip Flop Timing Diagram D time Clock Q

Q

8) Explain the operation of counter A counter is used to r ecord the number of pulses or events. Depending upon the configuration of the gates, they can be wired to count up or down in binary or decimal, asynchronously or synchronously. Below is an example of an asynchronous circuit which counts upward through the octal values. Notice that this str ucture is using a slightly different D flip-flop than was used in the previous examples. It is triggered by a High Low tr ansition. How can you tell? This type of circuit is also called a ripple counter.

Outputs

b0

D Q Pulses to be counted Clk

1

b1

D Q Clk

1

b2

D Q Clk

1

Q

1

Q

1

Q

1

Octal value in binary = b2 b 1 b0

Powered By www.technoscriptz.com

clock

b0 b1 b2

b2 b1 b0 000 2

001 2 010

2

011

2

100

2

101

2

110 2 111 2 000 2

repeat

Process timer: Used in combination with a line decoder, a counting circuit like this could be used to implement a process stepper . As the D flip-flops counts down through a binary 4 count, the complement of the output is sent to EN the decoder which enables one and only one of the output lines (enabled Low). The truth table for the decoder is P0 P1 given on the table below. A1

A0 P2 P3

Q

1

**2 to 4 line decod er 74LS139 D Q
**

0

D

Q

1

Clock

Clk

Q

1

Clk

Q

0

4 down ripple counter using 74LS74

A 1 0 0 1 1

A 0 0 0 1 1 0 1 1 1

P 0 1 0 1 1

P 1 1 1 1 1 0 1 1 0

P 2

P 3

9) Explain the Debouncing circuit: Real switches often do not make a nice clean tr ansition from one state to another. The signal given off by a simple contact switch from one line to another might give behavior similar to that shown by the diagram below. Vcc Vcc

A

B

Powered By www.technoscriptz.com

Line A

Line B

Switch in po sition A

Bounce as switch is opened at A

No contact during switch transition

Bounce as switch is closed at B

Switch in position B

Since there are many cases where the switch bounce will be recorded as a number of individual pulses or transitions, there is a need to debounce the signal that occurs during switching. Use of flip-flops is one simple way to accomplish a nice clean signal change. Any of the following digital flip flops will debounce a contact switch.

Output Output

Set D Q

Output

Q

Clk

Clear

10) Example of the octal ripple count ers using the JK flip-flop: This performs an upward asynchrous 8 count. A counter is used to record the number of pulses or events. Depending upon the configuration of the gates, they can be wired to count up or down in binary or decimal, asynchronously or synchr onously. Below is an example of an asynchronous circuit which counts upward through the octal values. Notice that this structur e is using a slightly different D flip-flop than was used in the previous examples. It is triggered by a High Low transition. How can you tell? This type of circuit is also called a ripple counter.

Powered By www.technoscriptz.com

The logic of the JK flip-flop can be summarized by the table below: Set Inputs Outputs Set Clear J K Clock Q 0 1 0 1 1 1 1 1 0 0 1 1 1 1 X X X 0 0 1 1 X X X 0 1 0 1 X X X 10 10 10 10 1 0 0 1 Illegal Latched 0 H 1 0 Toggle

Outputs

Q

J Q

Clock

Q K Clear

**all J=K=1 J Q Pulses to be counted Clk
**

1

J Q Clk

1

J Q Clk

1

Q

K

1

Q

K

1

Q1

K

Clear

Unit -III 11) J-K Flip-Flop. A JK flip-flop is similar to the SR Flip- Flop with one exception; If two High inputs occur simultaneously, the JK Flip- Flop output will toggle (reverse their output states)when the clock performs a high-to-low transition.. This eliminates the undefined output state (H-H) found in the SR flip-flop. The logic of the JK flip-flop can be summarized by the table below: Set Inputs Outputs Set Clear J K Clock Q 0 1 0 1 1 1 1 1 0 0 1 1 1 1 X X X 0 0 1 1 X X X 0 1 0 1 X X X 10 10 10 10 1 0 0 1 Illegal Latched 0 H 1 0 Toggle Q J Q

Clock

Q K Clear

Powered By www.technoscriptz.com

Use the JK flip-flop truth table shown above or the demo in the logicdemo.m program to understand its behavior. (let 1 = High and 0 = Low) Inputs Outputs Clear Set J K Clock Q H H H H H H H L L L L H H H H H H H H H H H H H H H H H H H L L L L H H H H H L L L H L H H L L L L H L L H H H H L L-H-L L H L L H L L L H L L L L H H H H H L-H-L

Q Respond to J&K

Time

Held in Clear Held in Set (or Preset)

Toggle

12)

Explain Digital IC chips:

Up until now, we've been talking about these logic gates as useful but vague logical or graphical abstractions. Each of the logic gates discussed is available as an easy to use integrated circuit (such as in the DIP (Dual Inline Package) chip shown to the right). There are two common families of chip TTL --transistor-transistor logic and CMOS – complimentary metal oxide semiconductor Some of the commonly available TTL chips include: 7400 Quad 2-Input NAND Gate 7402 Quad 2-Input NOR Gate 7404 Hex Inverter (NOT Gate)

Powered By www.technoscriptz.com

7408 7410 7411 7420 7421 7427 7430 7432 7442 7446 7454 7473 7474 7486 7489 7490 7491 7493 74138

Quad 2-Input AND Gate Triple 3-Input NAND Gate Triple 3-Input AND Gate Dual 4-Input NAND Gate Dual 4-Input AND Gate Triple 3-Input NOR Gate 8-Input NAND Gate Quad 2-Input OR Gate BCD to Decimal 4 to 10 Line Decoder BCD to 7 Segment Decoder/Driver 4-wide AND-OR- Invert Gate Dual J-K Flip-Flops with Clear Dual D Flip-Flop with Clear and Preset Quad 2-Input XOR Gate 64 bit Read/Write Memories Decade Counters 8-bit Shift Registers 4-bit Binary Counters 3 to 8 Line Decoder/Multiplexer

13) Explain PLD Programmable logic device A programmable logic device or PLD is an electronic component used to build reconfigurable digital circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time of manufacture. Before the PLD can be used in a circuit it must be programmed, that is, reconfigured. Using a ROM as a PLD Before PLDs were invented, read-only memory (ROM) chips were used to create ar bitrary combinational logic functions of a number of inputs. Consider a ROM with m inputs (the address lines) and n outputs (the data lines). When used as a memory, the ROM contains 2

m

words of n bits each. Now

imagine that the inputs are driven not by an m-bit addr ess, but by m independent logic signals. Theoretically, ther e are 2

m

**possible Boolean functions of these m
**

n

signals, but the structure of the ROM allows just 2

of these functions to be

Powered By www.technoscriptz.com

produced at the output pins. The ROM therefore becomes equivalent to n separate logic circuits, each of which generates a chosen function of the m inputs. The advantage of using a ROM in this way is that any conceivable function of the m inputs can be made to appear at any of the n outputs, making this the most general-purpose combinatorial logic device available. Also, PROMs (programmable ROMs), EPROMs (ultr aviolet-erasable PROMs) and EPROM‟s (electrically erasable PROMs) are available that can be programmed using a standard PROM programmer without r equiring specialized har dware or software. However, there ar e several disadvantages:

• •

they are usually much slower than dedicated logic circuits, they cannot necessarily provide safe "covers" for asynchronous logic transitions so the PROM's outputs may glitch as the inputs switch,

•

they consume more power,

They are often more expensive than programmable logic, especially if high speed FPGAs use a grid of logic gates, similar to that of an ordinar y gate array, but the programming is done by the customer, not by the manufacturer. The term "fieldprogrammable" means the array is done outside the factory, or "in the field." FPGAs are usually progr ammed after being soldered down to the circuit board, in a manner similar to that of lar ger CPLDs. In larger FPGAs the configuration is volatile, and must be re-loaded into the device whenever power is applied or different functionality is required. The main difference between FPGAs and CPLDs is that FPGAs have a volatile memory, thus it requires to be pr ogrammed after power up. CPLDs do not. Also, FPGAs usually consume more power than CPLDs due to their SRAM nature. Finally, CPLDs do not have as many registers or memory storage as FPGAs. In gener al CPLDs are a good choice for wide combinatorial logic applications while FPGAs are more suitable for large state machines (i.e. microprocessors).

Powered By www.technoscriptz.com

Other variants PLDs are being sold now that contain a microprocessor with a fixed function (the so-called core) surrounded by programmable logic These devices let designers concentrate on adding new features to designs without having to worry about making the microprocessor work. How PLDs retain their configuration A PLD is a combination of a logic device and a memory device. The memory is used to store the pattern that was given to the chip during programming. Most of the methods for storing data in an integrated circuit have been adapted for use in PLDs. SRAM, or static RAM, is a volatile type of memory, meaning that its contents are lost each time the power is switched off. SRAM-based PLDs therefore have to be programmed every time the circuit is switched on. This is usually done automatically by another part of the circuit. Flash memory is non-volatile, retaining its contents even when the power is switched off. It can be erased and reprogrammed as required. This makes it useful for PLD memory. As of 2005, most CPLDs are electrically programmable and er asable, and nonvolatile. This is because they ar e too small to justify the inconvenience of programming internal SRAM cells every time they start up, and EPROM cells are more expensive due to their ceramic package with a quartz window.

14) Explain EPROM realizat ion. An EPROM, or erasable programmable read only memory, is a type of memory chip that retains its data when its power supply is switched off. In other words, it is non-volatile. It is an array of floating-gate tr ansistor s individually

Powered By www.technoscriptz.com

programmed by an electronic device that supplies higher voltages than those nor mally used in digital circuits. Once programmed, an EPROM can be erased only by exposing it to strong ultraviolet light. That UV light usually has a wavelength of 253.7nm (for optimum er asure time) and belongs to the UVC range of UV light. EPROM‟s are easily recognizable by the transparent fused quartz window in the top of the package, through which the silicon chip is visible, and which permits exposure to UV light during erasing. Operation Development of the EPROM memory cell started with investigation of faulty integrated circuits where the gate connections of transistors had broken. Stored char ge on these isolated gates changed their properties. The EPROM was invented by Israeli engineer Dov Frohman of Intel in 1971 EPROM sizes and types EPROM‟s come in several sizes both in physical packaging as well and storage capacity. While par ts of the same type number fr om different manufacturers are compatible as long as they'r e only being r ead, there are subtle differences in the programming process. Most EPROMS could be identified by the programmer through "signature mode" by forcing 12V on pin A9 and reading out two bytes of data. However, as this was not universal, programmer software also would allow manual setting of the manufacturer and device type of the chip to ensur e proper programming. 15) Compare the digital logic families characteristics There are a number of commonly- available electronic logic families, as summarized in (NIM logic is a special case included for completeness. It will be considered mor e fully in the section on particle counting.) As you can see, the types differ in their elementary function and in whether they respond to current or voltage signals. Fan-out refer s to the ability of an

Powered By www.technoscriptz.com

output to drive more than one subsequent input, but this is not usually a problem. Fr om a design perspective, the speed of operation is often a deciding factor, along with cost and the ability to construct very complex single-chip circuits (Very Lar ge Scale Integration). You should also be aware that there ar e many ready-made functions available in each of the commercial logic families. These typically include multiinput gates, flip-flops, and adder circuits

Summary of Gate Characteristics Gate Type Charac TTL ECL CMOS NIM(neg) NIM(pos) Basic func. NAND OR,NOR NOR - Connection Current Voltage Voltage Current Voltage Logic 1 0 0.0 ® 0.8V 2.5 ® 5.0V -0.9V -1.8V 0 ® 2V 7 ® 10V +1 ® -2mA 4 ® 12mA 1.5 ® -2V 3 ® 12V

Fan-out 10 25 10-20 1 1-2 Gate delay 15ns 3ns 70ns 10ns 500ns Advantages Standard Cheap Noise immunity Disadv Can‟t drive cable Fast Low power Very cheap VLSI Modules Flexible Z=50W Modules Flexible

Noise immunity

Slow Staticsensitive

Costly Bulky Fan-out

Costly Bulky

and even complete CPUs. Ther e are also compatible interface circuits, such as display drivers, transmission line drivers, analog to digital converters and so on. For reasons of simplicity and reliability, you should make use of specialized units whenever possible. It is highly unlikely that you will ever need to build a logic function out of discrete tr ansistor s, resistors etc., so for the present we will treat the circuits as black boxes. If you do a lot of digital design you should gain at

Powered By www.technoscriptz.com

least a rough idea of how the functions are carried out bythe internal circuitr y, since that will help you use the building blocks more effectively. Unit-IV 16) With apt diagrams explain PAL and PLA. The term Programmable Arr ay Logic (PAL) is used to describe a family of programmable logic device semiconductors used to implement logic functions in digital circuits introduced by Monolithic Memories, Inc. PAL devices consisted of a small PROM (programmable read-only memory) core and additional output logic used to implement particular desired logic functions with few components.Using specialized machines, PAL devices were "field-pr ogrammable". Each PAL device was "one-time programmable" (OTP), meaning that it could not be updated and reused after its initial programming. (MMI also offered a similar family called HAL, or "hard array logic", which were like PAL devices except that they were mask- programmed at the factory.) The original 20 and 24-pin PALs were described by MMI as medium-scale integration (MSI) devices. PAL architecture

Powered By www.technoscriptz.com

The programmable elements (shown as a fuse) connect both the true and complemented inputs to the AND gates. These AND gates, also known as product terms, are ORed together to form a sum-of-products logic array. The PAL architecture consists of two main components: a logic plane and output logic macro cells. Progr ammable logic plane The programmable logic plane is a programmable read-only memory (PROM) array that allows the signals present on the devices pins (or the logical complements of those signals) to be routed to an output logic macrocell. PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-AND" plane used to implement "sum-of-products" binary logic equations for each of the outputs in terms of the inputs and either synchronous or asynchronous feedback fr om the outputs. Output logic The early 20-pin PALs had 10 inputs and 8 outputs. The outputs were active low and could be registered or combinational. Members of the PAL family were available with various output str uctures called "output logic macro cells" or OLMCs. Prior to the introduction of the "V" (for "variable") series, the types of OLMCs available in each PAL were fixed at the time of manufactur e. (The PAL16L8 had 8 combinational outputs and the PAL16R8 had 8 registered outputs. The PAL16R6 had 6 registered and 2 combinational while the PAL16R4 had 4 of each.) Each output could have up to 8 product terms (effectively AND gates), however the combinational outputs used one of the terms to control a bidirectional output buffer. There were other combinations that had fewer outputs with more product term per output and were available with active high outputs. The 16X8 family or registered devices had an XOR gate before the register.

Powered By www.technoscriptz.com

This fixed output structur e often frustrated designers attempting to optimize the utility of PAL devices because output structures of different types were often required by their applications Though some engineers pr ogrammed PAL devices by manually editing files containing the binary fuse pattern data, most opted to design their logic using a har dware description language (HDL) 17) Design a simple microprocessor:

Many times the most practical method to solve a system design problem is to use a standard microprocessor. Ther e are many single chip micr oprocessors with built in RAM and EPROM / EPROM available. The PIC family of processor fr om microchip offers a wide r ange of clock speeds, memory sizes, and analog I/O capability (ADCS) Microprocessors provide great flexibility because Systems can be upgraded in the field through software patches. Do not under estimate the cost of softwar e development for microprocessor based systems. Programmable Logic: A variety of programmable chips are available that can be more efficient than general purpose microprocessors. 1. Chips with programmable logic arrays 2. Chips with programmable inter connect 3. Chips with reprogrammable logic and interconnect. The System designer s should be familiar with these options for reasons. • First it allows the designer to completely assess a particular system requirement for an IC and r ecommend a solution given the system complexity, speed of operation etc. • Second it is familiarizes the IC designer with methods of mailing any chip reprogrammable at the hardware level and hence both more useful and of under spread use.

Powered By www.technoscriptz.com

Progr ammable Logic Devices: A PLA consists of an AND plane and an OR plane to compute any function expressed as a sum of products. Each transistor in the AND and OR array plane must be capable of being Progr ammed to be pr esent or not. This can be achieved by truly populating the AND and OR plane with a NOR structure at each PLA location. Each node is programmed with a floating gate transistor and a fusible link. 18) Explain the commonly available TTL sequential logic digit al IC chips 7475 Quad Latch :

7474 Dual D Flip-Flop With Preset and Clear:

7473 Dual Master Slave J- K Flip-Flop with Clear

7476 Dual Master-Slave J-K Flip-Flop with Clear and Preset

19) Explain the VHDL description of combinational networks with example The Synopsys tools to synthesize combinational logic circuits inot standard-cell circuit designs using Verilog as an input language.

Powered By www.technoscriptz.com

1. Background Logic synthesis tools allow designers to compile high-level descriptions of a circuit into standard-cell implementations that can be converted into chip layouts using placement and routing tools. 2. Describing Combinational Logic using Verilog HDL As discussed in class, the basic construct used to describe hardware in Verilog is the module. Modules describe the interface of a circuit element - its inputs and outputs, and either the structure or function or of the module. Structure is described using module instantiation - the creation of submodules which are connected together to implement a desired function. Function can be described using either assign statements or always blocks. The assign statement is preferr red for specifying simple logic, while the always block is needed for more complex functions. In this experiement, we will use an always block to describe the function of a binary decoder. The general structur e of a module description with an always block is shown below: module myLogic(i1, i2, ..., o1, o2, ...); input i1, i2, ...; output o1, o2, ...; reg o1, o2

always @(i1, i2, ...) begin ... statements that operate on i1, i2, ... o1 = ...; ... o2 = ...; ... o3 = ...; end endmodule

Powered By www.technoscriptz.com

Here the combination of the always and @() operators specify a block of logic that activates during simulation when one of the inputs i1, i2, ... changes. When simulating, the model waits for an input to change, then executes the code in the "begin ... end" block, change any outputs for which there are assignment operators, and then loops back to the @() operator to wait for another input change. when synthesizing combinational logic, keep in mind that your Verilogger input is a specifiction of a set of outputs that are combinational functions of its inputs. This is a key differ ence from a software pr ogram written in a language like C. Progr amming constructs like for loops can be used to make this description more concise, but they do not imply any sequential or procedural behavior. Instead, the Design Compiler expands or "unrolls" loop constructs to form a combinational logic function. The one exception to this rule is when an ouput is not specified for all possible values of the inputs. For example, this can occur when an if-then statement that assigns a value to an uninitialized variable without a corresponding assignment in the else statement. In this case, the Design Compiler will insert a latch to hold the previous value, since the previous value must be preserved if a new value is not specified. The design compiler works in two steps. In the first step, it translates the Verilog into hardware that implements the logic functions in a straightforward way without regard to cost. In the second step, it optimizes this logic and maps it cells in the MSU SCMOS standard cell library that we are using in our design projects. A major part of the Design Compiler's capabilities are directed toward optimizing logic under timing constraints. It contains a built-in timing analyzer that finds the longest paths in the synthesized logic network and compares their delay against timing constraints specified by the user. If the constraints are not met, it attempts to modify the design and notifies the user about whether or not the constraints were successfully met. Although this part of the Design Compiler is heavily used in "industrial strength" designs, we will not use it in this lab. 3. Prelab A skeleton of a 2-4 binary decoder is shown below. Complete this description by adding appropriate entries to the case statement. Write these entries down on a piece of paper and br ing these to lab with you. module dec2_4(d_in, d_out); input [1:0] d_in; output [3:0] d_out; reg [3:0] d_out; always @(d_in) begin case (d_in) 2'b00 : d_out = 4'b0001;

Powered By www.technoscriptz.com

/* add additonal cases here */ ... default : d_out = 4'bxxxx; endcase

end endmodule 20) Explain Full adder and write the program in structural Description ( Behavioral modeling ) Full adder is used for adding more than two numbers. It contains 3 inputs and one sum and one carry part. Progr am for Full adder Module FA(a, b, c) Input a; Input b; Input c; Output sum; Output carry; Wire s1, c1,c2, c3; Xor X1 (s1, a, b); X2 ( sum, s1, c); And a1 (c1, a, b); a2 (c2, a, c); a3 (c3, b, c); or b1 (carry , c1, c2, c3) ; end module Unit -V 21) Explain the compilat ion and simulation of VHDL code 1. Compilation Process: Compilation is a process that translates the design that are described by various methods of data entry to an inter mediate for mat.

Powered By www.technoscriptz.com

The Different Stages of Compiler are 1. Analysis 2. Generic hardware Generation 3. Logic Optimization 4. Binding Analysis The Syntax for the VHDL code is checked after that the design is converted in to uniform representation means that implementation of the design depends on how we configure the macro cells using mux array. Generic Hardware Generation: This will generate the hardware for the uniform representation of the design given by the analysis block. Binding: Binding means conversion of circuit according to the target device. Routing And Placement: The routing and placement of FPLD cells Timing Analysis: This will help us to decide the clocking speed of the circuit. SIMULATION This simulation software verifies the functionality of the design. Two kinds of simulation 1. Pre Simulation 2. Post Simulation 1. Pre Synthsis Simulation: By giving test data to the simulation. The simulation part doesnot include the delays introduced by the gates and wires. 2. Post Synthsis Simulation: The compilation part with delay is given to the post simulation. This method is based on the net list file and timing file , the simulation will generate output waveform 22) Explain VHDL operators 1. 2. 3. 4. Arithmetic Oper ator Logical Operator Bitwise Operator Conditional Operator

Powered By www.technoscriptz.com

5. 6. 7. 8.

Relational Oper ator Equality Operator Reduction Operator Shift Operator

1. Arithmetic Operator : + ( Unary & Binary Operator) -( Uanry minus) * Mulitiply / Divide % modulo 2. Logical Operator: && (Logical and) || (Logical or) ! (Logical Not 3. Bitwise Operator: | (binary or) & (Binary and) 4. Conditional Operator: Synatax: Con – exp?exp1:exp2 5. Relational Oper ator: > (greater than) < (less than) >= (greater than or equal to) <= (less than or equal to) 6. Equality Operator: = =(logical Equality) = = = (case Equality) = (Logical in equaloity) 7. Reduction Operator: & (reduction AND) | (reduction OR)

Powered By www.technoscriptz.com

8. Shift Operator: << (left shift) >> (right shift) 23) Design a Binary Mult iplier A multiplier for unsigned binary numbers. When we form the product A X B the first operand (A) is called the multiplicand and the second operand ( B) is called the multiplier. Example 13 x 11 in binary 1101 (13) 1011 (11) we can get 143. Operation: 1.A multiplication two 4 bit binary numbers required a 4 bit mulitiplicand register, a 4 bit multiplier register pr oduct, 2.If the multiplicand were shifted left each time before it was added to the accumulator. 3.The 4 bit from the accumulator and 4 bit fr om the multiplicand register re connected to the accumulator . 4.The sum 4 bit and the carry output from the adder are connected back to the accumulator. 5.An extra bit at the left end of the product register temporarily stores any carry that is generated when the multiplicand is added to the accumulator. 6.The control cicuit puts out the proper sequence of add and shift signal after a start signal(st=1)has been received. BEHAVIORAL Model For 4 x 4 binary multiplier Library BITLIB; Use BITLIB, bit_pack_all Enitity mult 4 x 4 is Port(clk,st: inbit;mplier,mcand:inbit_vector ,Done: outbit); End mult 4 x 4; Architectural behavioral of 4 x 4 is Signal state: integer r ange 0 to 9; Signal acc bitvector (8 down to 0): Alias: bit is acc( 0); Begin Process Begin Wait until clk=‟ 1‟; Case state is When 0 => If state „1‟ then

Powered By www.technoscriptz.com

Acc(8 down to 4) <=”0000” Acc(3 downto 0) <= mplier; State <=1; End if When 1/3/5/7=> If m=1 then Acc (8 downto 4) State <=state+1; Else Acc <+ „0‟ & acc(8 downto 0); State<=state+2; End if When 2/4/6/8=> Acc,=‟0‟ 4 acc(8 downto 1); state =state+1; end case end processdone <=‟1‟ when state =9 else 0; end behavioral Model FLIPFLOP using VHDL process Progr am for D flip-flop (Positive Edge Trigger ing) Module DFF(q.qbar, d, clk); Input d,clk; Output q.qbar; Reg q.qbar ; Always @ (pos edge clk) Begin Q=d; Qbar= ~d; End end module Progr am for D-Flip-flop (Negative Edge Triggering) Module dff(q.qbar, d, clk); Input d,clk; Output q.qbar; Reg q.qbar ; Always @(neg edge clk) Begin Q=d; Qbar= ~d; End End module

Powered By www.technoscriptz.com

24)

Explain Behavioral Description using example

This is the third style of modeling in verilog HDL. RTL modeling concentrates on specifying the movement at data among hardware sections. RTL specification is viewed as being the link between purely abstract modeling and har dware design. Procedural Costraint: 1. Intial Statement 2. Always Statement 1. Intial Statement: Syntax: Initial[timing control]procedural statement Eg: Reg count . . . . initial count=2; 2. Always Statement: Syntax: Always [timing contr ol]procedur al statement eg: always clock = ~ clock; Timing Controls: 1. delay control 2. event contr ol 1.Delay control:

Powered By www.technoscriptz.com

syntax: # delay procedur al statement; eg # 3 count= 2; 3. Event Control; 1.Edge triggering control 2.Level Triggering control 1. Edgetriggering event control Syntax: Event procedural statement; 2. Block Statement: Sequential Block: Syntax: Begin [: block id{declaration}] procedur al statements end; Parallel Block Syntax: Fork [: block id{declaration}] procedural statements join; 4. Procedure Statement It is an assignment statement with in the initial statement or an always statement. Only register data types areassigned in this type Eg: Reg[1:2] temp, a, b;

Powered By www.technoscriptz.com

. . . . . #2 temp = a & b; 5. IF statement Syntax: If(condition) Procedural statement; Else(condition) Procedural statement; End; 6. Case statement: Syntax: Case(expression)_ Procedural statement; End case; Eg: Case(operation) Add : z=a+b; Sub :z= a-b; Mul : z=a*b; End case

25) Explain about adder: Entity Declaration The entity declaration defines the NAME of the entity and lists the input and output ports. The general form is as follows, entity NAME_OF_ENTITY is [ generic generic_declarations);] port (signal_names: mode type; signal_names: mode type; : signal_names: mode type);

Powered By www.technoscriptz.com

end [NAME_OF_ENTITY] ; Structural modeling of design lends itself to hierarchical design, in which one can define components of units that are used over and over again. Once these components are defined they can be used as blocks, cells or macros in a higher level entity. This can significantly reduce the complexity of large designs. Hierarchical design approaches are always prefer red over flat designs. We will illustrate the use of a hierarchical design approach for a 4-bit adder, shown in Figure 4 below. Each full adder can be described by the Boolean expressions for the sum and carry out signals, sum = (A carry = AB + C(A B) C B)

In the VHDL file, we have defined a component for the full adder first. We used sever al instantiations of the full adder to build the structure of the 4-bit adder. We have included the libr ary and use clause as well as the entity declarations. Structural description The circuit of can also be described using a structural model that specifies what gates are used and how they are interconnected. The following example illustrates it.

architecture structural of BUZZER is -- Declarations component AND2 por t (in1, in2: in std_logic; out1: out std_logic); end component; component OR2 por t (in1, in2: in std_logic; out1: out std_logic); end component; component NOT1 por t (in1: in std_logic; out1: out std_logic); end component; -- declaration of signals used to interconnect gates signal DOOR_NOT, SBELT_NOT, B1, B2: std_logic; begin -- Component instantiations statements U0: NOT1 port map (DOOR, DOOR_NOT); U1: NOT1 port map (SBELT, SBELT_NOT); U2: AND2 port map (IGNITION, DOOR_NOT, B1); U3: AND2 port map (IGNITION, SBELT_NOT, B2);

Powered By www.technoscriptz.com

U4: OR2 port map (B1, B2, WARNING); end structural; Architecture body The architecture body specifies how the circuit operates and how it is implemented. As discussed earlier, an entity or circuit can be specified in a variety of ways, such as behavioral, structural (interconnected components), or a combination of the above. The architecture body looks as follows, architecture architecture_name of NAME_OF_ENTITY is -- Declarations -- components declarations -- signal declarations -- constant declarations -- function declar ations -- procedure declar ations -- type declarations : begin -- Statements : end architecture_name; One can add other libraries and packages. The syntax to declare a package is as follows: -- Package declaration Package name_of_package is package declarations end package nam e_of_package; -- Package body declarations package body nam e_of_package is package body declarations end package body name_of_package;

Powered By www.technoscriptz.com

- Introduction a PLC
- 74LS76
- Cong nghe FPGA2
- T2-2-LogicFamilyChar
- de
- KSOU_MScIT_2009_1
- d Latchandd Flipflopintroductionvlsicomputerscienceengineeringiiithyderabadvirtuallab 141107102401 Conversion Gate01
- Hardware Simulator
- DM74LS373N
- dpsd 2marks
- 74109
- SSSR labs VC Divider Operation Manual
- AD5410_5420
- 56_10_LOW
- ee101_dgtl_5
- hw6-solns
- SAA3010.pdf
- Ttttt Eeee As
- Verification of 8x10 Encoder and 10x8 Decoder with 3-bit down Ripple Counter for USB 3.0 Applications
- 17-Timing
- Digital Electronics
- Reversible Programmable Logic Array (RPLA) using Feynman & MUX Gates for Low Power Industrial Applications
- Speedometer
- SNUG Design Tips Paper
- ASIC Power Groid Analysis
- ch01
- Processor 5
- 132 Catalog
- dac7724
- ECE 202

- eee_5_8sem(electrical and electronics) syllabus
- induction motor
- Virtual Function
- prgm
- Power Line Commication
- Equa
- electrical machines- II(Unit 4)
- EC_1313 2m
- Capacitance of a Single Core Cable
- Abstract Class
- electrical machines- II(UNIT 2)
- Overloading
- Type Conversions 11
- Beam Design Sakthi.docxf587986
- A STUDY ON SPACE BASED POWER TRANSMISSION
- The Dls Technician’s Certificate 4
- Theory:The 555 Timer Configured for Monostable Operation
- Module Advanced Networking
- Module WindowsXPOverview
- Module Boot Process
- 2010 Monthly Calendar Purple Landscape
- Pc99 System Compliance Standards
- 136 Circuit Electronique
- Working With Flipflops
- A Ppc
- EC2254-NOL
- E-Cops Final J2EE
- Wireless LAN Simulation
- lic

Read Free for 30 Days

Cancel anytime.

Close Dialog## Are you sure?

This action might not be possible to undo. Are you sure you want to continue?

Loading