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MPASM™/MPLINK™ PICmicro® MCU Quick Chart

MPASM™ Assembler Usage
MPASM Directive Summary
Directive Description CONTROL DIRECTIVES
CONSTANT #DEFINE END EQU #INCLUDE ORG PROCESSOR RADIX SET #UNDEFINE VARIABLE Declare Symbol Constant Define Text Substitution End Program Block Define Assembly Constant Include Source File Set Program Origin Set Processor Type Specify Default Radix Assign Value to Variable Delete a Substitution Label Declare Symbol Variable constant <label> [= <expr>, ...,<label> [= <expr>]] #define <name> [[(<arg>,...,<arg>)]<value>] end <label> equ <expr> DW include <include_file> <label> org <expr> processor <processor_type> radix <default_radix> <label> set <expr> _ _MAXROM #undefine <label> RES variable <label> [= <expr>,...,] ERROR ERRORLEVEL LIST MESSG endw if <expr> ifdef <label> ifndef <label> while <expr> NOLIST PAGE SPACE SUBTITLE TITLE _ _badram <expr> _ _badrom <expr> cblock [<expr>] _ _config <expr> OR _ _config <addr>, <expr> (PIC18 MCU) config setting=value [, setting=value] [<label>] da <expr> [, <expr2>, ..., <exprn>] ENDM EXITM EXPAND LOCAL MACRO NOEXPAND ENDC FILL _ _ IDLOCS _ _MAXRAM Declare Data of One Word End CBlock Specify Memory Fill Value Set ID locations Specify max RAM adr Specify max ROM adr Reserve Memory DB DE DT Declare Data of One Byte Declare EEPROM Data Define Table

MPASM Directive Summary (Con’t)
Directive Description
Create Numeric/ Text Data

Syntax
data <expr>, [,<expr>,...,<expr>] data "<text_string>" [,"<text_string>",...] db <expr>[,<expr>,...,<expr>] de <expr>[,<expr>,...,<expr>] dt <expr>[,<expr>,...,<expr>] dw <expr> [,<expr>,...,<expr>] endc fill <expr>, <count> _ _idlocs <expr> _ _maxram <expr> _ _maxrom <expr> res <mem_units>

Syntax

DATA

LISTING
Issue an Error Message Set Message Level Listing Options User Defined Message Turn off Listing Output Insert Listing Page Eject Insert Blank Listing Lines Specify Program Subtitle Specify Program Title error "<text_string>" errorlevel 0|1|2|<+-><msg> list [<option>[,...,<option>]] messg "<message_text>" nolist page space [<expr>] subtitl "<sub_text>" title "<title_text>"

CONDITIONAL ASSEMBLY
ELSE ENDIF ENDW IF IFDEF IFNDEF WHILE Begin Alternative Assembly to IF End Conditional Assembly End a While Loop Begin Conditional ASM Code Execute If Symbol Defined Execute If Symbol Not Defined Perform Loop While True else endif

DATA
_ _BADRAM _ _BADROM CBLOCK _ _CONFIG Specify invalid RAM locations Specify invalid ROM locations Define Block of Constants Set configuration bits Set configuration bits (PIC18 MCU) Pack Strings in 14-bit Memory

MACROS
End a Macro Definition Exit from a Macro Expand Macro Listing Declare Local Macro Variable Declare Macro Definition Turn off Macro Expansion endm exitm expand local <label> [,<label>] <label> macro [<arg>,...,<arg>] noexpand

CONFIG DA

1

PIC12F629/675. PIC16X5X. PIC16C505 PIC12C67X. PIC12CE67X.lst file Suppress mp2hex. all members will be extracted /q /r Quiet mode Add/replace member MPASM Radix Types Supported Radix Binary Octal Decimal Hexadecimal (default) Character (ASCII) /t List members Extract member Syntax B‘<binary_digits>’ O‘<octal_digits>’ D‘<digits>’ .<label>] /x [<name>] idata [<address>] [<name>] idata_acs [<address>] pagesel <label> pageselw <label> [<name>] udata [<address>] [<name>] udata_acs [<address>] [<name>] udata_ovr [<address>] [<name>] udata_shr [<address>] Description Specify format of hex output file Display help screen Add directories to linker script search path Add directories to library search path Create map file ‘filename’ Specify number of lines per listing page Specify output file ‘filename’. Quiet mode Suppress mp2cod. PIC12C5XX. Default is a. then they are extracted.hex file /l pathlist /m filename /n length /o filename /q /w MPLIB™ Librarian Usage MPLIB Command Line Options Option /c /d Meaning Create library Delete member Description Creates a new LIBRARY with the listed MEMBER(s) Deletes MEMBER(s) from the LIBRARY.<digits> H‘<hex_digits>’ 0x<hex_digits> A‘<Character>’ ‘<character>’ Example /x B‘00111001’ O‘777’ D‘100’ . then they are replaced. If no MEMBER is specified.out.100 H‘9f’ 0x9f A‘C’ ‘C’ Instruction Sets Instruction Set Bit Width/Device Map Instruction Width 12 Bit 14 Bit 16 Bit Devices Supported PIC10F2XX.<label>] extern <label> [ . PIC16X PIC18X 2 .exe . PIC12CE5XX.prevent the generation of a .prevent the generation of a .cod file and a .MPASM™/MPLINK™ PICmicro® MCU Quick Chart MPASM Directive Summary (Con’t) Directive Description Syntax MPLINK™ Linker Usage MPLINK Command Line Options Option /a hexformat /h. /? /k pathlist OBJECT FILE DIRECTIVES ACCESS_OVR BANKISEL BANKSEL CODE CODE_PACK EXTERN GLOBAL IDATA IDATA_ACS PAGESEL PAGESELW UDATA UDATA_ACS UDATA_OVR UDATA_SHR Overlay section in Access RAM Select Bank for indirect Select RAM bank Executable code section Packed data in program memory Declare external label Export defined label Initialized data section Access initialized data section Select ROM page Select ROM page using WREG Uninitialized data section Access uninit data section Overlay uninit data section Shared uninit data section [<name>] access_ovr [<address>] bankisel <label> banksel <label> [<name>] code [<address>] [<name>] code_pack [<address>] extern <label> [ .exe . if no MEMBER is specified the LIBRARY is not altered No output is displayed If MEMBER(s) exist in the LIBRARY. otherwise MEMBER is appended to the end of the LIBRARY Prints a table showing the names of the members in the LIBRARY If MEMBER(s) exist in the LIBRARY.

. kk 8-bit. 3 . skip if zero WREG .d f. Z.. skip if zero f + 1 → dest f + 1 → dest.AND. N TO PD GIE Key to 12/14-Bit Instruction Sets (Con’t) Field Description Named Bits ALU Status bits: Carry. kkk 12-bit.NOT.d f... See d. Points to a Program Memory location.1 → dest f . Descriptors ( ) →. Used to select the current RAM bank. f → dest f → dest WREG → f i s t '' Named Registers BSR OPTION PCL PCH PCLATH PCLATU PRODH PRODL TBLATH TBLATL TBLPTR WREG Bank Select Register. Zero.d f. skip if zero Increment f Increment f. Digit Carry. constant data or label k 4-bit.. skip if zero Inclusive OR W and f Move f Move W to f No operation Rotate left f C Function WREG + f → dest WREG .XOR.1 → dest. Register file address (5-bit..d f. Negative Time-out bit Power-down bit Global Interrupt Enable bit(s) Named Device Features Program Counter Top-of-Stack Watchdog Timer Misc. Bits b d Bit address within an 8-bit file register (0 to 7) Destination select bit d = 0: store result in WREG d = 1: store result in file register f (default) Table pointer control i = 0: do not change i = 1: increment after instruction execution Destination select bit s = 0: store result in file register f and WREG s = 1: store result in file register f (default) Table byte select t = 0: perform operation on lower byte t = 1: perform operation on upper byte Bit values. The assembler will generate code with x = 0.d f.d f. DC. PC TOS WDT C. f → dest * Assuming default bit value for d. 7-bit or 8-bit) Peripheral register file address (5-bit) Port for TRIS Don’t care (‘0’ or ‘1’).OR.. as opposed to Hex value 12-Bit Instruction Set 12-Bit Byte-Oriented File Register Operations Hex 1Ef* 16f* 06f 040 26f* 0Ef* 2Ef* 2Af* 3Ef* 12f* 22f* 02f 000 36f* Mnemonic ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF f.. Working register (accumulator) register f 7. f → dest f . OPTION Register Program Counter Low Byte Program Counter High Byte Program Counter High Byte Latch Program Counter Upper Byte Latch Product of Multiply High Byte Product of Multiply Low Byte Table Latch (TBLAT) High Byte Table Latch (TBLAT) Low Byte 16-bit Table Pointer (TBLPTRH:TBLPTRL).d f f. It is the recommended form of use for compatibility with all Microchip software tools.d f. ↔ <> Contents Assigned to Register bit field Literals k Literal field.0 0Af* 3Af* 1Af* SUBWF SWAPF XORWF f.d f.MPASM™/MPLINK™ PICmicro® MCU Quick Chart Key to PIC10/12/16 MCU (12/14-Bit) Instruction Sets Key to 12/14-Bit Instruction Sets Field Description Register Files dest f p r x Destination either the WREG register or the specified register file location.d Rotate right f C register f 7. OV.d f...d f Description Add W and f AND W and f Clear f Clear W Complement f Decrement f Decrement f.WREG → dest f(0:3) ↔ f(4:7) → dest WREG .d Subtract W from f Swap halves f Exclusive OR W and f f . f → dest 0→f 0 → WREG .0 32f* RRF f. Overflow.d f.

f → d f→d 2'1'kkk 38kk 30kk 0062 0009 34kk 0008 0063 GOTO IORLW MOVLW OPTION RETFIE RETLW RETURN SLEEP kkk kk kk Goto address (k is nine bits) Incl.MPASM™/MPLINK™ PICmicro® MCU Quick Chart 12-Bit Bit-Oriented File Register Operations Hex 4bf 5bf 6bf 7bf 14-Bit Byte-Oriented File Register Operations (Con’t) Hex 00'1'f 0000 0Ddf Mnemonic BCF BSF BTFSC BTFSS f. OR literal and W Move Literal to W Load OPTION register Return from Interrupt kk Return with literal in W Return from subroutine Go into Standby Mode 4 . stop oscillator WREG → I/O control reg r kk . WREG → WREG 7bf BTFSS f. WREG → WREG kk → WREG WREG → OPTION Register TOS → PC..b Description Bit clear f Bit set f Bit test.. skip if set Function 0 → f(b) 1 → f(b) skip if f(b) = 0 skip if f(b) = 1 14-Bit Literal and Control Operations Hex 3Ekk 39kk 2'0'kkk Mnemonic ADDLW ANDLW CALL CLRWDT kk kk kkk Description Add literal to W AND literal and W Call subroutine Clear Watchdog Timer Function kk + WREG → WREG kk . WREG → WREG PC + 1 → TOS.b f.NOT.0 12-Bit Literal and Control Operations 02df SUBWF SWAPF XORWF f.. skip if zero Increment f Increment f.d f.. skip if 0 W .b f. skip if zero Inclusive OR W and f Move f Function W+f→d W .1 → d.XOR. skip if clear Bit test. TOS → PC 0 → WDT. skip if set Function 0 → f(b) 1 → f(b) skip if f(b) = 0 skip if f(b) = 1 Mnemonic MOVWF NOP RLF f.d Hex Ekk 9kk 004 Akk Dkk Ckk 002 8kk 003 00r Fkk Mnemonic ANDLW CALL CLRWDT GOTO IORLW MOVLW OPTION RETLW SLEEP TRIS XORLW r kk kk kk kk kk kk kk Description AND literal and W Call subroutine Clear WDT Goto address (k is nine bits) Incl.d f.b f. skip if clear Bit test. stop oscillator 14-Bit Instruction Set 14-Bit Byte-Oriented File Register Operations Hex 07df 05df 01'1'f 01xx 09df 03df 0Bdf 0Adf 0Fdf 04df 08df 0064 Mnemonic ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF f. kk → PC 0 → WDT (and Prescaler if assigned) kk → PC(9 bits) kk . TOS → PC TOS → PC 0 → WDT.d f.OR.d f. WREG → WREG kk → WREG WREG → OPTION Register kk → WREG. OR literal and W Move Literal to W Load OPTION Register Return with literal in W Go into Standby Mode Tristate port r Exclusive OR literal and W Function kk .d f..OR.AND.d Rotate right f C register f 7.b Description Bit clear f Bit set f Bit test.b 0Edf 06df Subtract W from f Swap halves f Exclusive OR W and f f-W→d f(0:3) ↔ f(4:7) → d W .d f..XOR..d f.AND.b f.d f.OR. 1 → GIE kk → WREG. f → d 14-Bit Bit-Oriented File Register Operations Hex 4bf 5bf 6bf Mnemonic BCF BSF BTFSC f.. f → d f-1→d f .. f → d 0→f 0→W .b f..d f. skip if 0 f+1→d f + 1 → d.0 0Cdf RRF f. WREG → WREG PC + 1 → TOS.d f Description Move W to f No operation Rotate left f C Function W→f register f 7.AND. kk → PC 0 → WDT (and Prescaler if assigned) kk → PC(9 bits) kk .d f.d f Description Add W and f AND W and f Clear f Clear W Complement f Decrement f Decrement f.

k 4-bit kk 8-bit kkk 12-bit Offsets.d Move File to W Negate File Set Carry Set Digit Carry Set Zero Skip on Carry Skip on Digit Carry Skip on No Carry Skip on No Digit Carry Skip on Non Zero Z Z b a * *+ *+* Bits RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register (default) Bit address within an 8-bit file register (0 to 7).destination address 0.d f.1 f.3 0x0A. Indirect addressing offset z' 7-bit offset value for indirect addressing of register files (source) z” 7-bit offset value for indirect addressing of register files (destination) k r x f z Literals Literal field. 5 .d f.0 3. See d. The mode of the TBLPTR register for the table read and table write instructions.2 k 3.1 f.WREG → WREG Description Skip on Zero Equivalent Operation(s) BTFSS BTFSC DECF BTFSC DECF MOVF 3.0 f. Register file address f 8-bit (0x00 to 0xFF) f' 12-bit (0x000 to 0xFFF) . or the direct address for Call/Branch and Return instructions.3 0x0A.2 Stat Bit Z Z Key to PIC18 MCU (16-Bit) Instruction Set Key to 16-Bit Instruction Set Field Description Register Files dest Destination either the WREG register or the specified register file location.1 3.d f.2 3.d 3.d k 3.MPASM™/MPLINK™ PICmicro® MCU Quick Chart 14-Bit Literal and Control Operations (Con’t) Hex 3Ckk 006r 3Akk 12/14-Bit Special Instruction Mnemonics (Con’t) Mnemonic SKPZ Mnemonic SUBLW TRIS XORLW kk r kk Description Subtract W from literal Tristate port r Exclusive OR literal and W Function kk .d k k k k k k k Description Add Carry to File Add Digit Carry to File Branch Branch on Carry Branch on Digit Carry Branch on No Carry Branch on No Digit Carry Branch on No Zero Branch on Zero Clear Carry Clear Digit Carry Clear Zero Long Call Equivalent Operation(s) BTFSC INCF BTFSC INCF GOTO BTFSC GOTO BTFSC GOTO BTFSS GOTO BTFSS GOTO BTFSS GOTO BTFSC GOTO BCF BCF BCF BCF/BSF BCF/BSF CALL BCF/BSF BCF/BSF GOTO MOVF COMF INCF BSF BSF BSF BTFSS BTFSS BTFSC BTFSC BTFSC 3.1 3.0 k 3.source address f” 12-bit (0x000 to 0xFFF) . It is the recommended form of use for compatibility with all Microchip software tools. 1 or 2 for FSR number Don’t care (‘0’ or ‘1’) The assembler will generate code with x = 0.d f Subtract Carry from File Subtract Digit Carry from File Test File 12/14-Bit Pseudo-Instructions 12/14-Bit Special Instruction Mnemonics Mnemonic ADDCF ADDDCF B BC BDC BNC BNDC BNZ BZ CLRC CLRDC CLRZ LCALL k f.1 k 3.XOR.2 3.0 f.1 Stat Bit Z Z Z WREG → I/O control reg r kk .d 3.0 3.0 3.4 k 0x0A.1 k 3.Post-Decrement register +* Pre-Increment register LGOTO k Long GOTO MOVFW NEGF SETC SETDC SETZ SKPC SKPDC SKPNC SKPNDC SKPNZ f f.1 f. Only used with table read (TBLRD) and table write (TBLWT) instructions: * No Change to register *+ Post-Increment register *. constant data or label.0 f.0 k 3.2 k 3.1 3.0 3.4 k f. WREG → WREG SUBCF SUBDCF TSTF f.1 3.d 3. Increments/Decrements n The relative address (2’s complement number) for relative branch instructions.2 0x0A.

..d. OV..d.AND..a f. File Select Register Program Counter Low Byte Program Counter High Byte Program Counter High Byte Latch Program Counter Upper Byte Latch Product of Multiply High Byte Product of Multiply Low Byte Status Register 8-bit Table Latch 21-bit Table Pointer (points to a Program Memory location) Working register (accumulator) 65f* CPFSGT f...a register f C 7..0 33f* RRCF f.d.MPASM™/MPLINK™ PICmicro® MCU Quick Chart Key to 16-Bit Instruction Set (Con’t) Field d PIC18 MCU Instruction Set PIC18 Byte-Oriented Register Operations Hex 27f* 23f* Description Destination select bit d = 0: store result in WREG d = 1: store result in file register f (default) Fast Call/Return mode select bit s = 0: do not update into/from shadow registers (default) s = 1: certain registers loaded into/from shadow registers (Fast mode) Bit values. skip if f=WREG Compare f with WREG.a 61f* CPFSLT f. PC+4 → PC else PC+2 → PC f–1 → dest f–1 → dest. f → dest 0→f . PC+4 → PC else PC+2 → PC f–WREG. if f < WREG.0 6 .d. Negative Time-out bit Power-down bit Peripheral Interrupt Enable bit Global Interrupt Enable bit(s) 2Bf* 3Ff* INCF INCFSZ f. skip if not 0 Increment f Increment f. skip if f > WREG Compare f with WREG. f → dest f → dest f' → f” WREG → f WREG * f → PRODH:PRODL -f → f register f C 7.a 13f* 53f* Cf' Ff” 6Ff* 03f* 6Df* 37f* IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF f.d.d.a f'. as opposed to Hex value Mnemonic ADDWF ADDWFC f....f” f. skip if not 0 Inclusive OR WREG with f Move f Move f' to fd” (second word) Move WREG to f Multiply WREG with f Negate f Rotate left f through Carry Rotate left f (no carry) Rotate right f through Carry Rotate right f (no carry) Function WREG+f → dest WREG+f+C → dest s 17f* 6Bf* 1Ff* 63f* ANDWF CLRF COMF CPFSEQ f.a Named Bits C.0 Named Registers BSR FSR PCL PCH PCLATH PCLATU PRODH PRODL STATUS TABLAT TBLPTR WREG Bank Select Register. if f=WREG.a register f 7. skip if 0 Decrement f.a f. if dest=0. if f > WREG. Descriptors ( ) → <> Contents Assigned to Register bit field 47f* RLNCF f.. PC+4 → PC else PC+2 → PC f+1 → dest. PC+4 → PC else PC+2 → PC f+1 → dest f+1 → dest.d.a 4Bf* INFSNZ f.a 4Ff* DCFSNZ f. Z..a register f 7. skip if 0 Increment f. DC. PC+4 → PC else PC+2 → PC f–WREG.d.a f.d. if dest=0.. Digit Carry. Zero.a f. Used to select the current RAM bank.0 43f* RRNCF f.a f. N TO PD PEIE GIE.a f.d.d.a Description ADD WREG to f ADD WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG..a '' WREG . GIEL/H ALU Status bits: Carry. if dest ≠ 0.a 07f* 2Ff* DECF DECFSZ f..d. PC+4 → PC else PC+2 → PC f–1 → dest..OR. Overflow.d..a f..NOT..a f.a f.. f → dest f–WREG. PC+4 → PC else PC+2 → PC WREG . if dest ≠ 0.d.d. skip if f < WREG Decrement f Decrement f.a f.a Named Device Features MCLR PC TOS WDT Master clear device reset Program Counter Top-of-Stack Watchdog Timer Misc.d.

PC+2+2*n→PC. else PC+2 → PC WREG . PC+4→PC. else PC+2→PC if Z=0. else PC+2→PC PC+2+2*n→ PC if Z=1. if f=0. 0 → WDT postscaler. else PC+2→PC 00FF 0010* s Return from interrupt (and enable interrupts) 0012* RETURN s Return from subroutine E1n E4n BNZ BOV n n 0003 SLEEP Enter SLEEP Mode * Assuming default bit value for s. PC+2+2*n→PC.a f. else PC+2→PC if N=1.d. WREGs → WREG. else PC+2→PC if N=0.WREG → dest 0004 f . f<7:4> → dest<3:0> PC+4 → PC. PCLATU/PCLATH unch 0 → WDT. 1 → TO. skip if set Bit Toggle f Function 0 → f<b> 1 → f<b> if f<b>=0. f → dest DAW CLRWDT Clear Watchdog Timer Decimal Adjust WREG 3Bf* 67f* 1Bf* SWAPF TSTFSZ XORWF f. PIC18 Control Operations Hex E2n E6n E3n E7n E5n D'1'n RCALL RESET RETFIE n Relative Call Software device reset PC+2 → TOS. BSRs → BSR. else PC+2→PC f<b> → f<b> EFkk Fkkk 0000 Fxxx 0006 GOTO n Go to address 1st word 2nd word No Operation No Operation Pop top of return stack (TOS) Push top of return stack (TOS) NOP NOP POP No Operation No Operation (2-word instructions) TOS-1 → TOS 0005 PUSH PC +2→ TOS * Assuming b = 0 and default bit value for a.a Description Bit Clear f Bit Set f Bit test f. PC+4→PC. PC+2+2*n→PC.d. else PC+2→PC if C=0.d. PCLATU/PCLATH unch TOS → PC. BSR → BSRs 0 → WDT.b.a f. n → PC<20:1> 5Ff* 5Bf* SUBWF SUBWFB f. 0 → WDT postscaler. else PC+2→PC if f<b>=1. WREGs → WREG.1 → PD if WREG<3:0> >9 or DC=1. WREG → WREGs. skip if 0 Exclusive OR WREG with f Function 0xFF → f WREG . PC+2+2*n→PC.XOR. STATUSs → STATUS.a f. PC+2+2*n→PC. else WREG<7:4> → WREG<7:4>.a f. else PC+2→PC if OV=1.C → dest Mnemonic CALL n. PC+2+2*n→ PC.d. if WREG<7:4> >9 or C=1.d. if s=1.a f. n → PC<20:1>. STATUS → STATUSs.a f.a f.a f .WREG . D'0'n E0n BRA BZ n n 7 . skip if clear Bit test f. WREG<7:4>+6→ WREG<7:4>. WREG<3:0>+6→ WREG<3:0>. PIC18 Bit-Oriented Register Operations Hex 91f* 81f* B1f* A1f* 71f* Mnemonic BCF BSF BTFSC BTFSS BTG f. else WREG<3:0> → WREG<3:0>. else PC+2→PC if OV=0.b.b. PC+2+2*n→PC. STATUSs → STATUS. if s=1. PC+2+2*n→PC. 0 → PD Mnemonic BC BN BNC BNN BNOV n n n n n Description Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Function if C=1.MPASM™/MPLINK™ PICmicro® MCU Quick Chart PIC18 Byte-Oriented Register Operations (Con’t) Hex 69f* 57f* PIC18 Control Operations (Con’t) Hex ECkk* Fkkk Mnemonic SETF SUBFWB f. 1 → TO.a * Assuming default bit values for d and a.b. BSRs → BSR.a f.s Description Call Subroutine 1st word 2nd word Function PC+4 → TOS.C → dest 0007 f<3:0> → dest<7:4>.b. PC+2+2*n→PC Same as MCLR reset TOS → PC.f .a Description Set f Subtract f from WREG with Borrow Subtract WREG from f Subtract WREG from f with Borrow Swap nibbles of f Test f. 1 → GIE/ GIEH or PEIE/GIEL. if s=1.

OR. (TOS) → PC (PC + 2) → TOS.A. (PCLATU) → PCU ((FSR2)+z’) → f” E8fk E8Ck 0014 kk .k k FSR(f . PIC.XOR.k → FSR2. and other countries. f” (destination) 2nd word Move z’ (source) to 1st word.A. kk → WREG WREG . MPLAB. Printed in the U. the Microchip logo. decrement FSR2 Subtract literal from FSR Subtract literal from FSR2 and return Mnemonic TBLRD* TBLRD*+ Description Table Read Table Read with post-increment Table Read with post-decrement Table Read with pre-increment Table Write Table Write with post-increment Function Prog Mem (TBLPTR) → TABLAT Prog Mem (TBLPTR) → TABLAT TBLPTR +1 → TBLPTR Prog Mem (TBLPTR) → TABLAT TBLPTR -1 → TBLPTR TBLPTR +1 → TBLPTR Prog Mem (TBLPTR) → TABLAT TABLAT → Prog Mem (TBLPTR) TABLAT → Prog Mem (TBLPTR) TBLPTR +1 → TBLPTR EB’1’z Fxzz MOVSS z’. (TOS) → PC 000B TBLRD+* 000C 000D TBLWT* TBLWT*+ The Microchip name and logo. FSR2-1 → FSR2 000A TBLRD*- E9fk E9Ck SUBFSR SUBULNK f. 3/05 © 2005.MPASM™/MPLINK™ PICmicro® MCU Quick Chart PIC18 Literal Operations Hex 0Fkk 0Bkk 09kk PIC18 Memory Operations (Con’t) Function WREG+kk → WREG WREG . (W) → PCL. DS30400G 8 .z” ((FSR2)+z’) → ((FSR2)+z”) EAkk PUSHL k k → (FSR2). MPASM and MPLINK are trademarks of Microchip Technology Incorporated in the U.WREG → WREG WREG .kk PIC18 MCU Extended Instruction Set PIC18 Extended Instructions Hex Mnemonic ADDFSR ADDULNK f. kk → WREG CALLW EB’0’z Ffff MOVSF z’.S.k k 010k 0Ekk 0Dkk 0Ckk 08kk 0Akk MOVLB MOVLW MULLW RETLW SUBLW XORLW k kk kk kk kk kk kk → BSR kk → WREG WREG * kk → PRODH:PRODL kk → WREG Description Add literal to FSR Add literal to FSR2 and return Call subroutine using WREG Function FSR(f)+k → FSR(f) FSR2+k → FSR2.S.AND. and other countries. All other trademarks mentioned herein are property of their respective companies. z” (destination) 2nd word Store literal at FSR2.f” PIC18 Memory Operations Hex 0008 0009 Move z’ (source) to 1st word. and PICmicro are registered trademarks of Microchip Technology Incorporated in the U.A. Microchip Technology Incorporated. All Rights Reserved.S. kk → WREG kk → FSRr Mnemonic ADDLW ANDLW IORLW kk kk kk Description Add literal to WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12 bit) 2nd word to FSRr 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG Hex 000E Mnemonic TBLWT*- Description Table Write with post-decrement Table Write with pre-increment Function TABLAT → Prog Mem (TBLPTR) TBLPTR -1 → TBLPTR TBLPTR +1 → TBLPTR TABLAT → Prog Mem (TBLPTR) 000F TBLWT+* EErk F0kk LFSR r. (PCLATH) → PCH.k) → FSR(f) FSR2 .