You are on page 1of 7

design

Edited by Bill Travis
ideas The best of
design ideas
! Check it out at:
www.edn.com

Data-acquisition system uses fault protection
Catherine Redmond, Analog Devices, Limerick, Ireland
ensitive systems, such as those When a fault condition occurs, the

S in aircraft, must withstand fault
conditions, thereby avoiding
component and system damage, be-
VSS
voltage on the input of the channel
protector exceeds a voltage set by the
supply-rail voltage minus the MOS-
cause a sensor failure could cause a FET’s threshold voltage. For a positive
PMOS
catastrophic event to occur.A channel overvoltage, this voltage is VDD⫺
protector, comprising two n-channel NMOS NMOS VTN, where VTN is the threshold volt-
MOSFETs connected in series with a age of the NMOS transistor (typical-
p-channel MOSFET, can protect sen- PMOS
ly, 1.5V). In the case of a negative over-
sitive components from voltage tran- voltage, the voltage is VSS⫺VTP, where
sients in the signal path, whether or VDD VSS VDD VTP is the threshold voltage of the
not the power supplies are present A channel protector can protect sensi- PMOS device (typically, ⫺2V). When
Figure 1
(Figure 1). The channel protector tive circuitry from voltage transients. the input of the channel protector ex-
acts as series resistor during normal ceeds either of these voltages, the pro-
operation. If the input exceeds the pow- tions in which correct power sequencing tector clamps the output within them.
er-supply voltages, one of the MOSFETs cannot be guaranteed and for hot-inser- These devices offer bidirectional fault and
turns off, clamping the output within the tion rack systems. Figure 2 shows an overvoltage protection, so you can use the
supply rails, thus protecting the circuitry ADG465 channel protector with an input inputs or outputs interchangeably. Figure
in the event of overvoltage or supply-loss signal that exceeds the power-supply volt- 3 shows the voltages and MOSFET states
conditions. Because channel protectors age. The protector clamps the output sig- for a positive-overvoltage event.
work regardless of the presence of the nal, protecting the sensitive components The output load limits the current
supplies, they are also ideal for applica- that follow the channel protector. during the fault condition to VCLAMP/RL
(Figure 4). If the supplies are off, the
VDD VSS
protector limits the fault current to
nanoamps. Figure 5 shows how you can
Figure 2 VIN
VD1 VS1
VOUT use the ADG466 channel protector to
protect the sensitive inputs of an instru-
ADG465
VIN
VOUT mentation amp from a sensor fault. In
applications that require a multiplexer in
VDD
VDD

Data-acquisition system
OUTPUT CLAMPED
uses fault protection ......................................69
AT VDDⳮ1.5V
Take steps to reduce
antiresonance in decoupling ......................70
The channel protector clamps overvoltage transients to a safe level. Precision level shifter has
VDD–VTN excellent CMRR ..............................................72
13.5V
Celsius-to-digital thermometer works
with remote sensor ........................................74
POSITIVE NMOS PMOS NMOS
OVERVOLTAGE Quasiresonant converter uses
(20V)
a simple CMOS IC..........................................74
SATURATED NONSATURATED NONSATURATED
Simple circuit serves
Figure 3 VDD VSS VDD as milliohmmeter ..........................................78
15V –15V 15V
Publish your Design Idea in EDN. See the
NOTE: VTN = NMOS-THRESHOLD VOLTAGE (1.5V). What’s Up section at www.edn.com.

The voltages and MOSFET states appear like this during a positive-overvoltage event.

www.edn.com April 15, 2004 | edn 69

MI o maintain power integrity on pc T 10 boards. A typical configuration VOLTAGE ⳮ30 might comprise five capacitors connect. 15V 13. The Figure 3 A typical decoupling configuration uses several antiresonance occurs when one ca- multilayer-ceramic capacitors connected in pacitor is still capacitive. Farmington Hills. while another A 400-nF X2Y capacitor yields a total decou- parallel. FIVE STANDARD CAPACITORS: 470. p-channel. n. OVERVOLTAGE EFFECTIVE OPERATION RL VCLAMP channel MOSFET connection. This 220-nF (801-nF TOTAL CAPACITANCE) ONE STANDARD 1206 1000-nF CAPACITOR parallel network provides 801-nF total ONE STANDARD 1206 10-nF CAPACITOR ONE STANDARD 1206 470-nF CAPACITOR capacitance to the power-distribution ONE STANDARD 1206 220-nF CAPACITOR BOARD S21 system. 100. G1 G2 400 nF onant frequency). ⳮ10 ⳮ20 bution system. 100. Each RETURN SRF can cause antiresonance in the par- Figure 1 allel decoupling configuration. X2Y Attenuators. you can POWER A 470 nF 1 nF 10 nF 100 nF 220 nF identify each capacitor’s SRF (self-res.com . If you measure each capacitor POWER Measurements with a vector-network analyzer reveal undesirable antiresonance effects. protecting the sensor or signal source as well as the output circuitry. Take steps to reduce antiresonance in decoupling Dale Sanders. the inputs or outputs VG – VT =13. Figure 2 is a plot of (801 nF TOTAL) each capacitor’s SRF. 1. assume the indi.801 ␮F TOTAL with a vector-network analyzer. has become inductive. as the output circuitry. as well as the SRF B GROUND of the overall parallel connection. ADG439F ADG466 – SENSOR 1 ADC DSP SENSOR 1 + – ADC DSP IN AMP + SENSOR 4 IN AMP ANALOG OUT DAC REFERENCE TO ACTUATOR ANALOG OUT DAC REFERENCE Figure 5 Figure 6 TO ACTUATOR In this circuit. 10 kHz 10 kHz 1 MHz 10 MHz 100 MHz 1 GHz 10 GHz vidual values of the capacitors are 470. the ADG466 channel protector guards the sensi. A multiplexer in a data-acquisition system protects the signal source as well tive inputs of an instrumentation amplifier from a sensor fault. To provide ⳮ60 broadband decoupling per. you need multiple capaci. pling capacitance of 800 nF. (dB␮V) ⳮ40 ed in parallel between the power and the ⳮ50 ground traces or planes.5V 20V channel analog multiplexer PMOS NMOS Figure 4 (Figure 6). 10.5V P– appear as open circuits.edn. 0 tors to decouple the power-distri. 70 edn | April 15.5V VT = 1. LLC. four.design ideas addition to channel protection. These multiplex- N+ N+ N+ NONSATURATED ers use a series n-channel. 0. During OPERATION SPACE-CHARGE N-CHANNEL (SATURATED) REGION IOUT fault conditions.왏 The output load limits the current to VCLAMP/RL during a fault condition. ONE STANDARD 1206 1-nF CAPACITOR 1. and 220 nF (Figure 1). 10. you can VD VG VS ⌬V VDD use the ADG439F fault-protected. 2004 www. ⳮ70 Figure 2 ⳮ80 formance.

from an A or a B terminal to FIVE STANDARD CAPACITORS: 470. 10. 100. ⳮ60 ⳮ70 ing for an X2Y component Figure 4 ⳮ80 from line to ground. from Johanson VOLTAGE (dB␮V) ⳮ40 Dielectrics (www. The transfer func. ground to shunt the ref- mon-mode rejection ra. you can turn your attention to the (nominally.differentially coupling the signal into the source impedance low to prevent gain er- tion of the amplifier circuit is differential amplifier’s inputs force the rors. you need to elim- inate the reference noise obtain a clean level- tors. Note that the reference volt. 1210.minimize gain error. In addition. mately 25 k⍀ for the each input in the circuit of INA133) to facilitate Figure 1 has an associated noise voltage noise cancellation. When. ⳮ50 com). Differential am. or 800 nF. 1 X2Y 1206 400 nF BOARD S21 either of the G1 or G2 terminals in Fig. Now.design ideas A way to considerably reduce the an. filter and rejects the refer- proximately 90 dB. Careful cabling and matching. 10 kHz 10 kHz 1 MHz 10 MHz 100 MHz 1 GHz 10 GHz er words. the differential INA133 can readily VREF amplifier acts as a lowpass achieve CMRRs of ap. 220nF (801-nF TOTAL CAPACITANCE) ure 3. So. 90 dB). _ erence noise to ground. Figure 4 shows pling as the standard decoupling con. 0805.plifier rejects it to the best of its ability buffer the inputs. You could mismatching limits the connect the X end of C1 to +V op amp’s CMMR (com. –V reference is low. plifiers contain precision 25k however.doesn’t occur naturally. VOUT but this solution may be 25k not use op amps in VIN2 + ineffective because the +IN circuits that require high source impedance of the CMRR. connected as The single X2Y decoupling capacitor displays no antiresonance effects. for example. VN2. VIN1 –IN 25k 25k SENSE to Now. Bushnell. Once this level shifting oc. If this situation age shifts the output signal. tio) to 40 dB. the use of X2Y same total capacitance as in Figure 1 nance effects. you must keep the signal (VN1. (Ca- ⳮ20 pacitors using X2Y technology are ⳮ30 available. FL ost designers make VIN2⫺VIN1⫹VREF ⫹VNREF. Figure 1 X ance of the differential ming internal matched amplifier low (approxi- resistors. This circuit can offer such high keeps the input imped- CMRR by trim. 1206. Assume that C1 allows the level shifter to act as a lowpass filter that rejects the reference noise. 1. 10 tiresonance effects is to use a single 400. that a single X2Y capacitor with the figuration but without the antireso. M level shifters with op amps and 1%- tolerance discrete resis. so you can. so ICs such as the nal source. sizes as standard capacitors (1812. Texas Instruments. so the differential am. The input noise is a com.com . then it is best to or differential. The source impedance should be V OUT ⫽(V REF ⫹V NREF )⫹(V IN2 ⫹V N2 )⫺ noise on the signal inputs to be equal less than 1/1000 the input impedance to (VIN1⫹VN1). Thus. 0 ⳮ10 nF X2Y capacitor for decoupling. you connect the matched internal resis. They C1 ence noise.(VN1⫽VN2). Discrete-resistor shifted signal. 2004 www.johansondielectrics. either single mon-mode signal. in Figure 3 would be double the capac- itance rating. INA133 X end of C1 to the VIN1 sig- tors. the total capacitance a 400-nF X2Y component supplies.왏 Precision level shifter has excellent CMRR Ronald Mancini. You measure the capacitance rat. and VNREF). because X2Y components saves pc-board space and provides the same broadband decou. VOUT⫽ 72 edn | April 15.왏 curs. and 0603). in oth.edn. components come in the same package reduces layout complexity.

In this application. and the pri- recovery and charging parasitic capaci. When the energy has discharged. It has a high common-mode volt. current increases linearly until the base of Q5 starts to conduct. During this phase of operation. You can typical offset. a ⫺4 to ⫹1V.␮A as the temperature varies from 0 to leads. This system precisely measures temperature at a remote racy of 1⬚C throughout ming potentiometer with location. you can thus use it at a remote lo- perature range of 0⬚C—the freezing 100⬚C. Wilmington. Analog Devices. IC1 OUT VIN AD7476 DIGITAL- DATA sistor. which would cause excessive MOSFET mary energy charges the output capaci- tances create high di/dt. the circuit off. which is the main losses. The AD8541 is a low-cost. When the supply starts. The mainly when current switches on. the boiling has an offset of 4V to provide sufficient shielded cable. the FET off. should be plifier. flyback operation then starts.you can calculate the temperature in Cel- The AD590 provides an output current er supply. The series Quasiresonant converter uses a simple CMOS IC Francesc Casanellas. four resistors.15 to 373. ZD1 conducts and enables the in. You can – + of the amplifier to vary AD590 omit the ADC if you need from 0 to 5V.왏 point of water. ature varies from 0 to GND ture sensor. When the F ply that has low noise and uses a sim- ple CMOS 4093 IC for its control. the resistor. You Figure 1 To guarantee the accu- could replace the trim.edn. The voltage across WIRES AD8541 rail-to-rail am. Diode avoid working with low gate voltages.rents. such as tion. The converter in Figure 1 put gate of the 4093 when the voltage is and R6 keep Q5 conducting and the MOS- (pg 76) has a low noise level.sired code at the output of the ADC.dure. voltage. and AD590 er.low-power. Aiguafreda. IC1. rail-to-rail operational am. 1. D5 cause of noise.the AD590 varies from 273. To MOSFET is on. At a known temperature. but the accuracy of the re.15 pickup and voltage drops in the signal tor of 50 mV/⬚C over the chosen tem.com . or the de- maining resistors is not critical. adjust trimming potentiometer R2 a precision resistor to minimize the scale. T1 causes the output voltage and an ADC. Spain igure 1 shows a flyback power sup.to obtain the desired voltage at the out- factor error. The 4V offset trimming potentiometer. The feedback resistor. the current 1k DD 1⬚C error over a 0 to _ through the feedback re- 100⬚C range (Figure 1). a + AD8541 OUTPUT to ⫹20 ␮A as the temper- low-cost AD590 tempera. The output swing of the amplifier 400H. You can calibrate out its 1-mV put of the amplifier. the range.age range and extremely low bias cur. This circuit can derive its power from by 20. Once you perform the calibration.15 location with less than R2 V ␮A. 2004 www. combination of R1 and R2 Y supply system to pre- cisely measure the temperature at a remote R1 2k R3 50k RF 50k develops a 1V drop. with less than 1⬚⬚C error over a 0 to 100⬚⬚C range.5⬚C on either end. an analog output.250V.design ideas Celsius-to-digital thermometer works with remote sensor Elana Lian and Chau Tran. it is immune to voltage-noise full-scale range of 0 to 5V with a scale fac. The output of output. and this transistor turns the MOSFET off. is 25 mV to 4. Thus. slowly switches current on at nearly zero auxiliary nonisolated winding through D3 (continued on pg 78) 74 edn | April 15. The converter works in the keeps the gate input high. varies from ⫺80 The circuit includes T1. tors. The positive input of the AD8541 cation.965V with a single 5V pow. RF. you need to per- an AD8400 or AD5273 form a calibration proce- digital potentiometer for easier calibra. because it high enough. limiting the output by about sius at any measured point inside the proportional to absolute temperature (1 0.25⬚C. achieve the required accuracy. 200k this resistor varies from plifier. Because the sensor has a current sets and scales the output to provide a a single 5V power supply. choose the grade of the AD590 sensor to rors. RF. and you adjust R2 to provide a nominal current of 353. MA ou can use a single. an LONG R4 100⬚C. range by multiplying the output voltage ␮A/K). The electrical noise of a converter arises boundary between discontinuous and continuous mode and switches on when the drain voltage is at its lowest value. You should use a twisted-pair or point of water—to 100⬚C. headroom for the AD590.

com .7k R7 12 4.edn.design ideas VCC C4 R4 D3 D6 R5 R3 C3 ZD1 + VOUT 10k D4 C7 4. this flyback power-supply circuit exhibits extremely low noise.7V D5 D2 + C5 5 33 ␮F 14 2222 R6 6 D1 ZD3 8. 2004 www. 76 edn | April 15.2k Q3 15V 14 Q1 1 8 R16 C1 3 10 1 ␮F 2 9 R15 100 7 4093 Q2 R17 R2 4.7k 11 R13 13 2907 1k OC1 C6 Q5 47 pF 4N35 C2 R8 R10 100 ␮F R1 Q4 470 2369 22k C10 R9 1k 2369 R12 C9 R11 470k 1 nF ZD2 C8 TL431 R14 Figure 1 Using a simple CMOS IC.

The usual RC circuit. An 78 edn | April 15. The output cal noise. Because the MOSFET turns on component values in Figure 1 are un- the voltage decreases. turns on. A the constant-current source. R5 and C5 allow the when current is zero. Lancaster Hunt Systems Ltd. The method uses a volt- between their VOUT and VADJ terminals. you should determine these MOSFET to turn on when the voltage may be high. Voltage regulation uses tradi. The ing noise. and it allows a low duty parasitic capacitance of the primary res. I discovered that a short circuit existed from a ground plane to a power plane. I logged onto the Internet to find quick dig in the old component bucket I was working on used a 3. I revealed a supply of LM317 variable-volt. further reducing switch- D5 stops conducting. These ICs provide 1. plies.edn. Shepperton. which outlined the basic four- wire method of making low-resistance measurements. optocoupler current adds to the shunt cycle at low loads. you can use it in most power sup- The time constant of R5 and C5 keeps turn-on losses. The charge slowly. The other problem to cess to a milliohmmeter or an equivalent age-reference IC as the input stage for a attack was the output-voltage range of tester for locating this type of short cir. but also reduces electri. So. circuit of Figure 1 not only minimizes tional. UK hen I was recently debugging a found the answer in a manufacturer’s age regulators. Note that many of the onate with the primary inductance and current. the gate resistor designated.25V W design. a constant voltage to attack the constant- current problem. It kills the current glitch when Q3 the MOSFET off for a while. so parasitic capacitances values to fit the application. using a TL431. I had to limit the voltage to 3.3V supply.com . The circuit cuit. It is more effective than the capacitance of the MOSFET plus the tional techniques.3V.design ideas (continued from pg 74) has reached the minimum value. 2004 www. so no recovery problems exist. as do the secondary values are valid only for this case. controlled constant-current source. The circuit around Q4 is op- diodes. I did not have ac- data sheet. so an easily constructible milliohmmeter.왏 Simple circuit serves as milliohmmeter AM Hunt.

design ideas S1A LM317. Be. I wanted short circuits. The current the voltage across the resistor using a no current is flowing and that the trace is source delivers either 10 or 100 mA. The purpose of S1 is to give longer and the other for 100 mA.Make your own milliohmmeter. then the reading is cause I wanted to use a 10⍀/V on the 100-mA bench supply or a 9V bat. To measure a low reading and low readings on the trace battery life.edn. You can calibrate the current small resistance. Q1 constant-current source.DVM (digital voltmeter). you attach test points A with the high reading. de. Q1. You set the source of the short circuit.8 tery. to locate the source by strapping a resistive load be. BD636 The DVM reads a voltage S1B delivers an output voltage IC1 that is proportional to the VIN V equal to the in. 2004 www. – BATTERY – SUPPLY any 3. using a voltage-regulator IC and some resistors. Look pending on which emitter resistor is in the 10⍀ and set one S2 position for 10 mA for high readings on the trace with the circuit. Ideally. So. 100 10 gested.3V logic on the To track down pc-board board. Con- voltage across the selected resistor to form tween test points A and B and measuring stant voltage along a trace indicates that the constant-current source.5V.and B across the resistance. and use the other to tor. configured as a DVM on a millivolt range. attach the voltage to be limited to unit with test points A and A 1. If you put if the output Figure 1 VADJ calibrate the circuit as sug- P1 P2 resistance is too high. LM317 OUT resistance under test.com . Attach one IC1 controls the base of DVM probe to test point A the npn Darlington transis. B shorted signals.왏 80 edn | April 15. The IC regulates the probe the circuit. + + 9V R1 R2 range and 100⍀/V on the BATTERY 68 6. I came up with the B across the suspected configuration in Figure 1. I used 5 and not the source of the short circuit. the voltage would fry 3V OR BENCH 10-mA range.