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ISO2-CMOS MT8870D/MT8870D-1


Integrated DTMF Receiver

Features ISSUE 3 May1995

• Complete DTMF Receiver Ordering Information
• Low power consumption MT8870DE/DE-1 18 Pin Plastic DIP
• Internal gain setting amplifier MT8870DC/DC-1 18 Pin Ceramic DIP
• Adjustable guard time MT8870DS/DS-1 18 Pin SOIC
MT8870DN/DN-1 20 Pin SSOP
• Central office quality MT8870DT/DT-1 20 Pin TSSOP
• Power-down mode -40 °C to +85 °C
• Inhibit mode
• Backward compatible with Description
MT8870C/MT8870C-1

The MT8870D/MT8870D-1 is a complete DTMF
Applications receiver integrating both the bandsplit filter and
• Receiver system for British Telecom (BT) or digital decoder functions. The filter section uses
CEPT Spec (MT8870D-1) switched capacitor techniques for high and low
• Paging systems group filters; the decoder uses digital counting
techniques to detect and decode all 16 DTMF tone-
• Repeater systems/mobile radio pairs into a 4-bit code. External component count is
• Credit card systems minimized by on chip provision of a differential input
• Remote control amplifier, clock oscillator and latched three-state bus
interface.
• Personal computers
• Telephone answering machine

VDD VSS VRef INH

Bias
PWDN Circuit VRef
Buffer

Q1
Chip Chip
Power Bias High Group Digital Code
Filter Detection Converter
Algorithm and Latch Q2
IN + Dial
Tone Zero Crossing
Filter Detectors Q3
IN -

GS Low Group
Filter Q4

to all St Steering
Chip
Clocks GT Logic

OSC1 OSC2 St/GT ESt STD TOE

Figure 1 - Functional Block Diagram

4-11

Pin Connections Pin Description Pin # Name Description 18 20 1 1 IN+ Non-Inverting Op-Amp (Input). 10 11 TOE Three State Output Enable (Input). Logic high inhibits the detection of tones representing characters A. Q1-Q4 Three State Data (Output). When enabled by TOE. 16 4-12 . 7 8 OSC1 Clock (Input). Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). +5V typical. the data outputs are high impedance. Active high. This pin is pulled up internally. its state is a function of ESt and the voltage on St. Nominally VDD/2 is used to bias inputs at mid-rail (see Fig. provide the code corresponding to the 14 15 last valid tone-pair received (see Table 1). B.579545 MHz crystal connected between pins OSC1 and OSC2 completes the internal oscillator circuit. A voltage less than VTSt frees the device to accept a new tone pair. 2 17 St/GT IN. A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. 9 10 VSS Ground (Input). NC No Connection. 15 17 StD Delayed Steering (Output). Gives access to output of front end differential amplifier for connection of feedback resistor. Logic high enables the outputs Q1-Q4. 6 6 PWDN Power Down (Input). 2 19 St/GT GS 3 16 ESt GS 3 18 ESt VRef 4 15 StD VRef 4 17 StD INH 5 14 Q4 INH 5 16 NC PWDN 6 13 Q3 PWDN 6 15 Q4 OSC1 7 12 Q2 NC 7 14 Q3 OSC2 8 11 Q1 OSC1 8 13 Q2 VSS 9 10 TOE OSC2 9 12 Q1 VSS 10 11 TOE 18 PIN CERDIP/PLASTIC DIP/SOIC 20 PIN SSOP/TSSOP Figure 2 . 8 9 OSC2 Clock (Output). 18 20 VDD Positive power supply (Input). 16 18 ESt Early Steering (Output). Any momentary loss of signal condition will cause ESt to return to a logic low. Powers down the device and inhibits the oscillator. 6 and Fig. 0V typical.MT8870D/MT8870D-1 ISO2-CMOS IN+ 1 18 VDD IN+ 1 20 VDD IN. returns to logic low when the voltage on St/GT falls below VTSt. 4 4 VRef Reference Voltage (Output). A 3. 3 3 GS Gain Select. C and D. The GT output acts to reset the external steering time-constant. 11. This pin input is internally pulled down. When TOE is logic low. 17 19 St/GT Steering Input/Guard time (Output) Bidirectional. This pin input is internally pulled down.Presents a logic high when a received tone-pair has been registered and the output latch updated. 5 5 INH Inhibit (Input). 7. 2 2 IN.12. 10). Inverting Op-Amp (Input).

A performed by an external RC time constant driven by complex averaging algorithm protects against tone ESt. Its architecture consists of a C VDD bandsplit filter section. When prior to limiting. the digital counting techniques to determine the receiver checks for a valid signal duration (referred frequencies of the incoming tones and to verify that to as character recognition condition). the bandwidths of which correspond to the low and high group frequencies. This averaging algorithm has been exceptional dial tone rejection (see Figure 3). assume an inactive state (see “Steering Circuit”). The some industry specifications) the “Early Steering” outputs of the comparators provide full rail logic (ESt) output will go to an active state. Each developed to ensure an optimum combination of filter output is followed by a single order switched immunity to talk-off and tolerance to the presence of capacitor filter section which smooths the signals interfering frequencies (third tones) and noise. Provided signal 0 AA AAAA AA AAA AAA AA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAA AA AAAA AAAAAA AAAAA AAA AAA AAAAAA PRECISE AA AAA AA AAA A AAAA AAA AAAAA AAAA AAA AAA AAAA AAAA AAAAAA AAAAAAA AA AA AAA DIAL TONES AA AAA AA AAA AA AA AAA AA AAA AAAA AAA A AAA AAAA AAA AAA AA AAA AAAA AAA AAAA AA AAA AAAA AA AAA X=350 Hz 10 AAA AA AA AAA A AAA AAAA AAA AA AA AA AA Y=440 Hz AA AA AAA AAAA AAA AA DTMF TONES AA 20 AAA AA AA AAA AA A=697 Hz ATTENUATION AA AAA AA (dB) AA AAA AA B=770 Hz AA AAA AA C=852 Hz 30 AA D=941 Hz AAA AA AA AAA AA AA E=1209 Hz AA AA AA F=1336 Hz AA AA AAA AA G=1477 Hz 40 AAAAAAA AAAAA AA AAA AAAA AAA AA AAA AAA AA AAAAAA AAA AA A A AA AAA AA AAA AA AA AAA H=1633 Hz AAA AAA AAA AA AAAA AAA AAA AA AAAAA AA AAA AAA AAAA AAA AA AAA AA AAAAAAA AAA AA AA AAA AA AAA AA AAA AA AAAA AAA AAA A AAAA A AAA AA AA AAA AAAAA AA AAA AAA AA AAA AAA AA 50 AA AAA A AA AA A AA AA 1kHz X Y A B C D E F G H FREQUENCY (Hz) Figure 3 . low power consumption and high performance. StD Filter Section MT8870D/ MT8870D-1 tGTA=(RC)In(VDD/VTSt) tGTP=(RC)In[VDD/(VDD-VTSt)] Separation of the low-group and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass Figure 4 . which separates the high and low group tones. ISO2-CMOS MT8870D/MT8870D-1 Functional Description VDD The MT8870D/MT8870D-1 monolithic DTMF receiver offers small size.Filter Response 4-13 . The filter section also providing tolerance to small frequency deviations incorporates notches at 350 and 440 Hz for and variations. This check is they correspond to standard DTMF frequencies. Any swings at the frequencies of the incoming DTMF subsequent loss of signal condition will cause ESt to signals. Limiting is performed by high-gain the detector recognizes the presence of two valid comparators which are provided with hysteresis to tones (this is referred to as the “signal condition” in prevent detection of unwanted low-level signals. Decoder Section Steering Circuit Following the filter section is a decoder employing Before registration of a decoded tone pair. followed by a digital counting St/GT vc section which verifies the frequency and duration of ESt the received tones before passing the corresponding R code to the output bus.Basic Steering Circuit filters. A logic high on ESt causes vc (see Figure 4) to simulation by extraneous signals such as voice while rise as the capacitor discharges.

The contents of the output latch are made 7 H X H 0 1 1 1 available on the 4-bit output bus by raising the three 8 H X H 1 0 0 0 state control input (TOE) to a logic high. D H L H 0 0 0 0 A H H L undetected. 5 H X H 0 1 0 1 signalling that a received tone pair has been 6 H X H 0 1 1 0 registered. Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will ESt a) decreasing tGTP. St/GT R2 R1 ESt b) decreasing tGTA. the delayed steering output flag (StD) goes high. as well as rejecting signals too short to be considered valid. after a 4 H X H 0 1 0 0 short delay to allow the output latch to settle. GT continues to drive 3 H X H 0 0 1 1 high as long as ESt remains high. Design tGTA=(RPC1)In(VDD/VTSt) information for guard time adjustment is shown in C1 RP=(R1R2)/(R 1+R2) Figure 5.1 µF is Different steering arrangements may be used to select independently the guard times for tone tGTP=(RPC1)In[VDD/(VDD-VTSt)] present (tGTP) and tone absent (tGTA). Component L=LOGIC LOW. Thus. the simple steering Table 1. (tGTP<tGTA) maintain signal condition long enough to be registered. a relatively short t REC with a long t DO would be appropriate for extremely noisy tGTP=(R1C1)In[VDD/(VDD-VTSt)] environments where fast acquisition time and VDD immunity to tone drop-outs are required. The 9 H X H 1 0 0 1 steering circuit works in reverse to validate the 0 H X H 1 0 1 0 interdigit pause between signals. H=LOGIC HIGH. the * H X H 1 0 1 1 receiver will tolerate signal interruptions (dropout) # H X H 1 1 0 0 too short to be considered a valid pause. allows the designer to C H L H 1 1 1 1 tailor performance to meet a wide variety of system requirements. 11) and tREC is the minimum signal duration to be recognized by the receiver. Finally. A H L H 1 1 0 1 together with the capability of selecting the steering B H L H 1 1 1 0 time constants externally. Functional Decode Table circuit shown in Figure 4 is applicable.MT8870D/MT8870D-1 ISO2-CMOS condition is maintained (ESt remains high) for the Digit TOE INH ESt Q4 Q3 Q2 Q1 validation period (tGTP). ANY L X H Z Z Z Z latching its corresponding 4-bit code (see Table 1) 1 H X H 0 0 0 1 into the output latch. leaving R to be The value of t DP is a device parameter (see Figure selected by the designer. At this point the GT output is 2 H X H 0 0 1 0 activated and drives vc to VDD.Guard Time Adjustment 4-14 . Z=HIGH IMPEDANCE X = DON‘T CARE values are chosen according to the formula: t REC=t DP+tGTP tID=tDA+t GTA recommended for most applications. A value for C of 0. the output code Guard Time Adjustment B H H L will remain the same as the C H H L previous detected code In many situations not requiring selection of tone D H H L duration and interdigital pause. Alternatively. (tGTP>tGTA) Figure 5 . This facility. vc reaches the threshold (V TSt) of the steering logic to register the tone pair. Guard time adjustment also allows the designer to tailor system parameters R1 R2 such as talk off and noise immunity. This may be VDD tGTA=(R1C1)In(VDD/VTSt) necessary to meet system specifications which place C1 both accept and reject limits on both tone duration RP=(R1R2)/(R1+R2) St/GT and interdigital pause.

752 L1 mH .Differential Input Configuration The internal clock circuit is completed with the addition of an external 3. It stops the oscillator and the + functions of the filters. However. well as a bias source (VRef) which is used to bias the R2=60kΩ. - IN- Inhibit mode is enabled by a logic high input to the pin 5 (INH). Figure 7 . ISO2-CMOS MT8870D/MT8870D-1 Power-down and Inhibit Mode A logic high applied to pin 6 (PWDN) will power down MT8870D/ the device to minimize the power consumption in a C1 R1 IN+ MT8870D-1 standby mode.e.432 C1 pF 4. The OSC1 OSC2 oscillator output of the first device in the chain is coupled through a 30 pF capacitor to the oscillator input (OSC1) of the next device.37 ∆f % ±0. The output code will remain the same as the previous detected R5 GS code (see Table 1).579545 MHz crystal and is normally connected as shown in Figure 10 (Single. To OSC1 of next Ended Input Configuration).. Refer to Figure 7 C for details. 896. which permits the 1 2 adjustment of gain with the feedback resistor R 5. it is possible C MT8870D/MT8870D-1 to configure several MT8870D/MT8870D-1 devices X-tal employing only a single oscillator crystal.915 Qm . inputs at mid-rail. R5 the input pins are connected as shown in Figure 10 VOLTAGE GAIN (Av diff)= R1 with the op-amp connected for unity gain and VRef biasing the input at 1/2VDD. i. Figure 6 shows the INPUT IMPEDANCE differential configuration. precision balancing X-tal=3. In a single-ended configuration. B.2% Table 2.Oscillator Connection Parameter Unit Resonator R1 Ohms 10. Provision is made for connection of R2 R5 a feedback resistor to the op-amp output (GS) for R3 = R 2+R5 adjustment of gain. It inhibits the detection of tones C2 R4 representing characters A.e. R3 R2 Differential Input Configuration VRef The input arrangement of the MT8870D/MT8870D-1 Differential Input Amplifier provides a differential-input operational amplifier as C1=C2=10 nF R1=R4=R 5=100 kΩ All resistors are ±1% tolerance. 4-15 . and D. The problems associated with unbalanced loading are not a concern with the C=30 pF arrangement shown. i.579545 MHz capacitors are not required.5 kΩ All capacitors are ±5% tolerance.984 C0 pF 37. (ZINDIFF) = 2 R1 2 + ωc Crystal Oscillator Figure 6 . R3=37.. Recommended Resonator Specifications Note: Qm=quality factor of RLC model. 1/2ΠƒR1C1. Subsequent devices OSC2 OSC1 are connected in a similar fashion. C.

St/GT GS ESt R3 R2 VRef StD INH Q4 PWDN Q3 OSC 1 Q2 NOTES: X1 R1 = 102KΩ ± 1% OSC 2 Q1 VSS TOE R2 = 71. C1=100nF ± 5% Figure 8 . it is recommended to ESt R2=2. As shown in the diagram.1% VDD = 5. 8. 9 illustrates the use of tGTA=(R1C1)In(VDD/VTSt) MT8870D-1 device in a typical receiver system.Single-Ended Input Configuration for BT or CEPT Spec 4-16 .MT8870D/MT8870D-1 ISO2-CMOS Applications RECEIVER SYSTEM FOR BRITISH TELECOM SPEC POR 1151 tGTP=(RPC1)In[VDD/(VDD-VTSt)] The circuit shown in Fig.Non-Symmetric Guard Time Circuit VDD C1 DTMF C2 Input R1 MT8870D-1 IN+ VDD IN.579545 MHz ± 0.C2 = 100 nF ± 5% X1 = 3.0V ± 5% Figure 9 . For better performance. This condition can be VDD RP=(R1R2)/(R1+R2) attained by choosing a suitable values of R 1 and R 2 C1 to provide 3 dB attenuation. the component values of R3 and C2 are the guard time R1 R2 Notes: requirements when the total component tolerance is R1=368K Ω ± 1% 6%. such that -34 dBm input St/GT signal will correspond to -37 dBm at the gain setting pin GS of MT8870D-1.5KΩ ± 1% R3 = 390KΩ ±1 % C1.2M Ω ± 1% use the non-symmetric guard time circuit in Fig. BT Spec defines the input signals less than -34 dBm as the non-operate level.

2 2.5 V VDD=5. unless otherwise stated.3 2.5 V VDD = 5. P U VDD=5.0V 5 Low level input voltage VIL 1.0V 6 Input leakage current IIH/IIL 0.25 V 2 Operating Temperature TO -40 +85 °C 3 Crystal/Clock Frequency fc 3. Derate above 75 °C at 16 mW / °C. All leads soldered to board. DC Electrical Characteristics .6 V T 15 S VRef output voltage VRef 2.579545 MHz 4 Crystal/Clock Freq.03 V No load 12 O High level output voltage VOH VDD-0. S VDD=5. 4-17 .5 20 µA TOE (pin 10)=0.1 µA VIN=VSS or VDD I 7 N Pull up (source) current ISO 7.1 % ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Parameter Sym Min Typ‡ Max Units Test Conditions 1 DC Power Supply Voltage VDD 4.3 VDD+0.579545 MHz Y 4 High level input VIH 3.4 V P 14 U Output high (source) current IOH 0.0V 11 Low level output voltage VOL VSS+0.75 5.0 9. ISO2-CMOS MT8870D/MT8870D-1 Absolute Maximum Ratings† Parameter Symbol Min Max Units 1 DC Power Supply Voltage VDD 7 V 2 Voltage on any pin VI VSS-0. VDD = 5.VDD=5.7 V No load.0V 16 VRef output resistance ROR 1 kΩ ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. IN-) RIN 10 MΩ @ 1 kHz 10 Steering threshold voltage VTSt 2.Tolerance ∆fc ±0. Functional operation under these conditions is not implied.0 mA P 3 L Power consumption PO 15 mW fc=3.0V± 5%.4 0.5 mA VOUT=0.0V.Voltages are with respect to ground (VSS) unless otherwise stated.03 V No load U 13 T Output low (sink) current IOL 1.5 2.0V 9 Input impedance (IN+.0 5.0V. VSS=0V. PWDN=5. -40°C ≤ TO ≤ +85°C.8 mA VOUT=4.0 2. Recommended Operating Conditions .5 V VDD=5.3 V 3 Current at any pin (other than supply) II 10 mA 4 Storage temperature TSTG -65 +150 °C 5 Package power dissipation PD 500 mW † Exceeding these values may cause permanent damage. Characteristics Sym Min Typ‡ Max Units Test Conditions 1 S Standby supply current IDDQ 10 25 µA PWDN=VDD U 2 P Operating supply current IDD 3.0V 8 T Pull down (sink) current ISI 15 45 µA INH=5.4 2.

2.3.5% ± 2 Hz 2.8.9.3.7. VSS=0V.3. 4. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.3.5.0 Vpp Load ≥ 100 kΩ to VSS @ GS 9 Maximum capacitive load (GS) CL 100 pF 10 Resistive load (GS) RL 50 kΩ 11 Common mode range VCM 2.3.5.2. 6.25 V biased at VRef =2. Signal condition consists of nominal DTMF frequencies.11 ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.75 V ≤ VIN ≤ 4. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.12 4 Frequency deviation accept ±1. 3. 10.unless otherwise stated.9 6 Third tone tolerance -16 dB 2. 4-18 .30 MHz 8 Output voltage swing VO 4. Characteristics Sym Min Typ‡ Max Units Notes* Valid input signal levels (each -29 +1 dBm 1. 7. using Test Circuit shown in Figure 10. VDD =5.3. * NOTES 1.4. 8. Gain Setting Amplifier Characteristics Sym Min Typ‡ Max Units Test Conditions 1 Input leakage current IIN 100 nA VSS ≤ VIN ≤ VDD 2 Input resistance RIN 10 MΩ 3 Input offset voltage VOS 25 mV 4 Power supply rejection PSRR 50 dB 1 kHz 5 Common mode rejection CMRR 40 dB 0. For an error rate of better than 1 in 10.9. Bandwidth limited (3 kHz ) Gaussian noise. Tone pair is deviated by ±1. -40°C ≤ TO ≤ +85°C .6.5 Vpp No Load MT8870D AC Electrical Characteristics .5% 2.5.10 7 Noise tolerance -12 dB 2.9 1 tone of composite signal) 27.0V±5%. 11. tone pause= 40 ms.10 8 Dial tone tolerance +22 dB 2.12 3 Positive twist accept 8 dB 2. VSS=0V.2. 9. Tone duration= 40 ms. Guaranteed by design and characterization. Digit sequence consists of all DTMF tones.4.5.6.3. 12.5 %± 2 Hz. 5. Referenced to lowest level frequency component in DTMF signal. Both tones in composite signal have an equal amplitude.5.9.0V ±5%.VDD=5.MT8870D/MT8870D-1 ISO2-CMOS Operating Characteristics .9.6.5 869 mVRMS 1.5. -40°C ≤ TO ≤ +85°C . Referenced to the minimum valid accept level.5.6.3.9.9 5 Frequency deviation reject ±3.000.3.9 2 Negative twist accept 8 dB 2.5 V 6 DC open loop voltage gain AVOL 32 dB 7 Unity gain bandwidth fC 0.4.

3.5.11 ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.9 7 Third zone tolerance -18. Tone pair is deviated by ±1.12 8 Noise tolerance -12 dB 2.0V 2 Input Signal Level Reject 1.13 4 Positive twist accept 8 dB 2. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load. tone pause= 40 ms.3.9.6. 7. * NOTES 1. 9. Referenced to the minimum valid accept level.8.9. Both tones in composite signal have an equal amplitude. Signal condition consists of nominal DTMF frequencies. 6.8 869 mVRMS -37 dBm Tested at VDD=5.9 6 Frequency deviation reject ±3.6. 10 input DTMF tone level at -25dBm (-28dBm at GS Pin) interference frequency range between 480-3400Hz.3. Digit sequence consists of all DTMF tones. Characteristics Sym Min Typ‡ Max Units Notes* Valid input signal levels (each -31 +1 dBm Tested at VDD=5.2. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.0V 1 1.10 9 Dial tone tolerance +22 dB 2.13 5 Frequency deviation accept ±1.5%± 2 Hz 2.9.5 %± 2 Hz.000.5 dB 2. Referenced to Fig. Tone duration= 40 ms.9 mVRMS 3 Negative twist accept 8 dB 2. -40°C ≤ TO ≤ +85°C .3. Referenced to lowest level frequency component in DTMF signal.5% 2. VDD =5.5. Bandwidth limited (3 kHz ) Gaussian noise.3.4.6.4. Guaranteed by design and characterization.5.9.3. 4.2. using Test Circuit shown in Figure 10. 10.6. 8.9.3.3.9 tone of composite signal) 21.5.9 10.5.5. For an error rate of better than 1 in 10. 11. ISO2-CMOS MT8870D/MT8870D-1 MT8870D-1 AC Electrical Characteristics .0V±5%. 13. 4-19 . 12.4.5. 5.7.3. VSS=0V. 2.3.

are not device specifications.5831 MHz 15 C Clock input rise time tLHCL 110 ns Ext. T 50 pF S 11 Propagation delay (TOE to Q DISABLE) tPTD 300 ns load of 10 kΩ. Used for guard-time calculation purposes only. 3. using Test Circuit shown in Figure 10.5795 3.579545 MHz ± 0.R2=100KΩ ± 1% R3=300KΩ ± 1% VSS TOE C1.5 4 8.1% Figure 10 . -40°C ≤ To ≤ +85°C .C2=100 nF ± 5% X-tal=3. VSS=0V.Single-Ended Input Configuration 4-20 .MT8870D/MT8870D-1 ISO2-CMOS AC Electrical Characteristics . These. clock 18 Capacitive load (OSC2) CLO 30 pF ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.0V±5%.4 µs TOE=VDD P 10 U Propagation delay (TOE to Q ENABLE) tPTE 50 ns load of 10 kΩ. 2. tPU equals time from PDWN going low until ESt going high. The adjustable settings of these minimums and maximums are recommendations based upon network requirements. user adjustable parameters. *NOTES: 1.VDD=5.5 ms Note 1 I 3 M Tone duration accept tREC 40 ms Note 2 I 4 Tone duration reject tREC 20 ms Note 2 N 5 G Interdigit pause accept tID 40 ms Note 2 6 Interdigit pause reject tDO 20 ms Note 2 7 Propagation delay (St to Q) tPQ 8 11 µs TOE=VDD 8 O Propagation delay (St to StD) tPStD 12 16 µs TOE=VDD U 9 T Output data set up (Q to StD) tQStD 3. VDD C1 DTMF Input C2 R1 MT8870D/MT8870D-1 IN+ VDD IN. With valid tone present at input. 50 pF 12 P Power-up time tPU 30 ms Note 3 D 13 W Power-down time tPD 20 ms N 14 Crystal/clock frequency fC 3. Characteristics Sym Min Typ‡ Max Units Conditions 1 Tone present detect time tDP 5 11 14 ms Note 1 2 T Tone absent detect time tDA 0. St/GT R3 GS ESt R2 VRef StD INH Q4 PDWN Q3 OSC 1 Q2 NOTES: X-tal OSC 2 Q1 R1.5759 3. clock L 16 O Clock input fall time tHLCL 110 ns Ext. clock C 17 K Clock input duty cycle DCCL 40 50 60 % Ext.

D) OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE. E) TONE #n + 1 DETECTED. G) END OF TONE #n + 1 DETECTED. tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECED AS VALID tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION tID MAXIMUM TIME BETWEEN VALID DTMF SIGNALS. St/GT STEERING INPUT/GUARD TIME OUTPUT. tGTP GUARD TIME. Q1 -Q 4 4-BIT DECODED TONE OUTPUT. TONE DURATION INVALID. EXPLANATION OF SYMBOLS Vin DTMF COMPOSITE INPUT SIGNAL. StD DELAYED STEERING OUTPUT. tGTA GUARD TIME. TONE DURATION VALID. ISO2-CMOS MT8870D/MT8870D-1 D EVENTS A B C E F G tREC tREC tID tDO TONE TONE Vin TONE #n #n + 1 #n + 1 tDP AA AA AA tDA AA ESt tGTP tGTA VTSt St/GT tPQ tQStD HIGH IMPEDANCE Q1-Q4 DECODED TONE # (n-1) #n # (n + 1) tPSrD StD tPTE tPTD TOE EXPLANATION OF EVENTS A) TONE BURSTS DETECTED. OUTPUTS REMAIN LATCHED. ESt EARLY STEERING OUTPUT. TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY HIGH IMPEDANCE). DRIVES EXTERNAL RC TIMING CIRCUIT. TONE DECODED AND LATCHED IN OUTPUTS C) END OF TONE #n DETECTED. TONE ABSENT DURATION INVALID. OUTPUTS REMAIN LATCHED UNTIL NEXT VALID TONE. tDO MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL. B) TONE #n DETECTED. Figure 11 . TONE DURATION VALID. A LOW LEVEL SHIFTS Q1-Q4 TO ITS HIGH IMPEDANCE STATE. TONE ABSENT. TOE TONE OUTPUT ENABLE (INPUT). TONE ABSENT DURATION VALID. INDICATES DETECTION OF VALID TONE FREQUENCIES. tDP TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS. F) ACCEPTABLE DROPOUT OF TONE #n + 1.Timing Diagram 4-21 . TONE ABSENT DURATION VALID. TONE PRESENT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. tDA TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS. OUTPUTS REMIAN LATCHED UNTIL NEXT VALID TONE. OUTPUTS NOT UPDATED.

MT8870D/MT8870D-1 ISO2-CMOS NOTES: 4-22 .