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Abstract: New equations are proposed for frequency and amplitude of a ring oscillator.

The method is general enough to be used for all types of delay stages. Using exact large-

signal circuit analysis, closed form equations for estimating the frequency and amplitude of

a high frequency ring oscillator are derived as an example. The method takes into account

the effect of various parasitic capacitors to have better accuracy. Based on the loop gain of

the ring, the transistors may only be in saturation or experience cutoff and triode regions.

The analysis considers all of the above mentioned scenarios respectively and gives distinct

D

equations. The validity of the resulted equations is verified through simulations using

TSMC 0.18 µm CMOS process. Simulation results show the better accuracy of the

proposed method compared with others.

trigonometric equations, large-signal analysis.

SI high-speed integrated circuits,

of

1 Introduction1 inherent nonlinear behavior of the RO, the accuracy of

Voltage controlled oscillators (VCO) are most the equations is limited only for these assumptions.

commonly used building blocks in communication

applications like phase locked loops (PLL) and clock

and data recovery circuits [1]-[5]. Due to lower power

ive

area, the ring oscillator (RO) is investigated in these

applications. RO circuits must satisfy some

specifications such as area, power, speed and phase

noise, posing challenges to circuit and system designers.

ch

Also the correct amplitude and low phase noise are two

criteria to obtain a suitable performance for VCO in a

circuit. Obtaining the transfer function or any

knowledge about the amplitude and frequency of the (a)

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[12]. Some simple mathematical equations have been

presented for frequency of oscillation of the RO,

commonly using small signal analysis [13]-[16]. All of

these equations assume the RO as a linear small-signal

circuit model and derive the oscillation frequency by

adding the parasitic and secondary effects to the simple

ideal frequency equation. However, because of the

Paper first received 20 Oct. 2008 and in revised form 16 Dec. 2008.

* Payam M. Farahabadi is with the Integrated Systems Research

Laboratory, Electrical and Computer Engineering Department, Babol

University of Technology, Mazandaran, Babol.

E-mail: pmasoomi@stu.nit.ac.ir (b) (c)

** The Authors are with the Babol University of Technology,

Mazandaran, Babol. Fig 1. (a) N-stage single-ended RO. (b) Delay stage, with

E-mails: h_miare@nit.ac.ir, e_zadeh@nit.ac.ir. resistor load (c) Transistor Level load for delay stage.

March 2009

Because of the unity feedback gain, the open loop

transfer function is the same as the loop transfer

function. Total phase shift around the loop is written as

(3) and for ω = 0 it is written like equation (4) that

means the oscillator locks at DC level for even N, so the

odd number of stages is necessary for oscillation in

single-ended ring oscillators [4].

φ (ω ) = −π − N tan −1 (ω / ω0 ) (3)

⎧2π N = 2n

φ (ω ) ω =0 =⎨ (4)

⎩π N = 2n − 1

ωosc for odd N by (5). Equation (5) is most commonly

Fig. 2. Parasitic capacitors in a delay stage used for the oscillation frequency of an RO in analog

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microelectronic design text books [12].

Moreover, all of these equations cannot represent ωosc = ω0 tan(π / N ) (5)

the amplitude of the output waveform of the RO

exactly.

This paper presents a novel method to derive

equations for both amplitude and oscillation frequency

of the RO. In this method, the parameterized waveforms

of the outputs are estimated and closed-form equations

SI With simple simulations, one can find that this

analysis is incorrect if the amplitude of outputs does not

meet the small signal conditions. Also, small signal

analysis does not give any idea about the amplitude of

oscillation.

of

for unknown parameters are derived using differential Considering RO as a chain of delay stages is another

equations. The rest of the paper is as follows: SECTION method which is also commonly used by designers.

II introduces mathematical principle used to compute Assuming a delay of td for each stage, total phase shift

the frequency of oscillation and a brief review of the 2π must be provided in the period of 2Ntd. Therefore,

existing methods. Section III describes the proposed the oscillation frequency is as (6):

ive

1

and the frequency of oscillation. A new technique based f = (6)

on large signal analysis is presented to derive exact 2 N ⋅ td

equations for the output frequency and amplitude in this

section. Simulation results are compared with the values A method to improve the accuracy of previous

equation is proposed in [13]. The oscillation frequency

ch

method in section IV. Finally, section V gives the in this method is given by (7). The set of parameters

conclusions. that have been used in this method is listed in Table 1.

2 Literature Review on Frequency Equations

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A ring oscillator consists of a number of gain stages

td Delay time of each stage in the RO

in a unity gain feedback loop. To achieve oscillation,

Equivalent resistance of the PMOS load of each

the circuit must satisfy two Barkhausen’s criteria that RL

delay stage

mean the total phase shift and the gain of the feedback Load capacitance of the delay stage without

loop must be 2π and one respectively. An N-stage ring CL

parasitic elements

oscillator is shown in Fig. 1. Small signal analysis and ISS Tail current used in the differential delay stage

the open loop transfer function for this circuit is written Peak to peak amplitude of the output voltage

as below: VSW

waveform

1 N ( g m R) N

H ( s ) = [− g m ( R || )] = (−1) N

Cs s (1)

(1 + ) N The time delay per stage is defined as the total

ω0 change in differential output of the midpoint of the

transition. This method only considers differential RO

ω 0 = 1 / RC (2) and cannot be extended to single ended structures.

Reference [14] models each delay stage as a simple

RC circuit. Using (8), with Vout(initial) equals to VDD

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and Vout(final) equals to VDD-VSW, the delay per stage first it is assumed that all transistors are all in the

equals to RLCLln2. Hence the frequency is given by (9). saturation region. This is a common assumption in all

the presented methods for representing the frequency of

1

f = (7) an RO. The proposed method is general enough to be

2 N ⋅ td applied on any structures but in this paper it is focused

on an N-stage single-ended ring oscillator with common

Vout (t ) = Vout ( final ) + [Vout (initial ) − Vout ( final )] source stages. More complete equations for the other

t (8) types of ring oscillator can be developed with the same

× exp( − ) analysis procedure. Assuming saturation for transistors,

RC

the differential equation of the circuit is obtained by a

Kirchhoff’s Current Law (KCL) at each drain node (Fig.

1

f = (9) 1(a)). Fig. 3 shows one common source stage of an RO

2 NRLCL ⋅ ln 2

with a resistor load and the currents used in mentioned

The method proposed in [15] assumes a ramp input KCL equation.

to find delay to time constant to obtain (10). Equations (12) and (13) represent a nonlinear N-

dimensional differential system. The effect of parasitic

D

1 capacitors that are shown in Fig. 2 is written as (14) for

f = (10)

2 N (0.8) R ⋅ (C DBn + C DBp + CGDn + CGDp + C L ) more accurate estimation. Pure sinusoid waveform as

(15) for the outputs is the key simplifying assumption

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This equation can be adapted for single-ended RO that leads to straightforward analysis along with

considered in this paper. The transistor parasitic accurate results. Assuming this, the analysis is devoted

elements that used in this equation are gate-drain, gate- to find amplitude, A, DC level, B, and frequency, ω.

bulk and drain-bulk capacitors. Parasitic capacitors in a Although the output of an RO will not be purely

delay stage are shown in Fig. 2. sinusoidal, the frequency representation of a practical

Another method to derive an equation for the

of

RO output shows that it is a reasonable assumption [2],

oscillation frequency of only differential ring oscillator [8].

is proposed in [16]. The final equation for obtaining the

frequency is as (11) which is similar to (7), but a large ⎧ V1 − VDD dV

⎪node1 : + C 1 + K (VN − Vth )2 = 0

signal analysis is used for calculating the value of ⎪ R dt

⎪node : 2 −

ive

capacitors accurately. V V dV

⎪ 2

DD

+ C 2 + K (V1 − Vth )2 = 0

⎨ R dt (12)

f =

I SS ⎪ M

⎡ C jn Ad n ⎤ ⎪

⎢C L + C gdp + + ⎥ ⎪ VN − VDD dV

⎢

V

(1 + DD ) mjn ⎥ ⎪⎩nodeN : + C N + K (VN −1 − Vth ) 2 = 0

⎢ pb n ⎥ R dt

ch

⎢ C Pd ⎥

π

2NV SW ×⎢ jswn n

+ (1 + cos( ))W nC gdon +⎥ (11)

1 W

⎢ V DD mjswn ⎥

⎢ (1 + ) N

⎥ K= µnCox ( ) (13)

pbswn 2 L

⎢ ⎥

⎢C jp Ad p + C jswp Pd n ⎥

⎢ ⎥

C = CL + Cgdp + Cgdn + Cdbp + Cdbn

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⎣ ⎦ (14)

HSPICE parameters of transistors. This method is more

accurate than other presented methods but it cannot The phase relation among the outputs of an N-stage

predict the amplitude or frequency when the transistors RO is shown in Fig. 4. Assuming equation for V2(t) as

change the operation region during oscillation. (15), the output of the first stage can be written as (16)

considering the phase relations in Fig. 4.

3 The Proposed Method T T

3.1 General Procedure V1 (t ) = V2 (t + (− ))

2 2N

The method proposed in this paper is based on the (16)

( N − 1)π

exact differential equations governing on the RO. These = B + A cos(ωt + )

N

equations are simply obtained using circuit analysis

methods. The proposed method presents exact equations Using a bit mathematical operations, equation (12),

to find the frequency, amplitude and DC level of the (15) and (16) can be combined and reduced to (17); the

output waveform of an RO while the last methods only basic trigonometric equation of the proposed method.

give approximate expressions for “td” or frequency. At

March 2009

explicitly. The amplitude is obtained in term of B and

other parameters as (21). Knowing the B and A, the

unknown frequency of oscillation is written as (22).

1

B =V +

th π (20)

2 RK cos

N

VDD − B

− K ( B − Vth ) 2

A= R (21)

K cos 2 (π / N )

B − VDD

+ K ( B − A sin(π / N ) − Vth ) 2

f = R (22)

Fig. 3. Definition of currents for KCL in a delay stage. 2π CA

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frequency, amplitude and DC level of an N-stage single-

ended ring oscillator just knowing the circuit

parameters. Equation (21) shows that the amplitude is

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just proportional to the circuit parameters except

capacitors. Also the frequency is inversely proportional

to the C and R in (22). Note that the assumptions here

are the output waveform is like a sinusoid and the

transistors are all in saturation region. To verify the

of

analysis above the following two conditions should be

met.

I. The transistors should not meet triode region that

means Vn−1 (t ) < Vn (t ) − Vth .

II. The transistors should not meet cutoff region that

ive

means B − A ≥ Vth .

Fig. 4. Phase relation between waveforms.

Defining the voltage across the Gate-Drain junction

in first delay stage as (23), if the first condition is

satisfied, the transistors remain in saturation region.

B + A cos ωt − VDD Using the maximum points as an additional condition,

− ωCA sin ωt +

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( N − 1)π

K ( B + A cos(ωt + ) − V )2 = 0 (25) must be satisfied for using the proposed equations.

N th

Otherwise, transistors experience the cutoff or triode

Equation (17) holds for every time especially for regions, so a more general analysis should be

performed.

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beneficial equations in (19). ( N − 1)π

V1 (t ) − V2 (t ) = A[cos(ωt + ) − cos ωt ]

I ) sin ωt = −1 , cos ωt = 0 N

II ) sin ωt = 0 , cos ωt = 1 (1 − 1)π ( N − 1)π

(18) ωt + + ωt ωt + − ωt

= −2 A sin N N (23)

III ) sin ωt = 0 , cos ωt = −1 sin

2 2

( N − 1)π ( N − 1)π

= −2 A sin(ωt + )sin( )

⎧ B − VDD π 2N 2N

⎪I ) + ωCA + K ( B − A sin − Vth ) 2 = 0

⎪ R N

⎪ B + A − V π ( N − 1)π π

⎨ II )

DD

+ K ( B − A cos − Vth ) 2 = 0 (19) max{V1 (t ) − V2 (t )} = 2 A sin( ) = 2 A cos (24)

⎪ R N 2N 2N

⎪ B − A − VDD π

⎪ III ) + K ( B + A cos − Vth ) 2 = 0

⎩ R N 2 A cos(π / N ) < Vth (25)

With simple calculations, the unknowns of (19) can

be obtained. At the first step, the DC level of the output

is obtained in term of circuit parameters as (20)

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3.2 Analytical Equations for The Case that critical points is written as (28)—(30) which are at the

Transistors Enter Triode region bottom of the next page. There are just two unknowns in

Closed-form equations for the cases that transistors both algebraic equations (28) and (29). Hence, the DC

meet the triode or cutoff region can be easily obtained level, B, and the amplitude, A, are obtained using a

with the same analysis. Fig. 5 illustrates the sample simple numerical solution method. Using the obtained

output voltages when the transistors meet both triode amplitude and DC level from (28) and (29) in (30), a

and saturation region during an oscillation period. This closed-form equation for frequency of oscillation is

plot gives the evidence that the output voltage of an RO written as (31). This expression is shown at the bottom

can be assumed as a sinusoid waveform if transistors of the next page.

meet the triode region yet. All the published methods

for estimating the frequency of an RO have not

represented the acceptable accuracy for the cases that

the operating region changes while this paper presents

closed-form equations for both amplitude and frequency

of the transistors meeting all operating regions.

The analysis proposed here is again based on the

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KCL equations at the output of each delay stage. These

equations can be written as (26).

⎧ V1 − VDD

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dV

⎪ R + C 1 + iD1 (t ) = 0

⎪ dt

⎪ 2V − V dV

⎪

DD

+ C 2 + iD2 (t ) = 0

⎨ R dt (26)

⎪M Fig. 5. Sample output voltages for the case that transistors

⎪

of

meet both triode and saturation regions during oscillation.

⎪ VN − VDD dV

⎪⎩ + C N + iDN (t ) = 0

R dt iD 2 ( t ) =

⎪ − ωCA sin ωt

The output voltage is assumed sinusoid waveform as R

ive

⎪ N −1

(15) to make the problem traceable. For instance, the ⎪+2K {[B + A cos(ωt + π ) −V th ](B + A cos ωt )

output of the second stage is considered as (15), so the ⎪ N

⎪− ( B + A cos ωt ) } = 0

2

first stage output is written as (16). The unknowns here for V 1 (t ) > V 2 (t ) +V th

⎪⎪ 2 (27)

are the frequency of oscillation, the output voltage ⎨

⎪ B + A cos ωt −V DD

amplitude and DC level of output that are f, A and B − ωCA sin ωt

ch

⎪ R

respectively. Considering the quadratic law between ⎪ N −1

Drain current and the Gate-Source voltage for the ⎪+ K ( B + A cos(ωt + π ) −V th ) 2 = 0

⎪ N

second transistor, M2, the Drain current is written as ⎪ for V 1 (t ) <V 2 (t ) +V th

(27) for second stage. As shown in Fig. 5, the outputs ⎪⎩

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these outputs cannot be obtained from any of presented B − A −V DD

expressions. Also, there is no analysis to estimate the ωt = π ⇒V 2 (t ) is minimum ⇒

R (28)

amplitude of the output waveform. In this section, each π (B − A ) 2

transistor may meet the both triode and saturation +2K {[B + A cos( ) −V th ](B − A ) − }= 0

N 2

regions during one period of oscillation, so the equation

for Drain current of second stage is written as (27) that π

ωt = − ⇒V 1 (t ) is minimum ⇒

is shown in bottom of this page. Substituting (26)-(27), N

the N-dimensional equations are obtained. Solving the π

B + A cos( ) −V DD

N π (29)

obtained equations using analytical rules is difficult, so + ωCA sin( )+

the critical points are considered to make the problem R N

2π

traceable. Choosing these critical points is based on K (B − A cos( ) −V th )2 = 0

having knowledge about the times when transistors are N

exactly in the triode or saturation region. For example, ωt = 0 ⇒V 2 (t ) is maximum ⇒

for the times ωt = 0, the output V2(t) is at maximum as it B + A −V DD π (30)

is shown in Fig. 5, so the transistor M2 is exactly in + K (B + A cos( ) −V th )2 = 0

R N

saturation region. The equations resulted from some

March 2009

π 2π

B + A cos( ) −V DD + RK (B − A cos( ) −V th )2

f = N N

π (31)

2π RCA sin( )

N

Transistors Enter Cut-Off region

Each transistor of an RO experiences the cut-off

region in a period of oscillation if the loop gain

increases. This occurs when the expression (32) is not

satisfied.

B − A ≤ Vth (32)

where A, B are obtained by solution of (28) and (29). Fig. 6. A period of oscillation of output voltage for the case

Fig. 6 shows a period of oscillation in the case that the that the transistors experience all possible regions.

expression (32) is not satisfied. This plot shows the all

operating regions that a transistor may enter under this

D

condition. Fig. 7 shows the circuit model for a delay

stage while each state occurring. At the beginning of the

period, transistor is off because of the low voltage at its

gate connection, so the circuit is modeled as an RC

circuit with a time constant. The transistor meets the

saturation region when the voltage at the Gate

connection overcomes the threshold voltage, Vth. In this

state, the transistor can be modeled as a voltage

SI

of

controlled current source (VCCS) and increasing the

gate voltage increases the current and causes the charge

of the capacitor decreases. If the Drain-Gate voltage of (a) (b)

the transistor becomes higher than threshold voltage,

Vth, transistor experiences deep triode and triode region

ive

respectively.

Here, the transistor can be modeled as a small

voltage controlled resistor that is parallel with load

resistor, R, so the output voltage decreases with a small

time constant because of small load resistor. Calculating

ch

and not necessary for the case.

1

A simple method based on a novel approximation is rd =

K [VN −1 (t ) − Vth ]

proposed here. Because of short times in each period

that transistors are in saturation and deep triode, it can

Ar

(c)

be assumed that transistors are only in triode and cutoff.

Hence, the output voltage is assumed as a triangular-like Fig. 7. Circuit models for each state occur in Fig.. 6. a)

periodic waveform. The output voltage at each stage is transistor off b) transistor is in saturation c) triode and deep

written as (33). triode region

VN (t ) = ⎨ DD (33)

⎩0 for t m < t < T

waveform for a three stage RO under this condition.

Because of the phase relation between outputs, each

transistor can experience the off region for only T/N of

time at the end of each period. Hence, the unknown

parameters, tm, Vm, that are shown in Fig. 8 can be easily

obtained. Equation (33) can be written for V2(t) at the

time tm as (34) and because of the phase relation, the Fig. 8. A period of oscillation of output voltage for the case

output V1(t) is written as (35). that transistors meet all regions.

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this, the size of the devices is changed in a wide range

V2 (t m ) = VDD (1 − e −tm / RC ) (34) to test the circuit in different scenarios. For instance, the

smaller transistor results in the smaller loop gain so that

V1 (t ) = V2 (t − T / N ) = V DD (1 − e − (tm −T / N ) / RC ) (35) the outputs are fine sinusoid wave forms. The frequency

is plotted as a function of CL in this case. Second

An additional condition here is the voltage at gate- experiment is performed while the both number of delay

drain junction must satisfy (36) for edge of triode stages and the sizes of the transistors are changed. In the

region. This condition occurs at time tm referring (37), third experiment, the amplitude and the frequency of

(38) and Fig. 8. Substituting (34)-(37) the unknown oscillation are measured while load resistor is varied

parameters can be defined as a function of T. Therefore, under simulation steps. These simulations are repeated

the only unknown parameter after all is period of output for the cases that transistors change the operation

waveform, T. region. The devices are larger to have more amplitude,

V2 (tm ) − V1 (tm ) = Vth (36) so the change of operation regions is guaranteed in each

scenario.

T

− ( tm − )/ RC Table 2. Comparison between simulation results and

VDD [1 − e−tm / RC ] − VDD [1 − e N

] = Vth (37)

D

calculated unknown parameters when devices enter the cutoff

region

VDD (eT / NRC − 1)

tm = RCLn (38)

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Vth Load Simulation results Calculated values

Capacitor

The same expression can be used for V1(t) at the CL (pF) Period (T) tm Period (T) tm

(nsec) (nsec) (nsec) (nsec)

time T as (39)-(40). Substituting (38)-(41) result in an

1 1.11 0.63 0.90 0.58

equation for the period of time, T, as (42).

2 1.22 0.71 1.13 0.70

of

( N − 1)

V1 (T ) = V2 (T − T / N ) = V2 [ T ] = Vm (39) 3 1.43 0.82 1.36 0.84

N

4 1.65 0.93 1.58 0.97

5 1.81 1.02 1.80 1.11

Vm = V2 (tm ) = VDD − Vth (eT / NRC − 1)−1 (40)

6 1.96 1.10 2.03 1.24

ive

VDD [1 − exp( − . )] = Vm (41) 8 2.30 1.30 2.48 1.50

N RC

9 2.44 1.40 2.69 1.65

N VDD 10 2.59 1.63 2.92 1.80

T= RC ln( )

ch

(42)

N −1 VDD − Vm Peak

Voltage 1.12 Volts 1.4 Volts

(Vm)

4 Simulation Versus Analytical Results

To evaluate the proposed method and compare with Table 3. Details of Technology, Supply Voltage, Load

Ar

competitive methods, a test benchmark is created in this Capacitor Range, Size and Threshold Voltages of Transistors

section using Advanced Design System software. The Technology TSMC 0.18 µm

TSMC 1.8 V, 0.18 µm CMOS process have been used Supply Voltage 1.8 V

in simulations. Table 3 gives the details of technology, Lmin 0.18 µm

supply voltage, load capacitor, size and threshold µn.Cox 275.6×10-6 F/(V.s)

voltages of the transistors used in simulations. First, a

Capacitor (max/min) 10 pF / 1 pF

single-ended ring oscillator is simulated using different

values of load capacitor for different oscillation Size for Saturation (W/L) 50

frequencies. The sizes of the transistors were chosen Size for Triode (W/L) 80

here such that the circuit would oscillate over a wide Size for Cut-off (W/L) 300

range of capacitor. Different size of transistors is chosen VTN (normal/low) 0.47 V / 0.267 V

to obtain all possible conditions in each experiment VTP (normal/low) -0.46 V / -0.37 V

because of the direct relation between the amplitude of

outputs and the loop gain. Higher loop gain causes

The calculated frequency by the proposed equations,

higher amplitude; consequently more nonlinear

(20), (21) and (22) when transistors are in the saturation

behavior and different waveforms are available. Due to

region are compared with the simulation results

March 2009

obtained by the other methods. These comparisons are one stage. The unknown parameters of the estimated

illustrated in Fig. 9 which shows the accuracy of output are calculated by equations (38), (39), (43).

proposed method. The equation that has been presented Estimated results and actual values undergoes the

in [12] is inaccurate and it was eliminated from the variation of output capacitance are given in Table 2. In

results to have better comparison. Fig. 10 illustrates the this experiment, the unknown parameters of the

simulation results compared with analytical equations estimated outputs are calculated by equations (38), (39),

(28), (29) and (31) for the case that the transistors meet (43) and a comparison between estimated and real

both saturation and triode region during oscillation. A values shows the accuracy of analytical equations.

numerical method using MATLAB software is used to Based on the presented plots, it is evident that the

solve the equations (28) and (30) to obtain the equations proposed in this paper appear to be more

amplitude and DC level of output. For the case that accurate for all simulations in comparison with the

transistors enter the cutoff region, Fig. 11 shows the others.

simulation results and the estimated output waveform of

13

12 eq.(6) eq.(9) eq.(10) Simulation This work

D

eq.(6)

11

7

10 eq.(9)

6.5

9

eq.(10) 6

Frequency (GHz)

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5.5

7

Frequency (GHz)

Simulation

6 5

This work

5 4.5

4 4

3 3.5

2 3

1

2.5

of

0

2

1 2 3 4 5 6 7 8 9 10

21 22 23 24 25 26

Load Capacitor CL (pf)

Load Resistor RD (Ω)

(a) (b)

ive

1 4.5

eq.(6)

0.9 Simulation 4

eq.(9)

0.8 This work

3.5

Frequency (GHz)

eq.(10)

0.7 simulation

3

Amplitude (Volt)

2.5

ch

0.5

2

0.4

1.5

0.3

1

0.2 3 5 7

0.1 50 15 12

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Transistors Sizes (W/L)

1 2 3 4 5 6

(c) (d)

Fig. 9. Comparison of simulation and analysis results when transistors are in saturation region.

(a) Frequency versus CL (b) Frequency versus RD (c) Amplitude versus RD (d) Frequency versus (N, W/L)

This paper has presented a novel method to derive provided for all operation regions of transistors but the

exact analytical equations for the amplitude and effect of channel length modulation and more parasitic

frequency of ring oscillators. The output signal is element are challenging points that limits the analysis.

assumed a sinusoidal waveform where the unknowns These equations will be of significant to be used in

are amplitude, frequency and DC level. Applying the guiding ring oscillator design. It also can provide

large signal analysis, the equations derived in this paper designers more insight not only into design

represent both amplitude and frequency more accurately methodology, but also for estimating the phase noise,

than previous equations for a ring oscillator. Nonlinear injection locking, etc; future works one may perform.

behavior of an oscillator can be explained easily with

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14

eq.(6) eq.(6) eq.(9) eq.(10) Simulation This work

3

12 eq.(9)

eq.(10)

10 Simulation 2.5

This work

Frequency (GHz)

8 2

Frequency (GHz)

6 1.5

4

1

2

0.5

0

1 2 3 4 5 6 7 8 9 10 0

Load Capacitor -CL (pf) 20 21 22 23 24 25

(a) (b)

D

5

1 eq.(6)

Simulation 4.5

eq.(9)

This work 4

0.8 eq.(10)

3.5

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Simulation

Frequency (GHz) 3

Amplitude (Volt)

This work

0.6 2.5

0.4 1.5

0.5

0.2

of

0

3 5 7

0

20 21 22 23 24 25 80 40 20

size of transistors (W/L)

(c) (d)

ive

Fig. 10. Comparison of simulation and analysis results when transistors meet the triode region

(a) Frequency versus CL (b) Frequency versus (N, W/L) (c) Amplitude versus RD (d) Frequency versus RD

1.4

ch

2001.

1.2

[3] Savoj J. and Razavi B., "A 10 Gb/s CMOS clock

output voltage (Volt)

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0.8 Simulation Output

phase detector," IEEE J. Solid-State Circuit, Vol.

0.6 36, pp. 761–768, May 2001.

Ar

0.2 IEEE J. Solid-State Circuits, Vol. 32, pp. 730–735,

0.0 May 1997.

[5] Sun L. and Kwasniewski T. A., "A 1.25-GHz 0.35-

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30

3.35

3.40

3.45

3.50

3.55

3.60

3.65

3.70

3.75

3.80

3.85

3.90

3.95

4.00

4.05

4.10

4.15

4.20

4.25

Fig. 11. Sample output voltage of an RO and the estimated ring oscillator," IEEE J. Solid-State Circuits, Vol.

waveform for the case that transistors meet cut-off region. 36, pp. 910–916, June 2001.

[6] Srivastava S. and Roychowdhury J., "Analytical

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[1] Hesieh Y.B. and Kao Y.H., "A Fully integrated ring oscillators," IEEE Trans. Circuits Syst. I,

spread-spectrum clock generator by using direct Regular Papers, Vol. 54, pp. 2321-2329, October

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D

from Sharif University of Technology in

14. 1994 and M.Sc. from Tarbiat Modares

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SI in 2002 respectively. Since 2003 He has

been member of Electrical and

Electronics Engineering Faculty of

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research interests are analog CMOS

integrated circuit design, RF microelectronics, Image

of

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[16] Docking S. and Sachdev M., "A method to drive an Ataollah Ebrahimzadeh received the

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1995 and M.Sc. from Amirkabir

oscillators," IEEE Trans. Circuits Syst. I, Vol. 50,

University of Technology in 1999 and

ive

Mashad in 2006 respectively. Since

2006 He has been member of Electrical

and Electronics Engineering Faculty of

Babol University of Technology. His

research interests is digital signal-type

ch

Ar

www.SID.ir

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