TDA8922C

2 × 75 W class-D power amplifier
Rev. 01 — 7 September 2009 Product data sheet

1. General description
The TDA8922C is a high-efficiency Class D audio power amplifier. Typical output power is 2 × 75 W with a speaker load impedance of 6 Ω. The TDA8922C is available in both HSOP24 and DBS23P power packages. The amplifier operates over a wide supply voltage range from ±12.5 V to ±32.5 V and features low quiescent current consumption.

2. Features
I Pin compatible with TDA8950/20C for both HSOP24 and DBS23P packages I Symmetrical operating supply voltage range from ±12.5 V to ±32.5 V I Stereo full differential inputs, can be used as stereo Single-Ended (SE) or mono Bridge-Tied Load (BTL) amplifier I High output power in typical applications: N SE 2 × 75 W, RL = 6 Ω (VDD = 30 V; VSS = −30 V) N SE 2 × 60 W, RL = 8 Ω (VDD = 30 V; VSS = −30 V) N BTL 1 × 155 W, RL = 8 Ω (VDD = 25 V; VSS = −25 V) I Low noise I Smooth pop noise-free start-up and switch off I Zero dead time switching I Fixed frequency I Internal or external clock I High efficiency I Low quiescent current I Advanced protection strategy: voltage protection and output current limiting I Thermal FoldBack (TFB) I Fixed gain of 30 dB in SE and 36 dB in BTL applications I Fully short-circuit proof across load I BD modulation in BTL configuration

3. Applications
I I I I DVD Mini and micro receiver Home Theater In A Box (HTIAB) system High-power speaker system

NXP Semiconductors

TDA8922C
2 × 75 W class-D power amplifier

4. Quick reference data
Table 1. General VDD VSS Vth(ovp) Iq(tot) supply voltage negative supply voltage Operating mode Operating mode
[1] [2]

Quick reference data Conditions Min 12.5 65 Typ 30 40 Max 32.5 70 70 Unit V V mA

Symbol Parameter

−12.5 −30

−32.5 V

overvoltage protection threshold VDD − VSS voltage total quiescent current Operating mode; no load; no filter; no RC-snubber network connected Tj = 85 °C; LLC = 22 µH; CLC = 680 nF (see Figure 10); RL = 6 Ω; THD + N = 10 %; VDD = 30 V; VSS = −30 V Tj = 85 °C; LLC = 22 µH; CLC = 680 nF (see Figure 10); RL = 8 Ω; THD + N = 10 %; VDD = 25 V; VSS = −25 V
[3]

Stereo single-ended configuration Po output power 75 W

Mono bridge-tied load configuration Po output power
[3]

-

155

-

W

[1] [2] [3]

VDD is the supply voltage on pins VDDP1, VDDP2 and VDDA. VSS is the supply voltage on pins VSSP1, VSSP2, VSSA and VSSD. Output power is measured indirectly; based on RDSon measurement; see Section 13.3.

5. Ordering information
Table 2. Ordering information Package Name TDA8922CJ TDA8922CTH DBS23P HSOP24 Description plastic, heatsink small outline package; 24 leads; low stand-off height Version SOT566-3 plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1 Type number

TDA8922C_1

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 01 — 7 September 2009

2 of 40

NXP Semiconductors

TDA8922C
2 × 75 W class-D power amplifier

6. Block diagram
VDDA
3 (20)

n.c.
10 (4)

STABI PROT 18 (12) 13 (7)

VDDP2
23 (16)

VDDP1
14 (8) 15 (9)

BOOT1

IN1M IN1P

9 (3) 8 (2) INPUT STAGE PWM MODULATOR SWITCH1 CONTROL AND HANDSHAKE DRIVER HIGH 16 (10) DRIVER LOW VSSP1 OSCILLATOR MODE MANAGER TEMPERATURE SENSOR CURRENT PROTECTION VOLTAGE PROTECTION OUT1

n.c. OSC MODE

11 (5) 7 (1) 6 (23)

mute STABI

TDA8922CTH (TDA8922CJ)

VDDP2 22 (15) BOOT2

SGND

2 (19) mute CONTROL SWITCH2 AND HANDSHAKE DRIVER HIGH 21 (14) DRIVER LOW 17 (11) 20 (13) OUT2

IN2P IN2M

5 (22) 4 (21) INPUT STAGE PWM MODULATOR

1 (18)

12 (6)

24 (17)

19 (-)

010aaa549

VSSA

n.c.

VSSD

n.c.

VSSP1

VSSP2

Pin numbers in brackets refer to type number TDA8922CJ.

Fig 1.

Block diagram

TDA8922C_1

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 01 — 7 September 2009

3 of 40

NXP Semiconductors

TDA8922C
2 × 75 W class-D power amplifier

7. Pinning information
7.1 Pinning

OSC IN1P IN1M n.c. n.c. n.c. PROT VDDP1 BOOT1

1 2 3 4 5 6 7 8 9

OUT1 10 VSSP1 11 VSSD 24 VDDP2 23 BOOT2 22 OUT2 21 VSSP2 20 n.c. 19 STABI 18 VSSP1 17 OUT1 16 BOOT1 15 VDDP1 14 PROT 13
010aaa546

1 2 3 4 5

VSSA SGND VDDA IN2M IN2P MODE OSC IN1P IN1M

STABI 12 VSSP2 13 OUT2 14 BOOT2 15 VDDP2 16 VSSD 17 VSSA 18 SGND 19 VDDA 20 IN2M 21 IN2P 22 MODE 23

TDA8922CJ

TDA8922CTH

6 7 8 9

10 n.c. 11 n.c. 12 n.c.

010aaa547

Fig 2.

Pin configuration TDA8922CTH

Fig 3.

Pin configuration TDA8922CJ

TDA8922C_1

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 01 — 7 September 2009

4 of 40

NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 7. 01 — 7 September 2009 5 of 40 .2 Pin description Table 3. the digital PWM signal is fed to a control and handshake block and to high. Symbol VSSA SGND VDDA IN2M IN2P MODE OSC IN1P IN1M n.c.and low-side driver circuits. Functional description 8. 2009. TDA8922C_1 © NXP B. This level-shifts the low-power digital PWM signal from a logic level to a high-power PWM signal switching between the main supply lines. Product data sheet Rev.c. All rights reserved. the audio input signal is converted into a digital Pulse Width Modulation (PWM) signal using an analog input stage and a PWM modulator. For each channel. VSSP2 OUT2 BOOT2 VDDP2 VSSD Pin description Pin TDA8922CTH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TDA8922CJ 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 negative analog supply voltage signal ground positive analog supply voltage channel 2 negative audio input channel 2 positive audio input mode selection input: Standby. PROT VDDP1 BOOT1 OUT1 VSSP1 STABI n. Mute or Operating mode oscillator frequency adjustment or tracking input channel 1 positive audio input channel 1 negative audio input not connected not connected not connected decoupling capacitor for protection (OCP) channel 1 positive power supply voltage channel 1 bootstrap capacitor channel 1 PWM output channel 1 negative power supply voltage decoupling of internal stabilizer for logic supply not connected channel 2 negative power supply voltage channel 2 PWM output channel 2 bootstrap capacitor channel 2 positive power supply voltage negative digital supply voltage Description 8.1 General The TDA8922C is a two-channel audio power amplifier that uses Class D technology. n.c. see Figure 1.c. A second order low-pass filter converts the PWM signal to an analog audio signal that can be used to drive a loudspeaker.V. n. To drive the output power transistors.

low distortion and low quiescent currents. 2009. along with some control logic. All rights reserved. The time constant required to apply the DC output offset voltage gradually between Mute and Operating mode levels can be generated using an RC network connected to pin MODE. the bias current is at a maximum. An example of a circuit for driving the MODE pin. an analog feedback loop and a differential input stage.6 kΩ 470 Ω MODE TDA8922C 5. If the capacitor was omitted. Example of mode selection circuit TDA8922C_1 © NXP B. all reference sources.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier The TDA8922C single-chip Class D amplifier contains high-power switches. de-muted and can deliver an output signal A slowly rising voltage should be applied (e. optimized for optimal pop noise performance. The bias-current setting of the (VI converter) input stages is related to the voltage on the MODE pin. the bias-current setting of the VI converters is zero (VI converters are disabled). In Operating mode. timing and handshaking between the power switches. Each of the two audio channels contains a PWM modulator. the very short switching time constant could result in audible pop noises being generated at start-up (depending on the DC output offset voltage and loudspeaker used). Product data sheet Rev. The two independent amplifier channels feature high output power. high efficiency. 01 — 7 September 2009 6 of 40 . an advanced protection strategy has been implemented to provide overvoltage. The TDA8922C also contains circuits common to both channels such as the oscillator. +5 V 5. In Mute mode. They can be connected in the following configurations: • Stereo Single-Ended (SE) • Mono Bridge-Tied Load (BTL) The amplifier system can be switched to one of three operating modes using pin MODE: • Standby mode: featuring very low quiescent current • Mute mode: the amplifier is operational but the audio signal at the output is suppressed by disabling the voltage-to-current (VI) converter input stages • Operating mode: the amplifier is fully operational. overtemperature and overcurrent protection. the mode interface and a digital timing manager.V.g. is shown in Figure 4. drivers.6 kΩ 10 µF mute/ operating S1 standby/ operating S2 SGND 010aaa583 Fig 4. To ensure maximum system robustness. via an RC network) to pin MODE to ensure pop noise-free start-up.

An overview of the start-up timing is provided in Figure 5. The audio signal becomes available after a second delay of 50 ms. 01 — 7 September 2009 7 of 40 . audio output (1) modulated PWM VMODE 50 % duty cycle operating > 4.V. Upper diagram: When switching from Standby to Mute. All rights reserved. Lower diagram: When switching directly from Standby to Operating mode. The audio signal will become available once VMODE reaches the Operating mode level (see Table 8).2 V 2. it is recommended that the time-constant applied to pin MODE be at least 500 ms for the transition between Standby and Operating modes. there is a delay of 100 ms before the outputs start switching. it is recommended that the time constant applied to pin MODE be at least 350 ms for the transition between Mute and Operating modes. Timing on mode selection input pin MODE TDA8922C_1 © NXP B. To start-up pop noise-free. there is a delay of approximately 100 ms before the output starts switching. Fig 5. To start-up pop noise-free. 2009.1 V < VMODE < 2.1 V < VMODE < 2. Product data sheet Rev. but not earlier than 150 ms after switching to Mute.2 V 2.9 V mute 0 V (SGND) standby 100 ms 50 ms > 350 ms time audio output (1) modulated PWM VMODE 50 % duty cycle operating > 4.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier To ensure the coupling capacitors at the inputs (CIN in Figure 10) are fully charged before the outputs start switching.9 V mute 0 V (SGND) standby 100 ms 50 ms > 350 ms time 010aaa584 (1) First 1⁄4 pulse down. a delay is inserted during the transition from Mute to Operating mode.

2009.3. thus avoiding beat tones (if the switching frequencies are different.1 Thermal FoldBack (TFB) If the junction temperature (Tj) exceeds the thermal foldback activation threshold.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 8. the gain is gradually reduced. it is recommended that an external clock circuit be used with all devices (see Section 13. A second order LC demodulation filter on the output converts the PWM signal into an analog audio signal. connected between pins OSC and VSSA. audible interference known as ‘beat tones’ can be generated). The carrier frequency is set to 345 kHz by connecting an external 30 kΩ resistor between pins OSC and VSSA. This will ensure that they operate at the same switching frequency. ROSC. eventually stabilizing the temperature.3 Protection The following protection circuits are incorporated into the TDA8922C: • Thermal protection: – Thermal FoldBack (TFB) – OverTemperature Protection (OTP) • OverCurrent Protection (OCP) • Window Protection (WP) • Supply voltage protection: – UnderVoltage Protection (UVP) – OverVoltage Protection (OVP) – UnBalance Protection (UBP) How the device reacts to a fault conditions depends on which protection circuit has been activated.3. See Table 9 for more details.1 Thermal protection The TDA8922C employes an advanced thermal protection strategy.V. 01 — 7 September 2009 8 of 40 . 8. If the temperature continues to rise.2 Pulse-width modulation frequency The amplifier output signal is a PWM signal with a typical carrier frequency of between 250 kHz and 450 kHz.1. The carrier frequency is determined by an external resistor. All rights reserved.4). Product data sheet Rev. OTP is activated to shut down the device completely. A TFB function gradually reduces the output power within a defined temperature range. If two or more Class D amplifiers are used in the same audio application. TDA8922C_1 © NXP B. 8. 8. The optimal carrier frequency setting is between 250 kHz and 450 kHz. This reduces the output signal amplitude and the power dissipation.

1. OCP is built in for each output power switch. the amplifier will shut down as soon as the temperature reaches the thermal protection activation threshold. for example. The amplifier will resume switching approximately 100 ms after the temperature drops below Tact(th_prot). Tact(th_prot). All rights reserved. TDA8922C_1 © NXP B. (3) Amplifier is switched off due to OTP. OCP is activated when the current in one of the power transistors exceeds the OCP threshold (IORM = 6 A) due. 01 — 7 September 2009 9 of 40 . The thermal behavior is illustrated in Figure 6. Product data sheet Rev. 2009.2 OverTemperature Protection (OTP) If TFB fails to stabilize the temperature and the junction temperature continues to rise. (2) Duty cycle of PWM output reduced due to TFB. the maximum output current delivered at the output stages is limited. to a short-circuit to a supply line or across the load. Fig 6.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier TFB is specified at the thermal foldback activation temperature Tact(th_fold) where the closed-loop voltage gain is reduced by 6 dB. 8. see Table 8 for more details. The TDA8922C amplifier distinguishes between low-ohmic short-circuit conditions and other overcurrent conditions such as a dynamic impedance drop at the loudspeakers. How the amplifier reacts to a short circuit depends on the short-circuit impedance: • Short-circuit impedance > Zth: the amplifier limits the maximum output current to IORM but the amplifier does not shut down the PWM outputs. The TFB range is: Tact(th_fold) − 5 °C < Tact(th_fold) < Tact(th_prot) The value of Tact(th_fold) for the TDA8922C is approximately 153 °C. Behavior of TFB and OTP 8. Effectively. The impedance threshold (Zth) depends on the supply voltage.3.3. Gain (dB) 30 dB 24 dB 0 dB (Tact(th_fold) − 5°C) Tact(th_prot) Tact(th_fold) 2 3 Tj (°C) 1 001aah656 (1) Duty cycle of PWM output modulated according to the audio input signal.V.2 OverCurrent Protection (OCP) In order to guarantee the robustness of the TDA8922C. this results in a clipped output signal across the load (behavior very similar to voltage clipping).

5 500 20 1000 20 1000 1000 [1] PWM output stops Short Short (Zth = 0 Ω) (Zth = 0. After a fixed period of 100 ms. 01 — 7 September 2009 10 of 40 .V. This can be avoided by increasing the value of CPROT (up to 220 pF) to delay amplifier switch-off. the amplifier shuts down completely and an internal timer is started. Table 4. when the TDA8922C is switching from Standby to Mute.5/ −29. the active power transistor is turned off and the other power transistor is turned on to reduce the current (CPROT is partially discharged). an internal current source is enabled that will discharge CPROT. If the fault condition that caused OCP to be activated persists long enough to fully discharge CPROT. Product data sheet Rev. TDA8922C_1 © NXP B. The average power dissipation will be low in this situation because the duty cycle is short. While OCP is activated. When CPROT is fully discharged. the amplifier will attempt to switch on again.3. The amplifier will continue trying to switch on every 100 ms. OCP ensures the TDA8922C amplifier is fully protected against short-circuit conditions while avoiding audio holes. CPROT will also prevent the amplifier switching off due to transient frequency-dependent impedance drops at the speakers.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier • Short-circuit impedance < Zth: the amplifier limits the maximum output current to IORM and at the same time discharges the capacitor on pin PROT.5 Ω) yes yes yes yes no yes yes yes no no Short (Zth = 1 Ω) yes yes yes no no TDA8922C 10 10 15 15 220 Tested using three samples and an external clock. once the overcurrent condition has been removed. 8. CPROT is partially discharge each time OCP is activated during a switching cycle. the amplifier will switch off completely and a restart sequence will be initiated.3 Window Protection (WP) Window Protection (WP) checks the conditions at the output terminals of the power stage and is activated: • During the start-up sequence. The amplifier will switch on. Type Current limiting behavior during low output impedance conditions at different values of CPROT[1] VDD/VSS VI (mV. When OCP is activated. Switching the amplifier on and off in this way will generate unwanted ‘audio holes’. The value of the protection capacitor (CPROT) connected to pin PROT can be between 10 pF and 220 pF (typically 47 pF). p-p) f (Hz) CPROT (pF) (V) +29. All rights reserved. but will fail if the output current still exceeds the OCP threshold. Normal operation is resumed at the next switching cycle (CPROT is recharged). and remain in Operating mode. 2009.

Vth(ovp). current limiting results in a clipped output signal. In all other cases. the UVP circuit will be activated and the system will shut down. the system will restart after a delay of 100 ms. Vth(uvp). 2009. see Section 8. If the supply voltage exceeds the maximum supply voltage threshold.4 Supply voltage protection If the supply voltage drops below the minimum supply voltage threshold. TDA8922C_1 © NXP B. The amplifier shuts down completely only if the short-circuit impedance is below the impedance threshold (Zth. the OVP circuit will be activated and the power stages will be shut down. 8. An additional UnBalance Protection (UBP) circuit compares the positive analog supply voltage (on pin VDDA) with the negative analog supply voltage (on pin VSSA) and is triggered if the voltage difference exceeds a factor of two (VDDA > 2 × |VSSA| OR |VSSA| > 2 × VDDA).3. the system will restart after a delay of 100 ms.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier Start-up will be interrupted If a short-circuit is detected between one of the output terminals and pin VDDP1/VDDP2 or VSSP1/VSSP2. Overview of TDA8922C protection circuits Restart directly N N N[2] Y N N N Restart after 100 ms N Y Y[2] N Y Y Y Pin PROT detection N N Y N N N N Protection name Complete shutdown TFB[1] OTP OCP WP UVP OVP UBP [1] [2] [3] N Y Y[2] N[3] Y Y Y Amplifier gain depends on the junction temperature and heatsink size. The short circuit will not generate large currents because the short-circuit check is carried out before the power stages are enabled. the system restarts after 100 ms.2). 8. The TDA8922C will wait until the short-circuit to the supply lines has been removed before resuming start-up. Table 5.2).V. Fault condition detected during any Standby-to-Mute transition or during a restart after OCP has been activated (short-circuit to one of the supply lines).4 Differential audio inputs The audio inputs are fully differential ensuring a high common mode rejection ratio and maximum flexibility in the application. When the supply voltage drops below Vth(ovp) again. Vth(ubp). An overview of all protection circuits and their respective effects on the output signal is provided in Table 5. Product data sheet Rev. WP will be activated when the amplifier attempts to restart after 100 ms (see Section 8. When the supply voltage difference drops below the unbalance threshold.3.3. The amplifier will not start-up again until the short circuit to the supply lines has been removed. 01 — 7 September 2009 11 of 40 . • When the amplifier is shut down completely because the OCP circuit has detected a short circuit to one of the supply lines. All rights reserved. Once the supply voltage rises above Vth(uvp) again.

Symbol ∆V IORM Tstg Tamb Tj VMODE VOSC VI VPROT VESD Iq(tot) VPWM(p-p) Parameter voltage difference repetitive peak output current storage temperature ambient temperature junction temperature voltage on pin MODE voltage on pin OSC input voltage voltage on pin PROT electrostatic discharge voltage total quiescent current peak-to-peak PWM voltage referenced to SGND pins IN1P. IN1M. Limiting values Table 6. The input configuration for a mono BTL application is illustrated in Figure 7. no load. IN1P IN1M Vin IN2P IN2M OUT1 SGND OUT2 power stage mbl466 Fig 7. This configuration: – minimizes power supply peak current – minimizes supply pumping effects. In practice (because of the OCP threshold) the output power can be boosted to twice the output power that can be achieved with the single-ended configuration. Mute modes maximum output current limiting Min 6 −55 −40 0 0 −5 0 −2000 −500 Max 65 +150 +85 150 6 +5 12 +2000 +500 70 120 Unit V A °C °C °C V V V V V mA V SGND + 6 V TDA8922C_1 © NXP B. 2009. 01 — 7 September 2009 12 of 40 . IN2P and IN2M referenced to voltage on pin VSSD Human Body Model (HBM) Charged Device Model (CDM) Operating mode. no filter no RC-snubber network connected on pins OUT1 and OUT2 referenced to SGND Conditions VDD − VSS.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier • Stereo operation: to avoid acoustical phase differences. especially at low audio frequencies • Mono BTL operation: the inputs must be connected in anti-parallel. Standby. the inputs should be in anti-phase and the speakers should be connected in anti-phase.V. Product data sheet Rev. Input configuration for mono BTL application 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All rights reserved. The output of one channel is inverted and the speaker load is connected between the two outputs of the TDA8922C.

no load. unless otherwise specified. Symbol Rth(j-a) Rth(j-c) Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions in free air Typ 40 1. Mute mode SE.5 −12. All rights reserved. no filter. Operating mode BTL. Mute mode BTL. Static characteristics Table 8.5 65 20 - Typ 30 −30 33 40 Max 32. no RC-snubber network connected Operating mode Operating mode Standby.3 µA V V V V µA V mV mV mV mV V Mode select input. Mute modes VDD − VSS VDD − VSS [3] [1] [2] Parameter Conditions Min 12. Static characteristics VDD = 30 V.8 650 6 0. fosc = 350 kHz. Operating mode [6] [6] Audio inputs.8 2. Product data sheet Rev. VSS = −30 V.5 −32. 01 — 7 September 2009 13 of 40 . pin STABI VO(STABI) output voltage on pin STABI Mute and Operating modes. pins OUT1 and OUT2 Stabilizer output. Thermal characteristics Table 7.9 6 150 ±25 ±150 ±30 ±210 10.5 V DC input SE. with respect to VSSD Temperature protection Tact(th_prot) thermal protection activation temperature 154 °C TDA8922C_1 © NXP B.2 [4] 480 110 0 9.3 Amplifier outputs. IN1P.5 70 25 70 Unit V V V V % mA Istb VMODE standby current voltage on pin MODE referenced to SGND Standby mode Mute mode Operating mode [4] [4][5] [4][5] [4][5] 0 0 2. pins IN1M. pin MODE II VI VO(offset) input current input voltage output offset voltage VI = 5. 2009.V.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 10. Symbol Supply VDD VSS Vth(ovp) Vth(uvp) Vth(ubp) Iq(tot) supply voltage negative supply voltage overvoltage protection threshold voltage undervoltage protection threshold voltage unbalance protection threshold voltage total quiescent current Operating mode. IN2P and IN2M 9.5 Unit K/W K/W 11. Tamb = 25 °C.1 4.

At a junction temperature of approximately Tact(th_fold) − 5 °C. the amplifier switches off.0 kΩ Min 290 250 Typ 345 - Max 365 450 Unit kHz kHz typical oscillator frequency oscillator frequency External oscillator input or frequency tracking. pin OSC voltage on pin OSC trip voltage tracking frequency [1] HIGH-level SGND + 4. slope is directly related to the time-constant of the RC network on the MODE pin VO (V) VO(offset)(on) Standby Mute On VO(offset)(mute) 0 0. see Figure 8. VSS is the supply voltage on pins VSSP1. unless otherwise specified. VSS = −30 V. Behavior of mode selection pin MODE 12. The slope caused by any DC output offset is determined by the time-constant of the RC network on pin MODE.1 2. Symbol Parameter Internal oscillator fosc(typ) fosc VOSC Vtrip ftrack TDA8922C_1 Conditions ROSC = 30. The transition between Standby and Mute modes has hysteresis.5 - © NXP B. Symbol Tact(th_fold) Parameter thermal foldback activation temperature Conditions closed loop SE voltage gain reduced with 6 dB [7] Min - Typ 153 Max - Unit °C [1] [2] [3] [4] [5] [6] [7] VDD is the supply voltage on pins VDDP1.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier Table 8. fosc = 350 kHz. Static characteristics …continued VDD = 30 V. VSSA and VSSD.5 VMODE (V) 010aaa585 Fig 8. With respect to SGND (0 V). gain reduction commences and at a junction temperature of approximately Tact(th_prot).V.8 2. Dynamic characteristics VDD = 30 V. Tamb = 25 °C. VSS = −30 V. 01 — 7 September 2009 14 of 40 .2 5.1 Switching characteristics Table 9. VSSP2. unless otherwise specified. Unbalance protection activated when VDDA > 2 × |VSSA| OR |VSSA| > 2 × VDDA. DC output offset voltage is gradually applied to the output during the transition between Mute and Operating modes.5 SGND + 5 500 - SGND + 6 V V kHz 900 SGND + 2. Tamb = 25 °C. while the slope of the transition between Mute and Operating modes is determined by the time-constant of the RC network on pin MODE. All rights reserved. VDDP2 and VDDA. 2009. Dynamic characteristics 12.9 4. Product data sheet Rev.

5 %. fi = 1 kHz. Rs = 0 Ω. Symbol Parameter Zi Ci tr(i) [1] [2] Conditions Min 1 - Typ - Max 15 100 Unit MΩ pF ns input impedance input capacitance input rise time from SGCN to SGND + 5 V [2] - When using an external oscillator. fi = 100 Hz Operating mode. fosc = 350 kHz. Tamb = 25 °C. RL = 6 Ω THD Gv(cl) SVRR total harmonic distortion closed-loop voltage gain supply voltage rejection ratio between pins VDDPn and SGND Operating mode. the frequency ftrack (500 kHz minimum.2 Stereo SE configuration characteristics Table 10. When tr(i) > 100 ns. Dynamic characteristics …continued VDD = 30 V.02 0. Product data sheet Rev. fi = 1 kHz Mute mode. fi = 100 Hz Standby mode. 2009. VSS = −30 V. Dynamic characteristics VDD = 30 V. 12. fi = 1 kHz Mute mode. fi = 100 Hz Standby mode. Tj = 85 °C THD = 0. unless otherwise specified. fi = 100 Hz Operating mode. fi = 6 kHz 29 0. All rights reserved.1 Ω[1]. fi = 100 Hz Zi Vn(o) input impedance output noise voltage between one of the input pins and SGND Operating mode. Rs(L) < 0. fi = 100 Hz between pins VSSPn and SGND Operating mode.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier Table 9. RL = 16 Ω RDSon(hs) RDSon(ls) TDA8922C_1 Min [2] Typ 58 75 Max Unit W W % % dB dB dB dB dB dB dB dB dB kΩ µV µV dB dB dB dB % % % mΩ mΩ [3] [3] Po = 1 W. CLC = 680 nF. 01 — 7 September 2009 15 of 40 . fi = 1 kHz Po = 1 W. Symbol Po Parameter output power Conditions L = 22 µH. inputs shorted Mute mode αcs |∆Gv| αmute CMRR ηpo channel separation voltage gain difference mute attenuation common mode rejection ratio output power efficiency fi = 1 kHz. 900 kHz maximum) will result in a PWM frequency fosc (250 kHz minimum. RL = 6 Ω THD = 10 %. unless otherwise specified. VSS = −30 V. Tamb = 25 °C.05 30 72 55 80 116 72 60 72 116 63 160 85 70 75 75 88 90 90 380 320 31 1 - [4] [4] [4] [4] 45 [4] [4] [4] [4] [5] - [6] [7] [8] high-side drain-source on-state resistance low-side drain-source on-state resistance [9] [9] - © NXP B. RL = 6 Ω. see Section 8. Vi = 2 V (RMS) Vi(CM) = 1 V (RMS) SE. the output noise floor will increase. RL = 6 Ω SE.V. 450 kHz maximum) due to the internal clock divider. RL = 8 Ω BTL.2.

fosc = 350 kHz. Vi = 2 V (RMS) Vi(CM) = 1 V (RMS) [5] [6] [7] - Rs(L) is the series resistance of the low-pass LC filter inductor used in the application.3. using AES17 20 kHz brick wall filter. limit is guaranteed but may not be 100 % tested. fi = 1 kHz Po = 1 W.3. fi = 100 Hz between pin VSSPn and SGND Operating mode. RL = 8 Ω. measured independently between VDDPn and SGND and between VSSPn and SGND. fi = 1 kHz. CLC = 680 nF (see Figure 10) THD = 0. Dynamic characteristics VDD = 25 V. 22 Hz to 20 kHz. 01 — 7 September 2009 16 of 40 . fi = 1 kHz. fi = 100 Hz Operating mode. 22 Hz to 20 kHz. unless otherwise specified. max. All rights reserved. based on RDSon measurement. fi = 100 Hz Operating mode. THD measured between 22 Hz and 20 kHz. 12.3 Mono BTL application characteristics Table 11. © NXP B. RL = 8 Ω THD Gv(cl) SVRR total harmonic distortion closed-loop voltage gain supply voltage rejection ratio between pin VDDPn and SGND Operating mode. RL = 8 Ω THD = 10 %. Vi = Vi(max) = 1 V (RMS). 2009. Vi = Vi(max) = 1 V (RMS). Tamb = 25 °C. fi = 1 kHz. fi = 6 kHz 45 0. using AES17 20 kHz brick wall filter.1 Ω [1]. based on RDSon measurement. TDA8922C_1 Product data sheet Rev. Leads and bond wires included. Output power is measured indirectly. VSS = −25 V.V. see Section 13. low noise due to BD modulation. Symbol Po Parameter output power Conditions Tj = 85 °C. fi = 100 Hz Standby mode. Vripple = Vripple(max) = 2 V (p-p). 22 Hz to 20 kHz. fi = 100 Hz Zi Vn(o) αmute CMRR [1] [2] [3] [4] [5] [6] [7] [4] [4] [4] [4] [4] [4] [4] [4] [2] Min Typ Max Unit [3] [3] 115 155 - W W % % dB dB dB dB dB dB dB dB dB kΩ µV µV dB dB Po = 1 W. using AES17 20 kHz brick wall filter.05 36 72 64 86 100 72 72 86 100 63 190 45 75 75 - input impedance output noise voltage mute attenuation common mode rejection ratio measured between one of the input pins and SGND Operating mode. see Section 13. LLC = 22 µH. using an AES17 20 kHz brick wall filter. Vripple = Vripple(max) = 2 V (p-p). THD measured between 22 Hz and 20 kHz. fi = 1 kHz Mute mode. using AES17 20 kHz brick wall filter.5 %. using an AES17 20 kHz brick wall filter. Po = 1 W.02 0.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier [1] [2] [3] [4] [5] [6] [7] [8] [9] Rs(L) is the series resistance of the low-pass LC filter inductor used in the application. limit is guaranteed but may not be 100 % tested. max. fi = 100 Hz Standby mode. fi = 1 kHz Mute mode. 22 Hz to 20 kHz. Rs = 0 Ω Mute mode fi = 1 kHz. fi = 1 kHz. Output power is measured indirectly. Rs(L) < 0.

All rights reserved.5 f osc ) R L + R DSon ( hs ) + R s ( L ) = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------2R L P o ( 0.2 Pin MODE To ensure a pop noise-free start-up.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 13. see Figure 4.V. Application information 13. Product data sheet Rev. 01 — 7 September 2009 17 of 40 .1 Mono BTL application When using the power amplifier in a mono BTL application. The bias-current setting of the VI converter input is directly related to the voltage on pin MODE.3. The value of the ripple current is dependent on the coil inductance and the voltage drop across the coil.2). A slow dV/dt on pin MODE results in a slow dV/dt for the DC output offset voltage. ensuring a pop noise-free transition between Mute and Operating modes. (see Figure 7). A time-constant of 500 ms is sufficient to guarantee pop noise-free start-up.3.5 ( V DD – V SS ) × ( 1 – t w ( min ) × 0. temperature dependent) fosc: oscillator frequency Remark: Note that Io(peak) should be less than 6 A (Section 8.5% ) (1) Maximum output current is internally limited to 6 A: 0. In turn the bias-current setting of the VI converters is directly related to the DC output offset voltage.1 Single-Ended (SE) Maximum output power: 2 RL -------------------------------------------------------. 13.5 ( V DD – V SS ) × ( 1 – t w ( min ) × 0. Io(peak) is the sum of the current through the load and the ripple current. TDA8922C_1 © NXP B.5 %): output power at the onset of clipping RL: load impedance RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent) Rs(L): series impedance of the filter coil tw(min): minimum pulse width (typical 100 ns. the inputs of the two channels must be connected in anti-parallel and the phase of one of the inputs must be inverted. In principle. the loudspeaker can be connected between the outputs of the two single-ended demodulation filters.5 f osc ) I o ( peak ) = ----------------------------------------------------------------------------------------------------R L + R DSon ( hs ) + R s ( L ) Where: (2) • • • • • • Po(0.3 Estimating the output power 13. 13. Figure 5 and Figure 8 for more information. 2009. an RC time-constant must be applied to pin MODE.× 0.

5 f osc ) I o ( peak ) = ---------------------------------------------------------------------------------------------R L + ( R DSon ( hs ) + R DSon ( ls ) ) + 2R s ( L ) Where: (4) • • • • • • • • Po(0. The value of the ripple current is dependent on the coil inductance and the voltage drop across the coil. it is recommended that all the devices run at the same switching frequency.3. The internal oscillator requires an external resistor ROSC. This disables the internal oscillator and causes the PWM to switch at half the external clock frequency. The external clock frequency is therefore twice the internal clock frequency (typically 2 × 350 kHz = 700 kHz). 01 — 7 September 2009 18 of 40 .4 External clock To ensure duty cycle-independent operation. An external low-noise oscillator is recommended for low-noise applications running at high supply voltages. temperature dependent) fosc: oscillator frequency Remark: Note that Io(peak) should be less than 6 A.5% ) (3) Maximum output current internally limited to 6 A: ( V DD – V SS ) × ( 1 – t w ( min ) × 0.V.5 %): output power at the onset of clipping RL: load impedance RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent) RDSon(ls): low-side RDSon of power stage output DMOS (temperature dependent) Rs(L): series impedance of the filter coil VP: single-sided supply voltage or 0. the external clock frequency is divided by two internally. The noise generated by the internal oscillator is supply voltage dependent. If several Class D amplifiers are used in a single application. 13. This can be achieved by connecting the OSC pins together and feeding them from an external oscillator. see Section 8.2. ROSC must be removed when using an external oscillator.5 Heatsink requirements An external heatsink must be connected to the TDA8922C. 13.3. 2009. Io(peak) is the sum of the current through the load and the ripple current.2 Bridge-Tied Load (BTL) Maximum output power: 2 RL -----------------------------------------------------------------. TDA8922C_1 © NXP B.5 f osc ) R L + R DSon ( hs ) + R DSon ( ls ) = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2R L P o ( 0. All rights reserved.× ( V DD – V SS ) × ( 1 – t w ( min ) × 0. it is necessary to force pin OSC to a DC level above SGND. When using an external oscillator.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 13. Product data sheet Rev. connected between pin OSC and pin VSSA.5 × (VDD + |VSS|) tw(min): minimum pulse width (typical 100 ns.

NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier Equation 5 defines the relationship between maximum power dissipation before activation of TFB and total thermal resistance from junction to ambient. (3) Rth(j-a) = 15 K/W. All rights reserved. (2) Rth(j-a) = 10 K/W. (4) Rth(j-a) = 20 K/W. 30 P (W) mbl469 (1) 20 (2) 10 (3) (4) (5) 0 0 20 40 60 80 100 Tamb (°C) (1) Rth(j-a) = 5 K/W.V. Fig 9. 2009. Efficiency measured as a function of output power is given in Figure 20. (5) Rth(j-a) = 35 K/W. (5) T j – T amb Rth ( j – a ) = ----------------------P Power dissipation (P) is determined by the efficiency of the TDA8922C. Power dissipation can be derived as a function of output power as shown in Figure 19. Derating curves for power dissipation as a function of maximum ambient temperature TDA8922C_1 © NXP B. 01 — 7 September 2009 19 of 40 . Product data sheet Rev.

5 K/W The derating curves for power dissipation (for several Rth(j-a) values) are illustrated in Figure 9.5 K/W Rth(c-h) (thermal resistance from case to heatsink) = 0. When the maximum expected ambient temperature is 50 °C. the voltage across the output capacitors of that voltage supply source increases and the supply voltage is pumped to higher levels. the TDA8922C is supplied by a symmetrical supply voltage (e. see Figure 9. 110 W.V. 2009. The maximum allowable power dissipation for a given heatsink size can be derived.g.g. i. a heatsink calculation is made for an 8 Ω BTL application with a ±30 V supply: The audio signal has a crest factor of 10 (the ratio between peak power and average power (20 dB)). energy is taken from one supply (e. a ‘pumping effect’ can occur. while a part of that energy is returned to the other supply line (e. the total Rth(j-a) becomes ( 150 – 50 ) ------------------------. A maximum junction temperature Tj = 150 °C is taken into account.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier In the following example.g.6 Pumping effects In a typical stereo single-ended configuration. or the required heatsink size can be determined. When the voltage supply source cannot sink energy. Thus. The average power is then 1⁄10 × 110 W = 11 W. OVP or UBP. 13. the peak RMS output power level is the 0.5 + 1) = 17.e. When the amplifier is used in an SE configuration.5 K/W to 1 K/W (dependent on mounting) So the thermal resistance between heatsink and ambient temperature is: Rth(h-a) (thermal resistance from heatsink to ambient) = 20 − (1.5 % THD level.= 20 K/W 5 Rth(j-a) = Rth(j-c) + Rth(c-h) + Rth(h-a) Rth(j-c) (thermal resistance from junction to case) = 1. Product data sheet Rev. The voltage increase caused by the pumping effect depends on: • • • • • Speaker impedance Supply voltage Audio signal frequency Value of supply line decoupling capacitors Source and sink currents of other channels Pumping effects should be minimized to prevent the malfunctioning of the audio amplifier and/or the voltage supply source. During one switching interval. TDA8922C_1 © NXP B. Amplifier malfunction due to the pumping effect can trigger UVP. at a required power dissipation level. VDD). VSS) and vice versa. this means that the average output power is 1⁄10 of the peak power. The dissipated power at an output power of 11 W is approximately 5 W. VDD = 30 V and VSS = −30 V). All rights reserved. 01 — 7 September 2009 20 of 40 .

2009. Product data sheet Rev. TDA8922C_1 © NXP B. In the case of stereo single-ended applications. for example. The power supply can also be adapted. 13.7 Application schematic Notes on the application schematic: • • • • Connect a solid ground plane around the switching amplifier to avoid emissions Place 100 nF capacitors as close as possible to the TDA8922C power supply pins Connect the heatsink to the ground plane or to VSSPn using a 100 nF capacitor Use a thermally conductive. Sil-Pad between the TDA8922C heat spreader and the external heatsink • The heat spreader of the TDA8922C is internally connected to VSSD • Use differential inputs for the most effective system level audio performance with unbalanced signal sources. by increasing the values of the supply line decoupling capacitors.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier The most effective way to avoid pumping effects is to connect the TDA8922C in a mono full-bridge configuration.V. In case of hum due to floating inputs. All rights reserved. 01 — 7 September 2009 21 of 40 . connect the shielding or source ground to the amplifier ground.4 on page 11). electrically non-conductive. it is advised to connect the inputs in anti-phase (see Section 8.

c. Typical application diagram . All rights reserved.V. 01 — 7 September 2009 © NXP B. TDA8922C_1 NXP Semiconductors +5 V RVDDA 10 Ω VDDA VDDP 5. 1 23 8 VSSP1 11 MODE VSSP 10 OUT1 CBO LLC RZO 22 Ω IN1M 3 9 BOOT1 + CLC 15 nF SGND CIN 470 nF 19 − CZO 100 nF TDA8922CJ 15 BOOT2 CBO 15 nF − IN2 + IN2P 22 14 OUT2 LLC 2 × 75 W class-D power amplifier CIN 470 nF IN2M 21 20 VDDA 18 VSSA 12 STABI 7 PROT 17 VSSD 16 VDDP2 13 VSSP2 RSN 10 Ω CVSSP 100 nF VDDP CSN 220 pF CSN 220 pF CLC RZO 22 Ω − CZO + 100 nF TDA8922C CVDDA 220 nF CVSSA 220 nF CSTAB 470 nF CPROT(1) CVDDP 100 nF CVP 100 nF VSSP VDDA VSSA VSSP VSSA VDDP VSSP 010aaa548 22 of 40 (1) The value of CPROT can be in the range 10 pF to 220 pF (see Section 8.c.3. 2009.6 kΩ 470 Ω VDDP CVDDP 470 µF CVP 22 µF mode control +5 V 470 kΩ 5.c. n.6 kΩ 10 µF 470 kΩ GND CVSSP 470 µF SINGLE-ENDED OUTPUT FILTER VALUES LOAD LLC CLC 6 Ω to 8 Ω 4 Ω to 8 Ω T2 HFE > 80 VSSP RVSSA 10 Ω VSSP VSSA mute/ operating 33 µH 22 µH 330 nF 470 nF 10 kΩ T1 HFE > 80 standby/ operating 10 kΩ SGND VSSA ROSC 30 kΩ mode control VDDP CVDDP 100 nF VSSP CVSSP 100 nF RSN 10 Ω CVP 100 nF VDDP CSN 220 pF CSN 220 pF VDDP1 + IN1 − CIN 470 nF CIN 470 nF IN1P 4 2 5 6 OSC n.2) Fig 10. n.xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev.

All rights reserved. (3) fi = 100 Hz. Product data sheet Rev. 01 — 7 September 2009 23 of 40 . (3) fi = 100 Hz. fosc = 350 kHz (external oscillator). THD + N as a function of output power.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 13.8 Curves measured in reference design (demonstration board) 10 THD+N (%) 1 010aaa565 10−1 (1) 10−2 (2) (3) 10−3 10−2 10−1 1 10 102 Po (W) 103 VDD = 30 V. SE configuration with 2 × 8 Ω load TDA8922C_1 © NXP B. Fig 11. (1) fi = 6 kHz. (1) fi = 6 kHz. 2009. SE configuration with 2 × 6 Ω load 10 THD+N (%) 1 010aaa566 10−1 (1) 10−2 (2) (3) 10−3 10−2 10−1 1 10 102 Po (W) 103 VDD = 30 V. Fig 12. (2) fi = 1 kHz. 2 × 6 Ω SE configuration. VSS = −30 V. 2 × 8 Ω SE configuration. THD + N as a function of output power. (2) fi = 1 kHz. fosc = 350 kHz (external oscillator).V. VSS = −30 V.

1 × 8 Ω BTL configuration.V. fosc = 350 kHz (external oscillator). fosc = 350 kHz (external oscillator). VSS = −25 V. THD + N as a function of frequency. 01 — 7 September 2009 24 of 40 . (1) Po = 1 W. SE configuration with 2 × 6 Ω load TDA8922C_1 © NXP B. 2009. (2) fi = 1 kHz. All rights reserved. (1) fi = 6 kHz. 2 × 6 Ω SE configuration. VSS = −30 V.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 10 THD+N (%) 1 010aaa567 10−1 (1) 10−2 (2) (3) 10−3 10−2 10−1 1 10 102 Po (W) 103 VDD = 25 V. Fig 14. (3) fi = 100 Hz. Fig 13. Product data sheet Rev. BTL configuration with 1 × 8 Ω load 10 THD+N (%) 1 010aaa568 10−1 (1) 10−2 (2) 10−3 10 102 103 104 fi (Hz) 105 VDD = 30 V. THD + N as a function of output power. (2) Po = 10 W.

(1) Po = 1 W. (2) Po = 10 W. All rights reserved. VSS = −25 V. THD + N as a function of frequency.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 10 THD+N (%) 1 010aaa569 10−1 (1) 10−2 (2) 10−3 10 102 103 104 fi (Hz) 105 VDD = 30 V. fosc = 350 kHz (external oscillator). Fig 15. fosc = 350 kHz (external oscillator). 01 — 7 September 2009 25 of 40 . BTL configuration with 1 × 8 Ω load TDA8922C_1 © NXP B. (1) Po = 1 W. VSS = −30 V. 2 × 8 Ω SE configuration. 2009. Fig 16. Product data sheet Rev. THD + N as a function of frequency. SE configuration with 2 × 8 Ω load 10 THD+N (%) 1 010aaa570 10−1 (1) 10−2 (2) 10−3 10 102 103 104 fi (Hz) 105 VDD = 25 V.V. 1 × 8 Ω BTL configuration. (2) Po = 10 W.

01 — 7 September 2009 26 of 40 . SE configuration with 2 × 8 Ω load TDA8922C_1 © NXP B. 2009. Channel separation as a function of frequency. 1 W and 10 W respectively. Fig 18. fosc = 350 kHz (external oscillator). fosc = 350 kHz (external oscillator).NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 0 αcs (dB) −20 010aaa571 −40 −60 (1) −80 (2) −100 10 102 103 104 fi (Hz) 105 VDD = 30 V. SE configuration with 2 × 6 Ω load 0 αcs (dB) −20 010aaa572 −40 −60 (1) −80 (2) −100 10 102 103 104 fi (Hz) 105 VDD = 30 V. All rights reserved.V. Fig 17. 2 × 8 Ω SE configuration. VSS = −30 V. Product data sheet Rev. VSS = −30 V. 1 W and 10 W respectively. 2 × 6 Ω SE configuration. Channel separation as a function of frequency.

V. (3) 1 × 8 Ω BTL configuration. SE configuration 100 η (%) 80 (1) (2) 010aaa574 (3) 60 40 20 0 0 20 40 60 80 100 120 Po (W) 140 160 fi = 1 kHz. VDD = 32 V. VSS = −25 V. (2) 2 × 6 Ω SE configuration. fosc = 350 kHz (external oscillator). (3) 1 × 8 Ω BTL configuration. (1) 2 × 8 Ω SE configuration. VSS = −32 V. VDD = 25 V. 01 — 7 September 2009 27 of 40 . 2009. VDD = 25 V. VDD = 32 V. VSS = −32 V. Fig 19. VSS = −25 V. VSS = −32 V. Product data sheet Rev. (2) 2 × 8 Ω SE configuration. Efficiency as a function of output power per channel. Fig 20. VDD = 32 V. fosc = 350 kHz (external oscillator). SE configuration TDA8922C_1 © NXP B. All rights reserved. VSS = −32 V.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 30 PD (W 20 (1) (2) (3) 010aaa573 10 0 10−2 10−1 1 101 102 Po (W) 103 fi = 1 kHz. Power dissipation as a function of output power per channel. (1) 2 × 6 Ω SE configuration. VDD = 32 V.

5 22. BTL configuration TDA8922C_1 © NXP B. Output power as a function of supply voltage.5 −12.5 VDD (V) −32. 01 — 7 September 2009 28 of 40 .5 20 −20 22.V. 6 Ω.5 VSS (V) Infinite heat sink used.5 −22. Fig 22. (1) THD + N = 10 %. 8 Ω. fi = 1 kHz.5 %.5 17. 6 Ω (4) THD + N = 0. (2) THD + N = 10 %. fosc = 350 kHz (external oscillator).5 25 −25 27.5 −17.5 VSS (V) Infinite heat sink used.5 32.5 VDD (V) −27. 2009. SE configuration 200 Po (W) 160 010aaa576 (1) 120 (2) 80 40 0 12. fosc = 350 kHz (external oscillator).5 15 −15 17. Output power as a function of supply voltage.5 −22.5 %.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 100 Po (W) 80 010aaa575 (1) (2) 60 (3) (4) 40 20 0 12.5 27. 8 Ω.5 −12. Fig 21. (2) THD + N = 0. fi = 1 kHz. All rights reserved. (1) THD + N = 10 %.5 %.5 −27. 8 Ω.5 −17. Product data sheet Rev. 8 Ω (3) THD + N = 0.

short on input pins. (3) Standby mode.V. Product data sheet Rev. Vripple = 2 V (p-p). VDD = 30 V. VDD = 25 V. Vi = 100 mV.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 40 (1) 010aaa577 Gv(cl) (dB) (2) 30 (3) 20 10 10 102 103 104 fi (Hz) 105 VDD = 30 V. VSS = −30 V. SVRR as a function of ripple frequency. 01 — 7 September 2009 29 of 40 . (1) 1 × 8 Ω BTL configuration. All rights reserved. 2009. LLC = 33 µH. VSS = −25 V. fosc = 350 kHz (external oscillator). Ci = 330 pF. VSS = −30 V. CLC = 330 nF. CLC = 680 nF. 2 × 8 Ω SE configuration. VDD = 30 V. VSS = −30 V. (1) Operating mode. (2) Mute mode. LLC = 33 µH. Fig 23. ripple on VDD TDA8922C_1 © NXP B. CLC = 330 nF. (3) 2 × 6 Ω SE configuration. Closed-loop voltage gain as a function of frequency −20 SVRR (dB) −60 010aaa578 (1) (2) −100 (3) −140 10 102 103 104 fi (Hz) 105 Ripple on VDD. Fig 24. VDD = 30 V. LLC = 15 µH. VSS = −30 V. (2) 2 × 8 Ω SE configuration.

All rights reserved. ripple on VSS 0 SVRR (dB) −40 (1) 010aaa586 −80 (2) (3) −120 10 102 103 104 fi (Hz) 105 Ripple on VDD. (2) Mute mode. (3) Standby mode. VDD = 30 V. (1) Mute mode. Vripple = 2 V (p-p). Vripple = 2 V (p-p). SVRR as a function of ripple frequency.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier −20 SVRR (dB) −60 010aaa579 (1) (2) −100 (3) −140 10 102 103 104 fi (Hz) 105 Ripple on VSS. VDD = 25 V. Fig 25. 01 — 7 September 2009 30 of 40 .V. 1 × 8 Ω BTL configuration. 2 × 8 Ω SE configuration. (2) Operating mode. 2009. (1) Operating mode. (3) Standby mode. VSS = −30 V. short on input pins. short on input pins. ripple on VDD TDA8922C_1 © NXP B. Product data sheet Rev. Fig 26. SVRR as a function of ripple frequency. VSS = −25 V.

2009. 01 — 7 September 2009 31 of 40 . (2) Mode voltage up. (2) Mute mode. (1) Operating mode. Vripple = 2 V (p-p). All rights reserved. (1) Mode voltage down. short on input pins. Product data sheet Rev. VSS = −30 V. VSS = −25 V.V. Vi = 100 mV. SVRR as a function of ripple frequency. VDD = 25 V. Fig 28. Output voltage as a function of mode voltage TDA8922C_1 © NXP B. Fig 27. ripple on VSS 102 Vo (V) 1 010aaa580 10−2 10−4 (1) (2) 10−6 0 2 4 VMODE (V) 6 VDD = 30 V.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 0 SVRR (dB) −40 010aaa587 (1) −80 (2) (3) −120 10 102 103 104 fi (Hz) 105 Ripple on VSS. 1 × 8 Ω BTL configuration. (3) Standby mode.

Product data sheet Rev. VSS = −30 V. Mute attenuation as a function of frequency TDA8922C_1 © NXP B. (1) 2 × 6 Ω SE configuration.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier −50 αmute (dB) −60 010aaa581 −70 (1) −80 (2) −90 10 102 103 104 fi (Hz) 105 VDD = 30 V. (2) 2 × 8 Ω SE configuration. 01 — 7 September 2009 32 of 40 . Fig 29.V. All rights reserved. Vi = 2 V (RMS). fosc = 350 kHz (external oscillator). 2009.

08 11.6 1.78 1. OUTLINE VERSION SOT411-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 98-02-20 02-04-24 Fig 30. 23 leads (straight lead length 3.3 0.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 14.60 0. Product data sheet Rev.0 12 2.27 5.35 29.54 1.55 30.65 0. All rights reserved.85 5.6 0.4 1.9 27.4 28. 01 — 7 September 2009 33 of 40 .5 6 10.85 1.15 1.2 1.35 0.75 0. Plastic or metal protrusions of 0.25 0.1 4.25 mm maximum per side are not included. 2009.43 2.9 1.8 4.2 mm) SOT411-1 non-concave x D Dh Eh view B: mounting base side A2 d β A5 A4 B j E2 E E1 L2 L1 L3 L 1 Z e e1 w M 23 Q m c e2 v M bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT A 2 mm A4 A5 bp c D (1) d D h E (1) e e1 e2 Eh E1 E2 j L L1 L2 L3 m Q v w x β Z (1) 12.15 6.65 2.8 Note 1.03 45° 13 9.7 2. Package outline SOT411-1 (DBS23P) TDA8922C_1 © NXP B.8 14 10.8 1.3 0.6 0.85 3.V. Package outline DBS23P: plastic DIL-bent-SIL power package.2 4.6 9.

1 0. Product data sheet Rev.53 0.5 3.6 0.9 2. OUTLINE VERSION SOT566-3 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 03-02-18 03-07-23 Fig 31. 2.9 E1 6. 3.04 0. All rights reserved.25 mm maximum per side are not included.2 θ 8° 0° +0.8 Q 1.25 0.35 A4(1) bp c D(2) D1 D2 1.V. 2009.9 E(2) 11.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier HSOP24: plastic.5 v w x y Z 2. 24 leads.8 12.0 13. Package outline SOT566-3 (HSOP24) TDA8922C_1 © NXP B.32 16.5 3.2 5.1 0.7 2.7 1. 01 — 7 September 2009 34 of 40 . Limits per individual lead.5 13. heatsink small outline package.5 e 1 HE 14.07 Notes 1.03 0.2 A3 0.0 −0.1 10.40 0.9 Lp 1. low stand-off height SOT566-3 E D x A X c y E2 HE v M A D1 D2 1 pin 1 index Q A2 E1 A4 Lp detail X 24 Z e bp 13 w M (A3) θ A 12 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A A2 max. Plastic or metal protrusions of 0.8 E2 2.23 15.08 0.25 0.

15. to form electrical circuits. and the time during which components are exposed to the wave • Solder bath specifications. cannot be wave soldered. including temperature and impurities TDA8922C_1 © NXP B. Product data sheet Rev. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs. including the board finish.3 Wave soldering Key characteristics in wave soldering are: • Process issues. Also. it is not suitable for fine pitch SMDs. the solder wave parameters. solder masks and vias Package footprints. All rights reserved. 01 — 7 September 2009 35 of 40 . There is no single soldering method that is ideal for all IC packages. board transport. The reflow soldering process involves applying solder paste to a board. clinching of leads.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs). The soldered joint provides both the mechanical and the electrical connection. including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15. 15. and leadless packages are all reflow solderable. followed by component placement and exposure to a temperature profile. due to an increased probability of bridging. such as application of adhesive and flux. Soldering of SMD packages This text provides a very brief insight into a complex technology. however.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. and some leadless packages which have solder lands underneath the body. Leaded packages. Packages with solder balls.6 mm cannot be wave soldered. which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered.V. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 15. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. leaded SMDs with leads having a pitch smaller than ~0. 2009. packages with solder balls. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board.

thus reducing the process window • Solder paste printing issues including smearing. release. this profile includes preheat.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions. reflow (in which the board is heated to the peak temperature) and cooling down. All rights reserved. the peak temperature must be low enough that the packages and/or boards are not damaged. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.V. as indicated on the packing. see Figure 32. 2009. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1. TDA8922C_1 © NXP B.6 1.5 Table 13. note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 32) than a SnPb process. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Table 12.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 15. Studies have shown that small packages reach higher temperatures during reflow soldering. Product data sheet Rev. and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic).5 > 2. 01 — 7 September 2009 36 of 40 .6 to 2. In addition.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering.5 ≥ 2. must be respected at all times.

TDA8922C_1 © NXP B. SnPb or Pb-free respectively. 16. Soldering of through-hole mount packages 16.3 Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package. forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.1 Introduction to soldering through-hole mount packages This text gives a very brief insight into wave.V. but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). The device may be mounted up to the seating plane. 2009. Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. 01 — 7 September 2009 37 of 40 . Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C. damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 32. contact may be up to 5 seconds. 16.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier temperature maximum peak temperature = MSL limit. Product data sheet Rev.2 Soldering by dipping or by solder wave Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. The total contact time of successive solder waves must not exceed 5 seconds. refer to Application Note AN10365 “Surface mount reflow soldering description”. depending on solder material applied. dip and manual soldering. either below the seating plane or not more than 2 mm above it. If the bit temperature is between 300 °C and 400 °C. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. Temperature profiles for large and small components For further information on temperature profiles. All rights reserved. 16. If the printed-circuit board has been pre-heated.

Revision history Release date 20090907 Data sheet status Product data sheet Change notice Supersedes Document ID TDA8922C_1 TDA8922C_1 © NXP B.V. the longitudinal axis must be parallel to the transport direction of the printed-circuit board. Product data sheet Rev. 17. 2009. 01 — 7 September 2009 38 of 40 . Revision history Table 15.4 Package related soldering information Table 14. DIP. For PMFP packages hot bar soldering or manual soldering is suitable. HDIP. SDIP. All rights reserved.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 16. SIL PMFP[2] [1] [2] Suitability of through-hole mount IC packages for dipping and wave soldering Soldering method Dipping suitable Wave suitable suitable[1] not suitable For SDIP packages. Package CPGA. HCPGA DBS. RDBS.

NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 01 — 7 September 2009 39 of 40 . nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. conveyance or implication of any license under any copyrights. Contact information For more information. including those pertaining to warranty. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document. In case of any inconsistency or conflict between information in this document and such terms and conditions. exhaustive or legally binding. For detailed and full information see the relevant full data sheet. and as such is not complete.4 Trademarks Notice: All referenced brands. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. service names and trademarks are the property of their respective owners. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale. This document contains data from the preliminary specification. This document contains the product specification. including without limitation specifications and product descriptions.com/profile/terms.2 Definitions Draft — The document is a draft version only. Product data sheet Rev. the full data sheet shall prevail.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. NXP Semiconductors does not give any representations or warranties. at any time and without notice. the latter will prevail. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. please send an email to: salesaddresses@nxp. please visit: http://www.V. patents or other industrial or intellectual property rights. All rights reserved. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. The term ‘short data sheet’ is explained in section “Definitions”. aircraft. damage. 18. military.3 Disclaimers General — Information in this document is believed to be accurate and reliable. death or severe property or environmental 18.com For sales office addresses. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. unless explicitly otherwise agreed to in writing by NXP Semiconductors. intellectual property rights infringement and limitation of liability. However. 2009. Please consult the most recently issued document before initiating or completing a design. product names. Exposure to limiting values for extended periods may affect device reliability. In case of any inconsistency or conflict with the short data sheet. Legal information 18. The content is still under internal review and subject to formal approval. Suitability for use — NXP Semiconductors products are not designed. 19. which is available on request via the local NXP Semiconductors sales office. as published at http://www. as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. expressed or implied.nxp.nxp. 18. which may result in modifications or additions. space or life support equipment.com. Export control — This document as well as the item(s) described herein may be subject to export control regulations.com TDA8922C_1 © NXP B.NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 18. Applications — Applications that are described herein for any of these products are for illustrative purposes only. This document supersedes and replaces all information supplied prior to the publication hereof. Export might require a prior authorization from national authorities.nxp. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document. authorized or warranted to be suitable for use in medical. The latest product status information is available on the Internet at URL http://www.

. . . .3.4 General description . . . . . . . . . . . . . . . . . . . . .2 8 8. . . . . . . 4 Pinning . . . . . . . . . . . . . . .4 17 18 18. . . . . .com Date of release: 7 September 2009 Document identifier: TDA8922C_1 . . . . . . . . . . . . . .2 8. .3. . . . . . . . . . . . . . . . . . . . 8 OverTemperature Protection (OTP) . 2 Block diagram .4 19 20 Soldering of through-hole mount packages . . . . . .3 13 13. . .6 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . .2 8. . . . . . . . . . . 21 Curves measured in reference design (demonstration board) . . . . . . . 8 Thermal protection . . . . .1 16. . . . . . . . . . . . . . . . . . . . . . . . 37 37 37 37 38 38 39 39 39 39 39 39 40 Please be aware that important notices concerning this document and the product(s) described herein. . . . . . 11 Differential audio inputs . . . . . . . . . .3 16. . . . . . . . . . 13 Static characteristics. . . . . 8 Protection . . . . . . . . . .1 18. .3. . . . . . . Legal information . . . . . . . For more information. . . . . 5 Pulse-width modulation frequency . . . . . . . . . . . . . . . . 35 Wave and reflow soldering . . . . . . . . . . . 17 Single-Ended (SE) . . . . . Package related soldering information . . . . . . . . . . . . . . 5 Functional description . 9 OverCurrent Protection (OCP) . . . . . .4 9 10 11 12 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 8. . . . . .3. . . .2 18. . . . . . . . . . .2 13.4 13. . . Contact information . . . . . All rights reserved. . . . . .nxp.3 15. . . . . . . . . . . . . . . . . . . . . . . . .7 13. . . . . . 18 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . . 35 Introduction to soldering . . 36 16 16. .3 8. . . . . . . . .1 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7. . . . . . . . . . . . Trademarks . . . . .3 18. . . . . 14 Stereo SE configuration characteristics . . . . . .4 8. . . . . . . . . .1 15. . . . 10 Supply voltage protection . .2 13. . 18 Heatsink requirements . . . . . 5 General . . . . . . . . .com For sales office addresses. . . . . . . . .V. . . . . . . . . .2 15. . . . . . Contents. . . . . . . . . . . . . . . 15 Mono BTL application characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . 17 Bridge-Tied Load (BTL) . . . . . . . . . . . . . . . . . . . . please visit: http://www. . . . . . . . .1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Limiting values. . . . . . 33 Soldering of SMD packages . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . 16 Application information. . . . . . . . . . . .1. . . . . . . .3. . . . . . 35 Wave soldering . . . . . . . . . .8 14 15 15. . . . . . . . . . . . . . .1 8. . . . . . . . . . . have been included in section ‘Legal information’. . . . . . . . . . . . . . . . . please send an email to: salesaddresses@nxp. 8 Thermal FoldBack (TFB) . . . . . .2 16. . . Disclaimers.3 13. . . 1 Quick reference data . . 9 Window Protection (WP). . . . . . . . . . . . . . Introduction to soldering through-hole mount packages . . . . . . . . . . . 2009. . . . . . . 14 Switching characteristics . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . .3. . . . . . . . . 17 Pin MODE. . . . . . . . . 1 Applications . . . . . . 17 Mono BTL application . . . . . . . . . . 17 Estimating the output power . . . . . . . . . . . . . .1 12. . © NXP B. . 18 External clock . .1 8. . . .5 13. . . . . . . . . . . . . . . . . . . . . . . . . Soldering by dipping or by solder wave . . . . . . . . . 13 Dynamic characteristics . . . . . . . . . . . . . . . . . . . .3. . . . . . . . . . . . . . . . . . . . . . . . . . . .NXP Semiconductors TDA8922C 2 × 75 W class-D power amplifier 20. . . . . . . . 35 Reflow soldering . . . 23 Package outline . . . .2 12. . .1 13. . . 2 Ordering information . . . . . . . . . . . . . . . Contents 1 2 3 4 5 6 7 7. . . . . . . . . .3 8. . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . .2 8. . 4 Pin description . . . . . . . . . . . . . . . . 20 Application schematic . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . .