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High-side current-sensing switched-mode regulator provides constant-current LED drive
Bradley Albing, Philips Medical Systems Inc, Cleveland, OH

M

any suitable circuits exist for driving LEDs in constant-current mode and from low-voltage sources. For example, references 1, 2, and 3 show circuits that use switched-moderegulator ICs and low-voltage sources to supply LED current. To produce a constant-current output using the circuit in Reference 2, you configure the regulator IC as a boost-mode switcher and use a resistor to sense the load current flowing in the LED string’s low side, or negative-return leg. The sense resistor produces a proportional voltage that’s applied to the LT1300’s Sense input through a 2.5V ref9V

erence diode. A voltage of 3.3V appearing at the LT1300’s feedback-input terminal, Pin 4, indicates that the circuit’s output is within regulation. In applications that require a series string of LEDs to operate with its low side connected to ground, current sensing must take place in the string’s high side. You can use either a rail-to-rail op amp and a handful of passive components or a dedicated current-sensing IC, such as Maxim’s MAX4073T, to accomplish high-side sensing. However, adding a current-sensing IC increases circuit cost. To complicate matters, in this applica-

High-side current-sensing switched-mode regulator provides constant-current LED drive ..........................95 Microcontroller’s DAC provides code analysis ..................................................96 Two gates and a microprocessor form digital PLL ..............................................98 Simple sine synthesizer generates 19-kHz pilot tone for FM baseband signal ..............................................................100
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LED D3 R1 10k
+

C1 120 F

L1 22 H VCC 6 IC1 LT1300 SW 7 4 2 C2 + 10 F R2 Q1 100k 2N4402 D1 1N5817 R4 15 1

LED D4 LED D5 LED D6 LED D7 2 D2 1N5248 18V R3 1k 3 LED D8 LED D9 LED D10

5 3 8 1

I-LIM SHDN P-GND GND

SENSE SEL

R5 1k

C3 1 F 9V RETURN

Figure 1
A single switched-mode-regulator IC drives a series-connected string of LEDs in constant-current mode. www.edn.com

S1 ON/OFF

April 14, 2005 | edn 95

” EDN.put to the DAC’s output pin and observe can set the oscilloscope’s horizontal ment. make ily add the constants as needed. 3. boosts 9V to drive the LED string. www.constant to the DAC whenever the voltage at a given time. As a precaution. you en. FL F inding out where your microcontroller’s firmware spends most of its VARIOUS FIRMWARE time can be a tedious task when you SUBROUTINES. by reserving all state constants’ valcode structure comprises a state machine you connect an oscilloscope’s vertical in. “1. The technique uses the DAC in microcontrollers such as Cypress MiFigure 1 OSCILLOSCOPE crosystems’s PSoC (programmablesystem-on-chip) family (Figure 1). Application Note 59.ues greater than 127 for error states. Heathrow. LT1300 data sheet. tion.3V at Sense Pin 4 of IC1. For examoperating states of your design. you create firmware enters a particular location.com 96 edn | April 14. you write the state ply by measuring the DAC’s dc output ed outputs are unsuitable for this appli. Sept 30. then you have already defined its output voltage. At a cur- Microcontroller’s DAC provides code analysis Dave Bordui. OR and breakpoint techniques. IC1. Resistor R4 serves as a current-sense resistor. ple. 2004.output pins.your oscilloscope includes measurement erates within its allowable update-rate able a DAC and configure it to drive one cursors. If sure that the microcontroller’s DAC opOnce you define the constants. Cypress Semiconductor. developing sufficient voltage drop to produce the requisite 3. a technique WAVEFORM that takes advantage of a feature that many microcontrollers now include ofERROR fers a simple debugging aid that allows CONDITION designers to easily monitor these and OR STATE other operations. Other such VARIABLES tasks include discovering why a state ma8-BIT chine doesn’t work as you intended and I/O PIN I/O DRIVER INTERNAL SUBROUTINE.design ideas rent of approximately 40 mA. Zener diode D2 limits the regulator’s output voltage in case the LED string or connector opens. cation. you can easily determine which range. In this Design Idea. you can eas. operation or during an error condition. 2005 . Fortunately. an LT1300. Linear Technology Corp. Then. To use this technique. only three conductors are available to connect a remotely mounted LED string. Switch S1 turns on the circuit by grounding IC1’s Pin 3. References 1. D3 through D10.edn. DEBUG VALUES Classic debugging methods can also become cumbersome when you attempt to observe error states or debug a programCHARACTERISTIC OPERATING flow problem. Caldwell. Next. transistor Q1 conducts and forces current through R3.displays as a characteristic waveform that indicates an error.5V battery powers white-LED driver. you can also mon. represents the firmware’s operation. blocks that includes true DACs that can deliver fixed dc levels. Otherwise. If You can define state constants to firmware “state constants” that represent you use an 8-bit DAC. If your itor the value of any 8-bit variable. Linear Technology Corp. and on/off switch S1 to the regulator circuitry. STATE. which the instrument sweep generator to trigger at a level that these constants. DAC where your code goes during real-time VARIABLE.highlight certain conditions. which presents a total forward-voltage drop of approximately 12V (Figure 1). bringing its output current into regulation. pg 96. use a conventional in-circuit emulator STATES. These devices provide a microcontroller core Put an unused internal DAC to work as a code analyzer and see where a microcontroller’s routines and an array of mixed-signal building go wrong. ERROR. you or contains a large “switch/case” state. 2. Other types of of the microcontroller’s unused analog portion of the firmware is executing simDACs that deliver pulse-width-modulat. Steve.

Although ital PLL’s output frequency locks to the clock-signal clock frequency to OR gate some interrupt-service-routine opera.36 .riod clock-frequency count. MS IC3 5V ou can use Microchip’s low-cost PIC16F818 VDD PIC16F818 microprocessor and a CLKOUT 15 pair of gates to construct a digital RA6 VDD 14 PLL that can clean noisy digital signals 1 12 3 PHASE-GATED CLOCK 12 f1 C1 over a range of 4 to 40 kHz. two. which corresponds to a phase of 0. Featuring RB8 11 2 IC2 13 0.com . after the division factor dicle or phase interval of the output freFor phase lock. the requires a minimal number of components.input frequency is 10 kHz. 2005 www. TareTronics Inc. K. This XNOR-based then divides the output of Timer 1 by is 50 sec. the digthe phase detector’s output along with quency’s next half-period. Applying which sets the length of the output fre.edn. clock pulses during each half-period in. As an example. its terval of output frequency. Thus. and put frequency.variable phase count yields a value of 20. The external input that execute in about 10 sec when IC3’s division factor for the clock-frequency signal’s input frequency drives the XNOR internal clock oscillator runs at 8 MHz. when the clock phase detector provides good perform. count that represents the phase of the gate’s remaining input to produce an out.After each Timer 2 interrupt.values in Equation 1 and solving for the The phase difference signal’s duty cy. the digital-PLL en13 RB7 CD4077B gine and lock detector can extract clock fOUT 2 fOUT RA3 and data information from noisy. the maximum signal-output frequency. associated with IC3’s Timer 1. the half-pepulses from IC2 to the internal prescaler able half-period count adjusts the out. Substituting these ance with noisy digital input signals. between the input and the output freThe interrupt-service-routine software quency.is typically as follows: If the input frequency decreases. frequency is 2 MHz. CONNECT PIN 14 TO VDD AND PIN 7 TO GROUND ON IC1 AND IC2. cle remains linear over a 0 to 180 range ference to Timer 2’s period register.riod of the output frequency increases.subtract it from the maximum half-peThe circuit applies phase-difference quency half-period. checks for phase lock. With its associated period register. When Timer 2’s count This microcomputer-based digital-PLL circuit locks to signals over a 4. is two. with these parameters.design ideas Two gates and a microprocessor form digital PLL Kenneth Martin. the vari. order analog PLL (Reference 1). Timer GROUND ALL UNUSED GATE INPUTS.four. the interrupt toggles an I/O port’s output to produce square-wave for Timer 2 closes the loop and deter. The half-period of 10 kHz input frequency. During each of the output able count changes in the direction necmation that writes to the period register frequency’s half-periods. two. frequency is within lock range. the output-frequency vides the variable phase count and you quency relative to the input frequency. or of two same-frequency signals. assume that the od. which represents the phase rupt-service routine toggles the output put frequency is phase-locked to the indifference.ing it toward a new match with the input Y 98 edn | April 14. SINGLE-OR GATE. The microprocessor then computes a byte of infor. or eight. shortrange radio signals (Figure 1). and the variable (1) length and the number of clock pulses it phase count becomes smaller. which drives mines the digital PLL’s key parameters.input frequency with a phase difference IC2 produces an output burst of 2-MHz tions slightly modify the result. four. the sive-nor) gate.mulates (integrates) the prescaled pulses. clock-frequency cycle count for each outone input of the external XNOR (exclu. Corinth. board area that’s approximately as large ILLUMINATED OPTIONAL IC2 IS A CD4071B OR FUNCTIONALLY EQUIVALENT WHEN as an aspirin. timer generates an interrupt. According contains depend directly on the duty cyto Equation 1. making K equal to one.two.to 40-kHz range and matches the byte in its period register. In addition. IC1. phase differ5 VSS CD4071B IC1 PHASE OR fIN ential.essary to achieve and maintain phase lock to set the duration of the next half-peri. The burst’s half-period lengthens. The routine subtracts the re.1. N0. LOCKED IC3 IS A CD4077B OR FUNCTIONALLY EQUIVALENT Figure 2 is analogous to a firstFigure 1 SINGLE-XNOR GATE. Timer 1 accu.sulting value from N0 and writes the dif. or 16. is 110. the inter. When you 18 LOCK INDICATOR RA1 LOCK construct it using a QFN-packaged miR1 croprocessor and discrete single-gate OPTIONAL 1k logic devices. 2 functions as a DCO (digitally controlled oscillator). and the output signal.1 F programmable lock range. the circuit occupies a pcNOTES: LED1 PINOUTS ARE FOR A PIC16F818 DIP. eight. The computed vari.This routine comprises 19 instructions put-frequency half-period. which di. and loop gain. this count of 36 . If the input lowering the output frequency and drivvides them by a preset factor of one. between the output and the frequency.output frequency.put’s frequency and phase. half-period must equal the input-fre. or 100 counts.

OR EIGHT 8-BIT TIMER 1L (COUNTER MODE) frequency. The range of 555 Hz.N0 reduces jitter. four. and 0 0. For a rewww. and the L R and L R signals consist of DSBSC (double-sideband-suppressed-carrier) modulation centered at 38 kHz. signal at the same frequency as the input source code. Equation 2 defines the digital PLL’s operation in phase-lock frequency. N0 is the maximum clock-frePERIOD REGISTER quency cycle count for each output-freFOR TIMER 2 quency half-period. If the input frequency increases. Gardner. the PLL adjustments of the values of N0 and K for lower limits of the lock range. and minimum frequency is reduce jitter. calculated value of phase-lock frequency Resolution of the DCO using Timer 2 the interrupt-service routine. Increasing K to 16 microprocessor’s on-chip oscillator to use niques.design ideas fCLK INPUT fIN PRESCALE + ONE. N0 Figure 2 + MAXIMUM fOUT eight. 2005 . For examis accurate to within 1. Timer 2 produces plementing more sophisticated lock-detion of parameters is repeatable.tection circuitry to determine whether You can manipulate Equation 2 to cy. Spain A multiplex signal comprises baseband information transmitted on a stereo analog FM-broadcast system. and a microprocessor frequency relative to the input frequency. and K is the division factor for the clock-frequency cycle count that represents the output phase of the output An XNOR-gate phase detector provides good performance with noisy signals.where HALF-PERIOD is the clock fref is the frequency. Simple sine synthesizer generates 19-kHz pilot tone for FM baseband signal Carlos Bernal and Diego Puyal.a center frequency of 9266 Hz. od register puts the PLL in “coast” mode.com 100 edn | April 14. and a lock design to a variety of applications by modifying the software and extending ations that slightly affect the timing. which is the assembly-language tal PLL’s “center frequency.25. Adding a constant value of 2. frequency. as well as the hex programwhich corresponds to a 90 phase angle. respectively. Phaselock Tech8989 Hz. Because the frequency relative to the input frequency. The 19-kHz pilot tone comprises a baseband signal.mum frequency of 8989 Hz. Departamento Ingeniería Electrónica y Comunicaciones. Using a relatively large value of ming file for IC3.5 switches between the counts to produce better performance.5 to the outYou can adapt the digital PLL’s basic put frequency’s period count compen.” set at 0. you can increase the clock Reference 1. the reverse occurs. and design-selected system parameters: (2) +2 34 N0 255.408 Hz. TWO.edn. a minisates for interrupt-service-routine oper. operation with any combina. PLL comprises only digital circuits and Depending on the integer count written Other expansion possibilities include imsoftware. is the phase of the fCLK output frequency relative to the input 8-BIT fOUT TIMER 2 frequency. center frequency is increases jitter. FOUR. plus one or more SCA (Subsidiary Com- munications Authorization) channels (Figure 1).tween discrete output frequencies that frequency range and making dynamic maining four. yields a maximum frequency of 9544 Hz an external 20-MHz crystal.408 to frequency to 5 MHz by configuring the 8989. whereas a smaller value of this Design Idea at www. set at 0.com. quency is 13.the input frequency falls within a certain solve for any variable in terms of the re. fCLK PERIOD quency.to its period register. Floyd M. discrete frequencies for output frequen. This Design Idea presents a low-cost method of generating the basic 19-kHz pilot tone. To calculate the upper and two adjacent counts produce. from the online version In the previous example. You can download and 0. To calculate the digi.an averaged but jittery output-frequency Listing 1. or 4419 Hz. Wiley-Interscience. When the input frequency falls be. maximum fre. Zaragoza.204 Hz. handles signal processing. Universidad de Zaragoza.5. The lock range is 13. or 16. To improve resolution and 11.5% over most establishes the time jitter of the output ple. stopping updates to Timer 2’s periof the PLL’s usable range. ISBN 0-471-04294-3. 1979.edn. K two. Second Edition.

86 MHz 90 10 fine phase adjustment to correct distortion Figure 2 and to resynchronize at zero The pilot-tone-generator circuit uses low-cost CMOS-logic circuits plus an analog multiplexer. In addition.nents with frequencies greater than 15 lot sine wave. You can expand the basic circuit by duwave and are relatively low to present of frequency fSIN. 2. 3. The resistors’ values are weighted to provide N 8 a zero-order hold circuit. An exterup/down counter.” low-impedance sources to eight.216-MHz signal clocks the second up/down counter and V a 38-kHz up/down control IC signal derived from higher R R R R MC14051 10 10 7. and sections kHz. R1 through R11. 7 USE 100-nF.com . To produce B 9 NOTES: C the composite multiplex RESISTOR TOLERANCE IS 1%. R GROUND UNUSED INPUTS ON IC . A 1.and L R-channel R Q3 6 R R 330 R 10 10 generation without chang22M 11 9 Q0 CLK ing components’ values.5k 6. In effect. and up/down counter. CC 1 2 1 14 15 1 3 1 2 3 4 5 CC 6 CC 4 2 7 3 8 9 4A 4B CC 5A 13 10 11 12 5B CC 1 102 edn | April 14.8k frequency taps on counter 13 3 PILOT-TONE X0 X OUTPUT 14 P IC2. 15 19 23 38 53 75 The low-distortion. IC2. any disL+R SCA1 SCA2 tortion in the pilot tone produces harL R L R (LSB) (USB) monics that can interfere with adjacent 99 sections of the signal. The same 20 IC IC 3 1 2 3 4 1 Q0 CLK B NODE HEF4069 HEF4069 circuit structure produces 4 2 EN IC Q1 V HEF4520 Q2 5 7 R L R.and R audio signals that have undergone reduce the distortion of the 19-kHz pi.network’s upper and lower ends with L symmetry to enhance the resolution and quately removes the alias frequencies. a simple passive RC nal audio source drives the resistor takes advantage of a sine wave’s inherent filter at the multiplexer’s output ade.edn. and the L R 5 X5 modulation in synchro2 X6 R 4 X7 36 nism with the 19-kHz pilot 6 INH tone because all clock pulses originate from a com11 R A 47 10 mon counter. analog multiplexer IC1 acts as trol signal for counter IC2. An m (2 N fSINE). crossing. conFigure 1 A typical FM-broadcast signal contains a complex spectrum. plus several attenuated plicating the resistor network. 2005 www. nected between the VCC and VCC supply rails (Figure 2). 12 11 P1 Q1 14 13 Q2 Using the specified com3 P2 2 P3 Q3 R IC 6 7 5 1 ponents. CERAMIC-BYPASS CAPACITORS V signal. Bi. multi“stiff. the outputs of both VEE ON V PINS OF ALL ICs. drives IC1 and most applications. where m 1.nary counter IC3 generates a 608-kHz lowpass-filtering to eliminate compoclock signal plus a 19-kHz up/down con. producing an of hex inverter IC1 serve as a crystal osapproximate sampled values of a sine N times Nyquist oversampled sine wave cillator and buffer. For plexer. Po12 10 C NODE Q1 EN IC V HEF4520 Q2 13 tentiometer P1 allows a 15 R 14 X Q3 4.alias frequencies centered at: fALIAS channel analog multiplexer IC1. The added circuitry X1 C C C 10k 15 R X2 1 nF 1 nF 1 nF generates the baseband 20 12 X3 1 X4 L R channel. the transmitted pilot tone and L R signal must synchronize at their respecSCA SERVICES tive zero crossings.design ideas ceiver to correctly demodulate the sigPILOT TONE nal. the circuit gener47 PE HEF4069 COUT 5 CIN ates a 19-kHz pilot tone 10 U/D 15 CLK with harmonics 60 dB be9 RST R low the fundamental and 36 synchronous with the maximums of the suppressed R 38-kHz carrier. 51 analog multiplexers sum in IC 4 6 P0 MC14516 Q0 an external network. 19-kHz pilot-tone MODULATION (kHz) generator comprises a resistive voltage divider.