SiT-AN10009 Rev. 1.

0 9 March 2009

Differential Output Terminations LVPECL, HCSL, LVDS, and CML 1 Introduction
SiTime offers a wide selection of differential outputs to facilitate various types of clock applications. This application note describes each output type and the recommended termination methods.

2 LVPECL
The SiTime LVPECL outputs use current-mode drivers, primarily to accommodate multiple signaling formats. Two types of LVPECL outputs are provided: “LVPECL DC-coupled” and “LVPECL AC-coupled”. The DC-coupled version has a 16 mA switched current driver while the AC-coupled version has a stronger driver with 22mA of switched current. Both types are available for 3.3V and 2.5V applications.

2.1 LVPECL DC-coupled
The structure of a SiTime DC-coupled LVPECL driver is shown in Figure 1.

VDD

Chip boundary
16mA 6mA 6mA

OUT+ OUT -

Figure 1. SiTime DC-coupled LVPECL Output Structure
-------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 1 SiT-AN10009 Rev 1.0
The information contained in this document is confidential and proprietary to SiTime Corporation. Unauthorized reproduction or distribution is prohibited.

OUT+ Z = 50 D+ OUT- Z = 50 D- 50 50 VT = VDD – 2. The outputs are terminated to VDD-2V via 50 resistors. LVDS. and temperature (PVT) variations. The 50 resistors should be placed as close to the receiver as possible.1. the usage of 1% precision resistors is recommended. Consequently. When it is not active. HCSL. thus creating a single-ended signal swing of 800mV. -------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 2 SiT-AN10009 Rev 1.0 The information contained in this document is confidential and proprietary to SiTime Corporation.3V and 2. The single-ended signal swing is 800mV nominally and could vary between 600 mV and 1000 mV due to process. it will source 22 mA of current (16 mA + 6 mA). When an output is active. the voltage developed across the 50 load resistor will vary between 1. Therefore. This termination method is shown in Figure 3. then each output can be terminated simply with a 50 resistor to the termination voltage as shown in Figure 2. voltage. a pull-up and a pull-down resistor forming a Thevenin Equivalent network can terminate the 50 transmission line while establishing an effective termination voltage of VDD-2V at the receiver.0V Figure 2. In addition.1 Termination Recommendations If a termination voltage source (VDD -2V) is readily available. large resistor variations may result in excessive voltage swing variations beyond the limits above. For systems sensitive to signal swings beyond the nominal range. the output voltage is proportional to the value of the load resistor. 2.1V and 300 mV.Differential Output Terminations LVPECL. Please note that the resistor values are different for 3. . DC-coupled LVPECL with load termination In applications where the termination voltage is not readily available. CML Each output is driven by two current sources: a switched 16 mA current source and a dedicated 6 mA constant current source. it will drive only 6 mA of current. Unauthorized reproduction or distribution is prohibited.5V operations.

thus reflecting back virtually all the signal from the load. DC-coupled LVPECL load termination with Thevenin Equivalent Network The termination methods in Figures 2 and 3 work well if the impedance of the PC trace and the impedance of the termination circuit at the load end are reasonably matched. HCSL. The termination at the receiver (load) end can be viewed as a RLC circuit with an impedance of Zload.5V R1 133 250 R2 82 62. the output impedance is the range of several K-ohms. some of the signal from the driver (source) will be reflected back. However.5 Figure 3. the source also has its own reflection coefficient ( Γ S) and it is defined as: ΓS = Z Source − Z o Z Source + Z o Equation 2 where Zsource is the impedance of the driver. Unauthorized reproduction or distribution is prohibited. so Γ S is close to 100%. LVDS. However. the majority of the signals will be absorbed by the load due to its low Γ L value. For the SiTime LVPECL current driver. The amount of signal reflected is determined by the reflection coefficient of the load ( Γ L). Fortunately.5 R3 133 250 R4 82 62.3V 2. the Γ L in terminated interfaces shown in Figures 2 and 3 is relatively small (less than 10%). so only a small amount of the signal will be reflected back towards the source. that is not always an adequate assumption because the termination circuit also includes the receiver’s input structure and the receiver’s package. Because Zload and Zo are seldom matched exactly. CML VDD R1 OUT+ R3 D+ Z = 50 OUT- Z = 50 D- R2 R4 VDD 3. . -------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 3 SiT-AN10009 Rev 1.0 The information contained in this document is confidential and proprietary to SiTime Corporation.Differential Output Terminations LVPECL. ΓL = Z Load − Z o Z Load + Z o Equation 1 Generally speaking.

0V VT = VDD – 2. the receiver inputs are biased by a 50 resistor to a termination voltage (VT). The value of VT is determined by the common mode voltage requirement of the receiver. causing the signal swing to reduce from 800 mV to 400 mV. may be used. In situations where the load reflection coefficient is relatively high.Differential Output Terminations LVPECL. thus increasing the signal swing for a 25 load from 400 mV to 550 mV. -------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 4 SiT-AN10009 Rev 1. 2.2 LVPECL AC-coupled If the LVPECL output drives a differential receiver with a different common mode voltage. the capacitor blocks the DC path for the driver’s outputs. A capacitor is used to block the DC path to the receiver. allowing its inputs to be biased by a separate circuit. CML For most applications. Figure 5 shows such a connection. HCSL. as shown in Figure 4. a double termination strategy.0V Figure 4. In this example. LVDS. a 25 equivalent load is presented to the LVPECL driver. the single termination at the load is sufficient. the user can choose the “LVPECL. If this signal level is insufficient for the receiver. additional 150 resistors are installed between the outputs and ground at the source end to provide the required DC current paths. Therefore.0 The information contained in this document is confidential and proprietary to SiTime Corporation. The switched current sources (see Figure 1) in these oscillators are enhanced from 16 mA to 22 mA. Unauthorized reproduction or distribution is prohibited. . AC Coupled” version of the oscillator with higher switched current drivers. AC-coupled LVPECL with double termination (source and load) With the addition of the 50 termination at the source. In an AC-coupled connection. then an AC-coupled connection is recommended. To eliminate this effect. the round trip reflected signal may result in erroneous triggering of the receiver. OUT+ Z = 50 D+ OUT- Z = 50 D- 50 50 50 50 VT = VDD – 2.

CML 100 nF OUT+ Z = 50 D+ 100 nF OUT- Z = 50 D- 150 150 50 50 VT (receiver dependent) Figure 5. some of them may require a larger signal swing. the 150 resistor at the source is in parallel with the 50 resistor at the load. DC-coupled” version with 16 mA current drivers is used.Differential Output Terminations LVPECL.0 The information contained in this document is confidential and proprietary to SiTime Corporation. AC-coupled LVPECL From the AC stand point. the receiver will observe a 595 mV signal swing. 3 HCSL The High Speed Current Steering Logic output (Figure 6) is driven by a 15 mA switched current source typically terminated to ground via a 50 resistor. . LVDS. For those applications. thus increasing the nominal signal swing to 825 mV. The nominal signal swing is 750 mV. While this signal level may be sufficient for most of the receivers. If the “LVPECL. HCSL output structure -------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 5 SiT-AN10009 Rev 1. the user could choose the “LVPECL. VDD 15mA Chip boundary OUT+ OUT- Figure 6. resulting in a 37.5 equivalent load to the driver. HCSL. AC Coupled” version with 22 mA current drivers. Unauthorized reproduction or distribution is prohibited.

resulting in a voltage difference of 350 mV between the receiver inputs. The resistor matches the impedance of the transmission lines and provides a current path for the signal. LVDS. and D. LVDS uses differential signals with low voltage swings to transmit data at high rates. the current will flow through transistor A. The 10 – 30 series resistor is not part of the termination circuit and its value is layout dependent. From an AC standard point. CML The HCSL interface is typically source-terminated with a 50 load as shown in Figure 7.5 mA nominal current source connected to differential outputs via a switching network. HCSL. Since the PC traces used in this interface has a characteristic impedance of 50 . .Differential Output Terminations LVPECL. virtually all the current from the driver will flow through the 100 resistor. The open-drain transistor at the output has fairly high impedance in the range of several kilo-ohms. C. the current will flow through transistor C. the impedance of the output transistor is parallel to the 50 load resistor. transistors A and B will be turned on. Because the impedance of the receiver is typically high. and return through transistor D. transistors C and D will be turned on.0 The information contained in this document is confidential and proprietary to SiTime Corporation. It is used as an overshoot limiter by slowing down the rapid rise of current from the output. In Figure 8. the 100 resistor. when the signal IN is low. B. The outputs are typically attached to 100-ohm differential transmission lines terminated with a 100 resistor at the receiver end. respectively. the 100 resistor. Figure 8 is the diagram of a LVDS driver consisting of a 3. When signal IN is high. SiTime recommends 20 ohms as the starting value for the series resistor.2V. any signal reflected from the load will be absorbed at the source. resulting in an equivalent resistance very close to 50 ohms. 10-30 OUT+ Z = 50 D+ 10-30 OUT- Z = 50 D- 50 50 Figure 7. -------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 6 SiT-AN10009 Rev 1. Unauthorized reproduction or distribution is prohibited. Signal switching is accomplished with four transistors labeled A. and return through transistor B. It is defined in the TIA/EIA-644 standard. The common mode voltage is specified at 1. HCSL Interface Termination 4 LVDS LVDS (Low-Voltage Differential Signaling) is a high-speed digital interface suitable for many applications that require low power consumption and high noise immunity.

1. LVDS. while a negative differential voltage represents a logic low level. A positive differential voltage represents a logic high level.5mA Figure 8.5V applications. .5mA Chip boundary IN C A IN OUT+ B D 100 OUT- 3. The high swing version is designed to be used in double termination configurations. 4. LVDS driver shown with termination resistor It is important to note that direction of the current flowing through the resistor changes according to the state of the output signal.3V and 2. the direction of the current flowing through the termination resistor determines whether a positive or negative differential voltage is registered. The normal swing version has a 3. Both versions are available for 3.5mA current source while the high swing version features a 7 mA current source. CML VDD 3. For the receiver.0 The information contained in this document is confidential and proprietary to SiTime Corporation. -------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 7 SiT-AN10009 Rev 1. so no external termination component is required with those receivers.1 DC Termination A LVDS interface with 100 differential traces is typically terminated at the receiver end with a 100 resistor across the differential inputs of the receiver (see Figure 9).1 Termination Recommendations 4.Differential Output Terminations LVPECL. SiTime provides two types of LVDS output swings: normal and high. Some receivers have incorporated the 100 resistor on-chip. HCSL. Unauthorized reproduction or distribution is prohibited.

The former configuration is shown in Figure 11 while the latter configuration is -------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 8 SiT-AN10009 Rev 1. LVDS. so the receiver must implement it own input bias circuit. the equivalent resistance seen by the output driver is reduced to 50 . HCSL. CML OUT+ Z = 50 D+ 100 OUT- Z = 50 Normal Swing D- Figure 9. AC termination can be configured as either a single termination at the load or as a double termination. a double termination arrangement may reduce the overall round trip reflection and prevent the erroneous triggering of the receiver (see Figure 10). LVDS single DC termination at the load For most applications. Unauthorized reproduction or distribution is prohibited. LVDS double DC termination 4.Differential Output Terminations LVPECL. A capacitor is used to block the DC current path from the driver. With a 100 resistor at both the source and the load.1 for more information.1. Please refer to section 2. then an AC termination is recommended. SiTime provides the “high swing” version for its LVDS drivers with a 7 mA current driver to restore the differential signal swing back to 750 mV. causing the output signal swing to be cut by half.1. In situations where the load reflection coefficient is relatively high.0 The information contained in this document is confidential and proprietary to SiTime Corporation. . a single termination at the load is sufficient.2 AC Termination If the LVDS driver and the receiver are operating with different common mode voltages. OUT+ Z = 50 D+ 100 OUT- 100 Z = 50 D- High Swing Figure 10.

LVDS single AC termination at the load The double terminations shown in Figures 12 and 13 are very similar. HCSL. They differ only by the position of the DC-blocking capacitor.0 The information contained in this document is confidential and proprietary to SiTime Corporation. the configuration shown in Figure 12 is recommended. During clock start-up. a valid clock signal will be available to the receiver sooner. 0. the capacitor in Figure 12 will be charged much faster than that in Figure 13. Because of its higher RC time constant.1uF Z = 50 D- High Swing Figure 12. it can sustain data sequences with longer ones and zeros without experiencing significant voltage droop.1uF Z = 50 D- Normal Swing Figure 11. Please note that the “high swing” version may be used with the double termination. On the other hand. If fast clock start-up is important.1uF OUT+ Z = 50 D+ 100 OUT- 0.Differential Output Terminations LVPECL.1uF OUT+ Z = 50 D+ 100 OUT- 100 0. the configuration shown in Figure 13 may be more advantageous. LVDS double AC termination with capacitor close to source In data transmission applications. CML shown in Figures 12 and 13. . which is the equivalent of 50 . The capacitor in Figure 12 is charged by the common mode current flowing through half the differential resistance. LVDS. Unauthorized reproduction or distribution is prohibited. -------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 9 SiT-AN10009 Rev 1. 0. the capacitor in Figure 13 is charged by the current through the resistance of the receiver’s inputs which can be in the range of kilo-ohms. Therefore.

external pull-up resistors are needed. Output structure of a CML driver -------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 10 SiT-AN10009 Rev 1. Unauthorized reproduction or distribution is prohibited. LVDS double AC termination with capacitor close to load 5 CML SiTime Current Mode Logic (CML) drivers are constructed with a NMOS open-drain differential pair and an 8 mA constant current source. .1uF OUT+ Z = 50 D+ 100 OUT- 100 0. The output structure is shown in Figure14. OUT+ OUT- 8 mA Chip boundary Figure 14. LVDS.1uF Z = 50 D- High Swing Figure 13. Voltage swing across a 50 resistor is typically 400 mV.0 The information contained in this document is confidential and proprietary to SiTime Corporation. Because the open-drain transistors are only capable of pulling down a signal. HCSL.Differential Output Terminations LVPECL. CML 0.

as shown in Figure 16. -------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 11 SiT-AN10009 Rev 1.1. SiTime offers the CML “high swing” version with 16 mA current drivers to restore the signal swing back to 400mV. In most cases.5V. 2. Because two 50 termination resistors are connected in parallel to the output.8V. Two output signal swing versions are supported: normal and high.3V.1 for more information. 5. Unauthorized reproduction or distribution is prohibited. The differential outputs are pulled up to a termination voltage VT. VDD is used as the termination voltage. a double termination strategy. their equivalent resistance is reduced to 25 . LVDS. The normal swing version is equipped with an 8 mA current source while the high swing version has a 16 mA current source. in applications where the driver and the receiver are operated at different VDDs. However. causing a 50% reduction in the output swing. HCSL. In such case.1.0 The information contained in this document is confidential and proprietary to SiTime Corporation. and 1. CML with single DC load termination In situations where the round trip reflections due to a relatively high load reflection coefficient may cause extra triggering of the receiver.1 DC Termination A typical CML termination is shown in Figure 15.Differential Output Terminations LVPECL.1 Termination Recommendations 5. . both the source and the load are typically terminated to the same VT. CML SiTime’s CML clocks can operate at 3. could be used. VT is typically set to the higher of the two VDDs. Please refer to section 2. OUT+ Z = 50 D+ OUT- Z = 50 D- Normal Swing 50 50 VDD ≤ VT ≤ 3.63V Figure 15.

As we explained in the previous section. a single termination at the load end is sufficient (Figure 17).63V Figure 16. 0. CML with double DC termination 5. so the user must provide a separate bias circuit for the receiver inputs.2 AC Termination An AC termination should be used if the receiver requires a different input bias. The DC path to the receiver is blocked by the capacitor.1. Unauthorized reproduction or distribution is prohibited. LVDS. CML single AC termination at the load end -------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 12 SiT-AN10009 Rev 1. The VT is typically the VDD of the driver. HCSL. In many cases.63V VDD ≤ VT ≤ 3. For noise sensitive application.63V Figure 17.1uF OUT+ Z = 50 D+ OUT- 0. a double termination configuration shown in Figures 18 and 19 can be used.1uF Z = 50 D- Normal Swing 50 50 VDD ≤ VT ≤ 3.0 The information contained in this document is confidential and proprietary to SiTime Corporation.Differential Output Terminations LVPECL. CML OUT+ Z = 50 D+ OUT- Z = 50 D- High Swing 50 50 50 50 VDD ≤ VT ≤ 3. the “High Swing” version may be used in double terminations to maintain a 400 mV signal swing. .

During clock start-up.63V VDD ≤ VT2 ≤ 3. CML 0.1uF D+ OUT- Z = 50 D- High Swing 50 50 50 50 VDD ≤ VT1 ≤ 3. VT1 is typically the VDD of the driver and VT2 is typically the VDD of the receiver.63V Figure 19. In Figure 19.1uF OUT+ Z = 50 0.0 The information contained in this document is confidential and proprietary to SiTime Corporation. HCSL. whereas the capacitor in Figure 19 is charged by the current through the resistance of the receiver’s inputs which can be in the range of kilo-ohms. VT1 and VT2 are typically set to VDD of the driver. CML double AC termination with capacitor close to source 0. CML double AC termination with capacitor close to load The double terminations shown in Figures 18 and 19 are very similar. They differ only by the position of the DC-blocking capacitor. the capacitor -------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 13 SiT-AN10009 Rev 1.1uF OUT+ Z = 50 D+ OUT- 0. The capacitor in Figure 18 is charged by the current flowing through the 50 termination resistor.1uF Z = 50 D- High Swing 50 50 50 50 VDD ≤ VT1 ≤ 3.Differential Output Terminations LVPECL. In Figure 18. . LVDS. Unauthorized reproduction or distribution is prohibited.63V Figure 18.63V VDD ≤ VT2 ≤ 3.

HCSL. with regard to this material. SiTime assumes no responsibility or liability for any loss. and any implied warranty arising from course of dealing or usage of trade. In data transmission applications. The information contained herein is subject to change at any time without notice.0 The information contained in this document is confidential and proprietary to SiTime Corporation. or (v) being subjected to unusual physical. LVDS. Products sold by SiTime are not suitable or intended to be used in a life support application or component. it can sustain data sequences with longer ones and zeros without experiencing significant voltage droop. Disclaimer: SiTime makes no warranty of any kind. (ii) misuse or abuse including static discharge.Differential Output Terminations LVPECL. Because of its higher RC time constant. as well as any common-law duties relating to accuracy or lack of negligence. CML in Figure 18 will be charged much faster than that in Figure 19. Unauthorized reproduction or distribution is prohibited. the configuration shown in Figure 19 may be more advantageous. Additionally. or (iv) improper installation. multiple current strength options in these clocks support double termination strategies without sacrificing signal swing voltages. 6 Conclusion This application note presented the SiT9102 and SiT9002 differential output driver models and the most commonly used termination recommendations for four types of differential outputs: LVPECL. the configuration shown in Figure 18 is recommended. express or implied. With such a rich selection of output types. or in other mission critical applications where human life may be involved or at stake. SiTime Corporation 990 Almanor Avenue Sunnyvale. LVDS. and specifically disclaims any and all express or implied warranties. including the implied warranties of merchantability and fitness for use or a particular purpose. to operate nuclear facilities.com © SiTime Corporation. Therefore. damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product. with respect to this material. (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions. statutory or otherwise. . thermal. warehousing or transportation. 2008-2009. HCSL. RAL -------------------------------------------------------------------------------------------------------------------------------------------SiTime Corporation 14 SiT-AN10009 Rev 1. handling. storage. neglect or accident. any SiTime product and any product documentation. and CML. CA 94085 USA Phone: 408-328-4400 http://www. If fast clock start-up is important. a valid clock signal will be available to the receiver sooner. either in fact or by operation of law. the user can easily find one that fits his/her design requirements.sitime. or electrical stress.