CMOS CIRCUIT DESIGN OF THRESHOLD GATES WITH HYSTERESIS Gerald E. Sobelman, Karl Fant Theseus Logic, Inc.

1080 Montreal Ave., Suite 200 St. Paul, MN 55116, USA sobelman@theseus.com,fant@theseus.com

ABSTRACT M-of-N threshold gates with hysteresis form a class of circuit elements that have important application in NULL Convention Logic ", a novel asynchronous logic design methodology. General design guidelines for these M-of-N gates are presented using CMOS technology. Three types of circuit implementations are discussed: static, semi-static and dynamic. In addition, initialization techniques are presented for use in establishing a known initial state. 1. INTRODUCTION The clocked synchronous paradigm is currently the dominant design methodology for digital systems. While this approach has enjoyed great success over many decades, limitations and drawbacks of the methodology exist. For example, the need for precise distribution of high-speed clocks over a large chip area is complex and the clock tree itself dissipates a significant fraction of the total power consumption. Also, the need to meet critical path constraints requires a complex timing analysis based on worst-case design where the performance is limited by the edges of the specified process, temperature and voltage ranges. These problems become more severe as device sizes continue to shrink and as clock frequencies continue to rise. Asynchronous design techniques have been proposed as an alternative to the clocked system methodology, and the subject has a long history [ 11. These approaches seek to overcome the above limitations by dispensing with the clock and using self-timed signaling to control the sequencing of computations in the system. While much research has been devoted to this area, no asynchronous approach has yet managed to gain a strong foothold in the design community. Most of these approaches are themselves highly complex and difficult to design. Also, their claimed advantages have, for the most part, not been sufficiently compelling for designers to consider adopting a major change in their existing methodology. NULL Convention Logic'" (NCL'") is a new clock-free, delay-insensitive logic design methodology [2,3] for digital systems. Unlike previous asynchronous design approaches, NCL circuits are very easy to design and analyze. In NCL, a circuit consists of an interconnection of primitive modules known as M-of-N threshold gates with hysteresis. All functional blocks, including both

combinational logic and storage elements, are constructed out of these same primitives. The designer simply specifies an interconnection of library modules in order to obtain a desired computational functionality. The circuit operates at the maximum speed of the underlying semiconductor device technology. In this paper, we will describe the transistor-level design criteria for CMOS implementations of the M-of-N gates. In section 2, the desired threshold and hysteresis behavior are explained. Then, in sections 3 - 5, various types of CMOS circuit implementations are presented. Initialization techniques are discussed in section 6. Finally, the results are summarized in section 7. 2. BEHAVIOR OF THRESHOLD GATES WITH HYSTERESIS The primitive element that we consider is an M-of-N threshold gate with hysteresis, which we refer to as simply an M-of-N gate. The abstract symbol for an M-ofN gate is shown in Figure 1. The cases of interest are those where M s N. An M-of-N gate is a generalization of both a Muller C-element [4] and a Boolean OR gate. Specifically, for N > 1, an N-of-N gate corresponds to an N-input Muller C-element. On the other hand, a 1-of-N gate corresponds to an N-input Boolean OR gate. The cases where both M > 1 and M < N are novel and have no counterparts in the literature.

z
AN

Figure 1. Symbol for a general M-of-N gate. The M-of-N gates operate on signals that can have two possible abstract values, which we refer to as DATA and NULL. In the normal mapping arrangement, DATA corresponds to a logic-1 voltage level while NULL corresponds to a logic-0 voltage level. The reverse mapping is also possible, as are mappings into units of current. There are two important aspects of the M-of-N gate, namely threshold behavior and hysteresis behavior. The threshold behavior means that the output becomes
DATA if at least M of the N inputs have become DATA.

The hysteresis behavior means that the output only changes after a sufficiently complete set of input values

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0-7803-4455-3/98/$10.00 0 1998 IEEE

If one of the inputs goes to 1. At that point. B and C is shown in Figure 5. Threshold gates with higher values of N can be synthesized using a multi-level tree of small-N gates. ' 9 A24 **'ANA 3. semi-static and dynamic CMOS circuits. As noted earlier. First. the Go to NULL block tums OFF and the Hold DATA block tums ON. the output remains at DATA until all N of the inputs become NULL. The general structure of a static N-of-N gate is shown in Figure 4. l . However. General structure of a static CMOS Mof-N gate. Similarly. this structure has been known in the literature as an implementation of Muller C elements [ ] 4. Static 2-of-3 gate. In the case of a transition to DATA. the Hold DATA block is ON if one or more of the inputs are 1. A1 A2 A3 AN b d b Figure 3. so that all of the PMOS transistors in the pull-up network (not counting the inverter) are ON. This should turn ON when any 2 of the 3 inputs go high. Because of the symmetry of the circuit. the Go to NULL and Hold NULL blocks are ON and Z goes low. the Z output does not change because the Hold NULL block. maintains a connection between the intermediate node and VDD. speed considerations will limit these structures to a maximum number of inputs. & i $ Z DATA DATA Figure 2. The forms for the other two blocks may be obtained by the following analytical procedure. We then reach a situation when all of the PMOS transistors in the pullup network (not counting the inverter) are OFF and all of the NMOS transistors in the pull-down network (not counting the inverter) are ON. the Hold NULL block tums OFF and the Go to DATA block tums ON. In the cases where M < N. Universal blocks within the static CMOS M-of-N gate. In this case.have been established. Also. which remains ON. the Go to DATA and Hold NULL are complementary to each other. it is clear that the Go to NULL block is only ON when all N inputs are 0. begin with the situation where all N inputs are 0. STATIC IMPLEMENTATION§ The general structure of a static M-of-N threshold gate with hysteresis is shown in Figure 2. The switching expression for this condition is as follows: 11-62 . typically N 5 6 . but their precise structures depend on the particular values of M and N. In the following sections. and all of the NMOS transistors in the pull-down network (not counting the inverter) are OFF. From these topologies. we will demonstrate how this desired abstract behavior is implemented using static. The properties of each implementation are pointed out. Because of the series chain in the Go to NULL block. A2+ :A I 4 AN-+.b . a 2-of-3 gate having inputs A. In the case of a transition to NULL. begin with the Go to DATA block. the Go to DATA and Hold DATA blocks are OFF. Note first that the Go to NULL and Hold DATA blocks assume their standard forms. forcing the Z output to DATA. the topologies of the Go to DATA and Hold NULL blocks must be determined for each case. Figure 4. the Go to NULL and Hold DATA blocks are complementary to each other and have the universal forms shown in Figure 3. - 6 Figure 5. For any M-of-N gate. a similar set of actions will occur for the transition of the output back to NULL. the output remains at NULL until at least M of the N inputs become DATA. For analysis of its operation. It is simplest to begin with the special case where M = N. General structure of a static CMOS Nof-N gate. At the same time. As an example. It is only when all N of the inputs go to 1 that the output can change.

Note that the equation for f implies that the Hold NULL block will be ON if two or more of the inputs are 0. which provides additional noise immunity. Since the NMOS and PMOS transistors in this inverter are weak. This is seen to be true because. if two or more of the inputs are 0.f = AB + BC + C A = A B + C(A + B) The structure of the Go to DATA block is obtained directly from this expression using the normal rules for constructing NMOS switching networks. The switching expression for the Go to DATA block is immediately obtained from the desired behavior of this gate: f = ABC + ABD + ACD + BCD This can be factored into a more compact form as follows: f = AB(C + D) + CD(A + B) The Hold NULL block is computed as follows: f wz Go to DATA Figure 7 General structure of a semi-static . This is a special attribute that is present in only a subset of all possible M-of-N gates. then the three input values would necessarily be below the threshold value for this particular gate. the topologies of the Go to DATA and Hold NULL blocks are identical. Note also that in this example. C and D. we obtain: f = . This robustness is due to several factors. First. Since the Hold NULL block is complementary to this. As a specific example. which agrees with the desired behavior for this gate. As a second and more complicated example. ’ = (A’ (A’ + B’ + C’)(A’ + B’ + D’) + C’ + D’)(B’ + C’ + D’) After expanding and simplifying terms. consider the design of a 3-of4 gate having inputs A. We refer to this as the self-dual properq. This form is used in order to obtain maximum robustness against charge sharing effects. threshold gate with hysteresis. $ (weak) T Figure 8. Static 3-of-4 gate. 4. they may not be able to source or sink current fast enough to completely counteract the effects of charge sharing. the weak inverter will eventually restore a partially degraded voltage level at the intemal node to the rail value. Go to NULL The final form for f leads directly to the topology of the Hold NULL block shown in Figure 5 using the normal rules for constructing PMOS switching networks. The factored equations for f and f lead directly to the circuit shown in Figure 6. the design of a semi-static 2-of-3 threshold gate with hysteresis is shown in Figure 8. B. Note that the 3-of-4 gate does not have the self-dual property. B and C inputs have been permuted so that only one intermediate node capacitance in the pull-down network will contribute to charge sharing when any one of the three inputs is high. However. its structure may be obtained by complementing the above expression and then simplifjling using DeMorgan’s laws as follows: f = [AB + A’B’ + B’C’ = A’B’ + C’(A’ + B’) + C(A + B)]’ = (A’ + B’)(C’ + A’B’) = A’C’ Figure 6. the current from the weak devices as well as the extra capacitance at the intemal node both act to limit the extent of charge sharing. 11-63 . each of the three intermediate nodes in the pull-down network would consist of a single shared diffision region. This agrees with the desired behavior for this particular gate. SEMI-STATIC IMPLEMENTATIONS The general structure of a semi-static M-of-N threshold gate with hysteresis is shown in Figure 7. note that the precise order of the A. Also. Note that the presence of the weak feedback inverter also provides some protection. Semi-static 2-of-3 gate.473’ + A’C’ + A’D’ + B’C’ + B’D’ + C’D’ A factored representation is as follows: f=(A’ + B’)(C’ + D’) + A’B’ + C’D’ Note that this result corresponds to the fact that the Hold NULL block will be ON provided that at least two of the four inputs are low. which would have a very small capacitance. in an actual physical layout. Note the structure of the NMOS transistors in the pulldown network is derived from the unfactoredform of the switching expression given earlier. Moreover.

the input data stream is continuous at a specified minimum rate. No. Minneapolis. A. April 19. T Network Node 1 G. MN. The general design procedures for static. 8. 9. DYNAMIC IMPLEMENTATIONS In many real-time computing applications. for their help in developing this technology and for their comments on this paper. 1995. Vrudhula. Brandt. Rick Stephani. Springer-Verlag. [2] Karl M. 1.” Proceedings. T PR l--RST Pull-Down Figure 10. 7. As a specific example of this technique. When -RST = 0. Figure 9. Rather. International Conference on Application-Specific Systems. 1996. the output Z is forced to 0 regardless of the states of the pull-up and pull-down networks. and the general block diagram for such a gate is shown in Figure 9. CONCLUSIONS 54 Go to DATA The general class of M-of-N threshold gates with hysteresis has been introduced and several types of CMOS circuit implementations have been proposed. we can eliminate the weak feedback inverter of the semistatic configuration. General structure of a dynamic threshold gate with hysteresis. Ross Smith.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems. for these kinds of applications. Brandt. General structure of a threshold gate with hysteresis and reset to 0. 1994. When RST = 1.-Y. there is no need to maintain state information with a feedback mechanism. In these situations. This general structure applies to any of the three circuit implementation styles discussed above.5. the M-of-N gate operates normally. pp. Vol. Brzozowski and C. K. Static 2-of-2 gate with reset to 0. (An analogous structure can be constructed for initializing Z to 1. Seger. Standard automated place and route tools can be combined with schematic capture or synthesis tools to produce a complete CAD environment for logical and physical design of systems within this framework. Architectures and Processors. the presence or absence of charge at an isolated node can be maintained on the order of a few milliseconds without any loss of information. “A Design of a Fast and Area Efficient Multi-Input Muller C-element. ACKNOWLEDGMENTS We thank Ryan Jorgenson. such as those involving signal processing. a dynamic 2-of-3 gate would have the same form as the circuit of Figure 8 except that the weak feedback inverter would be removed. S. including the appropriate optimizations for minimizing charge sharing effects. U. Dave Parker. A general mechanism for accomplishing this initialization is shown in Figure 10 for the case where the output Z can be initialized to 0. including one-dimensional and two-dimensional discrete cosine transform processors have been designed and fabricated using this methodology. Wuu and S. 6.-J. These gates are the primitive building blocks of NULL Convention Logic.) In the circuit. Sobelman is also with the University of Minnesota. “NULL Convention Logic? A Complete and Consistent Logic for Asynchronous Digital Circuit Synthesis. Research supported by Ballistic Missiles Defensehnovative Science and Technology and managed by the Office of Naval Research. a static 2-of-2 gate with the reset-to-0 capability is shown in Figure 11.463. the signal -RST is an active-low reset signal. 215-219. 2. For example. Thus. B. Fant and Scott A. [3] Karl M. [ 41 T. 261-273. 1 T Node 1 1-b- 2 A4 0 Figure 11. H. 11-64 . and several specific M-of-N gate design examples have been given. The resulting circuits are called dynamic M-of-N gates. Inc. Ching-Yi Wang and Ken Wagner of Theseus Logic. Several prototype chips. patent #5. REFERENCES [ l ] J. These circuit techniques can be used to construct an ASIC cell library of M-of-N gates for a range of values of M and N. Fant and Scott A. p. Asynchronous Circuits.E. INITIALIZATION TECHNIQUE§ In many applications.305. The form of the Go to NULL and Go to DATA blocks are the same as those used in the semi-static configuration. NULL Convention Logic SystemTM. semi-static and dynamic configurations have been described. David Lamb. 1993. it is necessary to be able to independently reset a given M-of-N gate to a known initial state.