Ruby Krishna.

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No. 29/10,4th Street, Rajaji Nagar, Villlivakkam, Chennai - 600049 Mobile: +91- 9444663336 Mail: rubykrishna@gmail.com

Objective
Looking for a challenging career in the field of electronics, which enhances my competency in System development & design and allows me to contribute to the growth of our organization.

Educational Qualification

Course M.E. in Applied Electronics B.E. in Electrical and Electronics H.S.C.

Institution SSN College of Engineering, Chennai. St.Peters Engineering College St.Johns Hr Sec School, Chennai. St.Johns Hr Sec School, Chennai.

Batch June ’09–’11 June ’04-’08

% Of Marks/CGPA 7.8 81%

June ’03-’04

89.92%

S.S.L.C.

June ’01 –’02

85%

Extra Curricular Activities:  Played for our school in a Ball Badminton Tournament and Secured First Place.  Active member of Youth Red Cross Association. Strength:
 Hard working nature and Strong reasoning skills.  Ability to get along with others.

18um (Models are extracted from latest mosis runs).Premanand. H spice 1) Dr. • A novel 2GS/s current steering DAC was designed using pseudo segmentation technique which is very less prone to non-linearity.OP-Amps Control Systems Digital Electronics Technical Proficiency Hardware Languages Simulator Back-End tools Programming Languages : Verilog : MATLAB. • The designed current steering provides excellent figure of merit when compared to the conventional current steering DAC. AGILENT ADS (Advance Design System) : PSPICE.PLL.V.C. Comparative analysis is done for the various existing architectures.Areas of Interest  VLSI-Analog& Mixed Signal    Electronic Circuits.Asst Professor SSN College of Engineering Tasks accomplished: • • • Schematic version of the Self referenced beta multiplier and Wide swing biasing circuit for the short channel process were designed. Tanner. HSPICE(Synopsys) :C Academic Projects Handled (Reverse chronology) Project Title: Duration: Simulation: Guide: Design of Current Steering Digital to Analog converter for UWB receiver six months project Matlab. TANNER EDA. Professor SSN College of Engineering 2) Mr.Vaithianathan. Schematic of the current steering DAC was developed by using Tanner(S edit) • • Tanner EDA (SEDIT) was used for net list generation and simulated outputs are obtained using HSPICE(Synopsys) Process -TSMC-0. .

Premanand. Project Title: Duration: Simulation: Guide: Design of Successive approximation ADC for UWB receiver one year project Matlab. Professor SSN College of Engineering Tasks accomplished: • • Schematic version of the Self referenced beta multiplier and Wide swing biasing circuit for the short channel process were designed. Tanner. • • • We have developed a Op-Amp with 100MHz unity gain frequency and a gain of 82DB and a phase margin of 600.Vaithianathan.Asst Professor SSN College of Engineering Tasks accomplished as on date: • Conventional SAR ADC is too slow which make it as a delimiting factor for high speed applications. spice Dr. differential cascade pass transistor logic flip flops were used in shift registers. spice 1) Dr.V.Project Title: Duration: Simulation: Guide: Design of Three stage operational amplifier using reverse nested miller hybrid indirect feedback compensation six month project Matlab. Tanner EDA (SEDIT) was used for net list generation and simulated outputs are obtained using HSPICE(Synopsys) A Hybrid compensation technique was used in order to facilitate the application of operational amplifiers in high speed data converter architectures. Tanner.C. Inorder to reduce the rise and fall time issues.Premanand. • Ultra high speed latched comparator was used which has a delay in the order of 300pS .C. Profesor SSN College of Engineering 2) Mr. • • High Speed switching drivers were designed using Precharge- evaluation logic with a minimum delay in the order of 60pS. Designed a High defined a Three Stage Operational Amplifier using Indirect Feedback Reverse Nested Miller Compensation.

• • Tanner EDA (SEDIT) was used for net list generation and simulated outputs are obtained using HSPICE(Synopsys) A 4 bit 200MS/s successive approximation ADC was designed and we are currently tuning the Analog to digital converter using time interleaving topology inorder to enhance the speed of the ADC towards 1GS/s. o Presented Paper on “Improving the efficiency solar collectors by using nanotechnology” And got second prize in a National level Technical Symposium “Ecognition-2006”. The phenomenon will continue indefinitely. the PLL tends to leave lock to approach the free running frequency of the VCO.Vaithianathan. • High Speed ADC. Our ‘hold time’ turned out to Paper presented in Symposium o Presented Paper on “Rural Electrification-A Simulative Analysis of SPV System”And got first prize in a National level Technical Symposium “Ultra Zone-2007”.V.S 15-4-1987. S. 22 Years. After the hold time has expired. Personal Profile: Name Date of Birth Age Father’s Name Mother’s Name : : Father’s Occupation : : : : Ruby Krishna. Asst.Sankaran Junior Engineer in Chennai Port Trust. be about 2us. Professor SSN Engineering College Simulation: Orcad-Pspice Project details: • PLL was able to achieve lock for frequency range from 30MHz to 110 MHz using PSPICE(A/D) • PLL will only be in lock for a short amount of time this is referred to as the ‘hold time.18um Technology Feb ’10 till May ‘10 Mr. Project Title: Duration: Guide: Design of Digital Phase Locked Loop using 0. S. will enable the usage of LIDAR(light detection and ranging) in adaptive speed control system in automobiles.Vetriselvi .

Playing Ball Badminton. Place: Chennai.S) .Sex Nationality Languages Known Hobbies Chatting. Cricket Declaration: I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the abovementioned particulars. Listening To Music : : : : Male Indian Tamil. English. (Ruby Krishna.