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5 4 3 2 1

Project code: 91.4CG01.001 SYSTEM DC/DC


ISL62392 42

JV50 Block Diagram PCB P/N


REVISION
: 48.4CG01.0SA
: 08245-SA
INPUTS OUTPUTS
5V_S5(6A)
3D3V_S5(7A)
DCBATOUT
5V_AUX_S5
3D3V_AUX_S5
PCB STACKUP
Mobile CPU SMSC SYSTEM DC/DC
D CLK GEN. EMC2102 TOP L1 TPS51124 43 D

ICS9LPRS365B Penryn 34 GND L2 INPUTS OUTPUTS


3
S L3 1D05V_S0(9A)
4, 5 DCBATOUT
S L4 1D5V_S3(12A)
VRAM
HOST BUS 667/800/1066MHz@1.05V 64MbX16X4 512M GND L5 RT9026 44

DDR3 Cantiga BOTTOM L6


1D5V_S3
DDR_VREF_S3
(1.2A)
800/1066 16,17
MHz PCIex16 VGA HDMI
AGTL+ CPU I/F 20
N10M-GE-1 RT9018 44
DDR Memory I/F 52~57
DDR3 INTEGRATED GRAHPICS LCD 1D5V_S3 1D1V_S0(2A)

LVDS, CRT I/F


18
800/1066 16,17
MHz 6,7,8,9,10,11 TPS51117
CRT 45
X4 DMI 19 DCBATOUT FBVDD(4A)
C-Link0
400MHz
MS/MS Pro/xD CHARGER
USB CardBus ISL88731A 47
RTS5159 /MMC/SD
31 INPUTS OUTPUTS

C C

DCBATOUT BT+
ICH9M
6 PCIe ports
LINE IN PCI/PCI BRIDGE LAN TXFM RJ45 CPU DC/DC
Giga LAN ISL6266A
ACPI 2.0 26 26 41
29 BCM5764 25
4 SATA
INPUTS OUTPUTS
12 USB 2.0/1.1 ports
Int MIC ETHERNET (10/100/1000MbE)
High Definition Audio DCBATOUT VCC_CORE

18 Codec AZALIA LPC I/F PWR SW


38A

Serial Peripheral I/F


New Card
ALC888S 32 TPS2231 32 VGA_CORE
27 Matrix Storage Technology(DO) RT8202A
Active Managemnet Technology(DO)
47
MIC In
PCIe Mini 1 Card INPUTS OUTPUTS
29
Wire LAN 33
DCBATOUT VGA_CORE
12,13,14,15 Mini 2 Card 13A
INT.SPKR 33
1.5W
OP AMP 3G card
GFXCORE
MAX9789A ISL6263A
B 29 30 46 B

LPC BUS INPUTS OUTPUTS

LINE OUT DCBATOUT VCC_GFXCORE

29 USB SPI BIOS LPC (7A)


SATA Mini USB KBC (2MB)
Winbond 36 DEBUG
HDD SATA Blue Tooth
23
Camera WPCE773
MODEM 21 CONN.36
RJ11 MDC Card 35
MEDIA
30 SATA USB KEY
Finger 38
ODD SATA
Printer 37
4 Port 24
22 Touch INT.
Pad 37 KB 35

A A

JV50

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

BLOCK DIAGRAM
Size Document Number Rev
A2
JV50 SB
Date: Thursday, January 08, 2009 Sheet 1 of 60
5 4 3 2 1
A B C CantigaDchipset and ICH9M I/O controller
E
ICH9M Functional Strap Definitions ICH9M Integrated Pull-up
ICH9 EDS 642879 Rev.1.5 page 92
and Pull-down Resistors Hub strapping configuration
Montevina Platform Design guide 22339 0.5
Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5 page 218
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
Select 011 = FSB667
offset 224h). This signal has weak internal pull-down CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0#
DPRSLPVR/GPIO16
PULL-UP 20K
PULL-DOWN 20K
CFG[4:3] Reserved 4
CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)

HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher


Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
without GNT3# being pulled down. GLAN_DOCK# The pull-up or pull-down active when configured for native CFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
11 = Disabled (default)
Integrated TPM will be enable. LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop
Rising Edge of PWROK. applications and required to be high for
LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister. NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
2 Flash-decriptor section of the Firmware. This 'Soft-Strap' is
activated only after enabling iTPM via CFG6.
2
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.

1 JV50
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reference
Size Document Number Rev
A3
JV50 SB
Date: Thursday, January 08, 2009 Sheet 2 of 60

A B C D E
A B C D E

SB 1202 3D3V_S0
3D3V_S0 1D05V_S0
SB 1202 SB 1202 SB 1202 SB 1202
1 R554 2 3D3V_VDD48_S0
0R0603-PAD

1
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SC4D7U6D3V3KX-GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SC4D7U6D3V3KX-GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
C456 C457 C455 C450 C417 C435 C444 C436 C416 C430 C419 C445 C448 C454 C418

SC4D7U6D3V3KX-GP

SC1U16V3ZY-GP
DY DY DY DY DY DY

2
4 SB 1202 4

3D3V_S0 3D3V_VDD48_S0 1D05V_S0

3D3V_S0
CL=20pF±0.2pF
U24

16

46
62
23

19
27
43
52
33
56
1

9
SB 1202 C453
R260 SC33P50V2JN-3GP

VDD48

VDDPLL3

VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
VDDREF

VDDPCI
VDDSRC
VDDCPU
10KR2J-3-GP 1 2 GEN_XTAL_OUT
DIS

2
X5 61 CLK_CPU_BCLK 4 CPU
2

PCLKCLK4 X-14D31818M-35GP CPUT0


60 CLK_CPU_BCLK# 4
CPUC0
82.30005.891
1

3 58 CLK_MCH_BCLK 6 NB

1
R254 GEN_XTAL_IN X1 CPUT1_F
1 2 2 57 CLK_MCH_BCLK# 6
10KR2J-3-GP C452 X2 CPUC1_F
UMA SC33P50V2JN-3GP
CPUT2_ITP/SRCT8
54
53
CLK_PCIE_ICH 13 SB DMI
CLK_PCIE_ICH# 13
2

CPUC2_ITP/SRCC8
4,7 CPU_SEL0 R2512 1 2K2R2J-2-GP CLK48 17
R253 2 USB_48MHZ/FSLA
31 CLK48_5158E 1 33R2J-2-GP
51 CLK_PCIE_NEW 32 NEWCARD
SRCT7/CR#_F
50 CLK_PCIE_NEW# 32
SRCC7/CR#_E
13 PM_STPPCI# 45
3D3V_S0 PCI_STOP#
RN48 13 PM_STPCPU# 44 48 CLK_PCIE_PEG 52 GPU
CPU_STOP# SRCT6
47 CLK_PCIE_PEG# 52
PCLKCLK2 modify by RF SRCC6
5 4
3 CPU_SEL2_R 3
4,7 CPU_SEL2 6
7
3
2 7
SRCT10
41
42
CLK_PCIE_LAN 25 LAN
15,16,17 SMBC_ICH SCLK SRCC10 CLK_PCIE_LAN# 25
8 1 PCLKCLK5 6
15,16,17 SMBD_ICH SDATA CR#_H
40
3D3V_S0 SRCT11/CR#_H CR#_G
13 CLK_PWRGD 63 39
SRN10KJ-6-GP C451 CK_PWRGD/PD# SRCC11/CR#_G
DY
RN46 2 1 10KR2J-3-GP 2R249 1 37
1 8 CPU_SEL2_R
SRCT9
38
CLK_PCIE_MINI1 33 WLAN
13 CLK_ICH14 SRCC9 CLK_PCIE_MINI1# 33
13 CLK48_ICH 2 7 CLK48 SC47P50V2JN-3GP PCLKCLK0 DY 8
PCI0/CR#_A
35 PCLK_KBC 3 6 PCLKCLK4 PCLKCLK1 10 34 CLK_MCH_3GPLL 7 NB CLK
PCI1/CR#_B SRCT4
13 PCLK_ICH 4 5 PCLKCLK5 36,51 PCLK_FWH R255 2 1 33R2J-2-GP PCLKCLK2 11 35 CLK_MCH_3GPLL# 7
PCI2/TME SRCC4
1PCLKCLK3 12
TPAD14-GP TP158 PCLKCLK4 PCI3
SRN33J-7-GP -1 13
PCI4/27_SELECT SRCT3/CR#_C
31 CLK_PCIE_MINI2 33 3G
PCLKCLK5 14 32
PCI_F5/ITP_EN SRCC3/CR#_D CLK_PCIE_MINI2# 33
-1
28 CLK_PCIE_SATA 12 SB SATA
CLK_ICH14 SRCT2/SATAT
1 2 29 CLK_PCIE_SATA# 12
EC25 SC33P50V2JN-3GP SRCC2/SATAC
4,7 CPU_SEL1 64
PCLK_FWH CPU_SEL2_R FSLB/TEST_MODE
1 2 5
REF0/FSLC/TEST_SEL -1 DIS
EC24 SC33P50V2JN-3GP DREFSSCLK_1 1 RN42
PCLK_ICH 1 2 55
27MHZ_NONSS/SRCT1/SE1
24
25 DREFSSCLK_1#
4
3 2 SRN33J-5-GP-U
VGA_XIN1 52 GPU
NC#55 27MHZ_SS/SRCC1/SE2 OSC_SPREAD 52
EC23 SC33P50V2JN-3GP
PCLK_KBC DREFCLK_1 1 RN44
1 2 20 4 NB

GNDSRC
GNDSRC
GNDSRC
GNDCPU
GNDREF
SRCT0/DOTT_96 DREFCLK 7

GNDPCI
EC39 SC33P50V2JN-3GP 21 DREFCLK_1# 3 2 SRN0J-6-GP

GND48
SRCC0/DOTC_96 DREFCLK# 7
CLK48_ICH 1 2

GND

GND

GND
EC48 SC33P50V2JN-3GP UMA
3D3V_S0 1 4 RN76
ICS9LPRS365BKLFT-GP-U 2 3 SRN0J-6-GP
DREFSSCLK 7 NB
DREFSSCLK# 7

18
15
1

22
30
36
49
59
26

65
2 2
71.09365.A03
EMI capacitor for Antenna team suggestion UMA -1

4
3
2
1
VGA_XIN1 1 2
RN47 EC68 DY SC33P50V2JN-3GP
SRN10KJ-6-GP OSC_SPREAD 1 2
DY EC69 DY SC33P50V2JN-3GP
ICS9LPRS365YGLFT setting table
PIN NAME DESCRIPTION

5
6
7
8
RN45
1 8 PCLKCLK0
13 SATACLKREQ#
Byte 5, bit 7 2 7 PCLKCLK1
7 CLK_MCH_OE#
0 = PCI0 enabled (default) 3 6 CR#_H
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
25 LAN_CLKREQ#
4 5 CR#_G SEL2 SEL1 SEL0
PCI0/CR#_A Byte 5, bit 6
33 WLAN_CLKREQ# CPU FSB
0 = CR#_A controls SRC0 pair (default), DY FSC FSB FSA
1= CR#_A controls SRC2 pair SRN470J-3-GP

Byte 5, bit 5 PIN NAME DESCRIPTION 1 0 1 100M X


0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 1 0 0 1 133M 533M
PCI1/CR#_B Byte 5, bit 4 0 = SRC3 enabled (default)
166M 667M
0 = CR#_B controls SRC1 pair (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair 0 1 1
1= CR#_B controls SRC4 pair SRCC3/CR#_D Byte 5, bit 0
200M 800M
0 = CR#_D controls SRC1 pair (default) 0 1 0
0 = Overclocking of CPU and SRC Allowed 1= CR#_D controls SRC4 pair
PCI2/TME 1 = Overclocking of CPU and SRC NOT allowed 0 0 0 266M 1067M
Byte 6, bit 7
0 = SRC7# enabled (default)
1
PCI3 SRCC7/CR#_E 1= CR#_F controls SRC6 JV50 1

0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96# Byte 6, bit 6
PCI4/27M_SEL 1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0#
SRCT7/CR#_F 0 = SRC7 enabled (default)
1= CR#_F controls SRC8 Wistron Corporation
0 =SRC8/SRC8# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
PCI_F5/ITP_EN 1 = ITP/ITP# Byte 6, bit 5 Taipei Hsien 221, Taiwan, R.O.C.
0 = SRC11# enabled (default)
Byte 5, bit 3 SRCC11/CR#_G 1= CR#_G controls SRC9 Title
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 6, bit 4 Clock Generator
SRCT3/CR#_C Byte 5, bit 2 0 = SRC11 enabled (default) Size Document Number Rev
0 = CR#_C controls SRC0 pair (default), SRCT11/CR#_H 1= CR#_H controls SRC10
JV50 SB
1= CR#_C controls SRC2 pair
Date: Thursday, January 08, 2009 Sheet 3 of 60
A B C D E
A B C D E

H_A#[35..3]
6 H_A#[35..3]
H_DINV#[3..0]
H_DINV#[3..0] 6
CPU1A 1 OF 4 1 TP74 TPAD14-GP H_DSTBN#[3..0]
H_DSTBN#[3..0] 6
H_A#3 J4 H1 1D05V_S0 H_DSTBP#[3..0]
A3# ADS# H_ADS# 6 H_DSTBP#[3..0] 6
H_A#4 L5 E2 H_BNR# 6
H_A#5 A4# BNR# Place testpoint on H_D#[63..0]
4 L4 G5 H_BPRI# 6 H_D#[63..0] 6 4
A5# BPRI#

ADDR GROUP 0
H_A#6 K5 H_IERR# with a GND

1
H_A#7 A6# 0.1" away
M3 H5 H_DEFER# 6
H_A#8 A7# DEFER# R88
N2 F21

CONTROL
A8# DRDY# H_DRDY# 6
H_A#9 J1 E1 56R2J-4-GP
A9# DBSY# H_DBSY# 6
H_A#10 N3
H_A#11 A10#
P5 F1 H_BREQ#0 6

2
H_A#12 A11# BR0# C104
P2
A12#
DY
H_A#13 L2 D20 H_IERR# 1 2
H_A#14 A13# IERR#
P4 B3 H_INIT# 12
H_A#15 A14# INIT# SC47P50V2JN-3GP
P1
H_A#16 A15#
R1 H4 H_LOCK# 6
A16# LOCK# CPU1B 2 OF 4
6 H_ADSTB#0 M1 H_CPURST# 6,51
ADSTB0#
6 H_REQ#[4..0] C1 H_RS#[2..0] 6 modify by RF
H_REQ#0 RESET# H_RS#0 H_D#0 H_D#32
K3 F3 E22 Y22
H_REQ#1 REQ0# RS0# H_RS#1 H_D#1 D0# D32# H_D#33
H2 F4 F24 AB24
H_REQ#2 REQ1# RS1# H_RS#2 H_D#2 D1# D33# H_D#34
K2 G3 E26 V24
H_REQ#3 REQ2# RS2# H_D#3 D2# D34# H_D#35
J3 G2 H_TRDY# 6 G22 V26
H_REQ#4 REQ3# TRDY# H_D#4 D3# D35# H_D#36
L1 F23 V23
REQ4# D4# D36#

DATA GRP0
DATA GRP2
G6 H_HIT# 6 H_THERMDA H_D#5 G25 T22 H_D#37
H_A#17 HIT# H_D#6 D5# D37# H_D#38
Y2 E4 H_HITM# 6 E25 U25

1
H_A#18 A17# HITM# H_D#7 D6# D38# H_D#39
U5 E23 U23
H_A#19 A18# XDP_BPM#0 TP28 TPAD14-GP C116 H_D#8 D7# D39# H_D#40
R3 AD4 1 K24 Y25
H_A#20 A19# BPM0# XDP_BPM#1 TP27 TPAD14-GP SC2200P50V2KX-2GP H_D#9 D8# D40# H_D#41
W6 XDP/ITP SIGNALS AD3 1 G24 W22

2
A20# BPM1# D9# D41#
ADDR GROUP 1

H_A#21 U4 AD1 XDP_BPM#2 1 TP26 TPAD14-GP H_THERMDC DY H_D#10 J24 Y23 H_D#42
H_A#22 A21# BPM2# XDP_BPM#3 TP32 TPAD14-GP 1D05V_S0 H_D#11 D10# D42# H_D#43
Y5 AC4 1 J23 W24
H_A#23 A22# BPM3# XDP_BPM#4 TP29 TPAD14-GP H_D#12 D11# D43# H_D#44
U1 AC2 1 H22 W25
H_A#24 R4
A23# PRDY#
AC1 XDP_BPM#5 1 TP30 TPAD14-GP Close to NB H_D#13 F26
D12# D44#
AA23 H_D#45
H_A#25 A24# PREQ# XDP_TCK TP34 TPAD14-GP H_D#14 D13# D45# H_D#46
T5 AC5 1 K22 AA24

1
3 H_A#26 A25# TCK XDP_TDI TP50 TPAD14-GP H_D#15 D14# D46# H_D#47 3
T3 AA6 1 H23 AB25
H_A#27 A26# TDI XDP_TDO TP31 TPAD14-GP R89 D15# D47#
W2 AB3 1 6 H_DSTBN#0 J26 Y26 H_DSTBN#2 6
H_A#28 A27# TDO XDP_TMS TP49 TPAD14-GP 68R2-GP DSTBN0# DSTBN2#
W5 AB5 1 6 H_DSTBP#0 H26 AA26 H_DSTBP#2 6
H_A#29 A28# TMS XDP_TRST# TP33 TPAD14-GP DSTBP0# DSTBP2#
Y4 AB6 1 6 H_DINV#0 H25 U22 H_DINV#2 6
H_A#30 A29# TRST# XDP_DBRESET#1 TP88 TPAD14-GP DINV0# DINV2#
U2 C20

2
H_A#31 A30# DBR#
V4 1 R97 2DY CPU_PROCHOT#_R 41
H_A#32 A31# 0R2J-2-GP H_D#16 H_D#48
W3 N22 AE24
H_A#33 A32# H_D#17 D16# D48# H_D#49
AA4
A33# THERMAL K25
D17# D49#
AD24
H_A#34 AB2 C90 SC47P50V2JN-3GP H_D#18 P26 AA21 H_D#50
H_A#35 A34# CPU_PROCHOT#_1 H_D#19 D18# D50# H_D#51
AA3 D21 1 2 R23 AB22
A35# PROCHOT# H_D#20 D19# D51# H_D#52
6 H_ADSTB#1 V1 A24 H_THERMDA 34 DY modify by RF L23 AB21
ADSTB1# THRMDA H_D#21 D20# D52# H_D#53
B25 H_THERMDC 34 M24 AC26
THRMDC D21# D53#

DATA GRP3
DATA GRP1
A6 H_D#22 L22 AD20 H_D#54
12 H_A20M# A20M# D22# D54#
A5 C7 H_D#23 M23 AE22 H_D#55
12 H_FERR# FERR# THERMTRIP# PM_THRMTRIP-A# 7,12,39 D23# D55#
ICH

C4 H_D#24 P25 AF23 H_D#56


12 H_IGNNE# IGNNE# D24# D56#
PM_THRMTRIP# should connect to H_D#25 P23 AC25 H_D#57
ICH9 and MCH without T-ing H_D#26 D25# D57# H_D#58
12 H_STPCLK# D5 P22 AE21
STPCLK# PH @ page48 H_D#27 D26# D58# H_D#59
12 H_INTR C6
LINT0 HCLK BCLK0
A22 CLK_CPU_BCLK 3 T24
D27# D59#
AD21
B4 A21 H_D#28 R24 AC22 H_D#60
12 H_NMI LINT1 BCLK1 CLK_CPU_BCLK# 3 D28# D60#
A3 H_D#29 L25 AD23 H_D#61
12 H_SMI# SMI# 1D05V_S0 D29# D61#
H_D#30 T25 AF22 H_D#62
H_D#31 D30# D62# H_D#63
M4 N25 AC23

2
RSVD#M4 D31# D63#
N5 6 H_DSTBN#1 L26 AE25 H_DSTBN#3 6
RSVD#N5 DSTBN1# DSTBN3#
T2 M26 AF24
RESERVED

RSVD#T2 6 H_DSTBP#1 DSTBP1# DSTBP3# H_DSTBP#3 6


V3 Layout Note: 1KR2F-3-GP N24 AC20
RSVD#V3 6 H_DINV#1 DINV1# DINV3# H_DINV#3 6
B2 "CPU_GTLREF0" R312
RSVD#B2 0.5" max length. CPU_GTLREF0 COMP0 R71 1 27D4R2F-L1-GP
C3 AD26 R26 2

1 1
RSVD#C3 TEST1 GTLREF COMP0 COMP1
D2 C23 MISC U26 R67 1 2 54D9R2F-L1-GP

1
RSVD#D2 TEST2 TEST1 COMP1 COMP2 R57 1 27D4R2F-L1-GP
D22 DY

SC1KP50V2KX-1GP
D25 AA1 2
2 RSVD#D22 TEST2 COMP2 2
D3 R309 C526TPAD14-GP TP87 1RSVD_CPU_12 C24 Y1 COMP3 R60 1 2 54D9R2F-L1-GP
RSVD#D3 2KR2F-3-GP TEST4 TEST3 COMP3
F6 AF26

2
RSVD#F6 TEST4
TPAD14-GP TP25 1RSVD_CPU_13 AF1 E5 H_DPRSTP# 7,12,41
RSVD_CPU_11 TEST5 DPRSTP#
TPAD14-GP TP97 1 B1 TPAD14-GP TP180 1RSVD_CPU_14 A26 B5 H_DPSLP# 12

2
KEY_NC TEST6 DPSLP#
D24 H_DPWR# 6
BGA479-SKT6-GPU7 DPWR#
3,7 CPU_SEL0 B22 D6 H_PWRGD 12,39,51
BSEL0 PWRGOOD
62.10079.001 3,7 CPU_SEL1 B23
BSEL1 SLP#
D7 H_CPUSLP# 6
2nd = 62.10053.401 3,7 CPU_SEL2 C21
BSEL2 PSI#
AE6 H_PSI# 41

1
C102
BGA479-SKT6-GPU7

SC100P50V2JN-3GP
DY

2
Layout Note:
1D05V_S0 1 DY 2 TEST1 Comp0, 2 connect with Zo=27.4 ohm, make
R119 1KR2J-1-GP trace length shorter than 0.5" .
Net "TEST4" as short as possible, Comp1, 3 connect with Zo=55 ohm, make
1 DY 2 TEST2 trace length shorter than 0.5" .
XDP_TMS R54 1 2 54D9R2F-L1-GP R114 1KR2J-1-GP make sure "TEST4" routing is
C525
reference to GND and away other
XDP_TDI R55 1 2 54D9R2F-L1-GP 2DY 1 TEST4
SCD1U10V2KX-4GP noisy signals
XDP_BPM#5 R46 1 2 54D9R2F-L1-GP

XDP_TDO R47 1 2 54D9R2F-L1-GP


DY
H_CPURST# R113 1 2 51R2F-2-GP
DY
3D3V_S0 H_DPRSTP# 1 TP76 TPAD14-GP
1 JV50 1
H_DPSLP# 1 TP95 TPAD14-GP
H_DPWR# 1 TP114 TPAD14-GP
XDP_DBRESET# R105 1 2 1KR2J-1-GP H_PWRGD TP81 TPAD14-GP
DY H_CPUSLP#
1
1 TP78 TPAD14-GP Wistron Corporation
H_INIT# 1 TP92 TPAD14-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
H_CPURST# 1 TP86 TPAD14-GP Taipei Hsien 221, Taiwan, R.O.C.
XDP_TCK R32 1 2 54D9R2F-L1-GP
Place these TP on button-side, Title
XDP_TRST# R33 2 54D9R2F-L1-GP
1
easy to measure. CPU (1 of 2)
All place within 2" to CPU Size Document Number Rev

JV50 SB
Date: Thursday, January 08, 2009 Sheet 4 of 60
A B C D E
A B C D E

VCC_CORE VCC_CORE SB 1209

1
C86 C56 C85 C55 C87 C89 C88 C53 C50 C51 C52 C553 C538 C552 C539 C548 C547 C536 C537

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
2

2
DY DY DY DY DY DY
VCC_CORE
CPU1D 4 OF 4
VCC_CORE
4 A4 P6 4
CPU1C 3 OF 4 VSS VSS
A8 P21
VSS VSS
A11 P24
VSS VSS
A7 AB20 A14 R2
VCC VCC VSS VSS
A9 AB7 A16 R5
VCC VCC VSS VSS
A10 AC7 A19 R22
VCC VCC VSS VSS
A12 AC9 A23 R25
VCC VCC TPAD14-GP TP23 TP_AF2_CPU VSS VSS
A13 AC12 1 AF2 T1
VCC VCC VSS VSS
A15 AC13 B6 T4
VCC VCC VSS VSS
A17 AC15 B8 T23
VCC VCC VSS VSS
A18 AC17 B11 T26
VCC VCC VSS VSS
A20 AC18 B13 U3
VCC VCC VSS VSS
B7 AD7 B16 U6
VCC VCC VSS VSS
B9 AD9 B19 U21
VCC VCC VSS VSS
B10 AD10 B21 U24
VCC VCC VSS VSS
B12 AD12 B24 V2
VCC VCC VSS VSS
B14 AD14 C5 V5
VCC VCC VSS VSS
B15 AD15 C8 V22
VCC VCC VSS VSS
B17 AD17 C11 V25
VCC VCC VSS VSS
B18 AD18 C14 W1
VCC VCC VSS VSS
B20 AE9 C16 W4
VCC VCC VSS VSS
C9 AE10 C19 W23
VCC VCC VSS VSS
C10 AE12 C2 W26
VCC VCC VSS VSS
C12 AE13 C22 Y3
VCC VCC VSS VSS
C13 AE15 C25 Y6
VCC VCC VSS VSS
C15 AE17 D1 Y21
VCC VCC VSS VSS
C17 AE18 D4 Y24
VCC VCC 1D05V_S0 VSS VSS
C18
VCC VCC
AE20 SB 1208 D8
VSS VSS
AA2
D9 AF9 D11 AA5
3 VCC VCC VSS VSS 3
D10 AF10 D13 AA8
VCC VCC VSS VSS
D12 AF12 D16 AA11
VCC VCC VSS VSS
D14 AF14 D19 AA14
VCC VCC VSS VSS
D15 AF15 D23 AA16

1
VCC VCC C67 C75 C79 C80 C83 C84 VSS VSS
D17 AF17 D26 AA19
VCC VCC VSS VSS

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
D18 AF18 1D05V_S0_CPU E3 AA22
VCC VCC 1D05V_S0 VSS VSS
E7 AF20 E6 AA25

2
VCC VCC G2 VSS VSS
E9 E8 AB1
VCC VSS VSS
E10 G21 1 2 E11 AB4
VCC VCCP VSS VSS
E12
VCC VCCP
V6 DY DY E14
VSS VSS
AB8
E13 J6 GAP-CLOSE-PWR E16 AB11
VCC VCCP VSS VSS
E15 K6 E19 AB13
VCC VCCP VSS VSS
E17 M6 E21 AB16
VCC VCCP C57 C58 VSS VSS
E18 J21 E24 AB19
1

VCC VCCP VSS VSS


SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

E20 K21 F5 AB23


VCC VCCP VSS VSS
F7 M21 F8 AB26
VCC VCCP VSS VSS
F9 N21 F11 AC3
2

VCC VCCP VSS VSS


F10
VCC VCCP
N6 layout note: "1D5V_VCCA_S0" F13
VSS VSS
AC6
F12 R21 as short as possible F16 AC8
VCC VCCP VSS VSS
F14 R6 F19 AC11
VCC VCCP VSS VSS
F15 T21 F2 AC14
VCC VCCP VSS VSS
F17 T6 F22 AC16
VCC VCCP 1D5V_S0 VSS VSS
F18 V21 F25 AC19
VCC VCCP 1D5V_VCCA_S0 VSS VSS
F20 W21 G4 AC21
VCC VCCP FCM1608KF-1-GP VSS VSS
AA7 G1 AC24
VCC VSS VSS
AA9 B26 1 2 G23 AD2
VCC VCCA L18 VSS VSS
AA10 C26 G26 AD5
1

VCC VCCA C603 C6062nd = 68.00248.061 VSS VSS


AA12 H_VID[6..0] 41 H3 AD8
VCC H_VID0 VSS VSS
AA13 AD6 H6 AD11
SC10U6D3V5MX-3GP
SCD01U16V2KX-3GP

2 VCC VID0 H_VID1 VCC_CORE VSS VSS 2


AA15 AF5 H21 AD13
2

VCC VID1 H_VID2 VSS VSS


AA17 AE5 H24 AD16
VCC VID2 H_VID3 VSS VSS
AA18 AF4 J2 AD19
1

VCC VID3 H_VID4 VSS VSS


AA20 AE3 J5 AD22
VCC VID4 H_VID5 R25 VSS VSS
AB9 AF3 J22 AD25
VCC VID5 H_VID6 VSS VSS
AC10 AE2 J25 AE1
100R2F-L1-GP-U

VCC VID6 VSS VSS


AB10 K1 AE4
VCC VSS VSS
AB12 K4 AE8
2

VCC VSS VSS


AB14 AF7 VCC_SENSE 41 K23 AE11
VCC VCCSENSE VSS VSS
AB15 K26 AE14
VCC VSS VSS
AB17 L3 AE16
VCC VSS VSS
AB18 AE7 VSS_SENSE 41 L6 AE19
VCC VSSSENSE VSS VSS
L21 AE23
1

VSS VSS
Layout Note: L24 AE26 TP_AE26_CPU 1 TP174 TPAD14-GP
R24 VSS VSS TP_A2_CPU TP98 TPAD14-GP
M2 A2 1
BGA479-SKT6-GPU7 VCCSENSE and VSSSENSE lines VSS VSS
M5 AF6
100R2F-L1-GP-U

should be of equal length. VSS VSS


M22 AF8
VSS VSS
M25 AF11
2

VSS VSS
N1 AF13
Layout Note: VSS VSS
N4 AF16
Provide a test point (with VSS VSS
N23 AF19
no stub) to connect a VSS VSS
N26 AF21
VSS VSS
differential probe P3 A25 TP_A25_CPU 1 TP181 TPAD14-GP
between VCCSENSE and VSS VSS
AF25
VSSSENSE at the location VSS
where the two 54.9ohm
resistors terminate the BGA479-SKT6-GPU7
55 ohm transmission line.
1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (2 of 2)
Size Document Number Rev

JV50 SB
Date: Thursday, January 08, 2009 Sheet 5 of 60
A B C D E
5 4 3 2 1

NB1A 1 OF 10
H_A#[35..3]
H_D#[63..0] H_A#[35..3] 4
A14 H_A#3
4 H_D#[63..0] H_A#_3
H_D#0 F2 C15 H_A#4
H_D#1 H_D#_0 H_A#_4 H_A#5
G8 F16
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H13
H_D#3 H_D#_2 H_A#_6 H_A#7
E6 C18
1D05V_S0 H_D#4 H_D#_3 H_A#_7 H_A#8
G2 M16
H_D#5 H_D#_4 H_A#_8 H_A#9
D H_SWING routing Trace width and H6
H_D#_5 H_A#_9
J13 D
H_D#6 H2 P16 H_A#10
Spacing use 10 / 20 mil

1
H_D#7 H_D#_6 H_A#_10 H_A#11
F6 R16
R381 H_D#8 H_D#_7 H_A#_11 H_A#12
D4 N17
221R2F-2-GP H_D#9 H_D#_8 H_A#_12 H_A#13
H3 M13
H_D#10 H_D#_9 H_A#_13 H_A#14
H_SWING Resistors and M9
H_D#_10 H_A#_14
E17
H_D#11 M11 P17 H_A#15

2
Capacitors close MCH H_D#12 J1
H_D#_11 H_A#_15
F17 H_A#16
H_SWING H_D#13 H_D#_12 H_A#_16 H_A#17
500 mil ( MAX ) J2
H_D#_13 H_A#_17
G20
H_D#14 N12 B19 H_A#18

1
H_D#15 H_D#_14 H_A#_18 H_A#19
J6 J16

SCD1U10V2KX-4GP
1 H_D#16 H_D#_15 H_A#_19 H_A#20

C619
R382 P2 E20
100R2F-L1-GP-U H_D#17 H_D#_16 H_A#_20 H_A#21
L2 H16
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 J20
2

H_D#19 H_D#_18 H_A#_22 H_A#23


N9 L17

2
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 A17
H_D#21 H_D#_20 H_A#_24 H_A#25
M5 B17
H_D#22 H_D#_21 H_A#_25 H_A#26
J3 L16
H_D#23 H_D#_22 H_A#_26 H_A#27
N2 C21
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 J17
H_D#25 H_D#_24 H_A#_28 H_A#29
N5 H20
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 B18
H_D#27 H_D#_26 H_A#_30 H_A#31
P13 K17
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 B20
H_D#29 H_D#_28 H_A#_32 H_A#33
L7 F21
H_D#30 H_D#_29 H_A#_33 H_A#34
N10 K21
H_D#31 H_D#_30 H_A#_34 H_A#35
M3 L20
H_D#32 H_D#_31 H_A#_35
Y3
H_D#33 H_D#_32
AD14 H12 H_ADS# 4
C H_D#34 H_D#_33 H_ADS# C
Y6 B16 H_ADSTB#0 4
H_D#35 H_D#_34 H_ADSTB#_0
Y10 G17 H_ADSTB#1 4
H_D#36 H_D#_35 H_ADSTB#_1
Y12 A9 H_BNR# 4
H_D#37 H_D#_36 H_BNR#
Y14 F11 H_BPRI# 4
H_D#38 H_D#_37 H_BPRI#
Y7 G12

HOST
H_D#_38 H_BREQ# H_BREQ#0 4
H_D#39 W2 E9 H_DEFER# 4
H_D#40 H_D#_39 H_DEFER#
AA8 B10 H_DBSY# 4
H_D#41 H_D#_40 H_DBSY#
Y9 AH7 CLK_MCH_BCLK 3
H_D#42 H_D#_41 HPLL_CLK
AA13 AH6 CLK_MCH_BCLK# 3
H_D#43 H_D#_42 HPLL_CLK#
AA9 J11 H_DPWR# 4
H_D#44 H_D#_43 H_DPWR#
AA11 F9 H_DRDY# 4
H_D#45 H_D#_44 H_DRDY#
H_RCOMP routing Trace width and AD11
H_D#_45 H_HIT#
H9 H_HIT# 4
H_D#46 AD10 E12
Spacing use 10 / 20 mil H_D#_46 H_HITM# H_HITM# 4
H_D#47 AD13 H11
H_D#_47 H_LOCK# H_LOCK# 4
H_D#48 AE12 C9
H_D#_48 H_TRDY# H_TRDY# 4
H_D#49 AE9
H_D#_49
1 2 H_RCOMP H_D#50 AA2
R380 24D9R2F-L-GP H_D#51 H_D#_50
AD8
H_D#52 H_D#_51 H_DINV#[3..0]
AA3 H_DINV#[3..0] 4
H_D#53 H_D#_52 H_DINV#0
AD3 J8
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1
AD7 L3
H_D#55 H_D#_54 H_DINV#_1 H_DINV#2
AE14 Y13
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3
Place them near to the chip ( < 0.5") H_D#57
AF3
AC1
H_D#_56 H_DINV#_3
Y1
H_DSTBN#[3..0]
H_D#_57 H_DSTBN#[3..0] 4
H_D#58 AE3 L10 H_DSTBN#0
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1
AC3 M7
H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2
AE11 AA5
H_D#61 H_D#_60 H_DSTBN#_2 H_DSTBN#3
AE8 AE6
H_D#62 H_D#_61 H_DSTBN#_3 H_DSTBP#[3..0]
AG2 H_DSTBP#[3..0] 4
B H_D#63 H_D#_62 H_DSTBP#0 B
AD6 L9
H_D#_63 H_DSTBP#_0 H_DSTBP#1
M8
H_DSTBP#_1 H_DSTBP#2
AA6
H_DSTBP#_2 H_DSTBP#3
AE5
H_DSTBP#_3
H_REQ#[4..0] 4
1D05V_S0 B15 H_REQ#0
H_SWING H_REQ#_0 H_REQ#1
C5 K13
H_RCOMP H_SWING H_REQ#_1 H_REQ#2
E3 F13
2

H_RCOMP H_REQ#_2 H_REQ#3


B13
R370 H_REQ#_3 H_REQ#4
4,51 H_CPURST# C12 B14
1KR2F-3-GP H_CPURST# H_REQ#_4
4 H_CPUSLP# E11 H_RS#[2..0] 4
H_CPUSLP# H_RS#0
B6
H_RS#_0 H_RS#1
F12
1

H_AVREF H_RS#_1 H_RS#2


A11 C8
H_AVREF H_RS#_2
B11
H_DVREF
SCD1U16V2ZY-2GP
1

C614 CANTIGA-GM-GP-U-NF
R389 71.CNTIG.00U
2KR2F-3-GP
2
2

A JV50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (1 of 6)
Size Document Number Rev

JV50 SB
Date: Thursday, January 08, 2009 Sheet 6 of 60
5 4 3 2 1
5 4 3 2 1

1D05V_S0

NB1B 2 OF 10 2 1
NB1C 3 OF 10 R196 49D9R2F-GP Close to GMCH as 500 mils.
M36

DDR CLK/ CONTROL/COMPENSATION


RESERVED#M36 C270 SC47P50V2JN-3GP
N36 AP24 M_CLK_DDR0 16 18 L_BKLTCTL L32
RESERVED#N36 SA_CK_0 L_BKLT_CTRL PEG_CMP
R33 AT21 M_CLK_DDR1 16 35 GMCH_BL_ON G32 T37 2 1
RESERVED#R33 SA_CK_1 LCTLA_CLK L_BKLT_EN PEG_COMPI
T33
RESERVED#T33 SB_CK_0
AV24 M_CLK_DDR2 17 M32
L_CTRL_CLK PEG_COMPO
T36 DY modify by RF
AH9 AU20 M_CLK_DDR3 17
RESERVED#AH9 SB_CK_1 LCTLB_DATA
AH10 M33 PEG_RXN[15..0] 52
RESERVED#AH10 CLK_DDC_EDID L_CTRL_DATA PEG_RXN0
AH12 AR24 M_CLK_DDR#0 16 18 CLK_DDC_EDID K33 H44
RESERVED#AH12 SA_CK#_0 DAT_DDC_EDID L_DDC_CLK PEG_RX#_0 PEG_RXN1
AH13 AR21 M_CLK_DDR#1 16 18 DAT_DDC_EDID J33 J46
RESERVED#AH13 SA_CK#_1 L_DDC_DATA PEG_RX#_1 PEG_RXN2
K12 AU24 M_CLK_DDR#2 17 L44
RESERVED#K12 SB_CK#_0 PEG_RX#_2 PEG_RXN3
AL34 AV20 M_CLK_DDR#3 17 L40
RESERVED#AL34 SB_CK#_1 GMCH_LCDVDD_ON PEG_RX#_3 PEG_RXN4
AK34 18 GMCH_LCDVDD_ON M29 N41
RESERVED#AK34 LIBG L_VDD_EN PEG_RX#_4 PEG_RXN5
AN35 BC28 M_CKE0 16 C44 P48
RESERVED#AN35 SA_CKE_0 TPAD14-GP TP189 LVDS_IBG PEG_RX#_5
AM35 AY28 M_CKE1 16 1 L_LVBG B43 N44 PEG_RXN6
RESERVED#AM35 SA_CKE_1 R183 1 LVDS_VREF LVDS_VBG PEG_RX#_6 PEG_RXN7
T24 AY36 M_CKE2 17 2 E37 T43
RESERVED#T24 SB_CKE_0 0R0402-PAD LVDS_VREFH PEG_RX#_7 PEG_RXN8
D BB36 M_CKE3 17 E38 U43 D
SB_CKE_1 LVDS_VREFL PEG_RX#_8

RSVD
B31 18 GMCH_TXACLK- C41 Y43 PEG_RXN9
RESERVED#B31 LVDSA_CLK# PEG_RX#_9 PEG_RXN10
B2 BA17 M_CS0# 16 18 GMCH_TXACLK+ C40 Y48
RESERVED#B2 SA_CS#_0 LVDSA_CLK PEG_RX#_10 PEG_RXN11
M1 AY16 M_CS1# 16 18 GMCH_TXBCLK- B37 Y36
RESERVED#M1 SA_CS#_1 LVDSB_CLK# PEG_RX#_11 PEG_RXN12
AV16 M_CS2# 17 18 GMCH_TXBCLK+ A37 AA43
SB_CS#_0 LVDSB_CLK PEG_RX#_12

LVDS
AR13 M_CS3# 17 AD37 PEG_RXN13
SB_CS#_1 PEG_RX#_13 PEG_RXN14
AY21 18 GMCH_TXAOUT0- H47 AC47
RESERVED#AY21 LVDSA_DATA#_0 PEG_RX#_14 PEG_RXN15
BD17 M_ODT0 16 18 GMCH_TXAOUT1- E46 AD39
SA_ODT_0 LVDSA_DATA#_1 PEG_RX#_15
AY17 M_ODT1 16 18 GMCH_TXAOUT2- G40 PEG_RXP[15..0] 52
SA_ODT_1 LVDSA_DATA#_2 PEG_RXP0
BF15 M_ODT2 17 A40 H43
SB_ODT_0 LVDSA_DATA#_3 PEG_RX_0

GRAPHICS
BG23 AY13 M_ODT3 17 J44 PEG_RXP1
RESERVED#BG23 SB_ODT_1 PEG_RX_1 PEG_RXP2
BF23 18 GMCH_TXAOUT0+ H48 L43
RESERVED#BF23 M_RCOMPP LVDSA_DATA_0 PEG_RX_2 PEG_RXP3
BH18 BG22 18 GMCH_TXAOUT1+ D45 L41
RESERVED#BH18 SM_RCOMP M_RCOMPN LVDSA_DATA_1 PEG_RX_3 PEG_RXP4
BF18 BH21 SM_PWROK 39 18 GMCH_TXAOUT2+ F40 N40
RESERVED#BF18 SM_RCOMP# LVDSA_DATA_2 PEG_RX_4 PEG_RXP5
B40 P47
SM_RCOMP_VOH LVDSA_DATA_3 PEG_RX_5 PEG_RXP6
BF28 N43
SM_RCOMP_VOH SM_RCOMP_VOL DDR_VREF_S3_1 PEG_RX_6 PEG_RXP7
BH28 18 GMCH_TXBOUT0- A41 T42
SM_RCOMP_VOL LVDSB_DATA#_0 PEG_RX_7 PEG_RXP8
0.75V 18 GMCH_TXBOUT1- H38
LVDSB_DATA#_1 PEG_RX_8
U42
AV42 18 GMCH_TXBOUT2- G37 Y42 PEG_RXP9
SM_VREF DDR2 : connect to GND LVDSB_DATA#_2 PEG_RX_9 PEG_RXP10
AR36 J37 W47
SM_PWROK SM_REXT R4441 499R2F-2-GP LVDSB_DATA#_3 PEG_RX_10 PEG_RXP11
BF17 2 Y37
SM_REXT PEG_RX_11

1
BC36 DDR3_DRAMRST# DDR3_DRAMRST# 16,17 C335 18 GMCH_TXBOUT0+ B42 AA42 PEG_RXP12
SM_DRAMRST# LVDSB_DATA_0 PEG_RX_12

SCD1U10V2KX-4GP
18 GMCH_TXBOUT1+ G38 AD36 PEG_RXP13
LVDSB_DATA_1 PEG_RX_13 PEG_RXP14
B38 18 GMCH_TXBOUT2+ F37 AC48

2
DPLL_REF_CLK DREFCLK 3 LVDSB_DATA_2 PEG_RX_14

PCI-EXPRESS
A38 K37 AD40 PEG_RXP15
DPLL_REF_CLK# DREFCLK# 3 LVDSB_DATA_3 PEG_RX_15
E41 PEG_TXN[15..0] 52
DPLL_REF_SSCLK DREFSSCLK 3 PEG_TXN0_L C220 SCD1U10V2KX-5GP PEG_TXN0
DPLL_REF_SSCLK#
F41
DREFSSCLK# 3 PEG_TX#_0
J41 DIS 1 2
M46 PEG_TXN1_L DIS 1 2 C648 SCD1U10V2KX-5GP PEG_TXN1
TV_DACA PEG_TX#_1 PEG_TXN2_L C654 SCD1U10V2KX-5GP PEG_TXN2
F43 F25 M47 DIS 1 2

CLK
PEG_CLK CLK_MCH_3GPLL 3 TVA_DAC PEG_TX#_2
E43 CLK_MCH_3GPLL# 3 TV_DACB H25 M40 PEG_TXN3_L DIS 1 2 C228 SCD1U10V2KX-5GP PEG_TXN3
PEG_CLK# TV_DACC TVB_DAC PEG_TX#_3 PEG_TXN4_L C233 SCD1U10V2KX-5GP PEG_TXN4
K25
TVC_DAC PEG_TX#_4
M42 DIS 1 2
R48 PEG_TXN5_L DIS 1 2 C658 SCD1U10V2KX-5GP PEG_TXN5
PEG_TX#_5 PEG_TXN6_L C237 SCD1U10V2KX-5GP PEG_TXN6
H24
TV_RTN PEG_TX#_6
N38 DIS 1 2

TV
AE41 T40 PEG_TXN7_L DIS 1 2 C239 SCD1U10V2KX-5GP PEG_TXN7
DMI_RXN_0 DMI_TXN0 13 PEG_TX#_7 PEG_TXN8_L C265 SCD1U10V2KX-5GP PEG_TXN8
DMI_RXN_1
AE37
DMI_TXN1 13 PEG_TX#_8
U37 DIS 1 2
AE47 U40 PEG_TXN9_L DIS 1 2 C264 SCD1U10V2KX-5GP PEG_TXN9
DMI_RXN_2 DMI_TXN2 13 PEG_TX#_9 PEG_TXN10_L C269 SCD1U10V2KX-5GP PEG_TXN10
DMI_RXN_3
AH39
DMI_TXN3 13
C31
TV_DCONSEL_0 PEG_TX#_10
Y40 DIS 1 2
E32 AA46 PEG_TXN11_L DIS 1 2 C660 SCD1U10V2KX-5GP PEG_TXN11
TV_DCONSEL_1 PEG_TX#_11 PEG_TXN12_L C671 SCD1U10V2KX-5GP PEG_TXN12
DMI_RXP_0
AE40
DMI_TXP0 13 PEG_TX#_12
AA37 DIS 1 2
3,4 CPU_SEL0 T25 AE38 AA40 PEG_TXN13_L DIS 1 2 C666 SCD1U10V2KX-5GP PEG_TXN13
CFG_0 DMI_RXP_1 DMI_TXP1 13 PEG_TX#_13 PEG_TXN14_L C680 SCD1U10V2KX-5GP PEG_TXN14
3,4 CPU_SEL1 R25
CFG_1 DMI_RXP_2
AE48
DMI_TXP2 13 PEG_TX#_14
AD43 DIS 1 2
C 3,4 CPU_SEL2 P25 AH40 AC46 PEG_TXN15_L DIS 1 2 C679 SCD1U10V2KX-5GP PEG_TXN15 C
CFG_2 DMI_RXP_3 DMI_TXP3 13 PEG_TX#_15
P20 PEG_TXP[15..0] 52
CFG_3 GMCH_BLUE PEG_TXP0_L C213 SCD1U10V2KX-5GP PEG_TXP0
P24
CFG_4 DMI_TXN_0
AE35
DMI_RXN0 13 19 GMCH_BLUE E28
CRT_BLUE PEG_TX_0
J42 DIS 1 2

DMI
C25 AE43 L46 PEG_TXP1_L DIS 1 2 C647 SCD1U10V2KX-5GP PEG_TXP1
CFG_5 DMI_TXN_1 DMI_RXN1 13 GMCH_GREEN PEG_TX_1 PEG_TXP2_L C651 SCD1U10V2KX-5GP PEG_TXP2
N24
CFG_6 DMI_TXN_2
AE46
DMI_RXN2 13 19 GMCH_GREEN G28
CRT_GREEN PEG_TX_2
M48 DIS 1 2
1D5V_S3 PEG_TXP3_L C222 SCD1U10V2KX-5GP PEG_TXP3
M24
CFG_7 DMI_TXN_3
AH42
DMI_RXN3 13 PEG_TX_3
M39 DIS 1 2

CFG
E21 19 GMCH_RED GMCH_RED J28 M43 PEG_TXP4_L DIS 1 2 C229 SCD1U10V2KX-5GP PEG_TXP4
CFG9 CFG_8 CRT_RED PEG_TX_4 PEG_TXP5_L C663 SCD1U10V2KX-5GP PEG_TXP5
C23
CFG_9 DMI_TXP_0
AD35
DMI_RXP0 13 PEG_TX_5
R47 DIS 1 2

VGA
C24 AE44 G29 N37 PEG_TXP6_L DIS 1 2 C234 SCD1U10V2KX-5GP PEG_TXP6
CFG_10 DMI_TXP_1 CRT_IRTN PEG_TX_6
1

DMI_RXP1 13 PEG_TXP7_L C245 SCD1U10V2KX-5GP PEG_TXP7


N21
CFG_11 DMI_TXP_2
AF46
DMI_RXP2 13 PEG_TX_7
T39 DIS 1 2
R443 P21 AH43 19 GMCH_DDCCLK GMCH_DDCCLK H32 U36 PEG_TXP8_L DIS 1 2 C259 SCD1U10V2KX-5GP PEG_TXP8
3D3V_S0 80D6R2F-L-GP CFG_12 DMI_TXP_3 DMI_RXP3 13 GMCH_DDCDATA CRT_DDC_CLK PEG_TX_8 PEG_TXP9_L C253 SCD1U10V2KX-5GP PEG_TXP9
T21
CFG_13 19 GMCH_DDCDATA J32
CRT_DDC_DATA PEG_TX_9
U39 DIS 1 2
R20 19 GMCH_HSYNC 1 R189 2 GMCH_HS J29 Y39 PEG_TXP10_L DIS 1 2 C266 SCD1U10V2KX-5GP PEG_TXP10
CFG_14 0R0402-PAD CRT_HSYNC PEG_TX_10 PEG_TXP11_L C657 SCD1U10V2KX-5GP PEG_TXP11
M20 E29 Y46 DIS 1 2
2

M_RCOMPP CFG16 CFG_15 CRT_TVO_IREF PEG_TX_11


L21 19 GMCH_VSYNC 1 R188 2GMCH_VS L29 AA36 PEG_TXP12_L DIS 1 2 C667 SCD1U10V2KX-5GP PEG_TXP12
CFG_16 0R0402-PAD CRT_VSYNC PEG_TX_12 PEG_TXP13_L C664 SCD1U10V2KX-5GP PEG_TXP13
H21 AA39 DIS 1 2

GRAPHICS VID
CFG_17 PEG_TX_13 PEG_TXP14_L C672 SCD1U10V2KX-5GP PEG_TXP14
P29
CFG_18 GFX_VID[4..0] 46 PEG_TX_14
AD42 DIS 1 2
R193 1 DY 2 4K02R2F-GP CFG20 M_RCOMPN R28 1 UMA 2 CRT_IREF AD46 PEG_TXP15_L DIS 1 2 C686 SCD1U10V2KX-5GP PEG_TXP15
CFG20 CFG_19 GFX_VID0 R161 1K02R2F-1-GP PEG_TX_15
T28 B33
CFG_20 GFX_VID_0
1

B32 GFX_VID1
R442 GFX_VID_1 GFX_VID2 CANTIGA-GM-GP-U-NF
G33
R385 1 GFX_VID_2
DY 2 2K21R2F-GP CFG9 80D6R2F-L-GP F33 GFX_VID3 71.CNTIG.00U
GFX_VID_3 GFX_VID4
13 PM_SYNC# R29
PM_SYNC# GFX_VID_4
E33 FOR Cantiga: 1.02k_1% ohm
4,12,41 H_DPRSTP# B7 Teenah: 1.3k ohm
2

R556 1 PM_DPRSTP#
DY 2 2K21R2F-GP CFG16 16,17 PM_EXTTS#0 PM_EXTTS#0 N33 SB 1202
PM_EXTTS#1 PM_EXT_TS#_0
P32
PM_EXT_TS#_1 CRT_IREF routing Trace
PM

SB 1202 AT40 C34 GFXVR_EN


13,34 PWROK PWROK GFX_VR_EN width use 20 mil
RSTIN# AT11 1D05V_S0 PEG_TXN0_L UMA 1 2 C600 SCD1U10V2KX-5GP PEG_TXN0_L_1 UMA 1 4 RN82 HDMI_DATA2- 20,55
NB_THERMTRIP# RSTIN# PEG_TXP0_L
T20 UMA 1 2 C605 SCD1U10V2KX-5GP PEG_TXP0_L_1 2 3 SRN0J-10-GP-U HDMI_DATA2+ 20,55
THERMTRIP#

2
13,25,31,32,33,35,36,51,52 PLT_RST1# 2 1 PM_DPRSLPVR_MCH R32
100R2J-2-GP R203 DPRSLPVR R201
AH37 1KR2F-3-GP PEG_TXN1_L UMA 1 2 C596 SCD1U10V2KX-5GP PEG_TXN1_L_1 UMA 1 4 RN83
CL_CLK CL_CLK0 13 HDMI_DATA1- 20,55
1

C324 AH36 PEG_TXP1_L UMA 1 2 C598 SCD1U10V2KX-5GP PEG_TXP1_L_1 2 3 SRN0J-10-GP-U HDMI_DATA1+ 20,55
CL_DATA CL_DATA0 13
SC100P50V2JN-3GP BG48 AN36
ME

1
NC#BG48 CL_PWROK PWROK 13,34
DY BF48 AJ35
2

NC#BF48 CL_RST# CL_RST#0 13


SB 1202 BD48 AH34 MCH_CLVREF PEG_TXN2_L UMA 1 2 C589 SCD1U10V2KX-5GP PEG_TXN2_L_1 UMA 1 4 RN84 HDMI_DATA0- 20,55
NC#BD48 CL_VREF PEG_TXP2_L
BC48 UMA 1 2 C592 SCD1U10V2KX-5GP PEG_TXP2_L_1 2 3 SRN0J-10-GP-U HDMI_DATA0+ 20,55
NC#BC48

1
BH47
NC#BH47

1
4,12,39 PM_THRMTRIP-A# 1 R192 2 BG47 for HDMI port C C288 R200
0R0402-PAD NC#BG47 499R2F-2-GP PEG_TXN3_L
BE47 N28 UMA 1 2 C568 SCD1U10V2KX-5GP PEG_TXN3_L_1 UMA 2 3 RN85

SCD1U10V2KX-4GP
NC#BE47 DDPC_CTRLCLK HDMI_CLK- 20,55
BH46 M28 PEG_TXP3_L UMA 1 2 C561 SCD1U10V2KX-5GP PEG_TXP3_L_1 1 4 SRN0J-10-GP-U HDMI_CLK+ 20,55

2
B NC#BH46 DDPC_CTRLDATA B
BF46 G36

2
NC#BF46 SDVO_CTRLCLK GMCH_HDMI_CLK 20
NC

13,41 PM_DPRSLPVR 1 R195 2 PM_DPRSLPVR_MCH BG45 E36 GMCH_HDMI_DATA 20


NC#BG45 SDVO_CTRLDATA
MISC

0R0402-PAD BH44 K36 CLK_MCH_OE# CLK_MCH_OE# 3


NC#BH44 CLKREQ#
BH43 H36 MCH_ICH_SYNC# 13
NC#BH43 ICH_SYNC#
BH6
NC#BH6
FOR Cantiga:500 ohm
BH5 R555 R61
NC#BH5 Teenah: 392 ohm
BG4 B12 MCH_TSATN# PEG_RXP3 1 2UMA HDMI_DETECT#_L 1 2UMA
NC#BG4 TSATN# HDMI_DETECT# 20
BH3
NC#BH3 0R2J-2-GP 0R2J-2-GP
BF3
NC#BF3
BH2
NC#BH2 HDA_BCLK
BG2 B28 R419
NC#BG2 HDA_BCLK HDA_RST#
BE2 B30
NC#BE2 HDA_RST# HDA_SDI ACZ_SDIN3
BG1
NC#BG1 HDA_SDI
B29 1 2 UMA ACZ_SDIN3 12
BF1 C29 HDA_SDO
NC#BF1 HDA_SDO HDA_SYNC 33R2J-2-GP
BD1 A28
NC#BD1 HDA_SYNC
HDA

BC1
NC#BC1 RN36
F1 RN30
NC#F1 HDA_BCLK ACZ_BIT_CLK GMCH_RED
A47 1 8 ACZ_BIT_CLK 12 1 8
NC#A47 HDA_SYNC ACZ_SYNC_R GMCH_GREEN
2 7 ACZ_SYNC_R 12 2 7
HDA_RST# 3 6 ACZ_RST#_R ACZ_RST#_R 12 GMCH_BLUE 3 6
CANTIGA-GM-GP-U-NF HDA_SDO 4 5 ACZ_SDATAOUT_R ACZ_SDATAOUT_R 12 4 5
71.CNTIG.00U
UMA
SRN33J-4-GP SRN150F-1-GP
UMA/DIS RN32
1D05V_S0 1D5V_S3 GMCH_BL_ON 2 3
R445 1KR2F-3-GP GMCH_LCDVDD_ON 1 4
2 1 FOR Discrete change RN to 0 ohm UMA
1

SRN100KJ-6-GP
(66.R0036.A8L)
R387 SM_RCOMP_VOH
56R2J-4-GP UMA
1

C756 C759 1 2 HDA_BCLK LIBG 1 2


R441 EC21DY SC12P50V2JN-3GP R384 2K37R2F-GP
2

3K01R2F-3-GP RN31
MCH_TSATN# SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP
2

5 4 DIS
6 3 TV_DACC CRT_IREF 1 2
2

SM_RCOMP_VOL 7 2 TV_DACB R162 0R2J-2-GP


8 1 TV_DACA
2

C757 C760 UMA/DIS RN33


R446 GMCH_VS 2 3
GFXVR_EN 1KR2F-3-GP SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP SRN75J-1-GP GMCH_HS
GFXVR_EN 46 1 4
2

A A
DIS
FOR Discrete,change to 0 ohm SRN0J-10-GP-U
1
2

(66.R0036.A8L)
R178
DY 100KR2F-L1-GP
3D3V_S0 layout take note
1

RN34 UMA
LCTLA_CLK 4 1 Wistron Corporation
LCTLB_DATA 3 2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SRN10KJ-5-GP
RN35 Title
PM_EXTTS#0 4 1
PM_EXTTS#1 3 2 Cantiga (2 of 6)
Size Document Number Rev
SRN10KJ-5-GP
JV50 SB
Date: Thursday, January 08, 2009 Sheet 7 of 60
5 4 3 2 1
5 4 3 2 1

NB1D 4 OF 10 NB1E 5 OF 10
M_A_DQ[63..0] M_B_DQ[63..0]
16 M_A_DQ[63..0] 17 M_B_DQ[63..0]
M_A_DQ0 AJ38 BD21 M_B_DQ0 AK47 BC16
SA_DQ_0 SA_BS_0 M_A_BS#0 16 SB_DQ_0 SB_BS_0 M_B_BS#0 17
M_A_DQ1 AJ41 BG18 M_B_DQ1 AH46 BB17
SA_DQ_1 SA_BS_1 M_A_BS#1 16 SB_DQ_1 SB_BS_1 M_B_BS#1 17
M_A_DQ2 AN38 AT25 M_A_BS#2 16 M_B_DQ2 AP47 BB33 M_B_BS#2 17
M_A_DQ3 SA_DQ_2 SA_BS_2 M_B_DQ3 SB_DQ_2 SB_BS_2
AM38 AP46
M_A_DQ4 SA_DQ_3 M_B_DQ4 SB_DQ_3
AJ36 BB20 M_A_RAS# 16 AJ46
M_A_DQ5 SA_DQ_4 SA_RAS# M_B_DQ5 SB_DQ_4
AJ40 BD20 M_A_CAS# 16 AJ48 AU17 M_B_RAS# 17
M_A_DQ6 SA_DQ_5 SA_CAS# M_B_DQ6 SB_DQ_5 SB_RAS#
AM44 AY20 M_A_WE# 16 AM48 BG16 M_B_CAS# 17
M_A_DQ7 SA_DQ_6 SA_WE# M_B_DQ7 SB_DQ_6 SB_CAS#
AM42 AP48 BF14 M_B_WE# 17
M_A_DQ8 SA_DQ_7 M_B_DQ8 SB_DQ_7 SB_WE#
D AN43 AU47 D
M_A_DQ9 SA_DQ_8 M_B_DQ9 SB_DQ_8
AN44 AU46
M_A_DQ10 SA_DQ_9 M_A_DM[7..0] M_B_DQ10 SB_DQ_9
AU40 M_A_DM[7..0] 16 BA48
M_A_DQ11 SA_DQ_10 M_A_DM0 M_B_DQ11 SB_DQ_10 M_B_DM[7..0]
AT38 AM37 AY48 M_B_DM[7..0] 17
M_A_DQ12 SA_DQ_11 SA_DM_0 M_A_DM1 M_B_DQ12 SB_DQ_11 M_B_DM0
AN41 AT41 AT47 AM47
M_A_DQ13 SA_DQ_12 SA_DM_1 M_A_DM2 M_B_DQ13 SB_DQ_12 SB_DM_0 M_B_DM1
AN39 AY41 AR47 AY47
M_A_DQ14 SA_DQ_13 SA_DM_2 M_A_DM3 M_B_DQ14 SB_DQ_13 SB_DM_1 M_B_DM2
AU44 AU39 BA47 BD40
M_A_DQ15 SA_DQ_14 SA_DM_3 M_A_DM4 M_B_DQ15 SB_DQ_14 SB_DM_2 M_B_DM3
AU42 BB12 BC47 BF35
M_A_DQ16 SA_DQ_15 SA_DM_4 M_A_DM5 M_B_DQ16 SB_DQ_15 SB_DM_3 M_B_DM4
AV39 AY6 BC46 BG11
M_A_DQ17 SA_DQ_16 SA_DM_5 M_A_DM6 M_B_DQ17 SB_DQ_16 SB_DM_4 M_B_DM5
AY44 AT7 BC44 BA3
SA_DQ_17 SA_DM_6 SB_DQ_17 SB_DM_5

A
M_A_DQ18 BA40 AJ5 M_A_DM7 M_B_DQ18 BG43 AP1 M_B_DM6
SA_DQ_18 SA_DM_7 SB_DQ_18 SB_DM_6

B
M_A_DQ19 BD43 M_A_DQS[7..0] M_B_DQ19 BF43 AK2 M_B_DM7
SA_DQ_19 M_A_DQS[7..0] 16 SB_DQ_19 SB_DM_7
M_A_DQ20 AV41 AJ44 M_A_DQS0 M_B_DQ20 BE45 M_B_DQS[7..0]
SA_DQ_20 SA_DQS_0 SB_DQ_20 M_B_DQS[7..0] 17
M_A_DQ21 AY43 AT44 M_A_DQS1 M_B_DQ21 BC41 AL47 M_B_DQS0
M_A_DQ22 SA_DQ_21 SA_DQS_1 M_A_DQS2 M_B_DQ22 SB_DQ_21 SB_DQS_0 M_B_DQS1
BB41 BA43 BF40 AV48

MEMORY
M_A_DQ23 SA_DQ_22 SA_DQS_2 M_A_DQS3 M_B_DQ23 SB_DQ_22 SB_DQS_1 M_B_DQS2
BC40 BC37 BF41 BG41

MEMORY
M_A_DQ24 SA_DQ_23 SA_DQS_3 M_A_DQS4 M_B_DQ24 SB_DQ_23 SB_DQS_2 M_B_DQS3
AY37 AW12 BG38 BG37
M_A_DQ25 SA_DQ_24 SA_DQS_4 M_A_DQS5 M_B_DQ25 SB_DQ_24 SB_DQS_3 M_B_DQS4
BD38 BC8 BF38 BH9
M_A_DQ26 SA_DQ_25 SA_DQS_5 M_A_DQS6 M_B_DQ26 SB_DQ_25 SB_DQS_4 M_B_DQS5
AV37 AU8 BH35 BB2
M_A_DQ27 SA_DQ_26 SA_DQS_6 M_A_DQS7 M_A_DQS#[7..0] M_B_DQ27 SB_DQ_26 SB_DQS_5 M_B_DQS6
AT36 AM7 M_A_DQS#[7..0] 16 BG35 AU1
M_A_DQ28 SA_DQ_27 SA_DQS_7 M_A_DQS#0 M_B_DQ28 SB_DQ_27 SB_DQS_6 M_B_DQS7 M_B_DQS#[7..0]
AY38 AJ43 BH40 AN6 M_B_DQS#[7..0] 17
M_A_DQ29 SA_DQ_28 SA_DQS#_0 M_A_DQS#1 M_B_DQ29 SB_DQ_28 SB_DQS_7 M_B_DQS#0
BB38 AT43 BG39 AL46
M_A_DQ30 SA_DQ_29 SA_DQS#_1 M_A_DQS#2 M_B_DQ30 SB_DQ_29 SB_DQS#_0 M_B_DQS#1
AV36 BA44 BG34 AV47
M_A_DQ31 SA_DQ_30 SA_DQS#_2 M_A_DQS#3 M_B_DQ31 SB_DQ_30 SB_DQS#_1 M_B_DQS#2
AW36 BD37 BH34 BH41
M_A_DQ32 SA_DQ_31 SA_DQS#_3 M_A_DQS#4 M_B_DQ32 SB_DQ_31 SB_DQS#_2 M_B_DQS#3
BD13 AY12 BH14 BH37
M_A_DQ33 SA_DQ_32 SA_DQS#_4 M_A_DQS#5 M_B_DQ33 SB_DQ_32 SB_DQS#_3 M_B_DQS#4
AU11 BD8 BG12 BG9
M_A_DQ34 SA_DQ_33 SA_DQS#_5 M_A_DQS#6 M_B_DQ34 SB_DQ_33 SB_DQS#_4 M_B_DQS#5
BC11 AU9 BH11 BC2
M_A_DQ35 SA_DQ_34 SA_DQS#_6 M_A_DQS#7 M_B_DQ35 SB_DQ_34 SB_DQS#_5 M_B_DQS#6
BA12 AM8 BG8 AT2
SYSTEM
M_A_DQ36 SA_DQ_35 SA_DQS#_7 M_A_A[14..0] M_B_DQ36 SB_DQ_35 SB_DQS#_6 M_B_DQS#7
AU13 BH12 AN5

SYSTEM
SA_DQ_36 M_A_A[14..0] 16 SB_DQ_36 SB_DQS#_7
C M_A_DQ37 AV13 BA21 M_A_A0 M_B_DQ37 BF11 M_B_A[14..0] C
SA_DQ_37 SA_MA_0 SB_DQ_37 M_B_A[14..0] 17
M_A_DQ38 BD12 BC24 M_A_A1 M_B_DQ38 BF8 AV17 M_B_A0
M_A_DQ39 SA_DQ_38 SA_MA_1 M_A_A2 M_B_DQ39 SB_DQ_38 SB_MA_0 M_B_A1
BC12 BG24 BG7 BA25
M_A_DQ40 SA_DQ_39 SA_MA_2 M_A_A3 M_B_DQ40 SB_DQ_39 SB_MA_1 M_B_A2
BB9 BH24 BC5 BC25
M_A_DQ41 SA_DQ_40 SA_MA_3 M_A_A4 M_B_DQ41 SB_DQ_40 SB_MA_2 M_B_A3
BA9 BG25 BC6 AU25
M_A_DQ42 SA_DQ_41 SA_MA_4 M_A_A5 M_B_DQ42 SB_DQ_41 SB_MA_3 M_B_A4
AU10 BA24 AY3 AW25
M_A_DQ43 SA_DQ_42 SA_MA_5 M_A_A6 M_B_DQ43 SB_DQ_42 SB_MA_4 M_B_A5
AV9 BD24 AY1 BB28
M_A_DQ44 SA_DQ_43 SA_MA_6 M_A_A7 M_B_DQ44 SB_DQ_43 SB_MA_5 M_B_A6
BA11 BG27 BF6 AU28
M_A_DQ45 SA_DQ_44 SA_MA_7 M_A_A8 M_B_DQ45 SB_DQ_44 SB_MA_6 M_B_A7
BD9 BF25 BF5 AW28
M_A_DQ46 SA_DQ_45 SA_MA_8 M_A_A9 M_B_DQ46 SB_DQ_45 SB_MA_7 M_B_A8
AY8 AW24 BA1 AT33
M_A_DQ47 SA_DQ_46 SA_MA_9 M_A_A10 M_B_DQ47 SB_DQ_46 SB_MA_8 M_B_A9
BA6 BC21 BD3 BD33
M_A_DQ48 SA_DQ_47 SA_MA_10 M_A_A11 M_B_DQ48 SB_DQ_47 SB_MA_9 M_B_A10
DDR

AV5 BG26 AV2 BB16


M_A_DQ49 SA_DQ_48 SA_MA_11 M_A_A12 M_B_DQ49 SB_DQ_48 SB_MA_10 M_B_A11

DDR
AV7 BH26 AU3 AW33
M_A_DQ50 SA_DQ_49 SA_MA_12 M_A_A13 M_B_DQ50 SB_DQ_49 SB_MA_11 M_B_A12
AT9 BH17 AR3 AY33
M_A_DQ51 SA_DQ_50 SA_MA_13 M_A_A14 M_B_DQ51 SB_DQ_50 SB_MA_12 M_B_A13
AN8 AY25 AN2 BH15
M_A_DQ52 SA_DQ_51 SA_MA_14 M_B_DQ52 SB_DQ_51 SB_MA_13 M_B_A14
AU5 AY2 AU33
M_A_DQ53 SA_DQ_52 M_B_DQ53 SB_DQ_52 SB_MA_14
AU6 AV1
M_A_DQ54 SA_DQ_53 M_B_DQ54 SB_DQ_53
AT5 AP3
M_A_DQ55 SA_DQ_54 M_B_DQ55 SB_DQ_54
AN10 AR1
M_A_DQ56 SA_DQ_55 M_B_DQ56 SB_DQ_55
AM11 AL1
M_A_DQ57 SA_DQ_56 M_B_DQ57 SB_DQ_56
AM5 AL2
M_A_DQ58 SA_DQ_57 M_B_DQ58 SB_DQ_57
AJ9 AJ1
M_A_DQ59 SA_DQ_58 M_B_DQ59 SB_DQ_58
AJ8 AH1
M_A_DQ60 SA_DQ_59 M_B_DQ60 SB_DQ_59
AN12 AM2
M_A_DQ61 SA_DQ_60 M_B_DQ61 SB_DQ_60
AM13 AM3
M_A_DQ62 SA_DQ_61 M_B_DQ62 SB_DQ_61
AJ11 AH3
M_A_DQ63 SA_DQ_62 M_B_DQ63 SB_DQ_62
AJ12 AJ3
SA_DQ_63 SB_DQ_63

B B
CANTIGA-GM-GP-U-NF CANTIGA-GM-GP-U-NF
71.CNTIG.00U 71.CNTIG.00U

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (3 of 6)
Size Document Number Rev

JV50 SB
Date: Thursday, January 08, 2009 Sheet 8 of 60
5 4 3 2 1
5 4 3 2 1

7 OF 10 VCC_GFXCORE
1D5V_S3 NB1G

AP33 W28
VCC_SM VCC_AXG_NCTF
AN33 V28
VCC_SM VCC_AXG_NCTF 1D05V_S0 NB1F 6 OF 10
BH32
BG32
VCC_SM VCC_AXG_NCTF
W26
V26 DIS
FOR VCC CORE
VCC_SM VCC_AXG_NCTF
BF32 W25 1 2
VCC_SM VCC_AXG_NCTF R438 0R5J-1-GP
BD32 V25 AG34
VCC_SM VCC_AXG_NCTF VCC
BC32
VCC_SM VCC_AXG_NCTF
W24 DIS AC34
VCC
BB32 V24 1 2 AB34
VCC_SM VCC_AXG_NCTF R439 0R5J-1-GP VCC
BA32 W23 AA34
VCC_SM VCC_AXG_NCTF VCC

1
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
AY32 V23 C291 C287 C274 C249 C281 C280 C284 Y34
VCC_SM VCC_AXG_NCTF VCC
AW32 AM21 V34
VCC_SM VCC_AXG_NCTF VCC

SCD22U10V2KX-1GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
AV32 AL21 U34

2
VCC_SM VCC_AXG_NCTF VCC
AU32 AK21 AM33
VCC_SM VCC_AXG_NCTF VCC
D AT32 W21 AK33 D
VCC_SM VCC_AXG_NCTF VCC
AR32 V21 AJ33
VCC_SM VCC_AXG_NCTF VCC
AP32 U21 DY DY AG33

POWER
VCC_SM VCC_AXG_NCTF VCC
AN32 AM20 AF33
VCC_SM VCC_AXG_NCTF VCC
BH31 AK20
VCC_SM VCC_AXG_NCTF
BG31
VCC_SM VCC_AXG_NCTF
W20 Coupling CAP 370 mils from the Edge AE33
VCC
BF31 U20 AC33

VCC CORE
VCC_SM VCC_AXG_NCTF VCC
BG30 AM19 AA33
VCC_SM VCC_AXG_NCTF VCC
BH29 AL19 Y33
VCC_SM VCC_AXG_NCTF VCC
BG29 AK19 W33
VCC_SM VCC_AXG_NCTF VCC
BF29 AJ19 V33
VCC_SM VCC_AXG_NCTF VCC
BD29 AH19 U33
VCC_SM VCC_AXG_NCTF VCC

VCC SM
BC29 AG19 AH28
VCC_SM VCC_AXG_NCTF VCC_GFXCORE VCC
BB29 AF19 AF28
VCC_SM VCC_AXG_NCTF VCC
BA29
VCC_SM VCC_AXG_NCTF
AE19 -1 -1 SB 1202 AC28
VCC

1
AY29 AB19 C612 C289 AA28
VCC_SM VCC_AXG_NCTF VCC
AW29 AA19 AJ26
VCC_SM VCC_AXG_NCTF VCC

SC10U6D3V5MX-3GP

SCD1U10V2KX-4GP
AV29 Y19 AG26

2
VCC_SM VCC_AXG_NCTF VCC
AU29 W19 DY AE26

SCD47U6D3V2KX-GP
VCC_SM VCC_AXG_NCTF VCC

1
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
AT29 V19 TC18 C292 C277 C273 C276 C282 C302 C285 C275 1 C286 C271 C279 C278 AC26
VCC_SM VCC_AXG_NCTF VCC

SC1U10V3ZY-6GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
AR29 U19 AH25
VCC_SM VCC_AXG_NCTF VCC

ST220U2D5VBM-2GP
AP29 AM17 2 AG25

2
VCC_SM VCC_AXG_NCTF VCC
AK17 AF25
VCC_AXG_NCTF VCC
BA36 AH17 AG24
VCC_SM/NC VCC_AXG_NCTF VCC

POWER
BB24
VCC_SM/NC VCC_AXG_NCTF
AG17 Coupling CAP AJ23
VCC 1D05V_S0
BD16
VCC_SM/NC VCC_AXG_NCTF
AF17 DY UMA UMA DY UMA DY DY UMA DY UMA UMA UMA UMA AH23
VCC
VCC GFX NCTF

BB21 AE17 AF23


VCC_SM/NC VCC_AXG_NCTF VCC
AW16 AC17 AM32
VCC_SM/NC VCC_AXG_NCTF VCC_NCTF
AW13 AB17 T32 AL32
VCC_SM/NC VCC_AXG_NCTF VCC VCC_NCTF
AT13
VCC_SM/NC VCC_AXG_NCTF
Y17 Place on the Edge Coupling CAP VCC_NCTF
AK32
W17 AJ32
VCC_GFXCORE VCC_AXG_NCTF VCC_NCTF
V17 AH32
VCC_AXG_NCTF VCC_NCTF
AM16 AG32
VCC_AXG_NCTF VCC_NCTF
Y26 AL16 AE32
VCC_AXG VCC_AXG_NCTF VCC_NCTF
AE25 AK16 AC32
VCC_AXG VCC_AXG_NCTF VCC_NCTF
AB25 AJ16 AA32
VCC_AXG VCC_AXG_NCTF VCC_NCTF
AA25 AH16 Y32
VCC_AXG VCC_AXG_NCTF VCC_NCTF
AE24 AG16 W32
VCC_AXG VCC_AXG_NCTF VCC_NCTF
AC24 AF16 U32
VCC_AXG VCC_AXG_NCTF VCC_NCTF
AA24 AE16 AM30
VCC_AXG VCC_AXG_NCTF VCC_NCTF
Y24 AC16 AL30
VCC_AXG VCC_AXG_NCTF VCC_NCTF
C AE23 AB16 AK30 C
VCC_AXG VCC_AXG_NCTF VCC_NCTF
AC23 AA16 AH30
VCC_AXG VCC_AXG_NCTF VCC_NCTF
AB23 Y16 AG30
VCC_AXG VCC_AXG_NCTF VCC_NCTF
AA23 W16 AF30
VCC_AXG VCC_AXG_NCTF VCC_NCTF
AJ21 V16 AE30
VCC_AXG VCC_AXG_NCTF VCC_NCTF
AG21 U16 AC30
VCC_AXG VCC_AXG_NCTF VCC_NCTF
AE21 AB30
VCC_AXG VCC_NCTF
AC21 AA30
VCC_AXG VCC_NCTF
AA21 Y30
VCC_AXG VCC_NCTF
Y21 W30
VCC_AXG VCC_NCTF
AH20 FOR VCC SM V30

VCC NCTF
VCC_AXG VCC_NCTF
AF20 U30
VCC_AXG 1D5V_S3 VCC_NCTF
AE20 AL29
VCC_AXG VCC_NCTF
AC20 AK29
VCC_AXG VCC_NCTF
AB20 AJ29
VCC_AXG VCC_NCTF

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
AA20 C361 C367 C359 AH29
VCC_AXG VCC_NCTF

1
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
T17 C349 C323 C308 C348 AG29
VCC_AXG TC22 VCC_NCTF
T16 AE29
VCC_AXG VCC_NCTF

ST330U2D5VBM-GP
AM15 AC29

2
VCC_AXG DY VCC_NCTF
AL15
VCC_AXG DY DY VCC_NCTF
AA29
AE15 Y29
VCC_AXG VCC_NCTF
AJ15 W29
VCC_AXG VCC_NCTF
AH15 V29
VCC_AXG VCC_NCTF
AG15 AL28
VCC_AXG VCC_NCTF
AF15
VCC_AXG 80.3371V.12L VCC_NCTF
AK28
AB15
VCC_AXG
Place on the Edge VCC_NCTF
AL26
AA15 AK26
VCC_AXG VCC_NCTF
Y15 SB 1202 AK25
VCC GFX

VCC_AXG VCC_NCTF
V15 AK24
VCC_AXG VCC_NCTF
U15 AK23
VCC_AXG VCC_NCTF
AN14
VCC_AXG
AM14
VCC_AXG
U14 AV44 SM_LF1_GMCH CANTIGA-GM-GP-U-NF
VCC_AXG VCC_SM_LF
T14 BA37 SM_LF2_GMCH 71.CNTIG.00U
VCC SM LF

VCC_AXG VCC_SM_LF
AM40 SM_LF3_GMCH
VCC_SM_LF
AV21 SM_LF4_GMCH
VCC_SM_LF
AY5 SM_LF5_GMCH
VCC_SM_LF
AM10 SM_LF6_GMCH
VCC_SM_LF
BB13 SM_LF7_GMCH
VCC_SM_LF
SCD47U16V3ZY-3GP
C298

C340

C320
SC1U10V3KX-3GP

SC1U10V3KX-3GP
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
1

1
C350

C290

C347 C329
B VCC_AXG_SENSE AJ14 B
SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

46 VCC_AXG_SENSE VSS_AXG_SENSE VCC_AXG_SENSE


AH14
2

46 VSS_AXG_SENSE VSS_AXG_SENSE

CANTIGA-GM-GP-U-NF
71.CNTIG.00U
U60(ISL6263ACRZ-T-GP) place near Cantiga

place near Cantiga

A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cantiga (4 of 6)
Size Document Number Rev

JV50 SB
Date: Thursday, January 08, 2009 Sheet 9 of 60
5 4 3 2 1
5 4 3 2 1

5V_S0 Imax = 300 mA 3D3V_S0_DAC 1D05V_S0


UMA 3D3V_S0_DAC
U13 2 R378 1 73mA 3D3V_CRTDAC_S0 NB1H 8 OF 10 852mA

SC2D2U6D3V3MX-1-GP
1
SCD01U16V2KX-3GP

SCD1U10V2KX-4GP
0R0603-PAD C206 C617

SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SCD47U6D3V2KX-GP
1

1
C250

C267

C662

C670

C268

C263
1 5 R379 U13 1
VIN VOUT VTT
2 UMA UMA 0R2J-2-GP T13

1
GND C141 VTT 2
3 4 DY B27 U12

2
EN NC#4 VCCA_CRT_DAC VTT

SC22U6D3V5MX-2GP
BC1 A26 T12 DY

2
VCCA_CRT_DAC VTT
SC1U16V3ZY-GP

SC1U16V3ZY-GP
UMA U11

2
1

1
G9091-330T11U-GP VTT
T11
BC2 M_VCCA_DAC_BG VTT
74.09091.J3F A25 U10

CRT
3D3V_S0_DAC VCCA_DAC_BG VTT
UMA UMA B25 T10
2

2
VSSA_DAC_BG VTT
U9
D
1 R374 2 5mA VTT
T9
D

SCD1U10V2KX-4GP
0R0603-PADC625 C207 VTT
U8

1
R168 M_VCCA_DPLLA VTT
UMA UMA F47 T8

SCD01U16V2KX-3GP
1D05V_S0 0R2J-2-GP VCCA_DPLLA VTT
U7

VTT
M_VCCA_DPLLB VTT
DY L48 T7

2
VCCA_DPLLB VTT 1D05V_S0
U6
2 R371 1 65mA M_VCCA_DPLLA M_VCCA_HPLL AD1
VTT
T6 D5

PLL
2
0R0603-PAD VCCA_HPLL VTT 3D3V_S0 3D3V_HV_S0
U5 1
1

1
VTT
SC10U6D3V5MX-3GP

SCD1U10V2KX-4GP

C622 C624 R390 M_VCCA_MPLL AE1 T5


0R2J-2-GP 1D8V_TXLVDS_S0 VCCA_MPLL VTT 1D05V_HV_S0 2
V3 3 1 1 R376 2

SCD1U10V2KX-4GP
VTT R106 0R0603-PAD
DY SB 1208 U3
2

1
VTT

C621
UMA DY 10R2J-2-GP
C636 13.2mA J48
VCCA_LVDS VTT
V2
U2
2
BAT54-5-GP

A LVDS
2

SC27P50V2JN-2-GP VTT
J47 T2 83.BAT54.D81

2
VSSA_LVDS VTT
V1
1D5V_S0 VTT
U1
2 R399 1 65mA M_VCCA_DPLLB VTT
0R0603-PAD 1 R421 2 VCCA_PEG_BG AD48
1

VCCA_PEG_BG
SC10U6D3V5MX-3GP

SCD1U10V2KX-4GP

C642 C644 R40