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A Thesis

Submitted to the Graduate Faculty of the Louisiana State University and Agricultural and Mechanical College in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering

in The Department of Electrical and Computer Engineering

by Chandra Srinivasan Bachelor of Engineering, Mysore University, 1997 December 2003

To My parents and in loving memory of my grandmother

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Acknowledgements

I would like to acknowledge certain people who have encouraged, supported and helped me complete my thesis at LSU. I am very grateful to my advisor Dr. A. Srivastava for his guidance, patience and understanding throughout this work. His suggestions, discussions and constant encouragement has helped me to get a deep insight in the field of VLSI design. I would like to thank Dr. M. Feldman and Dr S. Kak for sparing their time to be a part of my thesis advisory committee. I am very thankful to Electrical Engineering Department for supporting me financially during my stay at LSU. I take this opportunity to thank my friends Harish, Kavitha, Sajida, Sunitha and Anand for their help and encouragement. I would also like to thank all my friends here who made my stay at LSU an enjoyable and a memorable one. I extend a special thank-you to Srinivas, my constant companion and beloved friend. Last of all I thank the Almighty Lord for keeping me in good health and spirits throughout my stay at LSU.

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.......1 The ALU Design and Operation ..................................................................................................1 Multiplexer....................................1 Future Work ..................................................1...............................................................................2 Full Adder Design..............1 Literature Review................................79 4........16 2.....................................................................................................................41 3..........................3 ALU Design .............................1 Multiplexer Design ......1 Delay Measurements for 4-Bit ALU.....................................88 CHAPTER 5: CONCLUSION AND FUTURE WORK .......................21 2.....4 Variable Threshold Voltage..........................5 Unit Capacitance...............................101 BIBLIOGRAPHY .........................64 CHAPTER 4: DESIGN ISSUES.............................................15 2...................................................................................109 iv .6 Design Issues .........................................................1.........39 3.39 3.....................................iii LIST OF TABLES.......................................1 Introduction............Table of Contents ACKNOWLEDGEMENTS..................................8 1................................................3 Arithmetic Logic Unit.......................................................3 Multiple-Input Floating Gate CMOS Inverter ...................................................................................................14 CHAPTER 2: MULTI-INPUT FLOATING GATE MOSFET (MIFG MOSFET).....................................................................76 4..............................1...36 CHAPTER 3: THE ALU DESIGN........................................................................vi LIST OF FIGURES ..................xi CHAPTER 1: INTRODUCTION ..............................................................34 2............................................1 1....vii ABSTRACT.........................................................3.............2 MIFG MOSFET Structure and Principle.............................70 4..............108 APPENDIX B: MOSFET MODELS PARAMETERS OF FABRICATED CHIP[35] ...............39 3......................................................................15 2..........70 4...........................................................104 APPENDIX A: MOSFET MODEL PARAMETERS [35]...2 Full Adder ............2 Chapter Organization ...................................27 2............................................... SIMULATIONS AND EXPERIMENTAL DATA ...............................................................................101 5...........

......................116 v .......110 VITA .....................................................................APPENDIX C: SIMULATING FLOATING GATE MOS DEVICE ......................

.............................................................................................................................48 Truth table of a full adder ..........4 4.....5 5..................................100 Comparison of between earlier full adder designs and our design with respect to transistor count.......................51 Truth table generated by inverters 1...................................1 3..........7 Variation in unit capacitance with respect to area and capacitance Note: C’ is the capacitance per unit area .......................................................65 Truth table for the 4-bit ALU...............61 Truth table generated by inverter pair #5 and #6 for OR gate .......1 4.................. 2 and 3 for SUM bit ..................................81 Input patterns for worst-case delay measurements ...............6 3....................................35 Truth table of a 4 to 1 multiplexer .............................................1 3...................7 4.................................................95 Delay measurements for all output bits of ALU for arithmetic and logical operations for post-layout simulated and experimental results..3 3............................4 3.............................................3 4...................................................................1 Number of additional gates and transistors required for different adder configurations[8]..........................................2 4.................75 Truth table for 4-bit ALU .........73 Time period and status of select signals S0 and S1 and value output Vout based on the select signals ..59 Truth table generated by inverter pair #1 and #4 for CARRY bit ...5 3............................................................................69 Truth table of 4 to 1 multiplexer ..........................................2 3...................................List of Tables 1........................1 vi ..................48 Truth table of a 2 to 1 multiplexer ............................................................102 2..

...............10 Transfer characteristics of 3-input floating gate CMOS inverters shown in Fig.18 Multi-input floating gate n-MOSFET ...................................9 with Wp/Wn ratios of 0.......1 2...............................List of Figures 1................................6 2...........................4 1..5 Block diagram of a 4-bit ripple carry adder (RCA).......................4ns..20 Multi-input floating gate p-MOSFET.................4 2....67 and 0............8....................9 A full adder design using six transistors[10] .......5....4µm..............6 Low power CMOS XOR and XNOR gates implemented with 4 transistors[9] ........ 0.............22 Capacitive networks formed for a multi-input floating gate CMOS inverter..5µm CMOS arithmetic logic unit[13]....8 2............28 1........................ 0....5 2....30 2...................................................12 Basic structure of a multi-input floating gate MOSFET..26 Transfer characteristics of a 4-input floating gate CMOS inverter..... respectively .....................4....7 1........8 2................ 2..20 Multi-input floating gate CMOS inverter ..................67 and 0...................................................................................8....................... 2............................................10 Six-transistor CMOS XOR-XNOR gates[12].......1 1... 0..................................3a 2......2 2........17 Terminal voltages and coupling capacitances of a multi-input floating gate MOSFET................. 0............................6 1............4 Block diagram of a 4-bit carry-skip adder (CSA) with skip module.........3b 2...................................23 A 4-input floating gate CMOS inverter ....3 1......9(a-d) 3-input CMOS inverter with Wp/Wn ratios of 0....25 Layout of a 4-input floating gate CMOS inverter Note:The capacitor dimension is 82..................................................4........2 Block diagram of 4-bit carry-lookahead adder (CLA) .................................................31 vii ............................................... 0...........................5 Manchester carry chain for a 4-bit adder .......8µmx18.....................................11 16-bit...............7 2....5................................2 1................

...........................9 3................1Pf ......................................................... W/L ratio of p-MOSFET = 8.............................................................1 3.................10 3...............6 3............................................................60 Full adder design using MIFG CMOS transistors ..............................5 3.......................63 Full adder design using MIFG CMOS transistors for arithmetic and logic operations....................72 2............................................0V Note: W/L ratio of n-MOSFET = 4.................12 Output waveforms for CMOS inverters with capacitor ratio C1/C2 varied from 1 to 4...32 2...................................2 viii ...........68 Layout of a 2 to 1 MUX..............................44 Circuit level diagram of a 2 to 1 multiplexer...............................................................6 CL = 0................................................40 Block diagram of a 4 to 1 multiplexer .......43 Block diagram of a 2 to 1 multiplexer .............................62 OR gate using MIFG CMOS inverters .............1 4.............................................................47 Logic level diagram of a full adder.5V as well as perfect output of 3..........................................................................................45 Block diagram of multiplexer logic at the input stage........38 Block diagram of a 4-bit ALU ............0/1/6 .15 4.....................................7 3.......................13 3......................71 Layout of a 4 to 1 MUX................2.................................................................................2 3........................53 XOR gate using MIFG CMOS inverters to generate SUM bit..............................50 Block diagram of a 4-bit ripple carry adder..............13 3...........................................................................................3 3...................33 Input and output waveforms for a 3-input floating gate CMOS inverter showing degraded output of 2....0/1......................................14 3...............42 Circuit diagram of 4 to 1 multiplexer using pass transistors ............................................55 AND gate using MIFG CMOS inverter to generate CARRY bit ................. 66 Block diagram of a 4-bit ALU ....46 Block diagram of multiplexer logic at the output stage.....4 3..12 3.11 3..................11(a-d) 3-input floating gate CMOS inverter with capacitor C1 varied from 100fF to 400ff......................8 3....................................................

.........................97 Waveforms for EXOR and EXNOR bits showing delay between post-layout simulation and experimental results...............................9 4....14 4.....77 Layout of a full adder.5 4..............17 MIFG CMOS equivalent circuit to realize OR operation..................16 4......83 Full chip layout for a 4-bit ALU Note: Individual building blocks such as FA and inverter are also included .......................................87 Post-layout waveforms for arithmetic operation (SUBTRACTION)...3 4 to 1 MUX output waveforms for all combinations of select signals S0 and S1...........................................89 Post-layout waveforms for arithmetic operation (DECREMENT) .............................19 4...................12 4.................8 4....93 Waveforms for SUM bit showing worst-case delay between post-layout simulation and experimental results..... using MIFG CMOS inverters ...........................................................................................80 Layout of a 4-bit ALU .....18 4.....................................15b 4........6 4....................................................................................................84 Photograph of a fabricated 4-Bit ALU chip.............................................10 4...............................................4 4...........15a Additional logic OR gate in full adder.......................98 Waveforms for OR and AND bits showing delay between post-layout simulation and experimental results...............91 4......................................85 Chip photograph of a fabricated 4-Bit ALU and test devices...............................................86 Post-layout waveforms for arithmetic operation (ADDITION) .........74 Circuit diagram of a full adder with additional OR logic.............................20 ix .................92 4.....................................7 4..... 99 4.......11 4..................................92 Post-layout waveforms for all LOGICAL operations...................................................................................................4.............................................................................90 Post-layout waveforms for arithmetic operation (INCREMENT)......................................................78 Post layout simulated waveforms for the full adder showing SUM and CARRY bits .....96 Waveforms for CARRY bit showing worst-case delay between post-layout simulation and experimental results..........13 4................

.....112 Input and output waveforms of a 4-input floating gate CMOS inverter of Fig..1................. C.......115 x ......C.....................1 C.....................................................2 Simulation model of a multi-input floating gate CMOS inverter ...............................

xi . There are several applications that stress on smaller chip area and reduced power.t transistor count. Implementing a design using multi-input floating gate MOSFETs brings about reduction in transistor count and number of interconnections. A comparison has been made between adders using different design methods w. analog and digital circuits. The design was fabricated using double polysilicon standard CMOS process by MOSIS in 1. uses the least number of transistors when compared to other designs.5µm technology. In the present work we have shown successful implementation of multi-input floating gate MOSFETs in ALU design. Multi-input floating gate devices have their use in memories. This changes the way a logic function can be realized. The experimental waveforms and delay measurements have also been presented. Multi-input floating gate (MIFG) transistors have been promising in realizing increased functionality on a chip. The advantage of bringing down the number of devices is that a design becomes area efficient and power consumption reduces.r. The ALU can perform four arithmetic and four logical operations. calculates the weighted sum of all input signals and then controls the ON and OFF states of the transistor. implemented using multi-input floating gate MOSFETs.Abstract Using the reconfigurable logic of multi-input floating gate MOSFETs. a 4-bit ALU has been designed for 3V operation. A multi-input floating gate MOS transistor accepts multiple inputs signals. This enhances the transistor function to more than just switching. It is seen that our design.

such as. power and speed requirements. many integrated circuits have been reported which are using multi. Furthermore. It has become essential to look into other methods of adding more functionality to a MOS transistor. The delay in an adder is dominated by the carry chain. carry. increased interconnections have limited circuit density on a chip.Chapter 1 Introduction Advancement in VLSI technology has allowed following Moore’s law [1] for doubling component density on a silicon chip after every three years.lookahead adder. The arithmetic logic unit (ALU) is the core of a CPU in a computer. Figure 1.1 shows a 4bit ripple carry adder. The adder cell is the elementary unit of an ALU. Some of the conventional types of adders are ripple-carry adder. Carry chain analysis must consider transistor and wiring delays.input floating gate MOSFETs in standard CMOS process. Carry. Ripple carry adder is an n-bit adder built from full adders. carry-skip adder and Manchester carry chain adder [8]. allowed for designs to be implemented using fewer transistors and reduced interconnections.lookahead adders first compute carry propagate and generate and then computes SUM and CARRY from them. Though MOS transistors have been scaled down. the size of transistor is limited by hot-carrier phenomena and increase in electric field that lead to degradation of device performance and device lifetime [2]. It allows for carry to be computed in 1 .input floating gate MOS transistor structure proposed by Shibata and Ohmi [3]. The constraints the adder has to satisfy are area. In published literature [4-7]. thus. the multiple. An enhancement in the basic function of a transistor has.

2 .A0 B0 A1 B1 A2 B2 A3 B3 CIN FULL ADDER C0 FULL ADDER C1 FULL ADDER C2 FULL ADDER C3 SUM0 SUM1 SUM2 SUM3 Figure 1.1: Block diagram of a 4-bit ripple carry adder (RCA).

Each of the adder configurations may or may not require additional logic apart from full adder design.each bit. The skip module determines whether it could just pass a carry in (C IN) the next four bits for addition or it has to wait until the carry out (C 3 ) propagates through the last full adder in the design. Carry. Layout becomes complex with multiple levels of lookahead. Figure 1. as the values must be routed back to adder from lookahead unit. However. the skip module can make the carry in (C IN) appear to skip through the four full adders. In terms of area efficiency ripple carry adder is preferred. As the node is pre-charged to a HIGH state the carry out remains HIGH.1 shows approximately how many additional gates and transistors are required for each of the adder configurations. Table 1. then both Gi and Pi are LOW. Figure 1. Gi is HIGH and hence the carry out node is discha rged. hence carry out node remains isolated from carry in and ground.2 shows a 4-bit carry. When one of the input bits is ‘1’.lookahead unit requires complex wiring between adders and lookahead unit. When input bits are ‘0’. Figure 1.lookahead adder. the delay time for worst case is more when compared to other adders [8]. Keeping in mind small layout area and less number of interconnections our ALU has been designed using ripple carry configuration. Propagate signal connects adjacent carry bits and Generate signal discharge the carry bit. In essence. The Manchester carry chain adder uses a precharged carry chain with P and G signals. When both bits are ‘1’.4 shows a Manchester carry chain. then Pi is HIGH and carry out follows carry in. 3 . Propagate signal Pi is the XOR of input bits Ai and Bi and generate signal Gi is the NAND of input bits Ai and Bi.3 shows a 4 -bit carry-skip adder and skip module used.

B0 A0 B1 A1 B2 A2 B3 A3 CIN FA G Sum0 CIN P G FA CIN P G FA CIN P G FA CIN P Sum1 Sum2 Sum3 G0 P0 CC 1 3 G1 P1 C2 G2 P2 C3 G3 Carry Generator P3 C4 Cout Figure 1.2: Block diagram of a 4-bit carry. 4 .lookahead adder (CLA).

B0 A0 B1 A1 B2 A2 B3 A3 CIN FA FA FA FA C3 Cout S0 S1 S2 S3 BP= P 3P2P1P0 Skip Module P0 P1 P3 P2 BP' Cout G0 G1 G2 G3 CIN BP Figure 1.3: Block diagram of a 4-bit carry-skip adder (CSA) with skip module. 5 .

6 .VDD ϕ P0 Carry out P1 P2 P3 Carry Carry in Ci G0 G1 G2 G3 ϕ VSS Figure 1.4: Manchester carry chain for a 4-bit adder.

1 Number of additional gates and transistors required for different 4-bit full adders [8] Adder type Additional logic required Ripple carry Carry skip Carry lookahead Manchester chain No additional logic required 10 gates + 6 transistors 16 gates + 18 transistors 1 gate + 23 transistors 7 .Table 1.

In another design of CMOS 1-bit full adder cell. design and simulation issues. The cell offers higher speed and lesser power consumption than standard 1-bit full adder cell.Adder (SERF) using 10 transistors. It uses four transistors for XOR and XNOR gates in CMOS as shown in Fig.1.5. 0. 1. Bui et al [9] have designed a low power 10-transistor full adder called Static Energy-Recovery Full. All units in this design operate in parallel and high speed is achieved. each with their distinct features that bring about optimum area and delay. ALU and full adder circuits have been implemented for optimum area and delay. 1. Radhakrishnan [12] has presented the design of low power CMOS full adder circuits using transmission function theory.8 shows a 16-bit. an overflow detector (OVF) and zero flag detector (ZERO). Past work related to multiple.4ns.input floating gate CMOS applications has been reviewed to give us an idea about its operation. Figure 1. 2. Some of them have been briefly described below to give us an idea of earlier work and shed light on different optimization techniques. The ALU employs a binary look-ahead carry (BLC) adder.7. 1.5µm CMOS ALU design [13]. This design uses six transistor CMOS XOR and XNOR gates as shown in Fig.6. The XOR and XNOR circuits designed by them do not directly connect to power and ground lines. 8 . which consists of a logical and arithmetic unit (LAU). respectively. a magnitude comparator (CMP). four transistor XOR and XNOR gates have been used [11].1 Literature Review In the past. Wang et al [10] have shown an improved version of XOR and XNOR gates that make use of six transistors as shown in Fig. A novel set of XOR and XNOR gates in combination with existing ones have been used.

5: Low power CMOS XOR and XNOR gates implemented with 4 transistors [9]. 9 .A XOR B A B VSS (a) VDD A B A XNOR B (b) Figure 1.

10 .6: A full adder design using six transistors [10].VDD A A XOR B VSS B Figure 1.

11 .7: Six-transistor CMOS XOR-XNOR gates [12].A B VDD (A⊕B) (A⊕B) (A⊕B)' VSS A B Figure 1.

5µm CMOS arithmetic logic unit [13].4ns. 12 . 0.B0-B15 A 0-A 15 ZERO LAU OVF CMP OVERFLOW on/off Multiplexer IN0~IN2 Zf Data out0-Data out15 Figure 1. 2.8: 16-bit.

In the following. 13 . we present the design of a 4-bit ALU for operation at 3. In [16]. a tunable current mirror has been designed where high precision is achieved even with small devices. Harrison et al [15] propose an analog floating memory element for on-chip storage of bias voltages. A floating gate technology has been used to eliminate off-chip biasing voltages in the existing systems by providing these voltages on-chip. The autozeroing floating gate amplifier (AFGA) uses tunneling and pFET hot electron injection to adaptively set its dc operating point. has enabled us to realize the full adder with fewer transistors. we present review of earlier work in the area of multiple. linear amplifiers with rail-to-rail operation with supply voltages less than 1V have been designed in floating gate CMOS.gate circuits is presented in [21]. short-wave ultraviolet light has been applied to floating. No additional circuitry is required. in designing the full adder. In [17].5µm CMOS process.gate devices to adjust threshold voltages for optimal performance in a circuit. when compared to previous designs. In the following chapters.input floating gate transistor. Floating gate MOS circuits have the inherent ability to adapt to the incoming and outgoing signals by continuously enabling various programming mechanisms. In [19]. An example of continuously adapting floating. The application of multi. using multiple-input floating gate MOSFETs in standard 1.gate voltages.input floating gate CMOS devices on which our design of a 4-bit ALU is based [14]. with arrays of programmable floating.0V.gate MOS devices have been used to compute a wide range of translinear functions [18]. that emulate computational and adaptive properties of biological synoptic elements. These arrays can be individually programmed by digital controls. Floating. Based on this property. single floating gate FETs. were developed [20].

input floating gate technology. Appendixes A and B summarize the SPICE MOSFET model parameters. Chapter 5 concludes the work.1. In Appendix C. floating gate MOSFET simulation in SPICE is presented. This chapter also covers the full adder circuit design implemented using multi. postlayout simulations and results are presented in the fourth chapter. The design methodology. its operations and implementation is discussed in chapter 3.input floating gate MOSFETs and inverter. The design of ALU.2 Chapter Organization Chapter 2 explains the structure and operation of multi. technology. 14 .

The output of the transistor is pulled to a ‘HIGH’ or ‘LOW’ state depending on the potential of the floating gate being lesser or greater than the threshold voltage of the device. The multi. The voltage on the gate is the result of the weighted sum of the input voltages. A number of input voltage signals are capacitively coupled to the input gate.input floating gate transistors uses fewer transistors and interconnections resulting in small area consumption.1 Introduction Multi. This leads to only a very negligible amount of charging and discharging currents and results in low power dissipation.Chapter 2 Multi-Input Floating Gate MOSFET (MIFG MOSFET) 2. which are capacitively coupled to the gate. Multi input floating gate MOSFET is defined as a transistor that switches to an ON or OFF state depending on the weighted sum of all input signals applied at its input gate [22]. This weighted sum calculation method of realizing logic functions is also termed as multiple value logic [23] There are certain advantages in using multiple. data converters. analog multipliers.input floating gate MOSFET is basically an enhancement of the basic MOSFET.valued logic for VLSI applications. EPROMs.input floating gate MOSFET operation depends on the weighted sum of voltages at input nodes. and EEPROMs [23-29]. Multiinput floating gate MOSFETs have been used to great advantage in digital and analog VLSI applications including analog filters. 15 . Any given function realized using multi.

At any instant. which is coupled to poly1 gate by capacitors between poly1 and poly2.input floating gate devices to be implemented in double polysilicon CMOS process.2 shows capacitive coupling between the multiple-input gates and floating gate and the channel.2. Cn. Q2 . which are inputs to the transistor. C1 . The basic structure of a multi. 16 . Vn ..2 MIFG MOSFET Structure and Principle The structure of multi. 30]: QF ( t ) = Q 0 + ∑ ( −Qi (t )) = ∑ Ci(Φ F (t ) − Vi( t )) i =1 i= 0 n n (2.1) or QF ( t ) = Φ F (t )∑ Ci − ∑ CiVi (t ) i= 0 i =0 n n (2. …. C2 . Figure 2. Q3 .2) Where n is the number of inputs. A number of control gates. VSS is the substrate voltage.2. C3 . C3 . 2. are formed over the floating gate using a second polysilicon layer (poly 2). V3 . …. The floating gate in the MOSFET extends over the channel and the field oxide. C2 . C0 is the capacitor between the floating gate and substrate. This structure makes it possible for multi. Q0 is the initial charge present on the floating gate. …. Q n are the charges stored in corresponding capacitors C1 .1 [3]. Q1 . In Fig. The corresponding terminal voltages are V1. …. 2. net charge QF(t) on the floating gate is given by the following equations [3. respectively. V2 . are the coupling capacitors between the floating gate and the inputs. Cn .input floating gate MOSFET comprises of the floating gate and number of input gates built on poly2. Qi(t) is the charge present in capacitor Ci and Φ F(t) is the potential at the floating gate.input floating gate MOSFET is presented in Fig.

input floating gate MOSFET. 17 .V1 V2 V3 Vn Input Gates Thin Oxide Floating Gate Gate Oxide n+ p-Si n+ Figure 2.1: Basic structure of a multi.

2: Terminal voltages and coupling capacitances of a multi.V1 V2 V3 Vn C1 C2 C3 Cn Floating Gate C0 V0 Figure 2. 18 .input floating gate MOSFET.

Setting VSS = 0V and applying the law of conservation of charge at the floating gate.2) can be expressed as follows: Φ F (0) ∑ Ci − ∑ CiVi( 0) = Φ F (t ) ∑ Ci − ∑ CiVi(t ). i= 0 i= 0 i =1 i =1 n n n n (2. (2.6) i Switching ON or OFF of the n-MOSFET depends on whether Φ F(t) is greater than or less than the threshold voltage of the transistor.and p-MOSFETs. (2.3(a-b) shows the symbols of multi. The value of Φ F determined by Eq. i =0 i =1 i= 0 i =1 n n n n (2. Eq. (2. 19 . The oxide capacitance C0 is assumed to remain constant. Eq.input floating gate n.5) Assuming zero initial charge on the floating gate in Eq. (2.5) reduces to Φ F (t ) = ∑ C V (t ) i i i =1 n ∑C i= 0 n (2.3) Or Φ F (t ) ∑ Ci − ΦF ( 0)∑ Ci = ∑ CiVi(t ) − ∑ CiVi( 0).6) holds true.2).4) Or Φ F (t ) = ΦF ( 0) + ∑ CiVi (t) − ∑ CiVi (0) i =1 i =1 i n n ∑C i= 0 n (2. Figure 2. as long as all the input capacitive coupling co-efficients remain unchanged during device operation.

Drain Floating Gate Vn V3 V2 V1 Source (a) Drain Floating Gate Vn V3 V2 V1 Substrate Source (b) Figure 2.3: (a) Multi.input floating gate n-MOSFET. 20 . (b) Multi.input floating gate pMOSFET.

Vn × Cn > Vth C1 + C 2 + C 3 + . The switching voltage is computed from the voltage transfer characteristics of a standard CMOS inverter and is given by the following equation [5].….1V and 0. Φ inv = (Φ go + Φ s1) 2 (2.Let us denote Vth as the threshold voltage of the transistor. Then the transistor turns on at the condition Φ F > Vth.5 [31].Vn are input voltages and C1.9) The capacitance network in an n. V 1 × C1 + V 2 × C 2 + V 3 × C 3 + . is greater than or less than the inverter threshold voltage or inverter switching voltage (Φ in ). C2. V1 . V2 .4 [3].C n are corresponding input capacitors.input floating gate CMOS inverter is shown in Fig. The switching of the floating gate CMOS inverter depends on whether Vin obtained from the weighted sum.input floating gate CMOS inverter is Vout = HIGH (3V) if Φ F < Φ inv = LOW (0V) if Φ F > Φ inv (2... C3 .…. Hence. Vin at the floating gate. the output (Vout ) of a multi. and is described by the following equation.8) Where Φ g0 and Φ s1 are the input voltages at which Vout is VDD-0. Weighted sum of all inputs is performed at the gate and is converted into a multiple-valued input voltage. Eq.Cn + Co (2.1V. 2.3 Multiple-Input Floating Gate CMOS Inverter Multiple.. 21 .7) 2. respectively. V3 .. 2.6) is used to determine voltage on the floating gate of the inverter. (2.input floating gate CMOS inverter is shown in Fig.

input floating gate CMOS inverter. 22 .VDD(3V) Vn Cn V3 V2 V1 C3 C2 C1 Vout CL VSS(GND) Figure 2.4: Multi.

23 .Vn Cn Coxp VDD (n-well) Cp V3 V2 V1 C3 C2 Coxn VSS (p-substrate) C1 Figure 2.input floating gate CMOS inverter.5: Capacitive networks formed for a multi.

All four input capacitors’ value was chosen to be 100 fF each.0V...7 shows the layout of a 4.Vn × Cn + VDD × Coxp C1 + C 2 + C3 + ...12) In Fig..6.input CMOS inverter is shown for which a layout was drawn and simulation was done on the extracted SPICE netlist. 24 .Cn + Coxn + Coxp + Cp (2. Coxp is between the floating gate and n-well and is connected to VDD. The switching threshold voltage of the floating gate MOSFET can be estimated from Eq.The gate oxide capacitance of a p-MOSFET. Φ F (t ) = ∑ C V (t) + C i i i =1 n 0 xp VDD (2.. At this point. A transient analysis is performed for the inverter for four different inputs. (2. ΦF = V 1 × C1 + V 2 × C 2 + V 3 × C3 + . The input voltages to the capacitors are pulse waveforms with varying pulse widths and time periods.13) as given below [32].11) Here VSS is taken to be the reference ground potential.input floating gate CMOS inverter.. Equation (2. Coxn is between the floating gate and p-substrate and is connected to VSS. Cp is the capacitance formed between polysilicon floating gate and substrate.6) is modified as follows.11) becomes. we should note the substrate potential so far has been assumed to be zero. a 4. Figure 2. Equation (2..10) ∑C i =0 n i Voltage on the floating gate is given by: ΦF = V 1 × C1 + V 2 × C 2 + V 3 × C 3 + . 2.Vn × Cn + VDD × Coxp + VSS × ( Cp + Coxn) C1 + C 2 + C 3 + .Cn + Coxn + Coxp + Cp (2. But this is not so when it comes to the p-channel MOSFET in the inverter because the n-well is biased to VDD . The maximum pulse voltage of the input waveforms is 3.

input floating gate CMOS inverter.0/1.6 Vout W/L=4.VDD (3V) C1 V1 C2 V2 V3 V4 C3 C4 CL W/L=4.0/1.6 VSS(GND) Figure 2. 25 .6: A 4.

Figure 2.7: Layout of a 4.4µm.8µm x 18. 26 .input floating gate CMOS inverter Note: The capacitor dimension is 82.

4µm. 2. 27 . A 3.0V). In this experiment. Figure 2.input floating gate inverter.Vinv = VDD + WnµnLn / WpµpLpVTn + VTp WnµnLn / WpµpLp + 1 (2. varying the Wp /Wn ratios of the inverter does the adjustment of threshold voltage. This corresponds to the steps seen in the output waveform of Fig. Figure 2. Capacitors C1 and C2 are connected permanently to VDD and VSS.input floating gate CMOS inverter [32]. As the input v oltage changes sequentially the output voltage varies. In multi. The bias voltages. The values for Wp and Wn are calculated as 3. 2. respectively to satisfy Vinv = VDD/2. the values of C1 . we see that the output is a perfect ‘1’ only when all 4 inputs are ‘0’(0V).9(a) shows a 3.8 shows the simulated transfer characteristics of a 4.input floating gate inverter lies in the fact that the switching voltage can be varied by selection of those capacitor values through which the inputs are coupled to the gate.input floating gate CMOS inverter.4 Variable Threshold Voltage The uniqueness of multi. The input capacitors are C1 .0V DC voltage is applied to input capacitor Cin . It follows that the output is a perfect ‘0’ when all 4 inputs are ‘1’(3.8.2µm and 10. Ordinarily. C2 and Cin were initially fixed at 100 fF each. C2 and Cin . VDD and VSS are 3. The mobility ratio for n-MOSFET and p-MOSFET is assumed to be 2. varying the coupling capacitances to the gate can vary the switching point in DC transfer characteristics. respectively.0 V and 0 V. respectively.5µm n-well CMOS process. Considering that we use this inverter for a digital application where the outputs need to be either ‘1’ or ‘0’. The lengths L n and Lp are set to minimum value used in 1.13) The values of VT n and VTp are obtained from SPICE parameters listed in Appendix A.

8: Transfer characteristics of a 4. 28 .input floating gate CMOS inverter.V(G1) t V(G2) t V(G3) t V(G4) t V(OUT) t Figure 2.

input floating gate CMOS inverter.11. 2.12) for multi. 2. the size of capacitor C1 is increased by 100fF progressively.9(a) but the Wp /Wn ratios of the inverters are varied as shown in the figure.10. 2. 2.8). The switching voltages marked on each of the voltage transfer characteristics are calculated from Eq.11. However. From the voltage transfer characteristics of Fig. The change in coupling capacitor ratio C1 /C2 changes the potential φ F on the floating gate. The input voltage given to each of the four circuits is the same. we see that as Wp /Wn ratio of the inverter increases.0/20.9(b-d) are essentially similar to Fig.The Wp /Wn ratio of the MOSFETs of the floating gate CMOS inverter is 8.12 shows the DC voltage transfer characteristics for all four configurations of Fig. 2. we notice that as the capacitor ratio C1 /C2 increases. This can be explained from Eq. A DC analysis was performed using SPICE for all four configurations of Fig. (2. Figures 2.10 shows the voltage transfer characteristics for all four configurations of Fig. From the voltage transfer characteristics. The output switches its state at different input voltages just as it would if the Wp /Wn ratio were to be varied. the switching voltage moves to the left. This can be explained by the shift in transfer characteristics to right as Wp /Wn ratio decreases [33].9.0. (2. 2. Figure 2.0/16. The switching voltage on each of the voltage transfer characteristics is marked. 2. where the Wp /Wn ratio is maintained constant at 8. Figure 2. the output waveform shifts in to the right. We repeat the simulation for another set of inverters shown in Fig.9. The same input voltage as in Fig.9 is applied to the circuits. 29 .

6 Vin Cin 100ff Vout Vin Cin 100ff Vout C2 W/L=20.0/1. respectively.0/1.4.9(a-d): 3.6 100ff CL C2 100ff W/L=10.6 100ff 100ff VDD(3V) C1 W/L=8.6 Vin Cin 100ff Vout Vin Cin 100ff Vout C2 W/L=12.0/1.0/1.0/1.6 100ff 100ff VDD(3V) C1 W/L=8.0/1. 0.VDD(3V) C1 W/L=8.6 CL VSS(GND) VSS(GND) Figure 2.0/1.6 100ff CL C2 100ff W/L=16.67 and 0.0/1. 0.8 . 30 .input CMOS inverter with Wp /Wn ratios of 0.6 CL VSS(GND) VSS(GND) (a ) (b) VDD(3V) C1 W/L=8.5.

8. 0.Figure 2.4. 0.10: Transfer characteristics of 3.67 and 0. 2.5. 31 .input floating gate CMOS inverters shown in Fig.9 with Wp /Wn ratios of 0.

11(a-d): 3. 32 .VDD (3V) C1 W/L=8.0/1.6 100ff 200ff VDD (3V) C1 W/L=8.6 CL VSS(GND) VSS(GND) (c) (d) Figure 2.0/1.6 Vin Cin 100ff Vout Vin Cin 100ff Vout C2 W/L=16.6 100ff CL C2 100ff W/L=16.input floating gate CMOS inverter with capacitor C1 varied from 100fF to 400fF.6 Vin Cin 100ff Vout Vin Cin 100ff Vout C2 W/L=16.0/1.0/1.6 CL VSS(GND) (a) VSS(GND) b) VDD (3V) C1 W/L=8.6 300ff 400ff VDD (3V) C1 W/L=8.6 100ff CL C2 100ff W/L=16.0/1.0/1.0/1.0/1.

12: Output waveforms for CMOS inve rters with capacitor ratio C1 /C2 varied from 1 to 4.Figure 2. 33 .

2.32 × 100 = 76% 9. The percentage variation in capacitance from desired value and the worst-case scenario of edges being reduced by 1µm is calculated.5 × 100 = 27% 501 . This table also includes the capacitor values in case of edges being shortened by 0. The key factor in designing capacitor values for multi.5µm standard CMOS process [35] varies from 580aF/µm2 to 620aF/µm2 for different runs. The rest of the capacitors in the circuits are either unit value or integral multiples of it.28 ×100 = 57% 21. Due to fabrication process variations in runs employed.5µm and 1.536 − 2. Since we do not have prior knowledge of which run would be used in fabrication of our chip an average value has been used.input floating gate designs is to start with a unit capacitance value [34]. The area capacitance parameter between poly1 and poly2 layers in 1.724 − 70.456 100.456 − 9.5 Unit Capacitance The floating gate CMOS circuit design layout faces certain shortcomings in fabrication process.0µm. designed capacitors may not turn out to be of right values. %change = 34 .724 501.236 For 20fF %change = For 100fF %change = For 500fF .536 21. Some of the floating gate designs are sensitive to capacitor changes and this may change the output values.236 − 364. Table 2. In our design we have used 596aF/µm2 .18 ×100 = 30% 100. For 10fF %change = 9.1 shows the minimum and maximum capacitance values obtained considering variations in area capacitance parameter.

72fF 364.920 fF 104.280 fF 75.28fF 98.220fF 2.456 fF 14.020 fF 521.384 fF 21.280fF 5.1.5fF C’ 596 aF/µm2 9.116 fF 501.180fF 487.080 fF 451.320 fF 15.9 fF 9.364 fF 2.236 fF 467.5 fF 9.5fF 9.980 fF 10 fF 3µx 3µ 2µx 2µ 6µx 6µ 20fF 5µx 5µ 3µx 3µ 13 µ x 13 µ 100fF 12 µ x 12 µ 11 µ x 11 µ 29 µ x 29 µ 500fF 28 µ x 28 µ 27 µ x 27 µ 35 .Table 2.420 fF 486.780 fF 89.320fF 20.020fF 83.824 fF 72.920 fF 5.484 fF C’ 620 aF/µm2 9.724 fF 85.536 fF 100.264 fF 434.78fF 454.Variation in unit capacitance with respect to area and capacitance Note: C’ is the capacitance per unit area Unit Capacitance Area Required 4µx 4µ C’ 580 aF/µm2 9.880fF 14.580 fF 2.480 fF 22.520fF 70.536 fF 5.

2. as shown below.From the above calculation. due to fabrication process.6 Design Issues An important factor affecting the accuracy of inversion threshold voltage is the presence of residual charge on floating gate after fabrication processes. To maintain the percentage change in capacitor value.(2. within 30% we need to use a unit capacitance value of atleast 500 fF. is calculated using Eq. With such UV irradiation technique. such residual charges can be reduced by exposure to ultraviolet light irradiation.12). 28]. ΦF = 500 × 3 + 500 × 3 + 500 × 3 =2. φ F. greater the unit capacitance value when compared to gate capacitance value. Consider a multi. it has been shown that initially fluctuating voltage converges to one final steady value [18. The probability of the functionality being affected reduces significantly in this case. The residual charge alters QF. ΦF = 500 × 0 + 500 × 0 + 500 × 0 =0V 1500 + 30 36 . When all three input are at logic ‘HIGH’ (3 V) and all three inputs are at logic ‘LOW’ (0V) then the voltage on the floating gate.9V 1500 + 30 where Cox is approximated to 30ff. lesser is the variation. However. Floating gate CMOS inverter gives a degraded output level when inputs are not uniform.input floating gate CMOS inverter with three inputs with coupling capacitances of 500fF each. it is seen that. This may vary from device to device also causing inaccuracies in output logic levels desired. the charge on floating gate that is responsible for fixing the inversion threshold voltage.

VC1 .96V 1500 + 30 500 × 0 + 500 × 0 + 500 × 3 =0. From Fig.input floating gate CMOS circuits are different from a standard CMOS inverter.3V 1500 + 30 = In these cases described above. Simulation techniques used for multi. 36]. Figure 2. Simulation using SPICE gives the problem of DC convergence. To overcome the problem different approaches have been explained in [6. We have used the method suggested by Yin et al [6].13 we see that when all three inputs are at ‘0’ the output voltage swings between 0V and 3V.When one of the inputs is logic ‘HIGH’ or two of the inputs are ‘HIGH’ then the voltage on floating gate is calculated as follows. It views the capacitors as open circuits initially and stops the simulation run.13 shows simulated waveforms for the above mentioned inverter. ΦF ΦF = 500 × 3 + 500 × 3 + 500 × 0 =1. but when one of the inputs is logic ‘HIGH’ or two of the inputs is ‘HIGH’ the output voltage swing is between 0V and 2. which is described in Appendix C. In such a case the output needs to be buffered to give complete swing.5V. 2. 7. the output does not swing completely between 3 V and 0V as all inputs do not have the same logic level. VC2 and VC3 are the input waveforms and VOUT is the output waveform. 37 . These techniques employ additional use of resistors and voltage controlled voltage sources (VCVS) for specifying the initial floating gate voltage.

1pF.0/1. Note: W/L ratio of the n-MOSFET = 4.0V. 38 .5V as well as perfect output of 3. Input and output waveforms for a 3-input floating gate CMOS inverter showing degraded output of 2.13. CL = 0.Figure 2.0/1.6. W/L of p-MOSFET = 8.6.

the full adder design has been implemented using MIFG CMOS inverters.0 V operation in which. The ALU has four stages. 37]. The input and output sections consist of 4 to 1 and 2 to 1 multiplexers. the ALU design consisting of eight 4 to 1 multiplexers. eight 2 to 1 multiplexers and four full adders.1 Multiplexer Design The multiplexers have been used in the ALU design for input and output signals selection. The 4-bit ALU was designed in 1. The multiplexer is implemented using pass transistors [33. In Fig. AND and OR. A set of three select signals has been incorporated in the design to determine the operation being performed and the inputs and outputs being selected.1 shows the 4-bit ALU with the CARRY bit cascading all the way from first stage to fourth stage. The four logical operations performed are EXOR.5µm. EXNOR. This design is 39 . The multiplexers were designed using the pass transistor logic. Figure 3. ADD. All of the multiplexers have been implemented using pass transistors. This chapter explains in detail the 4-bit ALU design. The ALU performs the following four arithmetic operations.1. INCREMENT and DECREMENT.1. 3. each stage consisting of three parts: a) input multiplexers b) full adder and c) output multiplexers.1 The ALU Design and Operation A 4-bit ALU has been designed for 3.Chapter 3 The ALU Design 3. and the full adder alone has been designed using MIFG CMOS logic. n-well CMOS technology. 3. SUBTRACT. Each stage is discussed in detail in the further sections of this chapter.

40 .S0 Logic 1 B0 B0' Logic 0 A0 S0 Logic 1 B1 B1' Logic 0 A1 S0 Logic 1 B2 B2' Logic 0 A2 S0 Logic 1 B3 B3' Logic 0 A3 S1 B0 S2 CIN SUM0 S0 S1 4:1 MUX 2:1 MUX AND0 EXOR0 FULL ADDER EXNOR0 OR0 4:1 MUX 2:1 MUX OUT0 S1 B1 S2 C0 SUM1 AND1 EXOR1 FULL ADDER EXNOR1 OR1 C1 S0 S1 4:1 MUX 2:1 MUX 4:1 MUX 2:1 MUX OUT1 S1 B2 S2 SUM2 AND2 EXOR2 FULL ADDER EXNOR2 OR2 C2 SUM3 AND3 EXOR3 FULL ADDER EXNOR3 OR3 C3 S0 S1 4:1 MUX 2:1 MUX 4:1 MUX 2:1 MUX OUT2 S1 B3 S2 S0 S1 4:1 MUX 2:1 MUX 4:1 MUX 2:1 MUX OUT3 Figure 3.1: Block diagram of a 4-bit ALU.

The input and the output stages have a combination of 2 to 1 multiplexer and 4 to 1 multiplexer to select one signal from a set of four signals.1. For S2 = 0. The select signals are S0 . The select signals S0 and S1 pick one of the four inputs or output signals and hence determine which of the four arithmetic or logical operations should be performed. The full adder performs the computing function of the ALU. The input and select signals have been named as IN n and Sn respectively.3 shows the circuit level diagram of the 4 to 1 MUX. with the subscript n indicating the correct signal number. one of the four arithmetic operations is performed and for S2 = 1.5 shows the circuit level diagram of the 2 to 1 MUX.2 shows the truth table for 2 to 1 MUX. S1 and S2 . 3. Table 3.1 shows the truth table for 4 to 1 MUX and Table 3. 3. 41 . 3. The output of the multiplexer stage is passed as input to the full adder. Figure 3. full adder forms the core of the entire design.2 Full Adder Design In ALU. Figure 3. Figures 3. The pass transistor design reduces the parasitic capacitances and results in fast circuits. Signal S2 determines if the operation being performed is arithmetic or logical. one of the four logical operations is performed. There are two kinds of multiplexers implemented: 2 to 1 multiplexer and 4 to 1 multiplexer.7 show how this logic has been implemented at input and output stage.6 and 3. respectively.4 shows the block diagram of a 2 to 1 MUX and Fig.2 shows the block diagram of a 4 to 1 MUX and Fig.simple and efficient in terms of area and timing. A combination of the 2 to 1 MUX and 4 to 1 MUX at the input and output stage selects the signals depending on the operation being performed. Transmission gates select one of the inputs based on the value of the control signal.

2: Block diagram of a 4 to 1 multiplexer. 42 .S0 S1 IN0 IN1 IN2 IN3 4 to 1 MUX OUT Figure 3.

0/1.6) IN1 (4.0/1.0/1. 43 .6/1.0/1.6) (9.S0 S 0' S1 S 1' (9.6) IN3 OUT (9.0/1.6) (9.6) (9.0/1.6) (9.6) (4.6) Figure 3.6/1.6) (4.6) (4.6) IN0 (4.6) (4.6/1.6) (9.6/1.0/1.6) (9.6/1.6) (4.6/1.3: Circuit diagram of 4 to 1 multiplexer using pass transistors.6) IN2 (4.0/1.6/1.6/1.

44 .S2 IN1 IN0 2 to 1 MUX OUT Figure 3.4: Block diagram of a 2 to 1 multiplexer.

6) S2' Figure 3.6) S2 Vout IN1 (9.0/1.0/1.5: Circuit level diagram of a 2 to 1 multiplexer.6) (4.6/1. 45 .S2' IN0 (9.6) (4.6/1.

46 .6: Block diagram of multiplexer logic at the input stage.S0 S1 B S2 VDD VSS B' B To Full Adder 4 to 1 MUX 2 to 1 MUX Figure 3.

S0 S1 SUM S2 EXOR EXNOR AND OR 4 to 1 MUX 2 to 1 MUX OUTPUT Figure 3. 47 .7: Block diagram of multiplexer logic at the output stage.

1 Truth table of a 4 to 1 multiplexer Select signal S1 Select signal S2 Selected input 0 0 1 1 0 1 0 1 IN 0 IN 1 IN 2 IN 3 Table 3.2 Truth table of a 2 to 1 multiplexer Select signal S2 Operation performed 0 1 Arithmetic Logical 48 .Table 3.

SUM = A ⊕ B ⊕ CIN CARRY = A • B + A • CIN + B • CIN (3. Figure 3. In RCA. the CARRY bit ripples all the way from first stage to nth stage. The outputs are SUM and CARRY. The Boolean expressions for the SUM and CARRY bits are as shown below. We ha ve used this ripple carry adder (RCA) configuration in our ALU design. This is in effect deleting the CARRY. In our design. B and CIN. Figure 3. The truth table also indicates the status of the CARRY bit. that is to say. then the previous carry is just propagated. It consists of three inputs and two outputs. The third input CIN represents carry input to the first stage. To construct an n -bit adder we have to cascade n such 1-bit adders.8 shows the logic level diagram of a full adder.1) (3. Depending on the status of input bits A and B. The delay in a RCA depends on the number of stages cascaded and also the input bits’ patterns. as the sum of A and B is ‘1’.9 shows the block diagram of a four-bit ripple carry adder. The truth table of a full adder is shown in Table 3. If both A and B are ‘1’s then carry is generated because summing A and B would make output SUM ‘0’ and CARRY ‘1’. If both A and B are ‘0’s then summing A and B would give us ‘0’ and any previous carry is added to this SUM making CARRY bit ‘0’. 49 .3. the CARRY bit is either generated or deleted or propagated [8]. If either one of A or B inputs is ‘1’.2) SUM bit is the EXOR function of all three inputs and CARRY bit is the AND function of the three inputs. we have designated the three inputs as A. if that carry bit has been generated or deleted or propagated.A full adder could be defined as a combinational circuit that forms the arithmetic sum of three input bits [38].

An Bn CIN SUM CARRY Figure 3.8: Logic level diagram of a full adder. 50 .

3 Truth table of a full adder A 0 0 0 0 1 1 1 1 B CIN SUM CARRY Carry Status 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 Delete Delete Propagate Propagate Propagate Propagate Generate Generate 51 .Table 3.

In a ripple carry adder. This way the CARRY bit need not ripple through the stages. On the other hand.For certain input patterns. This effectively reduces the delay in the circuit. is defined as worst-case delay over all possible input patterns. the worst-case delay occurs when a carry bit propagates all the way from least significant bit position to most significant bit position. 38]. The full adder constructed from MIFG devices uses only eight transistors. Tadder = (N-1) Tcarry + Tsum (3. a CARRY is neither generated nor propagated. In our design. The total delay of the adder would be an addition of delay of a SUM bit and delay of a CARRY bit multiplied by number of bits minus one in the input word. 52 .3) Where N is number of bits in input word. The logic function of XOR gate can be realized using MIFG CMOS transistors. required for generating the SUM output of the full adder. The unit size capacitance is 500 fF and other capacitors are integral multiples of the unit size capacitor. we have implemented the full adder design using MIFG CMOS devices. Essentially the SUM bit of a full adder involves building of XOR gates to realize its function and similarly CARRY bit needs AND gates to realize its Boolean expression.3) [37. Figure 3. Tcarry and Tsum are propagation delays from one stage to another. also called critical path. (3. The propagation delay of such a case. which might have to ripple through all the stages. This definitely increases the delay in the circuit. it is important to reduce Tcarry than Tsum as the former influences the total adder delay more. four MIFG transistors and four conventional transistors. certain input patterns generate carry bit in the first stage itself. For an efficient ripple carry adder.10 shows the XOR logic in MIFG CMOS. given by Eq.

A0

B0

A1

B1

A2

B2

A3

B3

Cin

FULL ADDER

C0 FULL ADDER

C1 FULL ADDER

C2 FULL ADDER

C3

SUM0

SUM1

SUM2

SUM3

Figure 3.9: Block diagram of a 4-bit ripple carry adder.

53

Inverters #1 and #2 are MIFG CMOS inverters and inverter #3 is a standard inverter required to complement the output from the MIFG inverters #1 and #2. The inputs to the first MIFG inverter are A, B and CIN. MIFG CMOS inverter #1 acts as the pre-gate input to inverter #2. The voltage on the floating gate of inverter #1 is determined by the following equation,

ΦF =

C(V A + VB + VCIN ) 3C + C 0 + Cp

(3.4)

Where VA, VB and VC are input voltages. C is the coupling capacitance for each input and C0 is the gate oxide capacitance and Cp is the parasitic capacitance. From extracted netlists of trial designs, we approximated the sum of gate oxide and parasitic capacitances to be nearly 250 fF. According to the principle of operation of the MIFG CMOS inverter, the output of inverter #1, V1 , changes state when Φ F goes above the threshold value of the device. The threshold voltage, Vth is approximately taken as 1.0V for n -MOSFET. Equations (3.5-3.8) show the calculation of Φ F for three exclusive combinations of inputs A, B and CIN using Eq. (3.4). The input voltage signals are set at 3V for logic ‘1’ and 0V for logic ‘0’.

ΦF = 500 × ( 0 + 0 + 0 ) + 500 × 0 =0V 3 × 500 + 250

(3.5)

so Φ F < Vth . Hence V1 is HIGH (logic ‘1’).

ΦF =

500 × ( 0 + 0 + 3 ) + 500 × 0 =0.85V 3 × 500 + 250

(3.6)

so Φ F < Vth . Hence V1 is HIGH (logic ‘1’).

54

VDD(3V)

500ff

#1

(13.6/1.6)

500ff 500ff 500ff

#2

(13.6/1.6)

VA VB VCIN

500ff 500ff

Inverter #3

W/L W/L

(n-MOSFET ) = (p-MOSFET ) =

8.8/1.6 10.4/1.6

V1 1000ff

(8.4/1.6) (19.6/1.6)

SUM

VSS(GND)

Figure 3.10: XOR gate using MIFG CMOS inverters to generate SUM bit.

55

5-3. The value of Φ F for the inverter #2 is computed by the following equation. ΦF = 500 × ( 3 + 3 + 3 ) + 500 × 0 =2.9) The output of MIFG inverter #2 should go LOW (logic ‘0’) only when odd number of inputs is HIGH (logic ‘1’) to realize an XOR function.10-3.10) so Φ F < Vth . however.ΦF = 500 × ( 0 + 3 + 3 ) + 500 × 0 =1.8) so Φ F > Vth . FF = 500 × ( 0 + 0 + 0 + 2 ×1. The output. Hence V1 is LOW (logic ‘0’).7V 3 × 500 + 250 (3. B.6V 5 × 500 + 550 (3. This has been addressed as one of the design issues in the second chapter.9V. Hence SUM is LOW (logic ‘0’). 56 .9.5V 3 × 500 + 250 (3. using equation 3. the value of Φ F is calculated for exclusive combinations of inputs A. (3. V1 is the input for MIFG inverter #2 along with inputs are A. We set the weight of coupling capacitor for input V to 2C in the second stage. It is degraded to around 1. The output V1 .8). B and CIN .13) below. Hence V1 is LOW (logic ‘0’).9 ) =0. pages 37-39. Substituting the values for voltage V1 from Eqs. is not completely pulled up to VDD (3V). This is shown in Eqs. The calculations are shown as follows. This allows for the floating 1 gate voltage Φ F of MIFG inverter #2 to be pulled LOW (logic ‘0’) even when just one of the inputs is HIGH (logic ‘1’). FF = C × VA + C × VB + C × VCIN + 2CV 1 5C + C 0 + Cp (3. Cin .7) so Φ F > Vth . Hence weight of capacitor coupling V1 to MIFG inverter #2 should be decided accordingly. (3.

for each of the inputs bits’ combination.10V 5 × 500 + 550 (3.14) and hence the status of output CARRY ΦF = 500 × ( 0 + 0 + 0 ) =0V 3 × 500 + 250 (3.9 ) =1.17) show the calculation of Φ F for three exclusive combinations of inputs are A.14) Equations (3. Hence SUM is LOW (logic ‘0’). (3. ΦF = C(V A + VB + VCIN ) 3C + C 0 + Cp (3. The inputs to the MIFG inverter are A.11 is a unit size capacitance of 500ff. B and CIN .FF = 500 × ( 0 + 0 + 3 + 2 × 1.4 gives the truth table for the SUM bit from Fig.15) so Φ F < Vth .11) so Φ F > Vth .5V 6 × 500 + 550 (3.12) so Φ F < Vth . Table 3. 3. Each input capacitor in Fig.13) so Φ F > Vth . FF = 500 × ( 0 + 3 + 3 + 2 × 0 ) =0.11 shows the AND logic required for generating the CARRY output of the full adder. Hence SUM is HIGH (logic ‘1’).10 and also shows the value of Φ F compared to threshold voltage. The voltage on the floating gate of inverter #1 is determined by the following equation. Vth .98V 5 × 500 + 550 (3. 57 . FF = 500 × ( 3 + 3 + 3 + 2 × 0 ) =1. Figure 3. Hence SUM is HIGH (logic ‘1’). Hence CARRY is LOW (logic ‘0’). 3. using Eq. Inverter #1 is a MIFG CMOS inverter and inverter #4 is a standard inverter required to complement the output from the MIFG inverter.15-3. B and CIN.

input OR function. 3.12. Table 3.13. ΦF = 500 × ( 3 + 3 + 3) =2.7V 3 × 500 + 250 (3. 3. Figure 3. 3.13 shows the additional circuit needed to realize a 2. ΦF = 500 × ( 0 + 3 + 3 ) =1. In the design of OR gate. Hence CARRY is HIGH (logic ‘1’). This is done by adding a unit capacitor which is connected permanently to VDD . Hence CARRY is LOW (logic ‘0’).5V 3 × 500 + 250 (3. To realize a 2. To realize this design with given MOSFET parameters. we see the need to precharge the floating gate to a certain voltage level.85V 3 × 500 + 250 (3. This table is similar to the truth table of an OR gate.11 for the CARRY bit.17) so Φ F > Vth .19) Voltage on floating gate of inverter #5 goes above threshold voltage whenever one of the input bits goes HIGH.18) so Φ F > Vth . the voltage on the floating gate of inverter #5 is determined by the equation. Inverter #6 complements the output of the MIFG inverter #5 to perform OR operation on inputs A and B. In Fig. 58 . Hence CARRY is HIGH (logic ‘1’).5 shows the truth table generated by inverter pair #1 and #4 from Fig. The combined logic for SUM and CARRY forming a complete full adder design is shown in Fig. The value of Φ F is compared with threshold voltage Vth .input OR gate. additional circuitry using MIFG MOSFETs is added to the full adder circuit. we need the floating gate voltage Φ F to go higher than threshold voltage whenever at least one input goes HIGH.16) so Φ F < Vth .ΦF = 500 × ( 0 + 0 + 3 ) =0. FF = C(VA + VB) + C × VDD 3C + C 0 + Cp (3.

1 > Vth Φ F = 0.4 Truth table generated by inverters 1.1 > Vth Φ F = 0.98 < Vth Φ F = 0.98 < Vth Φ F = 1.98 < Vth Φ F = 0.5 > Vth Sum-bit: inverter #3 output 0 1 1 0 1 0 0 1 59 . 2 and 3 for SUM bit VA 0 0 0 0 1 1 1 1 VB 0 0 1 1 0 0 1 1 VCIN 0 1 0 1 0 1 0 1 V1 1 1 1 0 1 0 0 0 ΦF Vth Φ F = 0.Table 3.98 < Vth Φ F = 1.6 < Vth Φ F = 1.

6 CARRY (8.8/1.11: AND gate using MIFG CMOS inverter to generate CARRY bit.4/1. 60 .4/1.6) Inverter #4 W/L (n-MOSFET) = 8.6) VSS(GND) Figure 3.VDD(3V) #1 VA VB VCIN 500ff 500ff 500ff (13.6/1.6 W/L (p-MOSFET) = 10.

Table 3.85 < Vth Φ F = 085 < Vth Φ F =1. VA 0 0 0 0 1 1 1 1 VB 0 0 1 1 0 0 1 1 VCIN 0 1 0 1 0 1 0 1 V1 1 1 1 0 1 0 0 0 ΦF Vth Φ F = 0 < Vth Φ F = 0.7 > Vth Φ F = 0.5 Truth table generated by inverters #1 and #4 for CARRY bit.7 > Vth Φ F = 1.5 > Vth Carry-bit: inverter #4 output 0 1 1 0 1 0 0 1 61 .85 < Vth Φ F = 1.7 > Vth Φ F = 2.

6 W/L (p-MOSFET ) = 10.6) Inverter #3 W/L (n-MOSFET ) = 8.VDD(3V) #1 (13.6 VSS(GND) Figure 3.12: Full adder design using MIFG CMOS transistors.4/1.6) VA VB VCIN 500ff 500ff 500ff 500ff 500ff 500ff 1000ff (8.6 W/L (p-MOSFET ) = 10.6 SUM CARRY (19.8/1.6) Inverter #4 W/L (n-MOSFET ) = 8.8/1.6/1. 62 .6) #2 (13.4/1.6/1.6/1.4/1.

6/1.6) VSS(GND) Figure 3.VDD(3V) #5 VA VB VDD(3V) 500ff 500ff 500ff (13.6 W/L (p-MOSFET) = 10. 63 .8/1.13: OR gate using MIFG CMOS inverters.6 A OR B (8.6) Inverter #6 W/L (n-MOSFET) = 8.4/1.4/1.

Each stage of the ALU has five inputs given to it. Table 3. 3. Hence OR bit is HIGH (logic ‘1’).20-3.8VV 3 × 500 + 200 (3. for all exclusive combinations of inputs A and B.15 shows the block diagram of the ALU for all four stages.6V 3 × 500 + 200 (3.19).8V 3 × 500 + 200 (3.14. FF = 500 × ( 3 + 3) + 500 × 3 =2. Logic ‘1’. B and complement of B (B’).20) so Φ F < Vth . Figure 3. ADD.21) so Φ F > Vth . Logic ‘1’ and Logic ‘0’ are realized by tying 64 . Hence OR bit is HIGH (logic ‘1’). AND and OR. Hence OR bit is LOW (logic ‘0’).6 shows how the output bit is obtained by variation of Φ F for different combinations of input bits and comparison of Φ F with threshold voltage Vth . Φ F pulls the output of the MIFG inverter to LOW. EXOR. So even if one input goes HIGH.This makes the floating gate of inverter #5 sensitive to small changes in voltage on it. (3. SUBTRACT. This circuit put together performs four arithmetic functions.3 ALU Design Each stage of the 4-bit ALU is comprised of the full adder block and the multiplexer block at the input and output stages.22) show the calculations for OR output bit using Eq. The full adder design along with the additional OR gate logic comprises of twelve transistors as shown in Fig. EXNOR. 3. Equations (3. FF = 500 × ( 0 + 0) + 500 × 3 =0. FF = 500 × ( 0 + 3) + 500 × 3 =1. INCREMENT and DECREMENT and four logical operations.20) so Φ F > Vth .1. Logic ‘0’. A.

6 > Vth OR output: inverter #6 output 0 1 1 1 65 .8 < Vth = 1.8 > Vth = 1.Table 3.8 > Vth = 2.6 Truth table generated by inverter pair #5 and #6 for the OR gate VA 0 0 1 1 VB 0 1 0 1 ΦF ΦF ΦF ΦF ΦF Vth = 0.

VDD(3V)

#1 (13.6/1.6) VA VB VCIN

500ff 500ff 500ff 500ff 500ff 500ff 1000ff (8.4/1.6)

#2

(13.6/1.6) Inverter #3 W/L (n-MOSFET) = 8.8/1.6 W/L (p-MOSFET) = 10.4/1.6

SUM CARRY

(19.6/1.6) Inverter #4 W/L (n-MOSFET) = 8.8/1.6 W/L (p-MOSFET) = 10.4/1.6

VDD(3V)

VSS(GND) #5

500ff 500ff (13.6/1.6) Inverter #6 W/L (n-MOSFET) = 8.8/1.6 W/L (p-MOSFET) = 10.4/1.6 A OR B (8.4/1.6)

VDD(3V)

500ff

VSS (GND)

Figure 3.14: Full adder design using MIFG CMOS transistors for arithmetic and logic operations.

66

the inputs to VDD and VSS, respectively in Fig. 3.15. The inputs, Logic ‘1’ and Logic ‘0’ are used for the INCREMENT and DECREMENT operations respectively. The complement of B is used for SUBTRACTION operation. The full adder performs the SUBTRACT operation by two’s complement method. An INCREMENT operation is analyzed as adding a ‘1’ to the addend and DECREMENT is seen as a subtraction operation. The outputs from the full adder are SUM, EXOR, EXNOR, AND and OR. Based on the condition of the select signals, the multiplexer stage selects the appropriate inputs and gives it to the full adder. The full adder computes the results. The multiplexer at the output stage selects the appropriate output and sends it out. Table 3.7 shows the truth table for the operations performed by the ALU based on the status of the select signals.

67

S0 Logic 1 B0 B0' Logic 0 A0 S0 Logic 1 B1 B1' Logic 0 A1 S0 Logic 1 B2 B2' Logic 0 A2 S0 Logic 1 B3 B3' Logic 0 A3

S1

B0

S2

CIN

SUM0

S0

S1

4:1 MUX

2:1 MUX

AND0 EXOR0 FULL ADDER EXNOR0 OR0

4:1 MUX

2:1 MUX

OUT0

S1

B1

S2

C0 SUM1 AND1 EXOR1 FULL ADDER EXNOR1 OR1 C1

S0

S1

4:1 MUX

2:1 MUX

4:1 MUX

2:1 MUX

OUT1

S1

B2

S2

SUM2 AND2 EXOR2 FULL ADDER EXNOR2 OR2 C2 SUM3 AND3 EXOR3 FULL ADDER EXNOR3 OR3 C3

S0

S1

4:1 MUX

2:1 MUX

4:1 MUX

2:1 MUX

OUT2

S1

B3

S2

S0

S1

4:1 MUX

2:1 MUX

4:1 MUX

2:1 MUX

OUT3

Figure 3.15: Block diagram of a 4-bit ALU.

68

Table 3.7 Truth table for the 4-bit ALU. S2 0 0 0 0 1 1 1 1 S1 S0 Operation performed 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 INCREMENT DECREMENT ADDITION SUBTRATION AND OR EXOR EXNOR 69 .

The MUX output. IN 0 is an input pulse of period 200ns. The width of PMOS transistors in multiplexers have been increased to reduce rise and fall times.6. The SPICE level 3 MOS model parameters was used for prelayout and post. IN 1 is a constant voltage of 3V. IN2 and IN 3 . 70 .1 Multiplexer The PMOS transistors in 4:1 multiplexer and 2:1 multiplexer have been designed with a W/L ratio of 9. In this figure. The 4 to 1 MUX designed was simulated by testing it for various combinations of select signals shown in Fig. 4.2 shows the layout of a 4 to 1 MUX.1 shows the layout of a 2 to 1 MUX. Figure 4.Chapter 4 Design Issues. Figure 4. IN 1 . The level 3 MOS model parameters are listed in Appendix A.03 tool in standard 1.1. IN 2 is complement of pulse IN 0 and IN 3 is a constant voltage of 0V.6 and NMOS transistors with a W/L ratio of 4.3. Table 4.0/1. Simulations and Experimental Data This chapter discusses the simulation and design issues associated with our ALU.6/1. V based on the select signals. The design is simulated using MicroSim Pspice tool.layout simulations.5µm CMOS technology. 4. The 4-bit ALU is designed using Tanner L-Edit 8. the out output waveform Vout follows one of the four inputs depending on status of select signals S0 and S1.2 shows time period and status of select signals S0 and S1 and output. depending on the status of select signals S0 and S1 is tabulated in Table 4. The experimental data has also been presented. selected from inputs IN 0 .

1: Layout of a 2 to 1 MUX.Figure 4. 71 .

72 .Figure 4.2: Layout of a 4 to 1 MUX.

1 Truth table of a 4 to 1 multiplexer Select signal S1 Select signal S2 Selected input 0 0 1 1 0 1 0 1 IN 0 IN 1 IN 2 IN 3 73 .Table 4.

74 .3: 4 to 1 MUX output waveforms for all combinations of select signals S0 and S1 .3V S0 0V 3V S1 0V t 3V IN0 0V t 3V IN1 0V 3V IN2 0V 3V IN3 0V 3V Vout 0V t 0ns 50ns 100ns 150ns TIME 200ns 250ns 300ns 350ns t t t t Figure 4.

Table 4.2 Time period and status of select signals S0 and S1 and value output Vout based on the select signals Time duration Select signals status Output of MUX 0-100ns 100-200ns 200-300ns 300-400ns S 0 = 1 S1 = 1 S 0 = 1 S1 = 0 S 0 = 0 S1 = 1 S 0 = 0 S1 = 0 Vout = IN3 (‘0’) Vout = IN2 (‘1’) Vout = IN1 (‘1’) Vout = IN0 (‘0’) 75 .

the SUM and CARRY bit waveforms have slow rise and fall times.4.4. When MIFG inverter #1 and #2 are cascaded. The inputs are coupled capacitively to the MIFG inverters. It is therefore necessary to resize the transistors by increasing their W/L ratios. In the cascaded stage. The layout of the full adder is shown in Fig. MIFG inverter #2 has a large parasitic capacitance of 300fF on its gate. These input capacitors also add up to the parasitic capacitance already present on the floating gates of MIFG inverters. To reduce these transition times. From the SPICE netlist.6. These capacitances cause rise and fall times of input signals to increase. the Wp /Wn ratios of the conventional inverters #3 and #4 were set to 10. The result of this is. This causes increase in the rise and fall times of the input waveform. input capacitors of MIFG inverter #2 act as load for inverter #1. In Fig. Figure 4. 76 . Slow rise and fall times cause delay in the output waveforms. The W/L ratios of MIFG inverter #1 for PMOS and NMOS transistors are 13.4/1. the parasitic capacitances are in the range of 100fF-400fF. the outputs of the MIFG inverters #1 and #2 still have slow rise and fall times.2 Full Adder The MIFG inverter has been realized using first polysilicon for the floating gate and input voltages are coupled via capacitors to the gate using second polysilicon contacts. W/L ratio of the NMOS transistor has been increased to 19. The full adder design occupies an area of 293 x 160µm2 .6 and 8. inverters #1 and #2 are MIFG CMOS inverters and inverters #3 and #4 are conventional CMOS inverters.6/1.4/8. respectively.5.6/1. 4.6 to reduce the fall time of the output of inverter #2. which is the invert of SUM bit. However.4 shows a MIFG CMOS full adder circuit. 4.8.

6) VDD(3V) VSS(GND) #5 500ff 500ff 500ff #6 (13.4/1. 77 .6) #3 (10.6) (10.6/1.6) (8.6) #2 (13.4/1.6) (8.4/1.6) SUM' SUM CARRY (19.6/1.8/1.8/1.6/1.6) (8.6) VDD (A + B) (8. with additional OR logic.6) VA VB VCIN 500ff 500ff 500ff 500ff 500ff 500ff 1000ff (8.4: Circuit diagram of a full adder.6/1.6) #4 (10.4/1.VDD (3V) #1 (13.6) VSS(GND) Figure 4.4/1. using MIFG CMOS inverters.8/1.

Figure 4. 78 .5: Layout of a full adder.

respectively. to improve delay of output signals.2 and 20. Adding resistors as explained in Appendix C modified the netlist to solve the problem of DC convergence in SPICE. We have used buffers with the Wp /Wn increasing progressively with each stage [39]. The input waveforms were pulse waveforms of following frequencies: 10MHz and 5MHz with 5 ns rise and fall times. the output from the multiplexer stage at the output is taken to a buffer chain. The full adder is configured as ripple carry adder.8/13. we have added buffers at the output of each stage of the 4-bit ALU.6µm The buffer stages also decrease distortion of the p waveforms at the output stages. Input B a pulse of 5MHz. Input CIN is a pulse of 5MHz. S1 and S2 are the select signals that decide the operation being performed.6/7.In our design. S0 . Appendix A shows the SPICE LEVEL 3 MOS model parameters.4/13.0V and VSS is 0. 16.3 Arithmetic Logic Unit The 4-bit ALU comprises of 4 to 1 and 2 to 1 multiplexers at the input and output sides and full adder with additional logic. The voltage levels of inp ut pulse depicting ‘1’ and ‘0’ states are 3V and 0V.3. The truth table for the eight operations performed by the ALU is shown in Table 4.6 shows the waveforms of the input signals and the output waveforms of SUM and CARRY bits. By adding appropriate input signals.0V. Input A is a pulse of 10MHz. 79 . transient analysis was performed. 4. The SUM and CARRY bit waveforms are as shown in Fig.6. 14. The layout was extracted to obtain the SPICE netlist.6. At each stage of the 4-bit ALU. The Wp /Wn ratios are 9. In SPICE. the supply voltage VDD is 3. 4. Four inverters of increasing Wp /Wn ratios form the buffer chain. Figure 4.6.2 where L = Ln = 1.8/9. simulations for the full adder circuit.

80 .6: Post layout simulated waveforms for the full adder showing SUM and CARRY bits.3V INPUT C IN 0V 3V INPUT A 0V 3V INPUT B 0V 3V CARRY 0V t t t t 3V SUM 0V 0ns 50ns 100ns 150ns TIME 200ns 250ns 300ns t Figure 4.

3 Truth table of a 4-bit ALU S2 0 0 0 0 1 1 1 1 S1 S0 Operation performed 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 INCREMENT DECREMENT ADDITION SUBTRATION AND OR EXOR EXNOR 81 .Table 4.

For SUBTRACTION.5µm CMOS process. The multiplexer logic at the output side of each stage of the ALU gives the final output. In case of arithmetic operations. The entire layout was placed in the 1. in effect. B’ (which is complement of B) and CIN.8.7. performs a SUBTRACT operation.5µ padframe. Connections were made for inputs. The layout of the 4-bit ALU is shown in Fig. CIN is set to ‘1’. outputs. The post. The post. The input.9. Adding inputs A. 4. supply voltages and ground pins on the padframe. the carry ripples from LSB to MSB position. The select signal S0 was tied to logic ‘0’ for ARITHMETIC operations and tied to logic ‘1’ for LOGIC operations.layout extracted netlist was modified to overcome the DC convergence problem of the simulator. The photograph of the chip including padframe is shown in Fig. 4. 4.10. The photograph of fabricated 4-Bit ALU chip is shown in Fig.11.layout extracted netlists. SPICE simulations for the 4-bit ALU were done for post. The multiplexer stage at the input passes on the complement of input B to the full adder. four stages of the full adder are cascaded in ripple carry adder configuration. The chip layout before fabrication is shown in Fig. and connected to logic ‘1’ for logical operations. Two pulse trains of frequencies 10MHz and 5MHz were applied to the inputs. two’s complement method is used. 82 . 4. For the layo ut of the 4-bit ALU.layout SPICE simulation waveform for arithmetic operation ADDITION is shown in Fig. 4. The 4-Bit ALU occupies approximately an area of 830 x 935 µm2 . For logical operations the output of each stage is independent of the other stages. Therefore the output of each stage depends on the previous stage. The design was fabricated in AMI 1.Signal S2 is connected to logic ‘0’ for arithmetic operations.

Figure 4.7: Layout of a 4-bit ALU. 83 .

84 .8: Full chip layout for a 4-bit ALU.Inverter 4-bit ALU Full Adder f Figure 4. Note: Individual building blocks such as inverter and FA are also included for testability.

Figure 4.9: Photograph of a fabricated 4-Bit ALU chip. 85 .

10: Chip photograph of a fabricated 4-Bit ALU and test devices.Figure 4. 86 .

layout waveforms for arithmetic operation (ADDITION). 87 .3V SELECT SIGNAL S2 = 0 0V t 3V INPUT CIN 0V 3V INPUT A 0V 3V INPUT B 0V 3V CARRY 0V 3V t t t t SUM 0V t 0ns 50ns 100ns 150ns TIME 200ns 250ns 300ns 350ns Figure 4.11: Post.

Figure 4. 88 .1 Delay Measurements for 4-Bit ALU The 4-Bit ALU performs four arithmetic and four logical operations.16 shows the waveform for the four logical operations. the signal S2 is connected to logic ‘1’. For logical operations.layout simulations were performed using model parameters of fabricated chip. The input CIN is set to logic ‘0’. From the Boolean equations for SUM and CARRY bits. 4. Hence it gives four outputs. 4.Figure 4. specific input patterns were chosen to obtain worst-case delay measurements.3. we realize that they are EXOR and AND operations respectively. All four stages of the 4-Bit ALU are identical. The invert of EXOR would give us EXNOR. DECREMENT is also a SUBTRACTION operation with ‘1’ being subtracted from operand A. The MOS model parameters of the fabricated chip are listed in Appendix B [35]. The full adder logic performs EXOR. The multiplexer logic at the output stage passes on one of the four full adder outputs as the final output. it is sufficient to measure the delay in only 1-bit stage of the ALU since each output bit is independent of the preceding stage. For logical operations.14 shows the waveforms signals for INCREMENT operation. EXNOR and OR operations. Figure 4.13 shows the waveforms for DECREMENT operation. The multiplexer passes a logic ‘1’ to the full adder which will be added to input A thus incrementing it. Additional logic as shown in Fig. Figure 4.12 shows the waveform for SUBTRACTION. INCREMENT operation is addition of ‘1’ to input A.15 has been added to the full adder to realize OR operation. The post. Simulations were performed using SPICE simulator. However for arithmetic operations. AND.

12: Post.layout waveforms for arithmetic operation (SUBTRACTION). 89 .3V INPUT A 0V 3V INPUT B' 0V t t 3V INPUT CIN 0V t 3V ALU OUPUT 0V t 0ns 50ns 100ns 150ns TIME 200ns 250ns 300ns 350ns Figure 4.

90 .13: Post.layout waveforms for arithmetic operation (DECREMENT).3V INPUT A 0V 3V LOGIC 0 0V t 3V INPUT CIN 0V t t 3V ALU OUPUT 0V t 0ns 50ns 100ns 150ns TIME 200ns 250ns 300ns 350ns Figure 4.

3V INPUT A 0V 3V LOGIC 1 0V

t

t

3V INPUT CIN 0V

t

3V ALU OUPUT 0V t 0ns 50ns 100ns 150ns TIME 200ns 250ns 300ns 350ns

Figure 4.14: Post- layout waveforms for arithmetic operation (INCREMENT).

91

An Bn CIN SUM

CARRY

(A + B) Additional logic for OR gate (a) VDD(3V)

#1 An Bn VDD C C C (13.6/1.6)

#2 (10.4/1.6)

(A + B) (8.4/1.6)

(8.8/1.6)

VSS(GND)

(b) Figure 4.15: (a) Additional logic OR gate in full adder (b) MIFG CMOS equivalent circuit to realize OR operation.

92

**3V SELECT SIGNAL S2 = 1 0V 3V INPUT A 0V 3V INPUT B 0V
**

t

t

t

3V OR 0V 3V AND 0V

t

t

3V EXOR 0V

t

3V EXNOR 0V

t

0ns

50ns

100ns

150ns TIME

200ns

250ns

300ns

350ns

Figure 4.16: Post- layout waveforms for all LOGICAL operations.

93

Input pattern [A3 A2 A1 A0 ] = [1 0 0 0] and [B3 B2 B1 B0 ] = [1 1 1 1] generate the maximum delay. Logical operations do not have any worst-case delay. Figure 4.5 has the delay measurements of arithmetic and logical operations tabulated for post-layout and experimental results 94 . Figure 4. The delay in simulated waveforms has been calculated for a load capacitance of 15pF.20 shows the post.18 shows the waveforms for CARRY bit. For INCREMENT operation the input pattern [A3 A2 A1 A0 ] = [1 1 1 1] when incremented by 1 generates a CARRY which trickles all the way from LSB to MSB. as each stage of the ALU is independent of the other. In case of ADDITION. The value 15pF is chosen because that is approximately how much capacitance the oscillator probe would provide in experimental setup.Table 4.4 gives the input pattern for worst-case delays in arithmetic operations. The worst-case delay input patterns for SUBTRACTION and DECREMENT are also chosen in the same way.19 shows the waveforms for logical operations EXOR and EXNOR.layout and experimental waveforms for logical operations AND and OR. the CARRY will have to propagate from MSB of A (A3 ) to LSB of A (A0 ) in order to perform SUBTRACT operation. Figure 4. The delay between the two waveforms shows the worst-case delay. Since MSB of A (A3 ) = logic ‘1’ and LSB of B (B0 ) = logic ‘0’. Table 4. The delays presented are the delays for just a single stage of the 4-bit ALU. The carry propagates from LSB to MSB position.17 shows the waveforms for SUM bit for postlayout simulation and experimental results. input patterns [A3 A2 A1 A0 ] = [0 0 01] and [B3 B2 B1 B0 ] = [1 1 1 1] and initial CARRY-IN as ‘0’. Figure 4.

Table 4.4 Input patterns for worst-case delay measurements A3 A2 A1 A0 (LSB) B3 B2 B1 B0 (LSB) ADDITION SUBTRACTION DECREMENT INCREMENT 0 1 1 1 0 0 0 1 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 95 .

5 3 2.5 0 -0.5 2 1.5 3 2.17: Waveforms for SUM bit showing worst-case delay between post-layout simulation and experimental results.5 0 Voltage (V) Input B 20 40 60 Time (ns) 80 100 120 simulated 3.5 1 0.5 2 1.5 0 -0. 96 .5 0 Voltage(V) Input A 20 40 60 80 100 Time (ns) 3. .5 1 0.5 3 2.5 0 -0.3.5 1 0.5 0 experimental Voltage (V) Sum 20 40 60 80 100 Time (ns) Figure 4.5 2 1.

18: Waveforms for CARRY bit showing worst-case delay between post.5 2 1.layout simulation and experimental results.5 1 0.5 0 -0.5 0 Voltage (V) Input B 20 40 60 Time (ns) 80 100 120 simulated 3.5 0 -0.5 1 0.5 2 1.5 0 20 40 60 80 100 Time (ns) experimental Volatge (V) Carry Figure 4.5 3 2.5 3 2. 97 .5 0 Voltage(V) Input A 20 40 60 80 100 Time (ns) 3.5 0 -0.5 1 0.3.5 3 2.5 2 1.

4 Voltage(V) 3 2 1 0 -1 0 20 40 Input A 60 80 100 Time (ns) 4 Voltage (V) 3 2 1 0 -1 0 20 40 60 Time (ns) 80 100 120 Input B simulated 4 Voltage (V) 3 2 1 0 -1 0 50 Time (ns) 100 EXOR experimental simulated 4 Voltage (V) 3 2 EXNOR 1 0 -1 0 50 Time (ns) 100 experimental Figure 4. 98 .layout simulation and experimental results.19: Waveforms for EXOR and EXNOR bits showing delay between post.

4 Voltage(V) 3 2 1 0 -1 0 20 40 Input A 60 80 100 Time (ns) 4 Voltage (V) 3 2 1 0 -1 0 20 40 60 Time (ns) 80 100 120 Input B simulated 4 Voltage (V) 3 2 1 0 -1 0 50 100 Time (ns) 150 200 OR experimental simulated 4 Voltage (V) 3 2 1 0 -1 0 50 Time (ns) AND experimental 100 Figure 4. 99 .20: Waveforms for OR and AND bits showing delay between post-layout simulation and experimental results.

Delay measurements for all output bits of ALU for arithmetic and logical operations for post.layout simulated and experimental results OPERATION SUM CARRY EXOR EXNOR OR AND DELAY Tp (ns) SIMULATED with CL = 15pf 26 17 26 28 27 28 DELAY Tp (ns) EXPERIMENTAL 32 22 28 31 28 32 100 .Table 4.5.

5. our full adder design implemented with multi. With 15pF simulated capacitive load. the maximum propagation delay is 32ns for the SUM bit. The 4-bit ALU uses a ripple carry adder configuration. The circuits are simulated in SPICE with MOSIS LEVEL 3 MOS model parameters. The full integrated circuit is designed and simulated in standard 1.input floating gate transistors.input floating gate transistors.5µm digital CMOS technology. When compared to conventional designs the reduction in number of transistors is nearly 84%. The physical layout for all circuits is drawn using L-Edit version 8. The principle of MIFG transistors. calculating weighted sum of all inputs at gate level and switching transistors ON or OFF depending upon calculated floating gate voltage greater than or less than switching threshold voltage.layout simulations included parasitic nodal capacitances to bring the simulation results as close as possib le to the real time results. The power dissipation is close to 0.1 shows a comparison in transistor count between earlier designs and our design.1 Future work An important aspect of designing circuits using floating gate devices is determining the value of unit capacitance ‘C’. The full adder with additional logic for OR operation has been designed entirely using multi.Chapter 5 Conclusion and Future Work An integrated circuit design has been presented for a 4-bit arithmetic logic unit using multiple-input floating gate MOSFETs. Compared with earlier reduced transistor designs for full adder. which affects the layout area and 101 .5mW.03. is utilized. The post. uses at least 43% lesser transistors. Table 5.

1 Comparison of between earlier full adder designs and our design with respect to transistor count Full adder Design Bui et al ‘s design [9] Wang et al’s design [10] Shams et al ‘s design [11] Radhakrishna’s design [12] MIFG full adder design [present] Number of transistors used 10 12 16 12 8 102 .Table 5.

level models is still an issue. Manufactures do not provide models for simulating floating gate MOSFETs. hence a special technique to simulate these devices with standard MOS models is required. Knowing the fabrication run being used and error percentage in process would give us feedback for designing with smaller capacitors. 103 .performance of the circuits. Future work could be extended to optimizing unit capacitance value. Realizing logic designs with smaller capacitors will reduce the power dissipation and make the layout more area efficient. Further work could also include extending the current design to include more number of input bits for the ALU. The practical design aspect of simulating floating gate MOSFET in SPICE using low.

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5 + CJSW = 1.615428E-7 + PHI = 0.6052099 ETA = 9.7508359 CGBO = 1E-10 MJ = 0.781647E-10 MJSW = 0.994094E-7 + PHI = 0.702724E5 NFS LD = 5.503416E5 NFS = 4.821829E-4 CGSO = 1.244664E-10 MJSW = 0.4898253 DELTA = 0.7 + UO + KP = 800 = 7.6662211 = 2.0708 TPG = 1 WD = 6.Appendix A MOSFET Model Parameters [35] nMOS Model Parameters .770051E11 LD = 7.8883154 CGBO = 1E-10 MJ = 0.327947E16 VTO = -0.1286211) 108 .05E-8 LEVEL = 3 NSUB = 5.7 + UO + KP = 159.MODEL NMOS NMOS ( + TOX = 3.3307574 THETA = 0.999921E-4 GAMMA = 0.76E-10 + CJ = 2.0710077 KAPPA = 1.05) pMOS Model Parameters .05E-8 LEVEL = 3 NSUB = 1E15 VTO = 0.0299117 + XJ = 3E-7 + CGDO = 1.4334195 + CJSW = 1.1329612 KAPPA = 10 TPG = -1 WD = 9.7292975 DELTA = 0.470055E-5 + RSH = 27.4903542 THETA = 0.8651299 ETA = 1 VMAX = 3.022339E-4 CGSO = 2.25E-10 + CJ = 3.401542E-5 VMAX = 3.25E-10 PB = 0.76E-10 PB = 0.440123E11 = 1E-12 GAMMA = 0.15092E-12 + RSH = 0.1878946 + XJ = 2E-7 + CGDO = 2.MODEL PMOS PMOS ( + TOX = 3.

4940829 DELTA = 0. MODEL CMOSN NMOS( + TOX = 3.Appendix B MOSFET Model Parameters of the Fabricated Chip [35] nMOS Model Parameters .766785E5 NFS = 6.5236605 THETA = 0.5 TPG = 1 WD = 7.438731E-5 MJSW = 0.09E-10 PB = 0.744678 CGBO = 1E-10 MJ = 0.75E-10 + CJ = 2.7620845 DELTA = 0.965467E-4 CGSO = 2.684773E-12 + RSH = 36.99916E-4 GAMMA = .1055522) 109 .195017E-5 LEVEL = 3 NSUB = 2.7 + UO + KP = 250 = 2.09E-10 + CJ = 2.34313E-7 VMAX = 2.619193E-10 MJSW = 0.05) LEVEL = 3 NSUB = 1E17 VTO = -0.4276703 + CJSW = 1.518964E11 LD = 9.9336344 = 7.8569392 THETA = 0.345228E5 NFS = 5.07E-8 + PHI = 0.75E-10 PB = 0.55184E-3 GAMMA = .5040447 + XJ = 2E-7 + CGDO = 2.6298903 ETA = 9.9048351 CGBO = 1E-10 MJ = 0.1344949 KAPPA = 200 TPG = -1 WD = 1E-6 VMAX = 9.944613E-4 CGSO = 1. MODEL CMOSP PMOS ( + TOX = 3.07E-8 + PHI = 0.5 + CJSW = 1.271014E-12 + RSH = 0.236957E-10 pMOS Model Parameters .7 + UO + KP = 702.8615406 ETA = 7.0474566 + XJ = 3E-7 + CGDO = 1.75325E15 VTO = 0.0734963 KAPPA = 0.567094E11 LD = 4.

Later in the transient analysis. Most circuit simulators replace the input coupling capacitors in floating gate devices with open circuits during DC analysis.7. A transient analysis is performed which starts of with all inputs and circuit power supplies set to 0V. we have simulated a 4-input floating gate CMOS inverter circuit of Fig. V2 . This initializes the voltage on the floating gate to zero. Using the model in [6]. Simulation ends at this point. C.1. V3 and V4 are the voltages of the input gates of the MIFG CMOS inverter. The difficulty in simulating MIFG devices is the inability of the simulator to converge when floating node exists.Appendix C Simulating Floating Gate MOS Device One of the practical design issues concerning circuits that implement floating gate devices is electrical simulation. Yin et al [6] have shown a very simple simulation model for the floating gate devices. C1 . C2 . In Fig. V1 . Solution to the problem of floating gate MOSFET is presented in several paper providing solutions for this problem [6. Ramirez-Angulo et al [36] have used a very high resistor element between the floating gate and ground along with voltage elements in the circuit to overcome this problem.1. Rodriguez-Villegas et al [7] have introduced an initial operating point in floating gate circuits by using additional network formed by resistors and voltage-controlled voltage sources (VCVS). as it is not able to converge. C. C3 and C4 are the input capacitors of 500fF 110 . Manufacturers of the simulation tools do not provide models for floating gate devices.36]. VF is the voltage on the floating gate. This requires from us to devise me thods of simulating floating gate device circuits. a stationary state is reached and this is used as fixed operation point for the rest of the simulations.

In our design to make R in the range of 1000G.1. Figure C. C. Ri is selected as Ri = 1/ kiCi. k is i i chosen as 1012 .1.2 shows the input and output waveforms generated by simulating the circuit of Fig.1 is described as follows. the relationship between the floating gate voltage and input gate voltages under the DC condition is given by equation C. To avoid the DC convergence problem. resistor element. C. G 1(V 1 − VF ) + G 2(V 2 − VF ) + G 3(V 3 − VF ) + G 4(V 4 − VF ) = 0 (C.1. VF = V 1 × C1 + V 2 × C 2 + V 3 × C 3 + V 4 × C 4 C1 + C2 + C3 + C4 (C. ki is chosen to make R as high as possible.2) In the circuit of Fig.1) where Gi = 1/Ri = kiCi and GTOT = ∑ G i i= 0 n where ki is a constant. 111 . C.1) reduces to the following form. R1 to R4 are inserted across each of the four input capacitors. For this model. The SPICE netlist for the circuit of Fig. Equation (C. The constant.each.

input floating gate CMOS inverter.C1 V1 1 VDD(3V) 500fF 4 R1 C2 500fF M13 V2 3 R2 C3 500fF M19 500fF 5 2 Vout V3 8 R3 C4 CL V4 6 Rn 7 VSS (0V) VF: Voltage on floating gate Figure C. 112 .1: Simulation model of a multi.

81) * 5 = fg (-19.53216f Cpar4 4 0 1.53216f r1 4 5 1e12ohms r2 3 5 1e12ohms r3 8 5 1e12ohms r4 6 5 1e12ohms r5 0 5 1e12ohms Vdd 1 0 dc 3v Vss 7 0 dc 0v V1 4 0 pulse(3V 0V 0N 1N 1N 60N 120N) V2 3 0 pulse(0V 3V 0N 1N 1N 60N 120N) V3 8 0 pulse(3V 0V 0N 1N 1N 60N 120N) V4 6 0 pulse(3V 0V 0N 1N 1N 60N 120N) .35936f Cpar8 8 0 1.tdb * Cell: fgmosfet1 Version 1.-7) * 2 = Vout (22. * TDB File: Z:\grad\chandra\1. probe 113 .5 * Extract Definition File: C:\Program Files\Tanner EDA\L-Edit Pro\tech\mosis\mAMI150.53216f Cpar5 5 0 152. tran 10ns 140ns .SPICE netlist for a 4-input floating gate CMOS inverter of the circuit of Fig.20 / Extract V8.37) * 6 = V4 (-255.20) * 4 = V1 (-252.20:16 * NODE NAME ALIASES * 1 = vdd (-5.73) * 8 = V3 (-254.76992f Cpar3 3 0 1.35) * 3 = V2 (-257.1 * Circuit Extracted by Tanner Research's L-Edit V8.20 .97664f Cpar2 2 0 5.ext * Extract Date and Time: 04/15/2002 .5layout \alulayoutprefab.-108) * 7 = vss (-8. C.-44) Cpar1 1 0 5.53216f Cpar7 7 0 4.80944f Cpar6 6 0 1.

994094E-7 + CGDO = 2.37024f * C7 PLUS MINUS (-236 39 -43 77) C2 5 6 499.4u AD=49.1878946 NFS = 5.76E-10 CGSO = 1.0708 + RSH = 0.1329612 + KP = 2.25E-10 CGSO = 2.7508359 MJ = 0.25E-10 CGBO = 1E-10 + CJ = 3.56p PD=24u AS=34.0299117 NFS = 4. MODEL NMOS NMOS (LEVEL = 3 + TOX = 3.6u W=10.3307574 + UO = 159.4334195 + CJSW = 1.4898253 + PHI = 0.37024f * C1 PLUS MINUS (-240 -87 -47 -49) .5 + CJSW = 1.1286211) M19 2 5 7 7 NMOS L=1.6u W=7.4903542 + UO = 800 ETA = 9.6052099 DELTA = 0.470055E-5 VMAX = 3.615428E-7 + CGDO = 1.781647E-10 MJSW = 0.0710077 + KP = 7.440123E11 TPG = -1 + XJ = 2E-7 LD = 1E-12 WD = 9..7 VTO = -0.401542E-5 VMAX = 3.327947E16 GAMMA = 0.999921E-4 THETA = 0.4u * M13 DRAIN GATE SOURCE BULK (10 -7 14 19) C8 5 3 499.37024f * C2 PLUS MINUS (-239 -151 -46 -113) C1 5 8 499.702724E5 KAPPA = 10 + RSH = 27.92p PD=30.6662211 ETA = 1 THETA = 0.56p PS=24u * M19 DRAIN GATE SOURCE BULK (10 47 14 65) M13 2 5 1 1 PMOS L=1.8651299 DELTA = 0.2u AD=34.770051E11 TPG = 1 + XJ = 3E-7 LD = 7.503416E5 KAPPA = 1.15092E-12 WD = 6.821829E-4 PB = 0.05) .76E-10 CGBO = 1E-10 + CJ = 2. END 114 .244664E-10 MJSW = 0. MODEL PMOS PMOS (LEVEL = 3 + TOX = 3.92p PS=30.022339E-4 PB = 0.05E-8 NSUB = 5.7 VTO = 0.7292975 + PHI = 0.05E-8 NSUB = 1E15 GAMMA = 0.4u AS=49.37024f * C8 PLUS MINUS (-240 -23 -47 15) C7 5 4 499.8883154 MJ = 0.

115 . C.input floating gate CMOS inverter of the circuit of Fig.1.2: Input and output waveforms of a 4.3V V1 0V 3V V2 0V t 3V V3 0V t t 3V V4 0V 3V Vout 0V t 0ns 20ns 40ns 60ns TIME 80ns 100ns 120ns 140ns t Figure C.

She has completed her undergraduation from Mysore University in Electrical Engineering in 1997. Her other interests include reading. in 2000. music and international cooking.Vita Chandra Srinivasan is from Bangalore. multiple. to pursue a master’s degree in electrical engineering.input floating gate MOSFETs and capacitive based architectures. Baton Rouge. 116 . She joined Louisiana State University. known as ‘silicon valley of India’. in the southern part of India. Her research interests include multivalued logic.

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