2011 Sixth IEEE International Symposium on Electronic Design, Test and Application

Automatic Y Yield Management Syst for tem Semico onductor Production Te est
Huiyuan Cheng
School of Engineering Monash University, Malaysia hche61@student.monash.edu

Melanie Po-Leen Ooi
School of Engineering Monash University, Malaysia melanie.ooi@monash.edu

Ye Chow Kuang School of Engineering S Mon nash University, Malaysia kuan ng.ye.chow@monash.edu

Eric Sim
School of Engineering Monash University, Malaysia kjsim4@student.monash.edu

Bryan Cheah
Global Yield Enhancement Team Freescale Semiconductor bryancheah@freescale.com

Serge Demidenko
Centre of Technology RMIT University, Vietnam R serge.demidenko@rmit.edu.vn

Abstract— Recurring defect cluster patterns on semiconductor faults in specific wafers can be linked to imperfectness/f manufacturing processes or alternatively - to failure or malfunctioning of production equipment (in our research we n assume that defects associated with deficien ncies/errors in the circuit design are not present). By identifying these patterns as g they occur, a fast and effective process moni itoring and control mechanism can be achieved, shortening the ti ime-to-yield period and reducing the loss in revenue due to avo oidable yield drop. Identifying these patterns manually could be a too complex and time consuming task. This research presents an automatic yield fect management system to extract and identify def clusters as well as perform yield analysis in a high-volume sem miconductor devise manufacturing. Keywords-semiconductor wafer technology, yield management, defect clusters, yield analysis

Figure 1. Defect cluster patterns: a) Bulls-Eye, b) Blob, c) Line, d) Edge, e) Hat, f) Ring ,

I.

INTRODUCTION

Modern semiconductor industry is facing a mounting pressure to lower the cost of the produced integrated circuits ers (IC) while further advancing their paramete and increasing functionality [1]. As a result it has become very essential for gh the IC manufacturers to achieve a hig manufacturing throughput without compromising quality an reliability of the nd final products. Unfortunately, in majority of cases new devices ing or products tend to have a low manufacturi yield. Thus in order to maintain the product’s profitability in a long run, it is e crucial that a steep yield ramp would be achieved in the shortest time possible [2]. High yield ramping can be gained ss through the effective manufacturing proces monitoring and good utilization of engineering resources. One of the indicators of possible p process faults or equipment degradation is an observed incre ease in the defect population in the final product. For fabricat semiconductor ted wafers, this is normally manifested thro ough presence of consistent and specific defect patterns. Fig gure 1 shows six commonly observed defect patterns on th semiconductor he wafers [3].

Each of these defect cluster patterns can be loosely tied to r possible specific manufacturin process or equipment issues. ng For instance, the Bulls-eye de efect pattern can be caused by contamination of a nozzle emp ployed to apply the photoresist coating on the wafer surface. By identifying such defect p patterns as and when they occur, a specific malfunctioning equi ipment or faulty process can be quickly pin-pointed and f fixed. However, the defect identification, classification an cause back-tracking analysis nd can be complex and time consu uming. Therefore it is essential to develop and engage automa ation tools for as many routine tasks as possible in the yield l learning and yield management area [4]. Some of the auto omation solutions have been introduced in the industry in th recent decade. One example he is Atmel’s adoption of the KL LA-Tencor's Klarity system [5], which reduced yield learning time from several months to a few weeks. n This research proposes an automatic yield management system that performs wafer-lev defect analysis through data vel mining. It provides com mputer-aided detection and recognition/classification of defect patterns on fabricated ring test data and performs an wafers using raw manufactur automatic yield analysis for the relevant wafer lot. e
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978-0-7695-4306-2/11 $26.00 © 2011 IEEE DOI 10.1109/DELTA.2011.53

Prior to any ion actual classification. Subsystem 1: SDC on This subsystem utilizes the Segmentatio with Detection and Cluster Extraction (SDC) algorithm described in [3]. Figure 4. ng Figure 5 The Cla assification System RMI has been used as a clas ssical tool for object recognition in the past 40 years [10]. or to be employ in conjunction yed to correlate the manufacturing yield with d defect cluster data for further analysis. the decisi tree has to be built based on a training set. It wa shown in [9] that RMI could as 255 261 . This method has bee shown to be accurate for this en classification task [6]. It performs g cluster segmentation using image processing methods and uses joint-count statistics to detect any non-ran ndom failures (or local defect patterns) on the wafer. Application of SDC system The original wafer map with random m. which could distort the clas ssification process. System Architecture A. One of them is associated wi the use of Artificial Neural ith Networks. Figure 4(b) shows an example of the local de efect pattern wafer map after application of SDC. These s subsystems can be used standalone if necessary. Unfortun nately it generates classification rules that are not transparent t the user. which es are extracted using the Handp picked (HP) Feature Extractor and Rotational Moment Invaria (RMI) Feature Extractor. Figure 5 shows the classification system.II. The SD algorithm is DC characterized by detection accuracy exceedin 90% [3].Figure 4(a). particularly in p aimed for mission critical app plications as it would fail any quality audits conducted by e end-client companies or safety enforcement/standardization bo odies. ant Figure 3. Previous he investigation showed that th Alternating Decision Tree (ADTree) was the most prom mising classifier for fabricated semiconductor wafers [9]. Their generated rules are fully transparent to the user allowing for a r monitoring and control over classification. om which produces a training set of all possible orientation of t defect clusters and their respec ctive defect type. SDC System Random failures manifest as a salt-and-pepper noise on the wafer map . The gradient boosting algorithm can be used with decision trees to improve d the classification accuracy significantly [8]. the cluster extraction combines the segmentation and d detection results to obtain the final defect cluster data. They may cause ina accuracy in cluster detection and classification. Subsystem 2: Classification n Classification can be achie eved through various methods. This is undesirable to for implementation in the semiconductor device production of integrated circuits manufacturing. Figure 3 shows the main stages of the algorithm. Decision trees are widely used in decision making based on data mining and mac chine learning. This comes fro a defect pattern simulator. Fin nally. The rules are generated based on the feature from the training set. failures (a) and after SDC application (b) r B. The SDC system extracts the oving the random defect clusters while simultaneously remo failure patterns. The proposed system empl loys decision tree classification method [7]. SYSTEM ARCHITECTU URE The proposed system includes three m main components (subsystems) as shown in Figure 2. Figure 2.

For instan nce. the analysis When implementing the sy shows a stable high yield ( (Figure 7) corresponding to a matured production process. B and C for the sake of confidentiality) were al identified for experimental tria of the proposed system over a period of 3 months. There is a noticea able yield drop in the shaded region I where a high percentage of blob and edge e defect patterns were detected. The features generated by RMI are d complemented by HP extracted ones. cted The efficiency of ADTree used in the cla assification system has been further expanded by employing data representation in a the complex number domain [11]. With the classification rules generated. Thus be improvement in the use of th existing test data and early he simulation in the production r ramp are required to obtain an objective and comprehensive e evaluation of the existing yield and its trend. EXAMPLE OF CLASSIFICATION RESULTS STORED IN CSV FILE S Lot ID AAA BBB Wafer ID XXX YYY Possible Class 1 Edge Blob Confidence for Class 1 50% 80% Possible C Class 2 Line Confidence for Class 2 30% - III. Thus it would be strongly desirable for the manufacturing engineers t look at the condition of the to equipment and parameters of t processes and to revise their the maintenance and process mo onitoring strategy if required. the classification results ar presented along re with their confidence score levels. Lot ID AAA shows an ambiguous case whereby two c possible classes are reported for the sam defect cluster me pattern. ts Figure 6.see Figure 1 c) and Fig gure 1 e). incurred if yield ramping is pe In fact in today’s semiconduc ctor industry an initial yield (at product introduction) and the yield ramp rate have replaced the final yield (at full capacity production) as key drivers of IC yield ramp rate can actually be profitability. The majority of yield improvement techniques employed in the industry rely upon availa ability of high volume of defect data. would have a negligible effect on the yield. This wa caused by the considerable as increase in the number of the L defect cluster patterns. It can be seen that the manu ufacturing yield fell down by approximately 10% over a sign nificant period of time (refer to the shaded region). This all lows the classifier to consider the correlation between the attributes when generating the classification rules. E PROTOTYPE IMPLEMENTATION The decision to transfer a new semiconductor product from an introductory stage to the high volume manufacturing is dependent on various importan factors including achievement nt of the required yield levels. they have a very little correlation with the yiel Solving these defect issues ld. II. However in some cases t these data may not be used in a full extend or could even b somewhat redundant. w where major systematic causes of defects have been already r rectified. Final decision is done by the yield engineer based on the scores provided. a line defect pattern located close to the wafer edge can al be classified as lso a hat defect pattern .be successfully employed to distinguish between different b defect patterns. m Note that certain defect cluster patterns co ould present some ambiguity in their classification. Yield Analysis Tool The relationship between defect cluster type and wafer yield es is presented in graphical form for easy interp pretation. In many cases y more important to profit m margin than the high-volume production yield. it op can be suggested that there may be process or equipment degradation causing it. The proposed automatic yield management d system is addressing this need. The main c characteristics of the devices are shown below in Table II. TABLE II. Table I shows an example s of classification stored as a comma-separa ated-values (CSV) file. ystem on Device B. two different handpicked features using complex numbe features can be compared at a time. Line 256 262 . it can be observed that there are periodic yield drops (see shaded regions I. Subsystem 3: Yield Analysis The yield analysis system correlates the yield of a particular wafer lot to its classification result (Figure 6). Examples of these are mean radius and the major axis length of the extrac cluster. CHARACTERISTICS OF THE DEVICES USED IN THE RESEARCH F Device A B C Feature Size (nm) 130 250 90 Die/Wafer D 402 984 384 Average Yield 60-80% Above 80% Below 60% C. Because the yield dro here is periodic in nature. Three different mass-produ uction devices (named as just Device A. Thus for each defect class. By representing the ers. pattern wafer maps from the SDC subsystem can be classified. However. Figure 7 shows the results of the yield analysis for one of the real-world e mass-produced semiconductor devices (nam here as Device med B due to confidentiality). The class with a higher confidence level is presented as the first possible one. III and IV) par rticularly when there is a high occurrence of the Blob defect c cluster patterns (in regions I. III and IV). the local defect . Figure 8 shows the yield a analysis results on Device A. Huge loss of revenue can be erformed at an insufficient pace. Hand dpicked features in [9] were geometrical descriptors of the defect clusters as d understood by a human classifier. Conversely although the edge defect clusters are consistently recurring throughout the obser rvation period. TABLE I.

. allowing for fast and high quality process monitoring and control. The Line defect cluster patterns are typically caused by incorrect mechanical handling of the wafers. such as speed of revolution during application of the photoresist layer. there was also a moderately high number of the Blob defect cluster patterns found. etc. Results of implementation of the automatic yield management system on Device A 257 263 . etching process (a common cause of blob defect cluster patterns). Thus the dies at the edges could have reliability issues during the earlier stages. In this particular case it can be clearly seen that if the proposed automatic yield management system would be incorporated at an earlier stage. recognition and correlation to manufacturing yield. data to decide if the WEE region should be extended. Device A Lot Level Yield Analysis Mean Yield Lot Yield Line Yield Lot ID Figure 8. Figure 9 shows that Device C has consistently low yield compared to Devices A and B. the reported yield management tool identified an unusually high occurrence of Edge defect cluster patterns for Device C. This can be resolved through the machine recalibration or replacement.and yield-related issues.Device B Lot Level Yield Analysis Mean Yield Lot Yield Blob Edge I Yield II III IV Lot ID Figure 7. the yield analysis and evaluation can be performed in real time). Note that Figure 9 was produced based on the wafer probe test results only. The experiments showed that the propose system could be very efficient in identifying and resolving a wide spectrum of defect classification . e. During the more than-3 month period of observation and data analysis. burn-in. ACKNOWLEDGMENT The authors would like to express their gratitude to Freescale Semiconductor for the valuable technical and specialist support provided by their teams in Malaysia and US. CONCLUSION This paper describes a proposed automatic yield management system. It produces a highly consistent analysis in real-time. The effectiveness of the presented system has been confirmed during the 3-month experimental trial with application to the high volume manufacturing program for three different IC types. It was recommended that the engineers closely examine the processes and equipment related to the wafer edge exclusion (WEE) region.g. customer returns. burn-in. Thus. The analysis could be further extended to include the final test. The system automates the repetitive tasks required in yield analysis such as defect cluster detection. etc. the problem could have been detected much earlier (after all. it is a prime target for yield improvement.. Results of implementation of the automatic yield management system on Device B Apparently in some wafer lots practically all the produced wafers had Line defect clusters. In addition. IV.

[3] [4] [5] KLA-Tencor. 324-329. New York: Springer. Enhancement”.html [6] C." in Fifth IEEE International Symposium on Electronic Design. W. H. R. 2002.com/corporate-releases/atmelr-adopts-klatencors-industry-leading-klarity-ace-yield-analysis-software-across-allof-its-fabs. Dec. M. Suk. A. [7] L. C. In: The Elements of Statistical Learning (2nd ed. Friedman. http://www.. Test and Application. P. 337–384. Stone. pp." International Journal of Intelligent Systems Technologies and Applications. CA: Wadsworth & Brooks. Cheng. 2009.net/Links/2009ITRS/Home2009. C. Tibshirani and J. P. Monterey." in Instrumentation and Measurement Technology Conference (I2MTC). [2] C. 15. pp. Classification and Regression Trees." Semiconductor International. Ooi. pp. "Evaluating the Performance of Different Classification Algorithms for Fabricated Semiconductor Wafers. pp. [9] J. 2002. Friedman.)." Boosting and Additive Trees". 2010. pp. J. N. Demidenko. [11] Y. pp. Ooi. 1984 [8] T. Weber.htm “Yield 2009. Results of implementation of the automatic yield management system on Device C REFERENCES [1] International Technology Roadmap for Semiconductors." in IEEE/SEMI Advanced SemiconductorM anufacturingC onference. "Yield Learning and the Sources of Profitability in Semiconductor Manuficturing and Process Development. et al. 258 264 . Flusser and T.Device C Lot Level Yield Analysis Mean Yield Lot Yield Blob Edge Yield Lot ID Figure 9. J. 2010. "Rotation Moment Invariants for Recognition of Symmetric Objects. 360-366. "Application of Neural Networks and Filtered Back Projection to Wafer Defect Cluster Identification." in 2002 Int’l Symposium on Electronic Materials and Packaging. C. "Automatic Defect Cluster Extraction for Semiconductors Wafers. Huang. 2002. R. Kamper and H. 2006. Olshen and C. no. 1999.itrs.-J. pp. to be published.-L. Chan. Kuang. 3784-3790." IEEE Transactions on Image Processing. P. 99-105. [10] J. 12. M. Y. R. vol. Ooi. http://www. [Online]. Breiman. "Automating Routine Tasks in Yield Management. "Complex Feature Alternating Decision Tree. Atmel Adopts KLA-Tencor's Industry-Leading Klarity ACE Yield-Analysis Software Across All of its Fabs.kla-tencor. 2010 IEEE. 1024-1029. 2010. and S. Pinto. 89-94. DELTA '10. Kuang and M.-L. H.-L. Hastie. Jun.

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