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Sequential Logic Design

Adapted from slides by R. H. Katz


Sequential Switching Networks
Simple Circuits with Feedback
Primitive memory elements created from cascaded gates

Simplest gate component: inverter

Basis for commercial static RAM designs

Cross-coupled NOR gates and NAND gates also possible

"1"
"0" Cascaded Inverters: Static Memory Cell

LD

\LD \LD Selectively break feedback path to load new


value into cell
A
Z
LD
Sequential Switching Networks
Inverter Chains
1 0 1 0 0
A
B C D E
X

Odd # of stages leads to ring oscillator Output high


Snapshot taken just before last inverter changes propagating
thru this stage

Timing Waveform: Period of Repeating Waveform ( tp)


Gate Delay ( td)

A (=X) 0 1

B 1
tp = n * td
C 0
n = # inverters
D 1

E 0
Sequential Switching Networks
Inverter Chains

Time 1 X X X X X
1 0 X X X X
1 0 1 X X X
1 0 1 0 X X
1 0 1 0 1 X
0
0 0 1 0 1
0 1 1 0 1 0
0 1 0 0 1 0
0 1 0 1 1 0
0 1 0 1 0 0
1

Propagation of Signals through the Inverter Chain


Sequential Switching Networks
Cross-Coupled NOR Gates

Just like cascaded inverters,


R with capability to force output
S to 0 (reset) or 1 (set)
R =>R-S latch or S-R latch
Q

S
\Q

Timing Waveform
Reset Hold Set Reset Set 100 Race

\Q

Forbidden Forbidden
State State
Sequential Switching Networks
State Behavior of R-S Latch

S R Q QQ QQ
01 10
0 0 hold
0 1 0 RESET state SET state
1 0 1
1 1 unstable
QQ
00
Truth Table Summary
of R-S Latch Behavior

QQ
11
Sequential Logic Networks
Theoretical R-S Latch State Diagram

SR = 00, 01 SR = 00, 10
SR = 1 0
QQ QQ
01 10
SR = 0 1
SR = 0 1 SR = 1 0
SR = 11
SR = 1 1 SR = 1 1

QQ
00

SR = 0 1 SR = 1 0
SR = 0 0
SR = 0 0, 11

QQ
11
Sequential Logic Networks
Observed R-S Latch Behavior

SR = 00, 01 SR = 00, 10
SR = 1 0
QQ QQ
01 10
SR = 0 1
SR = 0 1 SR = 1 0
SR = 11
SR = 1 1 SR = 1 1

QQ
00
SR = 0 0
SR = 0 0

Very difficult to observe R-S Latch in the 1-1 state

Ambiguously returns to state 0-1 or 1-0

A so-called "race condition"


Sequential Logic Networks
• Contact-Bounce Eliminator
+VCC +VCC +VCC

S Q

• 74LS279 Quad S-R Latch

1S1
1S2 1Q 1S1 1Q
1R 1S2
2S 2Q
2R
3S1
3Q 1R
3S2
3R
4S 4Q
4R
Sequential Switching Networks
Level-Sensitive Latch aka Gated R-S Latch

Schematic: \S
\Q
Gated R-S Latch

\R
Q
\enb

Timing Diagram:
Set Reset
100

\S
\R

\enb
Q
\Q
Sequential Switching Networks
• Gated R-S Latch
S S Q
Q
EN
EN

R Q
Q
R

• Gated D Latch

S D Q
Q
EN
EN

Q
Q
Sequential Switching Networks

7474
D Q
Edge triggered device sample inputs on the event
edge
Clk Transparent latches sample inputs as long as the
Positive edge-triggered clock is asserted
flip-flop

7476 Timing Diagram:


D Q
D
C

Clk Clk
Level-sensitive
latch
Q
Bubble here 7474
for negative
edge triggered Q
7476
device

Behavior the same unless input changes


while the clock is high
Sequential Switching Networks
Definition of Terms

Clock:
Periodic Event, causes state of memory
Tsu Th element to change
Input rising edge, falling edge, high level, low level

Setup Time (Tsu)


Clock Minimum time before the clocking event by
which the input must be stable
There
Thereisisaatiming
timing
"window"
"window" aroundthe
around the Hold Time (Th)
clocking
clockingevent
event Minimum time after the clocking event during
during
during which theinput
which the input which the input must remain stable
must remain stable
must remain stable
and
andunchanged
unchanged
in
inorder
order
to be recognized
to be recognized
Sequential Switching Elements
Typical Timing Specifications: Flip-Flops vs. Latches

74LS74 Positive
Edge Triggered Tsu Th T su Th
D Flip-flop 20 5 20 5
ns ns ns ns
D
Setup time Tw
Hold time 25
Minimum clock width ns
Propagation delays Clk
(low to high, high to low, Tplh T phl
max and typical) 25 ns 40 ns
13 ns 25 ns
Q

All measurements are made from the clocking event


that is, the rising edge of the clock
Sequential Switching Networks
Typical Timing Specifications: Flip-Flops vs. Latches

74LS76
Transparent T su Th Tsu Th
Latch 20 5 20 5
D ns ns ns ns
Setup time Tw
Hold time 20
Minimum Clock Width Clk ns
Propagation Delays: Tplh T phl
high to low, low to high, C»Q C»Q
maximum, typical 27 ns 25 ns
data to output Q
15 ns 14 ns
clock to output
T plh T phl
D »Q D »Q
27 ns 16 ns
15 ns 7 ns

Measurements from falling clock edge


or rising or falling data edge
Sequential Switching Networks
Latches vs. Flip-Flops

Input/Output Behavior of Latches and Flipflops


Type When Inputs are Sampled When Outputs are Valid
unclocked always propagation delay from
latch input change

level clock high propagation delay from


sensitive (Tsu, Th around input change
latch falling clock edge)

positive edge clock lo-to-hi transition propagation delay from


flip-flop (Tsu, Th around rising edge of clock
rising clock edge)

negative edge clock hi-to-lo transition propagation delay from


flip-flop (Tsu, Th around falling edge of clock
falling clock edge)

master/slave clock hi-to-lo transition propagation delay from


flip-flop (Tsu, Th around falling edge of clock
falling clock edge)
Sequential Switching Networks
R-S Latch Revisited

Truth Table: Derived K-Map:


Next State = F(S, R, Current State) S
SR
S (t) R ( t) Q ( t) Q ( t+ ∆ ) 00 01 11 10
Q( t )
0 0 0 0
0 0 1 1
H O LD 0 0 0 X 1
0 1 0 0
RESET 1 1 0 X 1
0 1 1 0
1 0 0 1
SET
1 0 1 1 R
1 1 0 X
N o t a llo w e d
1 1 1 X Characteristic Equation:

Q+ = S + R Q
S
R-S Q+ = S + (R + Q)
R Latch Q+
R
Q
Q \Q
R
S S
\Q
Sequential Switching Networks
J-K Flip-Flop
How to eliminate the forbidden state?

Idea: use output feedback to


guarantee that R and S are \Q
never both one --> J-K Latch K R \Q
R-S
J, K both one yields toggle latch
J S Q Q
J(t) K(t) Q(t) Q(t+∆)
0 0 0 0
HOLD
0 0 1 1
0 1 0 0
RESET
0 1 1 0 Characteristic Equation:
1 0 0 1 Q+ = Q K + Q J
SET
1 0 1 1
1 1 0 1
TOGGLE
1 1 1 0
Sequential Switching Networks
J-K Latch: Race Condition

Set Reset 100 Toggle

J
K
Q
\Q

Race Condition

Solution : Single State change per clocking event

--> Master/Slave Flip-Flop


Sequential Switching Network
Master/Slave J-K Flip-Flop
Master Stage Slave Stage

K \P \Q
R \Q R \Q
R-S R-S
Latch Latch
S Q S Q
J P Q

Clk
Sample inputs while clock high Sample inputs while clock low
Uses
Usestime
timeto
tobreak
breakfeedback
feedbackpath
pathfrom
fromoutputs
outputsto
toinputs!
inputs!
1's
Set Reset Catch Toggle 100

J
K
Clk Correct Toggle
P
Master
Operation
\P outputs

Q
Slave
\Q outputs
Sequential Switching Networks
Edge-Triggered Flip-Flops
1's Catching: a 0-1-0 glitch on the J or K inputs leads to a state change!
forces designer to use hazard-free logic

Solution: edge-triggered logic


Negative Edge-Triggered
D
D D flip-flop
Holds D when
clock goes low
0 4-5 gate delays
R
Q setup, hold times
Clk=1 necessary to successfully
latch the input
Q
S

0
Holds D when
clock goes low
D
D
Characteristic Equation:
Q+ = D
Negative edge-triggered FF
when clock is high
Sequential Switching Network
Edge-Triggered Flip-Flops
Step-by-step analysis

D 0 4
D D

D 3 D

R R
Q 6 Q
Clk=0 Clk=0

Q 5 Q
D S D S

D 2 D

D D'
D 1 0

D' ≠ D

Negative edge-triggered FF Negative edge-triggered FF


when clock goes high-to-low when clock is low
data is latched data is held
Sequential Switching Network
• Edge-Triggered Flip-Flops

R Q R Q

D
S Q 0 S Q
R Q R Q

Clk=1 Clk=0
S Q S Q
0 D
R Q R Q

D S Q D S Q

R Q

S Q
0/1
R Q

Clk=0
S Q
0/1 Q 1/0
R

D’ S Q
Sequential Switching Networks
• Edge-Triggered Flip-Flops
– D Flip-Flop
PRE (preset)
– J-K Flip-Flop

D Q J Q J Q

asynchronous
C C C
input
Q K Q K Q

CLR (clear)
– Toggle Flip-Flop
» Formed from J-K with both inputs wired together

T J Q

Clk C

K Q
Timing Methodologies
Cascaded Flip-Flops and Setup/Hold/Propagation Delays

Shift Register IN Q0 Q1
D Q D Q
New value to first stage
C Q C Q
while second stage
obtains current value CLK
of first stage

100

In
Correct Operation, Q0
assuming positive
Q1
edge triggered FF
Clk
Timing Methodologies
Cascaded Flip-Flops and Setup/Hold/Propagation Delays
Why this works:
Propagation delays far exceed hold times;
Clock period exceeds propagation delay + setup time

This guarantees following stage will latch current value


before it is replaced by new value

Assumes infinitely fast distribution of the clock

In
Tsu Tsu
20 ns 20 ns
Q0 Timing
Timingconstraints
constraints
guarantee
guaranteeproper
proper
T plh T plh operation
operationof
of
13 ns 13 ns cascaded components
Q1 cascaded components

Clk
Th Th
5 ns 5 ns
Timing Methodologies
Narrow Width Clocking versus Multiphase Clocking
Level Sensitive Latches vs. Edge Triggered Flip-Flops
Latches use fewer gates to implement a memory function

Less complex clocking with edge triggered devices

CMOS Dynamic Storage Element


\Clk2
Feedback path broken by two
phases of the clock
\(LD • Clk1)
(just like master/slave idea!)
Clk2
A Z 8 transistors to implement memory function

LD•Clk1 but requires two clock signals constrained


to be non-overlapping

Edge-triggered D-FF: 6 gates (5 x 2-input, 1 x 3-input) = 26 transistors!


Timing Methodologies
Narrow Width Clocking for Systems with Latches for State

Generic Block Diagram


for Clocked Sequential S
System t
Combinational
a
logic
state implemented by t
latches or edge-triggered FFs e

Clock

Two-sided Constraints:
must be careful of very fast signals as well as very slow signals!

Clock Width < fastest propagation through comb. logic


plus latch prop delay

Clock Period > slowest propagation through comb. logic


(rising edge to rising edge)
Timing Methodologies
Two Phase Non-Overlapped Clocking

Clock Waveforms: Ph1


must never overlap!

only worry about slow signals Ph2

Ph1 Ph1 Ph2 Ph2


Embedding CMOS storage
element into Clocked Sequential
Logic
Combinational
Logic 1 Note that Combinational Logic
can be partitioned into two
pieces

C/L1: inputs latched and stable


by end of phase 1; compute
Combinational between phases, latch outputs
Logic 2 by end of phase 2

C/L2: just the reverse


Timing Methodologies
Generating Two-Phase Non-Overlapping Clocks

Single reference clock


Phase 1 high while clock is low

Phase 2 high while clock is high

Phase X cannot go high until


phase Y goes low!

100

Clk
Phase 1

Phase 2

Non-overlap time can be increased by increasing the delay on


the feedback path
Timing Methodologies
The Problem of Clock Skew
Correct behavior assumes next state of all storage elements
determined by all storage elements at the same time

Not possible in real systems!


logical clock driven from more than one physical circuit with
timing behavior
different wire delay to different points in the circuit

Effect of Skew on Cascaded Flip-Flops:


FF0 samples IN FF1 samples Q0
100

In
CLK2 is a delayed
Q0 version of CLK1
Q1
Clk1
Clk2

Original State: Q0 = 1, Q1 = 1, In = 0
Because of skew, next state becomes: Q0 = 0, Q1 = 0,
not Q0 = 0, Q1 = 1
Realizing Circuits with Different Kinds of Flip-Flops
• Choosing a Flip-Flop
– R-S Clocked Latch:
» used as storage element in narrow width clocked systems
» its use is not recommended!
» however, fundamental building block of other flip-flop types
– J-K Flip-Flop:
» versatile building block
» can be used to implement D and T FFs
» usually requires least amount of logic to implement next state
function
» but has two inputs with increased wiring complexity
» because of 1's catching, never use master/slave J-K FFs
» edge-triggered varieties exist
– D Flip-Flop:
» minimizes wires, much preferred in VLSI technologies
» simplest design technique
» best choice for storage registers
– T Flip-Flop:
» doesn't really exist, constructed from J-K FFs
» usually best choice for implementing counters
– Preset and Clear inputs highly desirable!!
Realizing Circuits with Different Kinds of Flip-Flops
Characteristic Equations
R-S: Q+ = S + R Q Derived from the K-maps
for Q+ = f(Inputs, Q)
D: Q+ = D
E.g., J=K=0, then Q+ = Q
J-K: Q+ = J Q + K Q J=1, K=0, then Q+ = 1
J=0, K=1, then Q+ = 0
T: Q+ = T Q + T Q J=1, K=1, then Q+ = Q

Implementing One FF in Terms of Another

Q K
J Q
C D Q
D
K Q J
C Q

D implemented with J-K J-K implemented with D


Realizing Circuits with Different Kinds of Flip-Flops
Design Procedure
Excitation Tables: What are the necessary inputs to cause a
particular kind of change in state?
Q Q+ R S J K T D
0 0 X 0 0 X 0 0
0 1 0 1 1 X 1 1
1 0 1 0 X 1 1 0
1 1 0 X X 0 0 1 D
Q 0 1
Implementing D FF with a J-K FF: 0 0 1
1) Start with K-map of Q+ = f(D, Q)
1 0 1
2) Create K-maps for J and K with same inputs (D, Q)
Q+ = D
3) Fill in K-maps with appropriate values for J and K
to cause the same state changes as in the original K-map
D D
Q 0 1 Q 0 1
E.g., D = Q = 0, Q+ = 0
then J = 0, K = X 0 0 1 0 X X

1 X X 1 1 0

J= D K =D
Realizing Circuits with Different Kinds of Flip-Flops
Design Procedure (Continued)
Implementing J-K FF with a D FF:
1) K-Map of Q+ = F(J, K, Q)

2,3) Revised K-map using D's excitation table


its the same! that is why design procedure with D FF is simple!

JK J
Q 00 01 11 10
0 0 0 1 1
1 1 0 0 1

K
Q+ = D = JQ + KQ
Resulting equation is the combinational logic input to D
to cause same behavior as J-K FF. Of course it is identical
to the characteristic equation for a J-K FF.
Edge-Triggered Flip-Flops
• Positive Edge-Triggered D Flip-Flop (74LS74)

\PRE

\CLR Q

CLK \Q

D
Edge-Triggered Flip-Flops
• Positive Edge-Triggered J-K Flip-Flop (74LS109)

\PRE

\CLR Q

CLK \Q

\K
Flip-Flop Applications
• Parallel Data Storage
– 4-bit register

D0 D Q Q0
C
R

D1 D Q Q1
C
R

D2 D Q Q2
C
R

D3 D Q Q3
CLK C
R
CLR
Flip-Flop Applications
• Frequency Division

J Q J Q J Q fout
fin 1kHz
C C C
8kHz QA QB
K K K

fin
QA
QB
fout
Flip-Flop Applications
• Counting

J Q J Q J Q
Qc
CLK C C C
QA QB
K K K

CLK
QA
QB
QC

0 1 2 3 4 5 6 7 0
Multivibrator
• Bistable multivibrator
VCC
– two stable states
– latch, flip-flop
• Monostable multivibrator
– one stable state 5kΩ
– one shot Threshold
+
• Astable multivibrator -
Control
– no stable state voltage R
– oscillator Q
5kΩ S Output
• 555 timer
+
Trigger -

Discharge

5kΩ

GND Reset
Multivibrator
• 555 timer
VCC
– Monostable operation

5kΩ
R1
+
tW
tW = 1.1R1C1 -

R
Q
5kΩ S Output
+
-

C1 5kΩ

GND Reset
Multivibrator
• 555 timer
VCC
– Astable operation

5kΩ
R1
+
-
f = 1.44/(R1+2R2)C1
R
Q
duty cycle = (R1+R2)/(R1+2R2) 5kΩ S Output
+
-

R2

2/3VCC 5kΩ

1/3VCC
C1

GND Reset