UC1841 UC2841 UC3841
Programmable, Off-Line, PWM Controller
• • • • • • • • • • • • • • All Control, Driving, Monitoring, and Protection Functions Included Low-current, Off-line Start Circuit Voltage Feed Forward or Current Mode Control Guaranteed Duty Cycle Clamp PWM Latch for Single Pulse per Period Pulse-by-Pulse Current Limiting Plus Shutdown for Over-Current Fault No Start-up or Shutdown Transients Slow Turn-on Both Initially and After Fault Shutdown Shutdown Upon Over- or Under-Voltage Sensing Latch Off or Continuous Retry After Fault PWM Output Switch Usable to 1A Peak Current 1% Reference Accuracy 500kHz Operation 18 Pin DIL Package
The UC1841 family of PWM controllers has been designed to increase the level of versatility while retaining all of the performance features of the earlier UC1840 devices. While still optimized for highly-efficient bootstrapped primary-side operation in forward or flyback power converters, the UC1841 is equally adept in implementing both low and high voltage input DC to DC converters. Important performance features include a low-current starting circuit, linear feed-forward for constant volt-second operation, and compatibility with either voltage or current mode topologies. In addition to start-up and normal regulating PWM functions, these devices include built in protection from over-voltage, under-voltage, and over-current fault conditions with the option for either latch-off or automatic restart. While pin compatible with the UC1840 in all respects except that the polarity of the External Stop has been reversed, the UC1841 offers the following improvements: 1. Fault latch reset is accomplished with slow start discharge rather than recycling the input voltage to the chip. 2. The External Stop input can be used for a fault delay to resist shutdown from short duration transients. 3. The duty-cycle clamping function has been characterized and specified. The UC1841 is characterized for -55°C to +125°C operation while the UC2841 and UC3841 are designed for -25°C to +85°C and 0°to +70°C, respectively.
Note: Positive true logic, latch outputs high with set, reset has priority.
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PLCC-20. .85 -80 4. . . . RT = 20kΩ. RR = 10kΩ. and 0°C to +70°C for the UC3841. these specifications apply for TA = -55°C to +125°C for the UC1841. Pin 2 = 3. SOIC-18 (TOP VIEW) J or N. . . . . +VIN (Pin 15) (Note 2) Voltage Driven . . . . . . . .5V IIN = 20mA 33 4. . . . . . . . . . . .9 -80 4. . . . . . . . . . VIN = 20V. . . . . . . . . . -55°C to +150°C Storage Temperature Range. . . . . . . . . . . Currents are positive-into.5V Stop Input (Pin 4) . 20µJoules Driver Bias Current (Pin 14) . . . . . . . . . . . . . .95 5. . . . . .ABSOLUTE MAXIMUM RATINGS
Supply Voltage. .3 to +5. . . . . . . . Self-limiting PWM Output Voltage (Pin 12) . . . . Pin 13. . 100mA maximum . . negative-out of the specified terminal. . -0.5 to +5. . Note 3: Consult Packaging Section of Databook for thermal limitations and considerations of package. . . . -200mA Reference Output Current (Pin 16) . . .5 10 40 6 14 45 33 4. . . . . 16) . . . . . . Note 2: All pin numbers are referenced to DIL-18 package. . . . . . Steady-State (Pin 12) . . . . DW Package
Comp Start/UV OV Sense Stop Reset CUR Thresh CUR Sense Slow Start RT/CT Ramp VIN Sense PWM Out Ground Drive Bias +VIN Supply 5. . . . . . Internally clamped at 12V Power Dissipation at TA = 25°C (Note 3) . . . . . . +300°C Note 1: All voltages are with respect to ground. . 9-11. . . . . .5V Comparator Inputs (Pins 1. Current Limit Threshold = 200mV.5V VIN = 30V. . CR = . . 20mA VIN Sense Current (Pin 11). . . . . CT = 330pF 45 500 47 50 0. . . . . . . .5 53 1 55 43 500 45 50 0. .001mfd. . . . .15 -100 V mV mV V mA VIN = 30V. . -65°C to +150°C Lead Temperature (Soldering. . . 1000mW Power Dissipation at TC = 25°C (Note 3) . . . . .1 20 30 5. . . . . . .0V REF Inv. . . . . . 2000mW
UC1841 UC2841 UC3841
Operating Junction Temperature . . Input
1 2 3 4 5 7 8 9 10 11 12 13 14 15 17 18 19 20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated. . . . . . 10mA Current Limit Inputs (Pins 6 & 7) . . Pin 2 = 2. .0 10 10 5. . 40V PWM Output Current. . . . LCC-20 (TOP VIEW) Q or L Package
PACKAGE PIN FUNCTIONS FUNCTION PIN
DIL-18. . . . . . . . . . . . . . . +32V Current Driven.9 5. . . 7. . CT = . . . . . . 400mA PWM Output Peak Energy Discharge . . -0. . . . . . . . . . . . .001mfd. . . . . . . . .
UC1841 / UC2841 PARAMETER Power Inputs Start-Up Current Operating Current Supply OV Clamp Reference Section Reference Voltage Line Regulation Load Regulation Temperature Stability Short Circuit Current Oscillator Nominal Frequency Voltage Stability Temperature Stability Maximum Frequency TJ = 25°C VIN = 8 to 30V Over Operating Temperature Range RT = 2kΩ. TA = TJ. . .5 55 1 57 kHz % kHz kHz TJ = 25°C VIN = 8 to 30V IL = 0 to 10mA Over Operating Temperature Range VREF = 0. . . . . . . Input N. . . . . . . . . . . .5 10 40 6 14 45 mA mA V TEST CONDITIONS MIN TYP MAX MIN UC3841 TYP MAX UNITS
. -25°C to +85°C for the UC2841.0 10 10 5. 10 sec) .05 15 20 5. . .1 -100 4. . . . . -50mA Slow-Start Sink Current (Pin 8) .I. . . . . TJ = 25°C 4. . .
Current Limit Threshold = 200mV.0 0.5 to 5.0 5 430 -5 3.2 1.2 0. Pin 7 to 12.1 300 95 52 0.2V RSENSE to VREF = 10k IOUT = 20mA IOUT = 200mA VOUT = 40V Pin 8 to Pin 12. Stop Threshold Error Latch Activate Current Pins 2.4 4.0 2.9 0.5 2.UC1841 UC2841 UC3841 ELECTRICAL CHARACTERISTICS: Unless otherwise stated.2 -4.5 2 1 10 5 0. these specifications apply for TA = -55°C to +125°C for the UC1841.8 3.5 -14 -0.0 400 -0. AVOL = 0dB TJ = 25°C.2 10 500 4 42 47 0.5 5 2 0. 3.0 10 440 -5 3. Ramp Peak < 4.9 -11 -.2 10 500 % % V V µA ns ∆VO= 1 to 3V Minimum Total Range VCM = 1.2 0.VOH Driver Bias Leakage Slow-Start Saturation Slow-Start Leakage Current Control Current Limit Offset Current Shutdown Offset Input Bias Current Common Mode Range* VB = 0V IS = 10mA VS = 4.4 200 360 170 0.0 230 2.5 2.0 400 V µA µA µA V µA V µA V µA mV mV µA V ns Minimum Total Continuous Range.5 VCM = 5.5 60 0.001mfd. Minimum Ramp Current.1 300 95 52 0.4 -200 3 -10 0. RR = 10kΩ.0 -1. 5 = 10V Pin 2 = 2.1 0.5V
Current Limit Delay* TJ = 25°C.3 3. RL = 1kΩ 4 42 47 0.2 -4.2 1.0 220 2.
.4 -200 3 -10 0.4 4.9 -11 -.001mfd.5 mV µA µA dB V dB dB mA MHz V/µs Clamping Level ISENSE = -10µA ISENSE = 1.1 200 1.95 0.8 2. 5 Pins 3.3 70 70 80 80 -4 2 0.8 -10 1 66 3.8 2. and 0°C to +70°C for the UC3841.6 -120 2 -0.0 -1. CT = .4 2.0mA -0.6 -120 2 -0.95 0. Maximum Ramp Valley Ramp Peak Error Amplifier Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain Output Swing (Max.100mV) CMRR PSRR Short Circuit Current Gain Bandwidth* Slew Rate* PWM Section Continuous Duty Cycle Range* (other than zero) 50% Duty Cycle Clamp Output Saturation Output Leakage Comparator Delay* Sequencing Functions Comparator Thresholds Input Bias Current Input Leakage Start/UV Hysteresis Current Ext.0 2.4 200 400 -2 3.4 2.3 70 70 80 80 -4 2 0. -25°C to +85°C for the UC2841.1 0.7 0. TA = TJ.1 200 1.2 0.1 0 400 -2 3.5V Pin 4 Pin 4 = 0V. Output ≤ Ramp Peak .5V VIN = 8 to 30V VCOMP = 0V TJ = 25°C.7 0. 5 = 0V Pins 3. TJ = 25°C.8 3.1 0 370 Pin 7 = 0V -0. AVCL = 0dB 1 60 0.8 -10 66 3. VIN = 20V.3 3.0 0.6 4.5 -14 µA mA V V TEST CONDITIONS UC1841 / UC2841 MIN TYP MAX MIN UC3841 TYP MAX UNITS
Driver Bias Saturation Voltage.5 0.0V 0.9 0. Pin 3 > 3V 170 0. CR = . RT = 20kΩ. RL = 1k * These parameters are guaranteed by design but not 100% tested in production. IB = -50mA VIN .6 4.
PARAMETER Ramp Generator Ramp Current.2 0.
Terminates the PWM output pulse when set by inputs from either the PWM comparator. the pulse-by-pulse current limit comparator. Can also be used as an alternate maximum duty cycle clamp with an external voltage divider. Error Latch
2. Frequency = 2.
SEQUENCING FUNCTIONS 1. Clamps low to hold PWM OFF. When set by momentary input.2V. 100mA maximum current. Tracking 3. PWM Output Switch
CR is normally selected ≤ CT and its value will have some effect upon valley voltage. Error Amplifier
4.4V (typically 1. CR terminal can be used as an input port for current mode control. Slow Start
PROTECTION FUNCTIONS 1. and Driver Bias OFF. Supplies drive current to external power switch to provide turn-on bias. When sense voltage rises to 400mV (typical) above threshold. Conventional operational amplifier for closed-loop gain and phase compensation. Current Limiting
3. OV > 3. PWM Latch
7. With Pin 5 > 3. A capacitor here will slow the action of the error latch for transient protection by providing a typical delay of 13ms/µF. A voltage less than 0. With a decreasing voltage. a shutdown signal is sent to Error Latch. Start/UV Sense
2. this latch insures immediate PWM shutdown and hold off until reset. The output is held low by the slow start voltage at turn on in order to minimize overshoot. 40V clamp zener for chip OV protection. Upon release.8V will defeat the error latch and prevent shutdown.0V reference for internal usage only with nominal accuracy of ± 2%. it generates a turn-off command at a lower level separated by a 200µA hysteresis current. With an increasing voltage. External Stop
.8V. A voltage over 1. Error Latch will remain set. Error Latch resets when slow start voltage falls to 0. Transistor capable of sinking current to ground which is off during the PWM on-time and turns on to terminate the power pulse.4V if Reset Pin 5 < 2. Ramp Generator Develops a linear ramp with a slope defined externally by KC
where KC is a first order correction factor ≈ 0. Inputs to Error Latch are: a. unity-gain stable.0V for internal and external usage to 50mA.2V (typically 3V) b. Oscillator Generates a fixed-frequency internal clock from an external RT and CT. Reference Generator
5. Current Sense 400mV over threshold (typical).UC1841 UC2841 UC3841 FUNCTIONAL DESCRIPTION
PWM CONTROL 1. Disables most of the chip to hold internal current consumption low.6V) c. Limiting the minimum value for ISENSE will establish a maximum duty cycle clamp. PWM Comparator 6. rises with rate controlled by RSCS for slow increase of output pulse width. Differential input comparator terminates individual output pulses each time sense voltage rises above threshold. Stop > 2. Drive Switch 3. it generates a turn-on signal and releases the slow-start clamp at a start threshold. Generates output pulse which starts at termination of clock pulse and ends when the ramp input crosses the lowest of two positive inputs. Resets with each internal clock pulse.2V will set the Error Latch and hold the output off. or the error latch. Precision 5. Driver Bias 4. Current capacity is 400mA saturated with peak capacitance discharge in excess of one amp. until input voltage reaches start threshold. dv sense voltage = RRCR dt
3. Low output impedance.3 log (CT X 1012).
UC1841 UC2841 UC3841
Start/UV Hysteresis PWM Output-Saturation Voltage
PWM Output Minimum Pulse Width
Error Amplifier Open Loop Gain and Phase
are protective snubbers or additional interface circuitry which may be required by the choice of the highvoltage switch. Q1.
Not shown. or the application.2R1 = 12V R2 + R3
R1 + R2 + R3 UV Fault Voltage = 3 = 8V R2 + R3 R1 + R2 + R3 OV Fault Voltage = 3 = 32V R3
Current Limit = 200mV Current Fault Voltage = 600mV Duty Cycle Clamp = 50%
FLYBACK APPLICATION (A) In this application (see Figure A. N2. In addition to providing constant current drive pulses to the PIC661 power switch. however.UC1841 UC2841 UC3841 OPEN-LOOP TEST CIRCUIT
Nominal Frequency =
1 = 50 kHz RTCT
R1 + R2 + R3 Start Voltage = 3 +0. Control power is provided by RIN and CIN during start-up. the UC1841 is an ideal control circuit for DC to DC converters such as the buck regulator shown in Figure B opposite. next page). complete control is maintained on the primary side. for efficient operation after start. The error amplifier loop is closed to regulate the DC voltage from N2 with other outputs following through their magnetic coupling − a task made even easier with the UC1841’s feed−forward line regulation. An additional feature is the ability to
. and by a primary-referenced low voltage winding. one example of power transistor interfacing is provided on the following page. this circuit has full fault protection and high speed dynamic line regulation due to its feedforward capability. An extension to this application for more precise regulation would be the use of the UC1901 Isolated Feedback Generator for direct closed-loop control to an output.
REGULATOR APPLICATION (B) With the addition of a level shifting transistor. Qs.
UC1841 UC2841 UC3841
Figure A. Overall Schematic For A 300 Watt. UC1841 Programmable PWM Controller In A Simplified Flyback Regulator
Figure B. Off-line Power Converter Using The UC3841 For Control 7
Resistor R1 sets a 400mV offset across R2 (assuming R2 > RCS) so that both the Error Amplifier and Fault Shutdown can force the current completely to zero. R1 is used in conjunction with CR (not shown) to establish a minimum ramp charging current such that the ramp voltage reaches 4.6 4 l R (VARIAB ) ≈ + − R1 R2 R3
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. (603) 424-2410 • FAX (603) 424-3460
. • MERRIMACK.UC1841 UC2841 UC3841 ERROR LATCH INTERNAL CIRCUITRY PROGRAMMABLE SOFT START AND RESTART DELAY CIRCUIT
The Error Latch consists of Q5 and Q6 which. NH 03054 TEL. The purpose of Q1 is to provide an increasing ramp current above a threshold established by R2 and R3 such that the duty cycle is further reduced with increasing VIN. An activation time delay can be provided with an external capacitor on Pin 4 in conjunction with the ≈ 100µA collector current from Q4. or by a high signal on Pin 4. current sensing is ground referenced through RCS.6 5. In this mode.
CURRENT MODE CONTROL
VOLTAGE FEED-FORWARD COMBINED WITH MAXIMUM DUTY-CYCLE CLAMP
In this circuit. when both on. this point can also serve as a current sense port for current mode control.2V at the required maximum output pulse width. The minimum ramp current is: lR(MIN) = VREF − VIN SENSE 4V ≈ R1 R1
Since Pin 10 is a direct input to the PWM comparator. R2 is also used along with CF as a small filter to attenuate leadingedge spikes on the load current waveform. Reset is accomplished by either the Reset comparator or a low signal on Pin 4. current limiting can be accomplished by divider R3/R4 which forms a clamp overriding the output of the Error Amplifier. turns off the PWM Output and pulls the Slow-Start pin low. This latch is set by either the Over-Voltage or Current Shutdown comparators.
The threshold where VIN begins to add extra ramp current is: R2 + R3 VIN ≈ 5.6V R3 Above the threshold. the ramp current will be: VIN − 5. In this application.
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