You are on page 1of 571

Master Index 1

Product Selection Guide 2

The “Better” Program 3

B and UB Series Family Data 4

CMOS Handling and Design Guidelines 5

Data Sheets 6

CMOS Reliability 7

Equivalent Gate Count 8

Packaging Information 9
Including Surface Mounts
DATA CLASSIFICATION

Product Preview
This heading on a data sheet indicates that the device is in the formative
stages or in design (under development). The disclaimer at the bottom of the
first page reads: “This document contains information on a product under
development. Motorola reserves the right to change or discontinue this
product without notice.”

Advance Information
This heading on a data sheet indicates that the device is in sampling,
preproduction, or first production stages. The disclaimer at the bottom of the
first page reads: “This document contains information on a new product.
Specifications and information herein are subject to change without notice.”

Fully Released
A fully released data sheet contains neither a classification heading nor a
disclaimer at the bottom of the first page. This document contains information
on a product in full production. Guaranteed limits will not be changed without
written notice to your local Motorola Semiconductor Sales Office.

ii MOTOROLA CMOS LOGIC DATA


CMOS LOGIC
DATA

Prepared by
Technical Information Center

This book presents technical data for the broad line of CMOS logic integrated
circuits and demonstrates Motorola’s continued commitment to Metal–Gate
CMOS. Complete specifications are provided in the form of data sheets. In addi-
tion, a Product Selector Guide and a Handling and Design Guidelines chapter have
been included to familiarize the user with these circuits.
Motorola reserves the right to make changes without further notice to any prod-
ucts herein to improve reliability, function or design. Motorola does not assume any
liability arising out of the application or use of any product or circuit described here-
in; neither does it convey any license under its patent rights nor the rights of others.
Motorola products are not designed, intended, or authorized for use as compo-
nents in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Motorola products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Motorola and its offi-
cers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part. Motorola and are
registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment
Opportunity/Affirmative Action Employer.

Series C
 MOTOROLA INC., 1991
Previous Edition  1990
Printed in U.S.A. “All Rights Reserved”

MOTOROLA CMOS LOGIC DATA iii


iv MOTOROLA CMOS LOGIC DATA
Master Index 1
MASTER INDEX
This index includes Motorola’s entire MC14000 series CMOS products, although this book contains
data sheets for Logic Devices only. Data sheets for devices in the CMOS/NMOS Special Functions Data
book (DL130) are designated in the page number column as SF.
Products which have been cancelled are designated in the page number column as —.

Device Function Page


MC14000UB Dual 3–Input NOR Gate Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
MC14001B Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14001UB Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14002B Dual 4–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14002UB Dual 4–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14006B 18–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
MC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
MC14008B 4–Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27
MC14011B Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14011UB Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14012B Dual 4–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14012UB Dual 4–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14013B Dual D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–33
MC14014B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37
MC14015B Dual 4–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–41
MC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–47
MC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–54
MC14018B Presettable Divide–by–N Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–59
MC14020B 14–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–63
MC14021B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37
MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–67
MC14023B Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14023UB Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14024B 7–Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–72
MC14025B Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14025UB Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14027B Dual J–K Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–77
MC14028B BCD–to–Decimal/Binary–to–Octal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 6–81
MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 6–86
MC14032B Triple Serial Adder (Positive Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–92
MC14034B 8–Bit Universal Bus Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–97
MC14035B 4–Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–104
MC14038B Triple Serial Adder (Negative Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–92
MC14040B 12–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–108
MC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–112
MC14043B Quad NOR R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–116
MC14044B Quad NAND R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–116
MC14046B Phase–Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–120

CHAPTER 1 MOTOROLA CMOS LOGIC DATA


1–2
Device Function Page
MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–125
MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–129
MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–125
MC14051B 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . 6–133
MC14052B Dual 4–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . 6–133
MC14053B Triple 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . 6–133
MC14060B 14–Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–140
MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–144
MC14067B 16–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . 6–150
MC14068B 8–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14069UB Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–158
MC14070B Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–160
MC14071B Quad 2–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14072B Dual 4–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14073B Triple 3–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14075B Triple 3–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14076B Quad D–Type Register with Tri–State Outputs . . . . . . . . . . . . . . . . . . . . . . 6–162
MC14077B Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–160
MC14078B 8–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14081B Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14082B Dual 4–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14093B Quad 2–Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–166
MC14094B 8–Stage Shift/Store Register with Tri–State Outputs . . . . . . . . . . . . . . . . . 6–170
MC14097B Dual 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . 6–150
MC14099B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–174
MC14106B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–180
MC14160B Synchronous Presettable BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–184
MC14161B Synchronous Presettable 4–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . 6–184
MC14162B Synchronous Presettable BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–184
MC14163B Synchronous Presettable 4–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . 6–184
MC14174B Hex D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–193
MC14175B Quad D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–197
MC14194B 4–Bit Universal Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–201
MC14415 Quad Precision Timer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–205
MC14433 31/2 Digit A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14442 Microprocessor–Compatible A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14443 6–Channel A/D Converter Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF

MOTOROLA CMOS LOGIC DATA CHAPTER 1


1–3
Device Function Page
MC14444 Microprocessor–Compatible A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14447 6–Channel A/D Converter Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14457 Remote Control Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14458 Remote Control Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14460 Automotive Speed Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14466 Low Cost Smoke Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14467–1 Low Cost Smoke Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14468 Interconnectable Smoke Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14469 Addressable Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . SF
MC14490 Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–210
MC14495–1 Hexadecimal–to–7 Segment Latch/Decoder ROM/Driver . . . . . . . . . . . . . . . SF
MC14497 PCM Remote Control Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14499 7–Segment LED Display Decoder/Driver with Serial Interface . . . . . . . . . . . SF
MC14500B Industrial Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–217
MC14501UB Triple Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–223
MC14502B Strobed Hex Inverter/Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–227
MC14503B Hex 3–State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–231
MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . 6–235
MC14506UB Dual Expandable AOI Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–238
MC14508B Dual 4–Bit Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–243
MC14510B Presettable BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–248
MC14511B BCD–to–7–Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . 6–256
MC14512B 8–Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–262
MC14513B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . 6–266
MC14514B 4–Bit Transparent Latch/4–to–16 Line Decoder (High) . . . . . . . . . . . . . . . 6–274
MC14515B 4–Bit Transparent Latch/4–to–16 Line Decoder (Low) . . . . . . . . . . . . . . . 6–274
MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–280
MC14517B Dual 64–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–288
MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–292
MC14519B 4–Bit AND/OR Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–297
MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–292
MC14521B 24–Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–301
MC14522B Presettable BCD Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–307

CHAPTER 1 MOTOROLA CMOS LOGIC DATA


1–4
Device Function Page
MC14526B Presettable 4–Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–307
MC14527B BCD Rate Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–315
MC14528B Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–321
MC14529B Dual 4–Channel Analog Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–327
MC14530B Dual 5–Input Majority Logic Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–333
MC14531B 12–Bit Parity Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–338
MC14532B 8–Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–341
MC14534B 5 Cascaded BCD Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–347
MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–354
MC14538B Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–365
MC14539B Dual 4–Channel Data Selector/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . 6–373
MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–377
MC14543B BCD–to–7–Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . 6–382
MC14544B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . 6–387
MC14547B High–Current BCD–to–7–Segment Decoder/Driver . . . . . . . . . . . . . . . . . 6–393
MC14549B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–398
MC14551B Quad 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . 6–405
MC14553B 3–Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–412
MC14554B 2 X 2–Bit Parallel Binary Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–418
MC14555B Dual Binary to 1–of–4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . 6–422
MC14556B Dual Binary to 1–of–4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . 6–422
MC14557B 1–to–64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . 6–425
MC14558B BCD–to–7 Segment Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–429
MC14559B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–398
MC14560B NBCD Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–434
MC14561B 9’s Complementer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–445
MC14562B 128–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–451
MC14566B Industrial Time Base Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–455
MC14568B Phase Comparator and Programmable Counters . . . . . . . . . . . . . . . . . . . 6–461
MC14569B Programmable Dual 4–Bit Binary/BCD Down Counter . . . . . . . . . . . . . . . 6–471
MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–481
MC14573 Quad Programmable Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14574 Quad Programmable Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14575 Programmable Dual Op Amp/Dual Comparator . . . . . . . . . . . . . . . . . . . . . . . . SF
MC14580B 4 X 4 Multiport Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–484
MC14581B 4–Bit Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–489
MC14582B Look–Ahead Carry Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–494

MOTOROLA CMOS LOGIC DATA CHAPTER 1


1–5
Device Function Page
MC14583B Dual Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–498
MC14584B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–504
MC14585B 4–Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–507
MC14597B 8–Bit Bus–Compatible Counter Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–511
MC14598B 8–Bit Bus–Compatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . 6–511
MC14599B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–174
MC144110 Hex D/A Converter with Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC144111 Quad D/A Converter with Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145000 48–Segment Multiplexed LCD Driver (Master) . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145001 44–Segment Multiplexed LCD Driver (Slave) . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145026 Remote Control Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145027 Remote Control Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145028 Remote Control Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145029 Remote Control Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145040 Analog–to–Digital Converter with Serial Interface . . . . . . . . . . . . . . . . . . . . . . SF
MC145041 Analog–to–Digital Converter with Serial Interface . . . . . . . . . . . . . . . . . . . . . . SF
MC145104 PLL Frequency Synthesizer (Not Recommended for New Designs) . . . . . . SF
MC145106 PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145107 PLL Frequency Synthesizer (Not Recommended for New Designs) . . . . . . SF
MC145109 PLL Frequency Synthesizer (Not Recommended for New Designs) . . . . . . SF
MC145112 PLL Frequency Synthesizer (Not Recommended for New Designs) . . . . . . SF
MC145143 PLL Frequency Synthesizer (Not Recommended for New Designs) . . . . . . SF
MC145144 4–Bit Data Bus Input PLL Frequency Synthesizer
(Not Recommended for New Designs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145145–1 4–Bit Data Bus Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . SF
MC145146–1 4–Bit Data Bus Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . SF
MC145151–1 Parallel Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145152–1 Parallel Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145155–1 Serial Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145156–1 Serial Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145157–1 Serial Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145158–1 Serial Input PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SF
MC145159–1 Serial Input PLL Frequency Synthesizer with Analog Phase Detector . . . . . SF
MC145453 33–Segment LCD Driver with Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . SF

CHAPTER 1 MOTOROLA CMOS LOGIC DATA


1–6
Product Selection Guide 2
CMOS Selection Guide by Function

Device Function Page

NAND Gates
MC14011B Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14011UB Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14093B Quad 2–Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–166
MC14023B Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14023UB Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14012B Dual 4–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14012UB Dual 4–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14068B 8–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

NOR Gates
MC14001B Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14001UB Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14025B Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14025UB Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14000UB Dual 3–Input NOR Gate Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
MC14002B Dual 4–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14002UB Dual 4–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
MC14078B 8–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

AND Gates
MC14081B Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14073B Triple 3–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14082B Dual 4–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

OR Gates
MC14071B Quad 2–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14075B Triple 3–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
MC14072B Dual 4–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

Complex Gates
MC14070B Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–160
MC14077B Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–160
MC14501UB Triple Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–223
MC14506UB Dual Expandable AOI Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–238
MC14530B Dual 5–Input Majority Logic Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–333
MC14519B 4–Bit AND/OR Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–297
MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–481

Inverters/Buffers/Level Translator
MC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–125
MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–129
MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–125
MC14069UB Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–158
MC14502B Strobed Hex Inverter/Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–227
MC14503B Hex 3–State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–231
MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . 6–235
MC14584B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–504

CHAPTER 2 MOTOROLA CMOS LOGIC DATA


2–2
Device Function Page

Decoders/Encoders
MC14028B BCD–to–Decimal/Binary–to–Octal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 6–81
MC14511B BCD–to–7–Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . 6–256
MC14513B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . 6–266
MC14543B BCD–to–7–Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . 6–382
MC14544B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . 6–387
MC14547B High–Current BCD–to–7–Segment Decoder/Driver . . . . . . . . . . . . . . . . . 6–393
MC14558B BCD–to–7–Segment Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–429
MC14514B 4–Bit Transparent Latch/4–to–16 Line Decoder (High) . . . . . . . . . . . . . . . 6–274
MC14515B 4–Bit Transparent Latch/4–to–16 Line Decoder (Low) . . . . . . . . . . . . . . . 6–274
MC14532B 8–Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–341
MC14555B Dual Binary to 1–of–4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . 6–422
MC14556B Dual Binary to 1–of–4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . 6–422

Multiplexers/Demultiplexers/Bilateral Switches
MC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–47
MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–144
MC14551B Quad 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . 6–405
MC14053B Triple 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . 6–133
MC14052B Dual 4–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . 6–133
MC14097B Dual 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . 6–150
MC14529B Dual 4–Channel Analog Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–327
MC14539B Dual 4–Channel Data Selector/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . 6–373
MC14067B 16–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . 6–150
MC14051B 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . 6–133
MC14512B 8–Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–262
MC14519B 4–Bit AND/OR Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–297

Schmitt Triggers
MC14093B Quad 2–Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–166
MC14583B Dual Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–498
MC14106B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–180
MC14584B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–504

Flip–Flops/Latches
MC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–112
MC14043B Quad NOR R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–116
MC14044B Quad NAND R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–116
MC14076B Quad D–Type Register with Tri–State Outputs . . . . . . . . . . . . . . . . . . . . . . 6–162
MC14175B Quad D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–197
MC14013B Dual D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–33
MC14027B Dual J–K Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–77
MC14508B Dual 4–Bit Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–243
MC14174B Hex D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–193
MC14099B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–174
MC14597B 8–Bit Bus–Compatible Counter Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–511
MC14598B 8–Bit Bus–Compatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . 6–511
MC14599B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–174

MOTOROLA CMOS LOGIC DATA CHAPTER 2


2–3
Device Function Page

Shift Registers
MC14015B Dual 4–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–41
MC14517B Dual 64–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–288
MC14562B 128–Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–451
MC14557B 1–to–64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . 6–425
MC14006B 18–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
MC14014B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37
MC14021B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37
MC14034B 8–Bit Universal Bus Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–97
MC14094B 8–Stage Shift/Store Register with Tri–State Outputs . . . . . . . . . . . . . . . . . 6–170
MC14035B 4–Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–104
MC14194B 4–Bit Universal Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–201
MC14549B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–398
MC14559B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–398

Counters
MC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–54
MC14018B Presettable Divide–by–N Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–59
MC14020B 14–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–63
MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–67
MC14024B 7–Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–72
MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 6–86
MC14040B 12–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–108
MC14060B 14–Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–140
MC14160B Synchronous Presettable BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–184
MC14161B Synchronous Presettable 4–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . 6–184
MC14162B Synchronous Presettable BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–184
MC14163B Synchronous Presettable 4–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . 6–184
MC14510B Presettable BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–248
MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–280
MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–292
MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–292
MC14522B Presettable BCD Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–307
MC14526B Presettable 4–Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–307
MC14534B 5 Cascaded BCD Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–347
MC14553B 3–Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–412
MC14566B Industrial Time Base Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–455
MC14569B Programmable Dual 4–Bit Binary/BCD Counter . . . . . . . . . . . . . . . . . . . . . 6–471

Oscillators/Timers
MC14521B 24–Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–301
MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–354
MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–377

Multivibrators
MC14528B Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–321
MC14538B Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–365

CHAPTER 2 MOTOROLA CMOS LOGIC DATA


2–4
Device Function Page

Adders/Comparators
MC14008B 4–Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27
MC14032B Triple Serial Adder (Positive Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–92
MC14038B Triple Serial Adder (Negative Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–92
MC14560B NBCD Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–434
MC14561B 9’s Complementer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–445
MC14582B Look–Ahead Carry Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–494
MC14585B 4–Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–507

ALU/Rate Multipliers
MC14527B BCD Rate Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–315
MC14554B 2 X 2 Bit Parallel Binary Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–418
MC14581B 4–Bit Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–489

Parity Checker
MC14531B 12–Bit Parity Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–338

Memory
MC14580B 4 X 4 Multiport Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–484

Microprocessor/Industrial Control
MC14500B Industrial Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–217

Other Complex Functions


MC14046B Phase–Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–120
MC14415 Quad Precision Timer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–205
MC14490 Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–210
MC14568B Phase Comparator and Programmable Counters . . . . . . . . . . . . . . . . . . . 6–461

MOTOROLA CMOS LOGIC DATA CHAPTER 2


2–5
The “Better” Program 3
   
 
The “BETTER” program is offered on logic only, in dual–in–line plastic packages.

Better Processing — HOW TO ORDER


Standard Product Plus: MC14000B CP D
Part Standard BETTER
Identification Package PROCESSING
Level II (Suffix D) Suffix LEVEL II = SUFFIX D
• 100% burn–in to MIL–STD–883 test conditions — 160
Part Marking
hours at + 125°C or 1.0 eV Arrhenus time/temperature
equivalent. The Standard Motorola part number with the correspond-
ing “BETTER” suffix can be order from your local authorized
• 100% post burn–in functional and dc parametric tests at Motorola distributor or Motorola sales offices. “BETTER”
25°C (or max rated TA at Motorola’s option). Maximum pricing will be quoted as an adder to standard commercial
PDA of 2% (functional) and 5% (DC and functional). product price.

“RAP”
Reliability Audit Program
For Logic Integrated Circuits

1.0 INTRODUCTION all sales offices. Also available is the “Reliability and Quality
Handbook” which contains data for all Motorola Semiconduc-
The Reliability Audit Program developed in March 1977 is
tors (#BR518S).
the Motorola internal reliability audit which is designed to as-
sess outgoing product performance under accelerated stress RAP is a system of environmental and electrical tests per-
conditions. Logic Reliability Engineering has overall respon- formed periodically on randomly selected samples of stan-
sibility for RAP, including updating its requirements, interpret- dard products. Each sample receives the tests specified in
ing its results, administration at offshore locations, and section 2.0. Frequency of testing is specified per internal
monthly reporting of results. These reports are available at document 12MRM15301A.

CHAPTER 3 MOTOROLA CMOS LOGIC DATA


3–2
2.0 RAP TEST FLOW

Pull 500* piece sample from lot following Group A


acceptance.

45* 340 100

INITIAL
SEAL**
OP LIFE
40 HOURS
PTHB PTH*** TEMP CYCLES
48 HRS 48 HRS 40 CYCLES
INTERIM
ELECTRICAL
INTERIM
TEST
OP LIFE
210 HRS (ADDITIONAL)
ADD 460 CYCLES
FINAL
INTERIM INTERIM INTERIM #
ELECTRICAL TEST ELECTRICAL

ADD 500 CYCLES


FINAL
INTERIM*
TEST
PTH OP LIFE #
48 HRS 750 HRS
(ADDITIONAL) (ADDITIONAL)
TEMP CYCLES #
1000 CYCLES
(ADDITIONAL)
FINAL FINAL FINAL #
ELECTRICAL ELECTRICAL ELECTRICAL
(48 HRS) (96 HRS) (1000 HRS)
FINAL
ELECTRICAL
& SEAL**
(2000 CYCLES)

SCRAP SCRAP SCRAP


#One sample per month for FAST, LS, 10H, 10K, MG CMOS, and HSL CMOS.
* PTHB or PTH not required for hermetic products: reduce total sample size to 450 pcs.
** Seal (Fine & Gross Leak) required only for hermetic products.
*** PTH to be used when sockets for PTHB are not available.

3.0 TEST CONDITIONS AND COMMENTS 2. Any indicated failure is first verified and then submitted to
the Product Analysis Lab for detailed analysis.
PTHB — 15 psig/121°C/100% RH at rated VCC or VEE — to 3. Sampling to include all package types routinely.
be performed on plastic encapsulated devices
only. 4. Device types sampled will be by generic type within each
TEMP CYCLING — MIL–STD–883, Method 1010, Condi- logic I/C product family (CMOS, TTL, etc.) and will include
tion C, – 65°C/+ 150°C. all assembly locations (Korea, Philippines, Malaysia, etc.).
5. 16 hrs. PTHB is equivalent to approximately 800 hours of
v
OP LIFE — MIL–STD–883, Method 1005, Condition C
(Power plus Reverse Bias), TA = 145°C. 85°C/85% RH THB for VCC 15 V.
6. Only moisture related failures (like corrosion) are criteria
for failure on PTHB test.
NOTES:
7. Special device specifications (48A’s) for logic products will
1. All standard 25°C dc and functional parameters will be reference 12MRM15301A as source of generic data for
measured Go/No/Go at each readout. any customer required monthly audit reports.

MOTOROLA CMOS LOGIC DATA CHAPTER 3


3–3
B and UB Series Family Data 4
 
       
The CMOS Devices in this volume which have a B or UB Devices with specialized inputs, such as oscillator in-
suffix meet the minimum values for the industry–standard- puts, have unique input specifications.
ized# family specification. These standardized values are
shown in the Maximum Ratings and Electrical Characteris- Input Voltage
tics Tables. In addition to a standard minimum specification The input voltage specification is interpreted as the worst-
for characteristics the B/UB devices feature: case input voltage to produce an output level of “1” or “0”.
This “1” or “0” output level is defined as a deviation from the
• 3–18 volt operational limits
supply (VDD) and ground (VSS) levels. For a 5.0 V supply,
• Capable of driving two low–power TTL loads or one low– this deviation is 0.5 V; for a 10 V supply, 1.0 V; and for 15 V,
power Schottky TTL load over the rated temperature 1.5 V. As an example, in a device operating at a 5.0 V supply,
range the device with the input starting at ground is guaranteed to
• Direct Interface to High–Speed CMOS switch on or before 3.5 V and not to switch up to 1.5 V.
• Maximum input current of ± 1 µA at 15 volt power supply Switching and not switching are defined as within 0.5 V of the
over the temperature range ideal output level for the example with a 5.0 V supply. The
• Parameters specified at 5.0, 10, and 15 volt supply actual switching level referred to the input is between 1.5 V
• Noise margins: B Series and 3.5 V.
1.0 V min @ 5.0 V supply
Noise Margin
2.0 V min @ 10 V supply
The values for input voltages and the defined output devi-
2.5 V min @ 15 V supply
ations lead to the calculated noise margins. Noise margin is
UB Series defined as the difference between V IL or V IH and Vout
0.5 V min @ 5.0 V supply (output deviation). As an example, for a noninverting buffer at
1.0 V min @ 10 V supply V DD = 5.0 volts: V IL = 1.5 volts and Vout = 0.5 volts. There-
1.0 V min @ 15 V supply fore, Noise Margin equals V IL – Vout = 1.0 volt. This figure is
The industry–standardized maximum ratings are shown at useful while cascading stages (See Figure 1). With the input
the bottom of this page. Limits for the static characteristics to the first stage at a worst–case voltage level (V IL = 1.5 V),
are shown in two formats: Table 1 is in the industry format the output is guaranteed to be no greater than 0.5 volts with
and Table 2 is in the equivalent Motorola format. The a 5.0 volt supply. Since the maximum allowable logic 0 for
Motorola format is used throughout this data book. Additional the second stage is 1.5 volts, this 0.5 volt output provides a
specification values are shown on the individual data sheets. 1.0 volt margin for noise to the next stage.
Switching characteristics for the B and UB series devices
Output Drive Current
are specified under the following conditions:
Devices in the B Series are capable of sinking a minimum
Load Capacitance, CL, of 50 pF of 0.36 mA over the temperature range with a 5.0 V supply.
Input Voltage equal to VSS – VDD (Rail–to–Rail swing) This value guarantees that these CMOS devices will drive
Input pulse rise and fall times of 20 ns one low–power Schottky TTL input.
Propagation Delay times measured from 50% point of
input voltage to 50% point of output voltage B Series vs UB CMOS
Three different supply voltages: 5, 10, and 15 V The primary difference between B series and UB series
devices is that UB series gates and inverters are constructed
Exceptions to the B and UB Series Family with a single inverting stage between input and output. The
Specification decreased gain caused by using a single stage results in less
There are a number of devices which have a B or UB suffix noise immunity and a transfer characteristic that is less ideal.
whose inputs and/or outputs vary somewhat from the family The decreased gain is quite useful when CMOS Gates and
specification because of functional requirements. Some inverters are used in a “Linear” mode to form oscillators,
categories of notable exceptions are: monostables, or amplifiers. The decreased gain results in in-
creased stability and a “cleaner” output waveform. In addition
Devices with specialized outputs on the chip, such as to linear operation, the UB gates and inverters offer an in-
NPN emitter–follower drivers or transmission gates, do crease in speed, since only a single stage is involved.
not meet output specifications. The B and UB series, and devices with no suffix can be
#Specifications coordinated by EIA/JEDEC Solid–State Products used interchangeably in digital circuits that interface to other
Council. CMOS devices, such as High–Speed CMOS Logic.

CHAPTER 4 MOTOROLA CMOS LOGIC DATA


4–2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎÎ
ÎÎÎÎ Parameters Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
Î ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin, lout Input or Output Current (DC or Transient), ± 10 mA
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD

ÎÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎÎÎÎ
ÎÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎÎ
Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

5.0 V

VIL = 1.5 V Vout = 0.5 V Vout

FIRST STAGE VIL = 1.5 V SECOND STAGE


(NONINVERTING BUFFER) (NONINVERTING BUFFER)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Figure 1.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS

ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ


ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ Î ÎÎ
Î ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
T
Temp VDD
TLOW*
Limits
+ 25_C THIGH*

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Parameter
P Range (Vdc) Conditions
C di i Min Max Min Max Min Max Units
U i

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
IDD Quiescent Mil 5 0.25 0.25 7.5 µAdc

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Device Current 10 Vin = VSS or VDD 0.5 0.5 15
15 1.0 1.0 30

ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
GATES

ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Comm 5 All valid input 1.0 1.0 7.5 µAdc

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 combinations 2.0 2.0 15
15 4.0 4.0 30

ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Mil 5 1.0 1.0 30 µAdc

ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
VIN = VSS or VDD 2.0
4.0
2.0
4.0
60
120
µAdc

ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
BUFFERS, Comm 5 All valid input 4 4.0 30
FLIP–FLOPS 10 combinations 8 8.0 60

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 16 16.0 120

ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Mil 5 5 5 150 µAdc

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 VIN = VSS or VDD 10 10 300
15 20 20 600

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
MSI
ÎÎÎ
ÎÎÎ
ÎÎÎ
Comm 5 All valid input 20 20 150 µAdc

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 combinations 40 40 300
15 80 80 600

ÎÎÎÎÎÎ
ÎÎÎÎ
VOL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Low–Level
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
All 5 0.05 0.05 0.05 Vdc

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Output Voltage

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
VIN = VSS or VDD
|IO| < 1 µA
0.05
0.05
0.05
0.05
0.05
0.05

ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
VOH High–Level All 5 4.95 4.95 4.95 Vdc
Output Voltage 10 VIN = VSS or VDD 9.95 9.95 9.95

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 |IO| < 1 µA 14.95 14.95 14.95

ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
VIL Input All 5 VO = 0.5V or 4.5V 1.5 1.5 1.5 Vdc
Low Voltage#

ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
10 VO = 1.0V or 9.0V 3.0 3.0 3.0
B Types 15 VO = 1.5V or 13.5V 4.0 4.0 4.0

ÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
|IO| < 1 µA

MOTOROLA CMOS LOGIC DATA CHAPTER 4


4–3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications (continued)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS

ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ


ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ TLOW*
Limits
+ 25_C THIGH*

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Temp VDD
Parameter Range (Vdc) Conditions Min Max Min Max Min Max Units

ÎÎÎÎÎÎÎÎÎÎ
VIL

ÎÎÎÎÎÎÎÎÎÎÎÎ
Input
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
All
ÎÎÎ 5 VO = 0.5V or 4.5V 1.0 1.0 1.0

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ


ÎÎÎ
ÎÎÎ
ÎÎÎ
Low Voltage# 10 VO = 1.0V or 9.0V 2.0 2.0 2.0
UB Types 15 VO = 1.5V or 13.5V 2.5 2.5 2.5

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ |IO| < 1 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIH Input All 5 VO = 0.5V or 4.5V 3.5 3.5 3.5 Vdc
High Voltage#

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ


ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10 VO = 1.0V or 9.0V 7.0 7.0 7.0
B Types 15 VO = 1.5V or 13.5V 11.0 11.0 11.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
|IO| < 1 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIH Input All 5 VO = 0.5V or 4.5V 4.0 4.0 4.0 Vdc
High Voltage# 10 VO = 1.0V or 9.0V 8.0 8.0 8.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
UB Types

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
15 VO = 1.5V or 13.5V 12.5 12.5 12.5

ÎÎÎ
|IO| < 1 µA

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
IOL Output Low Mil 5 VO = 0.4V, mAdc
(Sink) Current VIN = 0 or 5V 0.64 0.51 0.36

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ 10 VO = 0.5V,

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIN = 0 or 10V 1.6 1.3 0.9
VO = 1.5V,

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15
VIN = 0 or 15V 4.2 3.4 2.4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Com 5 VO = 0.4V, mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIN = 0 or 5V 0.52 0.44 0.36
10 VO = 0.5V,

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIN = 0 or 10V 1.3 1.1 0.9
VO = 1.5V,

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15
VIN = 0 or 15V 3.6 3.0 2.4

ÎÎÎÎÎÎÎÎÎÎ
IOH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output High
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Mil
ÎÎÎ VO = 4.6V, mAdc

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ


ÎÎÎ
ÎÎÎ
ÎÎÎ
(Source) Current 5 VIN = 0 or 5V – 0.25 – 0.2 – 0.14
VO = 9.5V,

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
10 VIN = 0 or 10V – 0.62 – 0.5 – 0.35

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VO = 13.5V,
15 VIN = 0 or 15V – 1.8 – 1.5 – 1.1

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
Com

ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5
VO = 4.6V,
VIN = 0 or 5V – 0.2 – 0.16 – 0.12
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VO = 9.5V,
10 VIN = 0 or 10V – 0.5 – 0.4 – 0.3

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VO = 13.5V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 VIN = 0 or 15V – 1.4 – 1.2 – 1.0

ÎÎÎÎ
ÎÎÎÎ
IIN

ÎÎÎÎÎÎ
Input Current

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
Mil

ÎÎÎÎ ÎÎÎ
ÎÎÎ
Comm ÎÎÎ
ÎÎÎ
ÎÎÎ
15
15
VIN = 0 or 15V
VIN = 0 or 15V
± 0.1
± 0.3
± 0.1
± 0.3
± 1.0
± 1.0
µAdc
µAdc

ÎÎÎÎÎÎÎÎÎÎ
Ioz

ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
3–State Output

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Mil
ÎÎÎ
ÎÎÎ 15 VIN = 0 or 15V ± 0.4 ± 0.4 ± 12 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Leakage Current Comm 15 VIN = 0 or 15V ± 1.6 ± 1.6 ± 12 µAdc

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
CIN Input Capacitance All — Any Input 7.5 pF
per unit load
* TLOW = – 55_C for Military temperature range device, – 40°C for Commercial temperature range device.
THIGH = + 125_C for Military temperature range device, + 85_C for Commercial temperature range device.
#Applies for Worst Case input combinations.

CHAPTER 4 MOTOROLA CMOS LOGIC DATA


4–4
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Table 2. Motorola Format for CMOS Industry B and UB Series Specifications

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Characteristic
Ch i i ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Symbol
S b l
VDD
Vdc Min
– 55_C
Max Min
25_C
Max
+ 125_C
Min Max Unit
U i

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Voltage “0” Level VOL 5.0 — 0.05 — 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
“1” Level VOH
15
5.0

4.95
0.05


4.95
0.05


4.95
0.05
— Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = 0 or VDD 10 9.95 — 9.95 — 9.95 —
15 14.95 — 14.95 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Input Voltage B Types
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
“0” Level VIL Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 3.0 — 3.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 4.0 — 4.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 — 3.5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
10
15
7.0
11


7.0
11


7.0
11

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
Input Voltage UB Types “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.0 — 1.0 — 1.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 2.0 — 2.0 — 2.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 2.5 — 2.5 — 2.5
“1” Level VIH Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) 5.0 4.0 — 4.0 — 4.0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 8.0 — 8.0 — 8.0 —
(VO = 1.5 or 13.5 Vdc) 15 12.5 — 12.5 — 12.5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Drive Current B Gates

ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ IOH mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 — – 0.36 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ ÎÎÎÎ ÎÎÎ


ÎÎÎ
ÎÎÎ ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10 – 1.6 — – 1.3 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 — 0.36 —
(VOL = 0.5 Vdc) 10 1.6 — 1.3 — 0.9 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Drive Current UB Gates IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 — – 0.7 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 — – 0.14 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 — – 1.1 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 — 0.36 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Output Drive Current Other Devices
ÎÎÎ
ÎÎÎÎÎÎ IOH mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ
(VOH = 4.6 Vdc) Source 5.0 – 0.64 — – 0.51 — – 0.36 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 — 0.36 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Input Current

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Input Capacitance ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Iin
Cin
15



± 0.1



± 0.1
7.5


± 1.0

µAdc
pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Vin = 0)
Gate Quiescent Current IDD 5.0 — 0.25 — 0.25 — 7.5 µAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
(Per Package)
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ 10 — 0.5 — 0.5 — 15

ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 1.0 — 1.0 — 30
µAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
Flip–Flop and Buffer Quiescent Current IDD 5.0 — 1.0 — 1.0 — 30
(Per Package) 10 — 2.0 — 2.0 — 60

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 4.0 — 4.0 — 120

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MSI Quiescent Current IDD 5.0 — 5.0 — 5.0 — 150 µAdc
(Per Package) 10 — 10 — 10 — 300

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 20 — 20 — 600

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
LSI Quiescent Current IDD See Individual Data Sheets.

MOTOROLA CMOS LOGIC DATA CHAPTER 4


4–5
CMOS Handling and Design Guidelines 5
     
   

HANDLING PRECAUTIONS tions to a PC board are connected to an input of a CMOS


device, a resistor should be used in series with the input.
All MOS devices have insulated gates that are subject to This resistor helps limit accidental damage if the PC
voltage breakdown. The gate oxide for Motorola CMOS de- board is removed and brought into contact with static
vices is about 900 Å thick and breaks down at a gate–source generating materials. The limiting factor for the series
potential of about 100 volts. To guard against such a break- resistor is the added delay. This is caused by the time
down from static discharge or other voltage transients, the constant formed by the series resistor and input
protection networks shown in Figures 1A and 1B are used on capacitance. Note that the maximum input rise and fall
each input to the CMOS device. times should not be exceeded. In Figure 2, two possible
Static damaged devices behave in various ways, depend- networks are shown using a series resistor to reduce
ing on the severity of the damage. The most severely dam- ESD (Electrostatic Discharge) damage. For conve-
aged inputs are the easiest to detect because the input has nience, an equation for added propagation delay and
been completely destroyed and is either shorted to VDD, rise time effects due to series resistance size is given.
shorted to VSS, or open–circuited. The effect is that the de- 5. All CMOS devices should be stored or transported in
vice no longer responds to signals present at the damaged materials that are antistatic. CMOS devices must not be
input. Less severe cases are more difficult to detect because inserted into conventional plastic “snow”, styrofoam, or
they show up as intermittent failures or as degraded perfor- plastic trays, but should be left in their original container
mance. Another effect of static damage is that the inputs until ready for use.
generally have increased leakage currents. 6. All CMOS devices should be placed on a grounded
Although the input protection network does provide a great bench surface and operators should ground them-
deal of protection, CMOS devices are not immune to large selves prior to handling devices, since a worker can be
static voltage discharges that can be generated during han- statically charged with respect to the bench surface.
dling. For example, static voltages generated by a person Wrist straps in contact with skin are strongly recom-
walking across a waxed floor have been measured in the mended. See Figure 3 for an example of a typical work
4 –15 kV range (depending on humidity, surface conditions, station.
etc.). Therefore, the following precautions should be 7. Nylon or other static generating materials should not
observed: come in contact with CMOS devices.
1. Do not exceed the Maximum Ratings specified by the 8. If automatic handlers are being used, high levels of
data sheet. static electricity may be generated by the movement of
2. All unused device inputs should be connected to VDD or the device, the belts, or the boards. Reduce static build–
VSS. up by using ionized air blowers or room humidifiers. All
3. All low–impedance equipment (pulse generators, etc.) parts of machines which come into contact with the top,
should be connected to CMOS inputs only after the de- bottom, or sides of IC packages must be grounded to
vice is powered up. Similarly, this type of equipment metal or other conductive material.
should be disconnected before power is turned off. 9. Cold chambers using CO2 for cooling should be
4. Circuit boards containing CMOS devices are merely equipped with baffles, and the CMOS devices must be
extensions of the devices, and the same handling contained on or in conductive material.
precautions apply. Contacting edge connectors wired 10. When lead–straightening or hand–soldering is neces-
directly to device inputs can cause damage. Plastic sary, provide ground straps for the apparatus used and
wrapping should be avoided. When external connec- be sure that soldering ties are grounded.

INPUT PROTECTION NETWORK

VDD VDD

CMOS CMOS
TO CIRCUIT
INPUT INPUT
< 1500 Ω 300 Ω

VSS VSS

Figure 1a. Input Protection Network Figure 1b. Input Protection Network
Double Diode Triple Diode

CHAPTER 5 MOTOROLA CMOS LOGIC DATA


5–2
11. The following steps should be observed during wave 13. The use of static detection meters for production line
solder operations: surveillance is highly recommended.
a. The solder pot and conductive conveyor system of 14. Equipment specifications should alert users to the pres-
the wave soldering machine must be grounded to an ence of CMOS devices and require familiarization with
earth ground. this specification prior to performing any kind of mainte-
b. The loading and unloading work benches should nance or replacement of devices or modules.
have conductive tops which are grounded to an earth 15. Do not insert or remove CMOS devices from test
ground. sockets with power applied. Check all power supplies to
c. Operators must comply with precautions previously be used for testing devices to be certain there are no
explained. voltage transients present.
d. Completed assemblies should be placed in antistatic 16. Double check test equipment setup for proper polarity
containers prior to being moved to subsequent of VDD and VSS before conducting parametric or func-
stations. tional testing.
12. The following steps should be observed during board– 17. Do not recycle shipping rails or trays. Repeated use
cleaning operations: causes deterioration of their antistatic coating.
a. Vapor degreasers and baskets must be grounded to
an earth ground.
b. Brush or spray cleaning should not be used. RECOMMENDED FOR READING:
c. Assemblies should be placed into the vapor
degreaser immediately upon removal from the “Total Control of the Static in Your Business”
antistatic container.
d. Cleaned assemblies should be placed in antistatic Available by writing to:
containers immediately after removal from the clean- 3M Company
ing basket. Static Control Systems
e. High velocity air movement or application of solvents P.O. Box 2963
and coatings should be employed only when Austin, Texas 78769–2963
assembled printed circuit boards are grounded and Or by Calling:
a static eliminator is directed at the board. 1–800–328–1368

VDD

CMOS D1 CMOS
TO OFF–BOARD R1 INPUT TO OFF–BOARD R2 INPUT
CONNECTION OR CONNECTION OR
OUTPUT OUTPUT
D2

Advantage: Requires minimal board area Advantage: R2 < R1 for the same VSS
level of protection.
Disadvantage: R1 > R2 for the same level of Impact on ac and dc
protection, therefore rise and fall characteristics is minimized
times, propagation delays, and output
drives are severely affected. Disadvantage: More board area, higher initial cost
Note: These networks are useful for protecting the following
A digital inputs and outputs C 3–state outputs
B analog inputs and outputs D bidirectional (I/O) ports

PROPAGATION DELAY AND RISE TIME


vs. SERIES RESISTANCE
R [ t
where: C@k
R = the maximum allowable series resistance in ohms
t = the maximum tolerable propagation delay or rise time in seconds
C = the board capacitance plus the driven device’s
= input capacitance in farads
k = 0.7 for propagation delay calculations
k = 2.3 for rise time calculations

Figure 1. Networks for Minimizing ESD and Reducing


CMOS Latch Up Susceptibility

MOTOROLA CMOS LOGIC DATA CHAPTER 5


5–3
4 NOTES: 1. 1/16 inch conductive sheet stock covering bench
top work area.
2. Ground strap.
1 3. Wrist strap in contact with skin.
4. Static neutralizer. (Ionized air blower directed at
work.) Primarily for use in areas where direct
grounding is impractical.
2
5. Room humidifier. Primarily for use in areas where
5 the relative humidity is less than 45%. Caution:
building heating and cooling systems usually dry
the air causing the relative humidity inside of
3 buildings to be less than outside humidity.

RESISTOR =
1 MEGAOHM
Figure 2. Typical Manufacturing Work Station

POWER SUPPLIES the possibility of latch–up related failures. This system


protection can be provided by the power supply filter and/or
CMOS devices have low power requirements and the abil- voltage regulator.
ity to operate over a wide range of supply voltages. These CMOS devices can be used with battery or battery backup
two characteristics allow CMOS designs to be implemented systems. A few precautions should be taken when designing
using inexpensive, conventional power supplies, instead of battery–operated systems:
switching power supplies and power supplies with cooling 1. The recommended power supply voltage should be ob-
fans. In addition, batteries may be used as either a primary served. For battery backup systems such as the one in
power source or for emergency backup. Figure 5, the battery voltage must be at least 3.7 Volts
The absolute maximum power supply voltage for 14000 (3 Volts from the minimum power supply voltage and
Series Metal–gate CMOS is 18.0 Vdc. Figure 4 offers some 0.7 Volts to account for the voltage drop across the se-
insight as to how this specification was derived. In the figure, ries diode).
VS is the maximum power supply voltage and IS is the sus- 2. Inputs that might go above the battery backup voltage
taining current of the latch–up mode. The value of VS was should either use a series resistor to limit the input cur-
chosen so that the secondary breakdown effect may be rent to less than 10 mA or use the MC14049UB or
avoided. MC14050B high–to–low voltage translators.
In an ideal system design, a power supply should be 3. Outputs that are subject to voltage levels above VDD or
designed to deliver only enough current to insure proper below VSS should be protected with a series resistor to
operation of all devices. The obvious benefit of this type limit the current to less than 10 mA or with clamping
design is cost savings; an added benefit is protection against diodes.

IDD

LATCH
UP MODE
SECONDARY
BREAKDOWN

LOW CURRENT
JUNCTION
IS
AVALANCHE

VS VDD
VS = DATA SHEET MAXIMUM SUPPLY RATING

Figure 3. Secondary Breakdown Characteristics

CHAPTER 5 MOTOROLA CMOS LOGIC DATA


5–4
POWER SUPPLY

BATTERY BACKUP
LINE POWER ONLY BATTERY BACKUP RECHARGE
SYSTEM SYSTEM

MC14049UB
CMOS CMOS
MC14050B
SYSTEM SYSTEM

MC14049UB
MC14050B

Figure 4. Battery Backup Interface

INPUTS VDD = 5.0 Vdc

All inputs, while in the recommended operating range (VSS

Vout , OUTPUT VOLTAGE (V)


< Vin < VDD) can be modeled as shown in Figure 6. For input
SINGLE INPUT NAND, AND
voltages in this range, diodes D1 and D2 are modeled as
MULTIPLE INPUT NOR, OR
resistors, representing the reverse bias impedance of the 5.0
diodes. The maximum input current is worst case, 1 µA,
when the inputs are at VDD or VSS, and VDD = 15.0 V. This 4.0 SINGLE INPUT NOR, OR
model does not apply to inputs with pull–up or pull–down MULTIPLE INPUT NAND, AND
3.0
resistors.
2.0

1.0

0
VDD 0 1.0 2.0 3.0 4.0 5.0
R1 = R2 = HIGH Z Vin, INPUT VOLTAGE (V)

R1 Figure 6. Typical Transfer Characteristics


for Buffered Devices

For these reasons, all unused inputs should be connected


R2 7.5 pF
either to VDD or VSS. For applications with inputs going to
edge connectors, a 100 kilohm resistor to VSS should be
used, as well as a series resistor for static protection and
Figure 5. Input Model for VSS v Vin v VDD current limiting (Figure 8). The 100 kilohm resistor will help
eliminate any static charges that might develop on the
printed circuit board. See Figure 2 for other possible
protection arrangements.
When left open–circuited, the inputs may self–bias at or
near the typical switchpoint, where both the P–channel and FROM RS CMOS
EDGE
N–channel transistors are conducting, causing excessive DEVICE
CONNECTOR
current drain. Due to the high gain of the inverters (see
100 k
Figure 7), the device may also go into oscillation from any
noise in the system. Since CMOS devices dissipate the most
power during switching, this oscillation can cause very large
current drain and undesired switching. Figure 7. External Protection

MOTOROLA CMOS LOGIC DATA CHAPTER 5


5–5
For input voltages outside of the recommended operating CMOS outputs are limited to externally forced output
range, the CMOS input is modeled as in Figure 9. The voltages of VSS – 0.5 V v Vout v VDD + 0.5 V. When
resistor–diode protection network allows the user greater voltages are forced outside of this range, a silicon controlled
freedom when designing a worst case system. The device rectifier (SCR) formed by parasitic transistors can be
inputs are guaranteed to withstand voltages from VSS – 0.5 V triggered, causing the device to latch up. For more informa-
to VDD + 0.5 V and a maximum current of 10 mA. With the tion on this, see the explanation of CMOS Latch Up in this
above input ratings, most designs will require no special section.
terminations or design considerations. The maximum rated output current for most outputs is
10 mA. The output short–circuit currents of these devices
typically exceed these limits. Care must be taken not to ex-
ceed the maximum ratings found on every data sheet.
D1 For applications that require driving high capacitive loads
 1.5 k where fast propagation delays are needed (e.g., driving
power MOSFETs), two or more outputs on the same chip
may be externally paralleled.
D2 7.5 pF
CMOS LATCH UP
Latch up will not be a problem for most designs, but the
designer should be aware of it, what causes it, and how to
Figure 8. Input Model for Vin > VDD or Vin < VSS prevent it.
Figure 11 shows the cross–section of a typical CMOS in-
Other specifications that should be noted are the maxi- verter and Figure 12 shows the parasitic bipolar devices. The
mum input rise and fall times. Figure 10 shows the circuit formed by the parasitic transistors and resistors is the
oscillations that may result from exceeding the 15 µs basic configuration of a silicon controlled rectifier, or SCR. In
maximum rise and fall time at VDD = 5.0 V, 5 µs at 10 V, or the latch up condition, transistors Q1 and Q2 are turned ON,
4 µs at 15 V. As the voltage passes through the switching each providing the base current necessary for the other to
threshold region with a slow rise time, any noise that is on the remain in saturation, thereby latching the devices in the ON
input is amplified, and passed through to the output, causing state. Unlike a conventional SCR, where the device is turned
oscillations. The oscillation may have a low enough fre- ON by applying a voltage to the base of the NPN transistor,
quency to cause succeeding stages to switch, giving the parasitic SCR is turned ON by applying a voltage to the
unexpected results. If input rise or fall times are expected to emitter of either transistor. The two emitters that trigger the
exceed 15 µs at 5.0 V, 5 µs at 10 V, or 4 µs at 15 V, SCR are the same point, the CMOS output. Therefore, to
Schmitt–trigger devices such as the MC14093B, MC14583B, latch up the CMOS device, the output voltage must be great-
MC14584B, MC14106B, HC14, or HC132 are recommended er than VDD + 0.5 V or less than VSS – 0.5 V and have suffi-
for squaring–up these slow transitions. cient current to trigger the SCR. The latch–up mechanism is
similar for the inputs.
Once a CMOS device is latched up, if the supply current is
VDD not limited, the device will be destroyed. Ways to prevent
such occurrences are listed below:
Vin 1. Insure that inputs and outputs are limited to the maxi-
mum rated values, as follows:
VSS v
– 0.5 V ≤ Vin or Vout VDD + 0.5 V (referenced to VSS)
v
|Iin or Iout| 10 mA (unless otherwise indicated on the
data sheet)
VOH
2. If voltage transients of sufficient energy to latch up the
device are expected on the inputs or outputs, external
Vout
protection diodes can be used to clamp the voltage.
Another method of protection is to use a series resistor
VOL
to limit the expected worst case current to the maximum
rating of 10 mA. (See Figure 2).
3. Sequence power supplies so that the inputs or outputs
Figure 9. Maximum Rise and Fall Time Violations of CMOS devices are not active before the supply pins
are powered up (e.g., recessed edge connectors and/
OUTPUTS or series resistors may be used in plug–in board ap-
plications).
All CMOS B–Series outputs are buffered to insure consis- 4. Voltage regulating or filtering should be used in board
tent output voltage and current performance. All buffered out- design and layout to insure that power–supply lines are
puts have guaranteed output voltages of VOL = 0.05 V and free of excessive noise.
VOH = VDD – 0.05 V for Vin = VDD or VSS and lout = 0 µA. The 5. Limit the available power supply current to the devices
output drives for all buffered CMOS devices are such that that are subject to latch–up conditions. This can be ac-
1 LSTTL load can be driven across the full temperature complished with the power supply filtering network or
range. with a current–limiting regulator.

CHAPTER 5 MOTOROLA CMOS LOGIC DATA


5–6
P–CHANNEL N–CHANNEL
INPUT

VDD VDD P–CHANNEL N–CHANNEL VSS


OUTPUT
OUTPUT OUTPUT

N+
FIELD OXIDE ÇÇÇ
P+ P+
FIELD OXIDE
N+
ÇÇ N+ P+
FIELD OXIDE

N – SUBSTRATE P – WELL

Figure 10. CMOS Wafer Cross Section

Q1
N–CHANNEL OUTPUT
N+ N+ N– N–SUBSTRATE RESISTANCE
VDD
VSS N–
P–
P+
VDD
VSS P–
P–WELL RESISTANCE P+
Q2 P–CHANNEL OUTPUT

Figure 11. Latch Up Circuit Schematic

MOTOROLA CMOS LOGIC DATA CHAPTER 5


5–7
CMOS Handling and Design Guidelines 5
     
   

HANDLING PRECAUTIONS tions to a PC board are connected to an input of a CMOS


device, a resistor should be used in series with the input.
All MOS devices have insulated gates that are subject to This resistor helps limit accidental damage if the PC
voltage breakdown. The gate oxide for Motorola CMOS de- board is removed and brought into contact with static
vices is about 900 Å thick and breaks down at a gate–source generating materials. The limiting factor for the series
potential of about 100 volts. To guard against such a break- resistor is the added delay. This is caused by the time
down from static discharge or other voltage transients, the constant formed by the series resistor and input
protection networks shown in Figures 1A and 1B are used on capacitance. Note that the maximum input rise and fall
each input to the CMOS device. times should not be exceeded. In Figure 2, two possible
Static damaged devices behave in various ways, depend- networks are shown using a series resistor to reduce
ing on the severity of the damage. The most severely dam- ESD (Electrostatic Discharge) damage. For conve-
aged inputs are the easiest to detect because the input has nience, an equation for added propagation delay and
been completely destroyed and is either shorted to VDD, rise time effects due to series resistance size is given.
shorted to VSS, or open–circuited. The effect is that the de- 5. All CMOS devices should be stored or transported in
vice no longer responds to signals present at the damaged materials that are antistatic. CMOS devices must not be
input. Less severe cases are more difficult to detect because inserted into conventional plastic “snow”, styrofoam, or
they show up as intermittent failures or as degraded perfor- plastic trays, but should be left in their original container
mance. Another effect of static damage is that the inputs until ready for use.
generally have increased leakage currents. 6. All CMOS devices should be placed on a grounded
Although the input protection network does provide a great bench surface and operators should ground them-
deal of protection, CMOS devices are not immune to large selves prior to handling devices, since a worker can be
static voltage discharges that can be generated during han- statically charged with respect to the bench surface.
dling. For example, static voltages generated by a person Wrist straps in contact with skin are strongly recom-
walking across a waxed floor have been measured in the mended. See Figure 3 for an example of a typical work
4 –15 kV range (depending on humidity, surface conditions, station.
etc.). Therefore, the following precautions should be 7. Nylon or other static generating materials should not
observed: come in contact with CMOS devices.
1. Do not exceed the Maximum Ratings specified by the 8. If automatic handlers are being used, high levels of
data sheet. static electricity may be generated by the movement of
2. All unused device inputs should be connected to VDD or the device, the belts, or the boards. Reduce static build–
VSS. up by using ionized air blowers or room humidifiers. All
3. All low–impedance equipment (pulse generators, etc.) parts of machines which come into contact with the top,
should be connected to CMOS inputs only after the de- bottom, or sides of IC packages must be grounded to
vice is powered up. Similarly, this type of equipment metal or other conductive material.
should be disconnected before power is turned off. 9. Cold chambers using CO2 for cooling should be
4. Circuit boards containing CMOS devices are merely equipped with baffles, and the CMOS devices must be
extensions of the devices, and the same handling contained on or in conductive material.
precautions apply. Contacting edge connectors wired 10. When lead–straightening or hand–soldering is neces-
directly to device inputs can cause damage. Plastic sary, provide ground straps for the apparatus used and
wrapping should be avoided. When external connec- be sure that soldering ties are grounded.

INPUT PROTECTION NETWORK

VDD VDD

CMOS CMOS
TO CIRCUIT
INPUT INPUT
< 1500 Ω 300 Ω

VSS VSS

Figure 1a. Input Protection Network Figure 1b. Input Protection Network
Double Diode Triple Diode

CHAPTER 5 MOTOROLA CMOS LOGIC DATA


5–2
11. The following steps should be observed during wave 13. The use of static detection meters for production line
solder operations: surveillance is highly recommended.
a. The solder pot and conductive conveyor system of 14. Equipment specifications should alert users to the pres-
the wave soldering machine must be grounded to an ence of CMOS devices and require familiarization with
earth ground. this specification prior to performing any kind of mainte-
b. The loading and unloading work benches should nance or replacement of devices or modules.
have conductive tops which are grounded to an earth 15. Do not insert or remove CMOS devices from test
ground. sockets with power applied. Check all power supplies to
c. Operators must comply with precautions previously be used for testing devices to be certain there are no
explained. voltage transients present.
d. Completed assemblies should be placed in antistatic 16. Double check test equipment setup for proper polarity
containers prior to being moved to subsequent of VDD and VSS before conducting parametric or func-
stations. tional testing.
12. The following steps should be observed during board– 17. Do not recycle shipping rails or trays. Repeated use
cleaning operations: causes deterioration of their antistatic coating.
a. Vapor degreasers and baskets must be grounded to
an earth ground.
b. Brush or spray cleaning should not be used. RECOMMENDED FOR READING:
c. Assemblies should be placed into the vapor
degreaser immediately upon removal from the “Total Control of the Static in Your Business”
antistatic container.
d. Cleaned assemblies should be placed in antistatic Available by writing to:
containers immediately after removal from the clean- 3M Company
ing basket. Static Control Systems
e. High velocity air movement or application of solvents P.O. Box 2963
and coatings should be employed only when Austin, Texas 78769–2963
assembled printed circuit boards are grounded and Or by Calling:
a static eliminator is directed at the board. 1–800–328–1368

VDD

CMOS D1 CMOS
TO OFF–BOARD R1 INPUT TO OFF–BOARD R2 INPUT
CONNECTION OR CONNECTION OR
OUTPUT OUTPUT
D2

Advantage: Requires minimal board area Advantage: R2 < R1 for the same VSS
level of protection.
Disadvantage: R1 > R2 for the same level of Impact on ac and dc
protection, therefore rise and fall characteristics is minimized
times, propagation delays, and output
drives are severely affected. Disadvantage: More board area, higher initial cost
Note: These networks are useful for protecting the following
A digital inputs and outputs C 3–state outputs
B analog inputs and outputs D bidirectional (I/O) ports

PROPAGATION DELAY AND RISE TIME


vs. SERIES RESISTANCE
R [ t
where: C@k
R = the maximum allowable series resistance in ohms
t = the maximum tolerable propagation delay or rise time in seconds
C = the board capacitance plus the driven device’s
= input capacitance in farads
k = 0.7 for propagation delay calculations
k = 2.3 for rise time calculations

Figure 1. Networks for Minimizing ESD and Reducing


CMOS Latch Up Susceptibility

MOTOROLA CMOS LOGIC DATA CHAPTER 5


5–3
4 NOTES: 1. 1/16 inch conductive sheet stock covering bench
top work area.
2. Ground strap.
1 3. Wrist strap in contact with skin.
4. Static neutralizer. (Ionized air blower directed at
work.) Primarily for use in areas where direct
grounding is impractical.
2
5. Room humidifier. Primarily for use in areas where
5 the relative humidity is less than 45%. Caution:
building heating and cooling systems usually dry
the air causing the relative humidity inside of
3 buildings to be less than outside humidity.

RESISTOR =
1 MEGAOHM
Figure 2. Typical Manufacturing Work Station

POWER SUPPLIES the possibility of latch–up related failures. This system


protection can be provided by the power supply filter and/or
CMOS devices have low power requirements and the abil- voltage regulator.
ity to operate over a wide range of supply voltages. These CMOS devices can be used with battery or battery backup
two characteristics allow CMOS designs to be implemented systems. A few precautions should be taken when designing
using inexpensive, conventional power supplies, instead of battery–operated systems:
switching power supplies and power supplies with cooling 1. The recommended power supply voltage should be ob-
fans. In addition, batteries may be used as either a primary served. For battery backup systems such as the one in
power source or for emergency backup. Figure 5, the battery voltage must be at least 3.7 Volts
The absolute maximum power supply voltage for 14000 (3 Volts from the minimum power supply voltage and
Series Metal–gate CMOS is 18.0 Vdc. Figure 4 offers some 0.7 Volts to account for the voltage drop across the se-
insight as to how this specification was derived. In the figure, ries diode).
VS is the maximum power supply voltage and IS is the sus- 2. Inputs that might go above the battery backup voltage
taining current of the latch–up mode. The value of VS was should either use a series resistor to limit the input cur-
chosen so that the secondary breakdown effect may be rent to less than 10 mA or use the MC14049UB or
avoided. MC14050B high–to–low voltage translators.
In an ideal system design, a power supply should be 3. Outputs that are subject to voltage levels above VDD or
designed to deliver only enough current to insure proper below VSS should be protected with a series resistor to
operation of all devices. The obvious benefit of this type limit the current to less than 10 mA or with clamping
design is cost savings; an added benefit is protection against diodes.

IDD

LATCH
UP MODE
SECONDARY
BREAKDOWN

LOW CURRENT
JUNCTION
IS
AVALANCHE

VS VDD
VS = DATA SHEET MAXIMUM SUPPLY RATING

Figure 3. Secondary Breakdown Characteristics

CHAPTER 5 MOTOROLA CMOS LOGIC DATA


5–4
POWER SUPPLY

BATTERY BACKUP
LINE POWER ONLY BATTERY BACKUP RECHARGE
SYSTEM SYSTEM

MC14049UB
CMOS CMOS
MC14050B
SYSTEM SYSTEM

MC14049UB
MC14050B

Figure 4. Battery Backup Interface

INPUTS VDD = 5.0 Vdc

All inputs, while in the recommended operating range (VSS

Vout , OUTPUT VOLTAGE (V)


< Vin < VDD) can be modeled as shown in Figure 6. For input
SINGLE INPUT NAND, AND
voltages in this range, diodes D1 and D2 are modeled as
MULTIPLE INPUT NOR, OR
resistors, representing the reverse bias impedance of the 5.0
diodes. The maximum input current is worst case, 1 µA,
when the inputs are at VDD or VSS, and VDD = 15.0 V. This 4.0 SINGLE INPUT NOR, OR
model does not apply to inputs with pull–up or pull–down MULTIPLE INPUT NAND, AND
3.0
resistors.
2.0

1.0

0
VDD 0 1.0 2.0 3.0 4.0 5.0
R1 = R2 = HIGH Z Vin, INPUT VOLTAGE (V)

R1 Figure 6. Typical Transfer Characteristics


for Buffered Devices

For these reasons, all unused inputs should be connected


R2 7.5 pF
either to VDD or VSS. For applications with inputs going to
edge connectors, a 100 kilohm resistor to VSS should be
used, as well as a series resistor for static protection and
Figure 5. Input Model for VSS v Vin v VDD current limiting (Figure 8). The 100 kilohm resistor will help
eliminate any static charges that might develop on the
printed circuit board. See Figure 2 for other possible
protection arrangements.
When left open–circuited, the inputs may self–bias at or
near the typical switchpoint, where both the P–channel and FROM RS CMOS
EDGE
N–channel transistors are conducting, causing excessive DEVICE
CONNECTOR
current drain. Due to the high gain of the inverters (see
100 k
Figure 7), the device may also go into oscillation from any
noise in the system. Since CMOS devices dissipate the most
power during switching, this oscillation can cause very large
current drain and undesired switching. Figure 7. External Protection

MOTOROLA CMOS LOGIC DATA CHAPTER 5


5–5
For input voltages outside of the recommended operating CMOS outputs are limited to externally forced output
range, the CMOS input is modeled as in Figure 9. The voltages of VSS – 0.5 V v Vout v VDD + 0.5 V. When
resistor–diode protection network allows the user greater voltages are forced outside of this range, a silicon controlled
freedom when designing a worst case system. The device rectifier (SCR) formed by parasitic transistors can be
inputs are guaranteed to withstand voltages from VSS – 0.5 V triggered, causing the device to latch up. For more informa-
to VDD + 0.5 V and a maximum current of 10 mA. With the tion on this, see the explanation of CMOS Latch Up in this
above input ratings, most designs will require no special section.
terminations or design considerations. The maximum rated output current for most outputs is
10 mA. The output short–circuit currents of these devices
typically exceed these limits. Care must be taken not to ex-
ceed the maximum ratings found on every data sheet.
D1 For applications that require driving high capacitive loads
 1.5 k where fast propagation delays are needed (e.g., driving
power MOSFETs), two or more outputs on the same chip
may be externally paralleled.
D2 7.5 pF
CMOS LATCH UP
Latch up will not be a problem for most designs, but the
designer should be aware of it, what causes it, and how to
Figure 8. Input Model for Vin > VDD or Vin < VSS prevent it.
Figure 11 shows the cross–section of a typical CMOS in-
Other specifications that should be noted are the maxi- verter and Figure 12 shows the parasitic bipolar devices. The
mum input rise and fall times. Figure 10 shows the circuit formed by the parasitic transistors and resistors is the
oscillations that may result from exceeding the 15 µs basic configuration of a silicon controlled rectifier, or SCR. In
maximum rise and fall time at VDD = 5.0 V, 5 µs at 10 V, or the latch up condition, transistors Q1 and Q2 are turned ON,
4 µs at 15 V. As the voltage passes through the switching each providing the base current necessary for the other to
threshold region with a slow rise time, any noise that is on the remain in saturation, thereby latching the devices in the ON
input is amplified, and passed through to the output, causing state. Unlike a conventional SCR, where the device is turned
oscillations. The oscillation may have a low enough fre- ON by applying a voltage to the base of the NPN transistor,
quency to cause succeeding stages to switch, giving the parasitic SCR is turned ON by applying a voltage to the
unexpected results. If input rise or fall times are expected to emitter of either transistor. The two emitters that trigger the
exceed 15 µs at 5.0 V, 5 µs at 10 V, or 4 µs at 15 V, SCR are the same point, the CMOS output. Therefore, to
Schmitt–trigger devices such as the MC14093B, MC14583B, latch up the CMOS device, the output voltage must be great-
MC14584B, MC14106B, HC14, or HC132 are recommended er than VDD + 0.5 V or less than VSS – 0.5 V and have suffi-
for squaring–up these slow transitions. cient current to trigger the SCR. The latch–up mechanism is
similar for the inputs.
Once a CMOS device is latched up, if the supply current is
VDD not limited, the device will be destroyed. Ways to prevent
such occurrences are listed below:
Vin 1. Insure that inputs and outputs are limited to the maxi-
mum rated values, as follows:
VSS v
– 0.5 V ≤ Vin or Vout VDD + 0.5 V (referenced to VSS)
v
|Iin or Iout| 10 mA (unless otherwise indicated on the
data sheet)
VOH
2. If voltage transients of sufficient energy to latch up the
device are expected on the inputs or outputs, external
Vout
protection diodes can be used to clamp the voltage.
Another method of protection is to use a series resistor
VOL
to limit the expected worst case current to the maximum
rating of 10 mA. (See Figure 2).
3. Sequence power supplies so that the inputs or outputs
Figure 9. Maximum Rise and Fall Time Violations of CMOS devices are not active before the supply pins
are powered up (e.g., recessed edge connectors and/
OUTPUTS or series resistors may be used in plug–in board ap-
plications).
All CMOS B–Series outputs are buffered to insure consis- 4. Voltage regulating or filtering should be used in board
tent output voltage and current performance. All buffered out- design and layout to insure that power–supply lines are
puts have guaranteed output voltages of VOL = 0.05 V and free of excessive noise.
VOH = VDD – 0.05 V for Vin = VDD or VSS and lout = 0 µA. The 5. Limit the available power supply current to the devices
output drives for all buffered CMOS devices are such that that are subject to latch–up conditions. This can be ac-
1 LSTTL load can be driven across the full temperature complished with the power supply filtering network or
range. with a current–limiting regulator.

CHAPTER 5 MOTOROLA CMOS LOGIC DATA


5–6
P–CHANNEL N–CHANNEL
INPUT

VDD VDD P–CHANNEL N–CHANNEL VSS


OUTPUT
OUTPUT OUTPUT

N+
FIELD OXIDE ÇÇÇ
P+ P+
FIELD OXIDE
N+
ÇÇ N+ P+
FIELD OXIDE

N – SUBSTRATE P – WELL

Figure 10. CMOS Wafer Cross Section

Q1
N–CHANNEL OUTPUT
N+ N+ N– N–SUBSTRATE RESISTANCE
VDD
VSS N–
P–
P+
VDD
VSS P–
P–WELL RESISTANCE P+
Q2 P–CHANNEL OUTPUT

Figure 11. Latch Up Circuit Schematic

MOTOROLA CMOS LOGIC DATA CHAPTER 5


5–7
Data Sheets 6
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14000UB
Dual 3-Input NOR" Gate
Plus Inverter L SUFFIX
CERAMIC
The MC14000UB dual 3–input NOR gate plus inverter is constructed with CASE 632
MOS P–channel and N–channel enhancement mode devices in a single
monolithic structure. These complementary MOS logic gates find primary
use where low power dissipation and/or high noise immunity is desired. P SUFFIX
PLASTIC
• Diode Protection on All Inputs
CASE 646
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Swing Independent of Fanout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Pin–for–Pin Replacement for CD4000UB D SUFFIX

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SOIC
MAXIMUM RATINGS* (Voltages Referenced to VSS) CASE 751A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VDD
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage
Parameter Value
– 0.5 to + 18.0
Unit
V
ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
MC14XXXUBCP Plastic
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V MC14XXXUBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
MC14XXXUBD SOIC
lin, lout Input or Output Current (DC or Transient), ± 10 mA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
Î ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C
LOGIC DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
_C 3

4 6
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 5
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
11

12 10

CIRCUIT SCHEMATIC 13

14 11 12 13 8
VDD 8 9
VDD = PIN 14
3 VSS = PIN 7

4
PIN ASSIGNMENT
9
5 NC 1 14 VDD
NC 2 13 IN 3B
IN 1A 3 12 IN 2B
IN 2A 4 11 IN 1B
IN 3A 5 10 OUTB

VSS OUTA 6 9 OUTC


7 6 10
VSS 7 8 IN 1C

NC = NO CONNECTION

MC14000UB MOTOROLA CMOS LOGIC DATA


6–2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C + 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
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15 — 0.05 — 0 0.05 — 0.05

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ÎÎÎÎ
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ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

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ÎÎÎÎ
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ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc

ÎÎÎÎÎÎÎÎÎÎ
(VO = 4.5 Vdc)

ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ

ÎÎÎÎ
1.0

ÎÎÎ

ÎÎÎÎ
2.25

ÎÎÎ
1.0

ÎÎÎÎ

ÎÎÎ
1.0
(VO = 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VO = 13.5 Vdc)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15


2.0
2.5


4.50
6.75
2.0
2.5


2.0
2.5

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 Vdc) 5.0 4.0 — 4.0 2.75 — 4.0 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VO = 1.0 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VO = 1.5 Vdc)
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
8.0
12.5


8.0
12.5
5.50
8.25


8.0
12.5

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 0.62 — – 0.5 – 0.9 — – 0.35 —
(VOH = 13.5 Vdc) 15 – 1.8 — – 1.5 – 3.5 — – 1.1 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6


0.51
1.3
0.88
2.25


0.36
0.9


mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
Quiescent Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(Per Package)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10


0.25
0.5


0.0005
0.0010
0.25
0.5


7.5
15
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.3 µA/kHz) f + IDD/N µAdc
(Dynamic plus Quiescent, 10 IT = (0.6 µA/kHz) f + IDD/N

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Per Gate, CL = 50 pF) 15 IT = (0.8 µA/kHz) f + IDD/N
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA MC14000UB


6–3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time tTHL ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (1.5 ns/pF) CL + 25 ns

ÎÎÎÎÎ
5.0

ÎÎÎÎ

ÎÎÎÎ
100

ÎÎÎÎ
200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
tTHL = (0.75 ns/pF) CL + 12.5 ns

ÎÎÎÎÎÎÎ
tTHL = (0.55 ns/pF) CL + 9.5 ns
10
15


50
40
100
80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 30 ns tPHL 5.0 — 115 230

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 22 ns 10 — 55 110

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.50 ns/pF) CL + 15 ns 15 — 40 80
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD
20 ns 20 ns
VDD
14 INPUT 90%
INPUT 50%
PULSE 10% VSS
GENERATOR OUTPUT tPHL tPLH
90% VOH
7 VSS CL OUTPUT 50%
10%
VOL
tTHL tTLH

Figure 1. Switching Time Test Circuit and Waveforms

16 16
VDD = 15 Vdc VDD = 15 Vdc
TA = 25°C UNUSED INPUTS
14 14 CONNECTED TO VSS
a
Vout , OUTPUT VOLTAGE (Vdc)

Vout , OUTPUT VOLTAGE (Vdc)

a ONE INPUT ONLY


ID , DRAIN CURRENT (mAdc)

12 12
c b AND INVERTER 10 Vdc
10 Vdc
10 b TWO INPUTS 10 a TA = + 125°C
a b
c THREE INPUTS a b b TA = – 55°C
c b a
8.0 8.0 8.0

6.0 5.0 Vdc ID = 15 Vdc 6.0 6.0 5.0 Vdc


b
4.0 4.0 4.0
c a ID = 10 Vdc
a b
2.0 2.0 2.0

0 0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 0 2.0 4.0 6.0 8.0 10 12 14 16
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)

Figure 2. Typical Voltage and Current Figure 3. Typical Voltage Transfer


Transfer Characteristics Characteristics versus Temperature

MC14000UB MOTOROLA CMOS LOGIC DATA


6–4
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14001B
Quad 2-Input NOR Gate
B-Suffix Series CMOS Gates MC14002B
The B Series logic gates are constructed with P and N channel Dual 4-Input NOR Gate
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired.
MC14011B
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
Quad 2-Input NAND Gate
• All Outputs Buffered
• Capable of Driving Two Low–power TTL Loads or One Low–power MC14012B
Schottky TTL Load Over the Rated Temperature Range. Dual 4-Input NAND Gate
• Double Diode Protection on All Inputs Except: Triple Diode Protection
on MC14011B and MC14081B
• Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix
MC14023B
Devices (Exceptions: MC14068B and MC14078B) Triple 3-Input NAND Gate

MC14025B
Triple 3-Input NOR Gate

MC14068B
8-Input NAND Gate
L SUFFIX P SUFFIX D SUFFIX
CERAMIC
CASE 632
PLASTIC
CASE 646
SOIC
CASE 751A MC14071B
Quad 2-Input OR Gate
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
Plastic
Ceramic MC14072B
MC14XXXBD SOIC Dual 4-Input OR Gate

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.
MC14073B
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit
Triple 3-Input AND Gate

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VDD

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
MC14075B
Triple 3-Input OR Gate

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
lin, lout

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Input or Output Current (DC or Transient),

ÎÎÎÎÎÎ
ÎÎÎ
per Pin
± 10 mA
MC14078B
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ 8-Input NOR Gate
PD Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C
MC14081B
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur. Quad 2-Input AND Gate
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C MC14082B
Dual 4-Input AND Gate
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA MC14001B


6–5
LOGIC DIAGRAMS

NOR NAND OR AND

MC14001B MC14011B MC14071B MC14081B


Quad 2–Input NOR Gate Quad 2–Input NAND Gate Quad 2–Input OR Gate Quad 2–Input AND Gate

1 1 1 1
3 3 3 3
2 2 2 2

5 5 5 5
2 INPUT

4 4 4 4
6 6 6 6

8 8 8 8
10 10 10 10
9 9 9 9

12 12 12 12
11 11 11 11
13 13 13 13

MC14025B MC14023B MC14075B MC14073B


Triple 3–Input NOR Gate Triple 3–Input NAND Gate Triple 3–Input OR Gate Triple 3–Input AND Gate

1 1 1 1
2 9 2 9 2 9 2 9
8 8 8 8
3 INPUT

3 3 3 3
4 6 4 6 4 6 4 6
5 5 5 5
11 11 11 11
12 10 12 10 12 10 12 10
13 13 13 13

MC14002B MC14012B MC14072B MC14082B


Dual 4–Input NOR Gate Dual 4–Input NAND Gate Dual 4–Input OR Gate Dual 4–Input AND Gate

2 2 2 2
3 1 3 1 3 1 3 1
4 4 4 4
4 INPUT

5 5 5 5
9 9 9 9
10 13 10 13 10 13 10 13
11 11 11 11
12 12 12 12
NC = 6, 8 NC = 6, 8 NC = 6, 8 NC = 6, 8

MC14078B MC14068B
8–Input NOR Gate 8–Input NAND Gate
VDD = PIN 14
2 2
VSS = PIN 7
3 3
4 4 FOR ALL DEVICES
8 INPUT

5 5
13 13
9 9
10 10
11 11
12 NC = 6, 8 12 NC = 6, 8

MC14001B MOTOROLA CMOS LOGIC DATA


6–6
PIN ASSIGNMENTS

MC14001B MC14002B MC14011B MC14012B


Quad 2–Input NOR Gate Dual 4–Input NOR Gate Quad 2–Input NAND Gate Dual 4–Input NAND Gate

IN 1A 1 14 VDD OUTA 1 14 VDD IN 1A 1 14 VDD OUTA 1 14 VDD


IN 2A 2 13 IN 2D IN 1A 2 13 OUTB IN 2A 2 13 IN 2D IN 1A 2 13 OUTB
OUTA 3 12 IN 1D IN 2A 3 12 IN 4B OUTA 3 12 IN 1D IN 2A 3 12 IN 4B
OUTB 4 11 OUTD IN 3A 4 11 IN 3B OUTB 4 11 OUTD IN 3A 4 11 IN 3B
IN 1B 5 10 OUTC IN 4A 5 10 IN 2B IN 1B 5 10 OUTC IN 4A 5 10 IN 2B
IN 2B 6 9 IN 2C NC 6 9 IN 1B IN 2B 6 9 IN 2C NC 6 9 IN 1B
VSS 7 8 IN 1C VSS 7 8 NC VSS 7 8 IN 1C VSS 7 8 NC

MC14023B MC14025B MC14068B MC14071B


Triple 3–Input NAND Gate Triple 3–Input NOR Gate 8–Input NAND Gate Quad 2–Input OR Gate

IN 1A 1 14 VDD IN 1A 1 14 VDD NC 1 14 VDD IN 1A 1 14 VDD


IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C IN 1 2 13 OUT IN 2A 2 13 IN 2D
IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C IN 2 3 12 IN 8 OUTA 3 12 IN 1D
IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C IN 3 4 11 IN 7 OUTB 4 11 OUTD
IN 3B 5 10 OUTC IN 3B 5 10 OUTC IN 4 5 10 IN 6 IN 1B 5 10 OUTC
OUTB 6 9 OUTA OUTB 6 9 OUTA NC 6 9 IN 5 IN 2B 6 9 IN 2C
VSS 7 8 IN 3A VSS 7 8 IN 3A VSS 7 8 NC VSS 7 8 IN 1C

MC14072B MC14073B MC14075B MC14078B


Dual 4–Input OR Gate Triple 3–Input AND Gate Triple 3–Input OR Gate 8–Input NOR Gate

OUTA 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD NC 1 14 VDD


IN 1A 2 13 OUTB IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C IN 1 2 13 OUT
IN 2A 3 12 IN 4B IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C IN 2 3 12 IN 8
IN 3A 4 11 IN 3B IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C IN 3 4 11 IN 7
IN 4A 5 10 IN 2B IN 3B 5 10 OUTC IN 3B 5 10 OUTC IN 4 5 10 IN 6
NC 6 9 IN 1B OUTB 6 9 OUTA OUTB 6 9 OUTA NC 6 9 IN 5
VSS 7 8 NC VSS 7 8 IN 3A VSS 7 8 IN 3A VSS 7 8 NC

MC14081B MC14082B
Quad 2–Input AND Gate Dual 4–Input AND Gate

IN 1A 1 14 VDD OUTA 1 14 VDD


IN 2A 2 13 IN 2D IN 1A 2 13 OUTB
OUTA 3 12 IN 1D IN 2A 3 12 IN 4B
OUTB 4 11 OUTD IN 3A 4 11 IN 3B
IN 1B 5 10 OUTC IN 4A 5 10 IN 2B
IN 2B 6 9 IN 2C NC 6 9 IN 1B
VSS 7 8 IN 1C VSS 7 8 NC NC = NO CONNECTION

MOTOROLA CMOS LOGIC DATA MC14001B


6–7
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc

ÎÎÎÎÎÎÎÎÎÎ
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ

ÎÎÎÎ
1.5

ÎÎÎ

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15


3.0
4.0


4.50
6.75
3.0
4.0


3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11


7.0
11
5.50
8.25


7.0
11

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6


0.51
1.3
0.88
2.25


0.36
0.9


mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
Quiescent Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(Per Package)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10


0.25
0.5


0.0005
0.0010
0.25
0.5


7.5
15
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.3 µA/kHz) f + IDD/N µAdc
(Dynamic plus Quiescent, 10 IT = (0.6 µA/kHz) f + IDD/N

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Per Gate, CL = 50 pF) 15 IT = (0.9 µA/kHz) f + IDD/N
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.

MC14001B MOTOROLA CMOS LOGIC DATA


6–8
B–SERIES GATE SWITCHING TIMES

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Rise Time, All B–Series Gates tTLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tTLH = (1.35 ns/pF) CL + 33 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
tTLH = (0.60 ns/pF) CL + 20 ns
tTLH = (0.40 ns/PF) CL + 20 ns
5.0
10


100
50
200
100

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Fall Time, All B–Series Gates tTHL ns
tTHL = (1.35 ns/pF) CL + 33 ns 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tTHL = (0.60 ns/pF) CL + 20 ns 10 — 50 100
tTHL = (0.40 ns/pF) CL + 20 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Time tPLH, tPHL ns
MC14001B, MC14011B only

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.90 ns/pF) CL + 80 ns 5.0 — 125 250

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 32 ns 10 — 50 100
tPLH, tPHL = (0.26 ns/pF) CL + 27 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
All Other 2, 3, and 4 Input Gates
tPLH, tPHL = (0.90 ns/pF) CL + 115 ns 5.0 — 160 300

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 47 ns 10 — 65 130

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns 15 — 50 100
8–Input Gates (MC14068B, MC14078B)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.90 ns/pF) CL + 155 ns 5.0 — 200 350

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 62 ns 10 — 80 150
tPLH, tPHL = (0.26 ns/pF) CL + 47 ns 15 — 60 110
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

14 VDD 20 ns 20 ns
VDD
INPUT 90%
INPUT 50%
PULSE 10% 0V
OUTPUT tPHL tPLH
GENERATOR

CL 90% VOH
* 50%
OUTPUT 10%
INVERTING VOL
tTHL tTLH
tPLH tPHL
7 VSS OUTPUT VOH
90%
NON–INVERTING 50%
* All unused inputs of AND, NAND gates must be connected to VDD. 10% VOL
All unused inputs of OR, NOR gates must be connected to VSS. tTLH tTHL

Figure 1. Switching Time Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATA MC14001B


6–9
CIRCUIT SCHEMATIC
NOR, OR GATES

MC14001B, MC14071B
One of Four Gates Shown
VDD
14 VDD
1, 6, 8, 13

*
2, 5, 9, 12

3, 4, 10, 11
MC14025B, MC14075B
One of Three Gates Shown

7 VSS VDD
VSS
1, 3, 11
* Inverter omitted in MC14001B

2, 4, 12

14 VDD

*
MC14002B, MC14072B
One of Two Gates Shown VSS
9, 6, 10
VDD VDD
3, 9
8, 5, 13
2, 10
7 VSS
14 VDD
VSS
* * Inverter omitted in MC14025B

VSS 1, 13

5, 11 SAME AS
4, 12 ABOVE
7 VSS
* Inverter omitted in MC14002B

VDD MC14078B
Eight Input Gate
2

14 VDD

VSS
4 SAME AS
5 ABOVE
SAME AS 13
9
10 ABOVE
11 SAME AS
12 ABOVE
7 VSS

MC14001B MOTOROLA CMOS LOGIC DATA


6–10
CIRCUIT SCHEMATIC
NAND, AND GATES

MC14011B, MC14081B
One of Four Gates Shown
14 VDD

MC14023B, MC14073B
3, 4, 10, 11
One of Three Gates Shown
VDD 2, 5, 9, 12

1, 6, 8, 13
7 VSS
* Inverter omitted in MC14011B

2, 4, 12 14 VDD

1, 3, 11
VSS
*
VDD

9, 6, 10
MC14012B, MC14082B
8, 5, 13
One of Two Gates Shown
VDD
7 VSS
VSS
* Inverter omitted in MC14023B

14 VDD
MC14068B
VDD Eight Input Gate 2, 10

*
3, 9
VSS
1, 13
4, 12 SAME AS
VDD 5, 11 ABOVE
2
* Inverter omitted in MC14012B 7 VSS

VSS
5 SAME AS
4 ABOVE
14 VDD

VSS

VDD
9 SAME AS
13
10 ABOVE
11 SAME AS
12 ABOVE

7 VSS

VSS

MOTOROLA CMOS LOGIC DATA MC14001B


6–11
TYPICAL B–SERIES GATE CHARACTERISTICS

N–CHANNEL DRAIN CURRENT P–CHANNEL DRAIN CURRENT


(SINK) (SOURCE)
5.0 – 10
– 9.0
4.0 – 8.0 TA = – 55°C
ID , DRAIN CURRENT (mA)

ID , DRAIN CURRENT (mA)


– 7.0
TA = – 55°C – 40°C
3.0 – 6.0
– 40°C
– 5.0
+ 85°C + 25°C + 25°C
2.0 – 4.0 + 85°C
+ 125°C
– 3.0 + 125°C
1.0 – 2.0
– 1.0
0 0
0 1.0 2.0 3.0 4.0 5.0 0 – 1.0 – 2.0 – 3.0 – 4.0 – 5.0
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

Figure 2. VGS = 5.0 Vdc Figure 3. VGS = – 5.0 Vdc

20 – 50
18 – 45
TA = – 55°C
16 – 40
ID , DRAIN CURRENT (mA)

ID , DRAIN CURRENT (mA)

14 – 40°C – 35
12 + 25°C – 30 TA = – 55°C
+ 85°C
10 – 25 – 40°C
8.0 + 125°C – 20 + 25°C
+ 85°C
6.0 – 15
4.0 – 10 + 125°C

2.0 – 5.0
0 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 – 1.0 – 2.0 – 3.0 – 4.0 – 5.0 – 6.0 – 7.0 – 8.0 – 9.0 – 10
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

Figure 4. VGS = 10 Vdc Figure 5. VGS = – 10 Vdc

50 – 100
45 – 90
40 – 80
ID , DRAIN CURRENT (mA)

ID , DRAIN CURRENT (mA)

35 TA = – 55°C – 70
30 – 40°C – 60
TA = – 55°C
25 + 25°C – 50 – 40°C
20 + 85°C – 40 + 25°C
+ 125°C + 85°C
15 – 30
+ 125°C
10 – 20
5.0 – 10
0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 0 – 2.0 – 4.0 – 6.0 – 8.0 – 10 – 12 – 14 – 16 – 18 – 20
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

Figure 6. VGS = 15 Vdc Figure 7. VGS = – 15 Vdc


These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.

MC14001B MOTOROLA CMOS LOGIC DATA


6–12
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)

V out , OUTPUT VOLTAGE (Vdc) VOLTAGE TRANSFER CHARACTERISTICS

V out , OUTPUT VOLTAGE (Vdc)


SINGLE INPUT NAND, AND SINGLE INPUT NAND, AND
5.0 MULTIPLE INPUT NOR, OR MULTIPLE INPUT NOR, OR
10

4.0 8.0
SINGLE INPUT NOR, OR SINGLE INPUT NOR, OR
3.0 MULTIPLE INPUT NAND, AND 6.0 MULTIPLE INPUT NAND, AND
2.0 4.0

1.0 2.0

0 0
0 1.0 2.0 3.0 4.0 5.0 0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)

Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc

16 DC NOISE MARGIN
SINGLE INPUT NAND, AND
14 MULTIPLE INPUT NOR, OR The DC noise margin is defined as the input voltage range
V out , OUTPUT VOLTAGE (Vdc)

from an ideal “1” or “0” input level which does not produce
12
output state change(s). The typical and guaranteed limit val-
SINGLE INPUT NOR, OR
10 MULTIPLE INPUT NAND, AND
ues of the input values VIL and VIH for the output(s) to be at a
fixed voltage VO are given in the Electrical Characteristics
8.0 table. VIL and VIH are presented graphically in Figure 11.
Guaranteed minimum noise margins for both the “1” and
6.0
“0” levels =
4.0 1.0 V with a 5.0 V supply
2.0 2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
0
0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc)

Figure 10. VDD = 15 Vdc

Vout VDD Vout VDD

VO VO

VO VO

VDD VDD
0 Vin 0 Vin

VIL VIH VIL VIH


VSS = 0 VOLTS DC
(a) Inverting Function (b) Non–Inverting Function

Figure 11. DC Noise Immunity

MOTOROLA CMOS LOGIC DATA MC14001B


6–13
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14001UB
Quad 2-Input NOR Gate
UB-Suffix Series CMOS Gates MC14002UB
The UB Series logic gates are constructed with P and N channel Dual 4-Input NOR Gate
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired. The UB set of CMOS gates are inverting
MC14011UB
non–buffered functions. Quad 2-Input NAND Gate
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Linear and Oscillator Applications MC14012UB
• Capable of Driving Two Low–power TTL Loads or One Low–power Dual 4-Input NAND Gate
Schottky TTL Load Over the Rated Temperature Range
• Double Diode Protection on All Inputs
• Pin–for–Pin Replacements for Corresponding CD4000 Series UB Suffix
MC14023UB
Devices Triple 3-Input NAND Gate

MC14025UB
LOGIC DIAGRAMS Triple 3-Input NOR Gate
MC14001UB MC14002UB MC14011UB
Quad 2–Input Dual 4–Input Quad 2–Input
NOR Gate NOR Gate NAND Gate
L SUFFIX
1 2 1
3 3 CERAMIC
2 3 2 CASE 632
1
5 4 5
4 4
6 5 6
8 9 8
10 10 P SUFFIX
9 10 9
13 PLASTIC
12 11 12
11 11 CASE 646
13 12 13
NC = 6, 8

D SUFFIX
MC14012UB MC14023UB MC14025UB
SOIC
Dual 4–Input Triple 3–Input Triple 3–Input
CASE 751A
NAND Gate NAND Gate NOR Gate
1 1 ORDERING INFORMATION
2 2 9
2 9 MC14XXXUBCP Plastic
3
1 8 8 MC14XXXUBCL Ceramic
4 3 3 MC14XXXUBD SOIC
5
4 6 4 6 TA = – 55° to 125°C for all packages.
9
5 5
10
13 11 11
11
12 10 12 10 This device contains protection circuitry to
12
NC = 6, 8 13 13 guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
VDD = PIN 14 any voltage higher than maximum rated volt-
VSS = PIN 7 ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
v v
FOR ALL DEVICES
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.

MC14001UB MOTOROLA CMOS LOGIC DATA


6–14
PIN ASSIGNMENTS

MC14001UB MC14002UB MC14011UB


Quad 2–Input NOR Gate Dual 4–Input NOR Gate Quad 2–Input NAND Gate

IN 1A 1 14 VDD OUTA 1 14 VDD IN 1A 1 14 VDD


IN 2A 2 13 IN 2D IN 1A 2 13 OUTB IN 2A 2 13 IN 2D
OUTA 3 12 IN 1D IN 2A 3 12 IN 4B OUTA 3 12 IN 1D
OUTB 4 11 OUTD IN 3A 4 11 IN 3B OUTB 4 11 OUTD
IN 1B 5 10 OUTC IN 4A 5 10 IN 2B IN 1B 5 10 OUTC
IN 2B 6 9 IN 2C NC 6 9 IN 1B IN 2B 6 9 IN 2C
VSS 7 8 IN 1C VSS 7 8 NC VSS 7 8 IN 1C

MC14012UB MC14023UB MC14025UB


Dual 4–Input NAND Gate Triple 3–Input NAND Gate Triple 3–Input NOR Gate

OUTA 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD


IN 1A 2 13 OUTB IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C
IN 2A 3 12 IN 4B IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C
IN 3A 4 11 IN 3B IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C
IN 4A 5 10 IN 2B IN 3B 5 10 OUTC IN 3B 5 10 OUTC
NC 6 9 IN 1B OUTB 6 9 OUTA OUTB 6 9 OUTA
VSS 7 8 NC VSS 7 8 IN 3A VSS 7 8 IN 3A

NC = NO CONNECTION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
PD

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
_C

†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

MOTOROLA CMOS LOGIC DATA MC14001UB


6–15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc

ÎÎÎÎÎÎÎÎÎÎ
(VO = 4.5 Vdc)

ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ

ÎÎÎÎ
1.0

ÎÎÎ

ÎÎÎÎ
2.25

ÎÎÎ
1.0

ÎÎÎÎ

ÎÎÎ
1.0
(VO = 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VO = 13.5 Vdc)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15


2.0
2.5


4.50
6.75
2.0
2.5


2.0
2.5

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 Vdc) “1” Level IIH 5.0 4.0 — 4.0 2.75 — 4.0 — Vdc
(VO = 1.0 Vdc) 10 8.0 — 8.0 5.50 — 8.0 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VO = 1.5 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
Output Drive Current ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 12.5 — 12.5 8.25 — 12.5 —
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 1.2 — – 1.0 – 1.7 — – 0.7 —
(VOH = 4.6 Vdc) 5.0 – 0.25 — – 0.2 – 0.36 — – 0.14 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
– 0.62
– 1.8


– 0.5
– 1.5
– 0.9
– 3.5


– 0.35
– 1.1

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 0.25 — 0.0005 0.25 — 7.5 µAdc
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Gate CL = 50 pF)
ÎÎÎ
IT 5.0
10
15
IT = (0.3 µA/kHz) f + IDD/N
IT = (0.6 µA/kHz) f + IDD/N
IT = (0.8 µA/kHz) f + IDD/N
µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.

MC14001UB MOTOROLA CMOS LOGIC DATA


6–16
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 — 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 10 — 90 180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (1.1 ns/pF) CL + 10 ns 15 — 65 130

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time tTHL ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (1.5 ns/pF) CL + 25 ns

ÎÎÎÎÎ
5.0

ÎÎÎÎ

ÎÎÎÎ
100

ÎÎÎÎ
200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
tTHL = (0.75 ns/pF) CL + 12.5 ns

ÎÎÎÎ
tTHL = (0.55 ns/pF) CL + 9.5 ns

ÎÎÎ
10
15


50
40
100
80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, tPHL ns
tPLH, tPHL = (1.7 ns/pF) CL + 30 ns 5.0 — 90 180

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 22 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.50 ns/pF) CL + 15 ns 15 — 40 80
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

20 ns 20 ns
VDD
14 INPUT VDD
90%
50%
PULSE INPUT OUTPUT 10% 0V
GENERATOR tPHL tPLH
* CL 90% VOH
OUTPUT 50%
INVERTING
10% VOL
7 VSS
* All unused inputs of AND, NAND gates must be tTHL tTLH
connected to VDD.
All unused inputs of OR, NOR gates must be
connected to VSS.

Figure 1. Switching Time Test Circuit and Waveforms

MC14001UB CIRCUIT SCHEMATIC MC14002UB CIRCUIT SCHEMATIC


(1/2 of Device Shown)
VDD VDD 14
3 14 10 2, 9

1 8 3, 10

2 9 4, 11

5, 12

1, 13

6 13

5 12
VSS 7

4 7 11
VSS

MOTOROLA CMOS LOGIC DATA MC14001UB


6–17
MC14011UB CIRCUIT SCHEMATIC MC14012UB CIRCUIT SCHEMATIC MC14023UB CIRCUIT SCHEMATIC
(1/4 of Device Shown) (1/2 of Device Shown) (1/3 of Device Shown)

14 VDD
14 VDD 14 VDD

3, 4, 10, 11 1, 13
6, 9, 10
1, 6, 8, 13 2, 9
5, 1, 11
2, 5, 9, 12 3, 10

7 VSS 4, 11 4, 2, 12

5, 12
3, 8, 13
7 VSS
7 VSS

MC14025UB CIRCUIT SCHEMATIC 16 16


VDD = 15 Vdc TA = + 25°C VDD = 15 Vdc Unused input
(1/3 of Device Shown) 14 Unused input 14 connected to
b
Vout , OUTPUT VOLTAGE (Vdc)

Vout , OUTPUT VOLTAGE (Vdc)


connected to a VSS.

I D, DRAIN CURRENT (mAdc)


14 VDD 12 12
VSS.
10 Vdc a One input only 10 Vdc a TA = + 125°C
1, 3, 11 10 b Both inputs 10
b TA = – 55°C
2, 4, 12 8.0 8.0 8.0
b a a b
8, 5, 13
6.0 6.0 6.0
9, 6, 10 5.0 Vdc 5.0 Vdc
15 Vdc
4.0 b a 4.0 4.0
a 10 Vdc a b
b
2.0 2.0 2.0
7 VSS 0 0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 0 2.0 4.0 6.0 8.0 10 12 14 16
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)

Figure 2. Typical Voltage and Figure 3. Typical Voltage Transfer


Current Transfer Characteristics Characteristics versus
Temperature

0 10
c a 15 Vdc
b a
VGS = – 5.0 Vdc c
– 2.0 8.0
I D, DRAIN CURRENT (mAdc)

b VGS = 10 Vdc
I D, DRAIN CURRENT (mAdc)

a b
a TA = – 55°C
b TA = + 25°C c
– 4.0 6.0
c TA = + 125°C
a TA = – 55°C
c b TA = + 25°C
– 6.0 4.0 c TA = + 125°C
– 10 Vdc b
c a
– 8.0 b – 15 Vdc 2.0
b 5.0 Vdc
c
a a
– 10 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0 2.0 4.0 6.0 8.0 10
VDS, DRAIN VOLTAGE (Vdc) VDS, DRAIN VOLTAGE (Vdc)

Figure 4. Typical Output Source Figure 5. Typical Output Sink


Characteristics Characteristics

MC14001UB MOTOROLA CMOS LOGIC DATA


6–18
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14006B
18-Bit Static Shift Register
The MC14006B shift register is comprised of four separate shift register L SUFFIX
CERAMIC
sections sharing a common clock: two sections have four stages, and two
CASE 632
sections have five stages with an output tap on both the fourth and fifth
stages. This makes it possible to obtain a shift register of 4, 5, 8, 9, 10, 12,
13, 14, 16, 17, or 18 bits by appropriate selection of inputs and outputs. This
part is particularly useful in serial shift registers and time delay circuits. P SUFFIX
PLASTIC
• Output Transitions Occur on the Falling Edge of the Clock Pulse CASE 646
• Fully Static Operation
• Can be Cascaded to Provide Longer Shift Register Lengths
• Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX
• Capable of Driving Two Low–power TTL Loads or One Low–power SOIC
Schottky TTL Load Over the Rated Temperature Range CASE 751A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Pin–for–Pin Replacement for CD4006B

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ORDERING INFORMATION
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MC14XXXBCP Plastic
Symbol Parameter Value Unit MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C
TRUTH TABLE
(Single Stage)
Dn C Qn+1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
0 0
TL Lead Temperature (8–Second Soldering) 260 _C 1 1
* Maximum Ratings are those values beyond which damage to the device may occur. x Qn
X = Don’t Care
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

BLOCK DIAGRAM
1 13 4 11 12 5 10 6 8 9
DP1 Q4 DP5 Q8 Q9 DP10 Q13 DP14 Q17 Q18

VDD = PIN 14 D D D D D D
VSS = PIN 7 4 4 1 4 4 1
NC = PIN 2 STAGES STAGES STAGE STAGES STAGES STAGE
C C C C C C

CLOCK 3

LOGIC DIAGRAM
(ONE REGISTER STAGE)
C C
#
*
DATA D+1
* Transmission Gate (C) #Inverter used only on the first stage of
1 C C each four–stage element.

Input to output is
IN OUT (A) A bidirectional low impedance when control input 1 is “low” and control input 2 is “high”.
(B) An open circuit when control input 1 is “high” and control input 2 is “low”.
2
(C)

MOTOROLA CMOS LOGIC DATA MC14006B


6–19
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ

ÎÎÎÎ
1.5

ÎÎÎ

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15


3.0
4.0


4.50
6.75
3.0
4.0


3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
7.0

ÎÎÎÎ

ÎÎÎ
7.0

ÎÎÎÎ
5.50

ÎÎÎ

ÎÎÎÎ
7.0

ÎÎÎ

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (1.3 µA/kHz) f + IDD
IT = (2.6 µA/kHz) f + IDD
IT = (3.9 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching)

ÎÎÎ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

PIN ASSIGNMENT

DP1 1 14 VDD
NC 2 13 Q4
C 3 12 Q9
DP5 4 11 Q8
DP10 5 10 Q13
DP14 6 9 Q18
VSS 7 8 Q17

NC = NO CONNECTION

MC14006B MOTOROLA CMOS LOGIC DATA


6–20
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol VDD Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 220 ns

ÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 77 ns
tPHL 5.0
10


300
110
600
220

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 55 ns 15 — 80 160

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 200 100 — ns
10 120 60 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl
15

5.0
80


40

5.0

2.5 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 8.3 4.2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 12 6.0
µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Rise and Fall Time** tTLH 5.0 — — 15
tTHL 10 — — 5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu
15

5.0

0

– 50
4

— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 0 – 15 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 0 – 8.0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Time th 5.0 180 75 — ns
10 90 25 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
* The formulas given are for the typical characteristics only at 25_C.
15 75 20

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

** When shift register sections are cascaded, the maximum rise and fall times of the clock input should be equal to or less than the rise and fall times
** of the data outputs driving data inputs, plus the propagation delay of the output driving stage for the output capacitance load.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

VDD = – VGS Vout VDD = VGS Vout

14 14

CLOCK Q4 CLOCK Q4
DP1 Q8 DP1 Q8
Q9 Q9
DP5 Q13 DP5 Q13
DP10 Q17 IOH DP10 Q17 IOL
DP14 Q18 DP14 Q18

7 VSS EXTERNAL VSS EXTERNAL


POWER POWER
SUPPLY SUPPLY

Figure 1. Typical Output Source Current Figure 2. Typical Output Sink Current
Characteristics Test Circuit Characteristics Test Circuit

MOTOROLA CMOS LOGIC DATA MC14006B


6–21
VDD
14
PULSE
GENERATOR CLOCK Q4
DP1 Q8
Q9
DP5 Q13 CL CL
DP10 Q17 14
TEST 8 9
DP14 Q18
1/3 MC14000
PRESET 7
7 VSS CL CL CL CL OR EQUIV
50
ID
µF

1
f
CLOCK 50%

DATA

Figure 3. Power Dissipation Test Circuit and Waveforms

VDD

14

PULSE
CLOCK Q4
GENERATOR 1
DP1 Q8
Q9
DP5
Q13 CL
DP10 Q17 CL
PULSE CL
DP14 Q18
GENERATOR 2 CL
CL
7 VSS CL

20 ns 20 ns tWL tWH

90% VDD
CLOCK 50%
10% VSS
th “1” th “0”
tsu “1” tsu “0”
90% VDD
DATA 50%
10% VSS

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
4–STAGE 20 ns 20 ns tPLH tPHL

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
OUTPUT VOH
90%
Q4, Q8 50%
10% VOL
Q13, Q17 tTLH tTHL

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
tPHL
5–STAGE VOH

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
OUTPUT 90%
50%
Q9, Q18 10% VOL

ÉÉÉ
tTLH tTHL

ÉÉÉ
Output state can change since data previously clocked in might be in either state.

Figure 4. Switching Time Test Circuit and Waveforms

MC14006B MOTOROLA CMOS LOGIC DATA


6–22
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14007UB
Dual Complementary Pair
Plus Inverter L SUFFIX
CERAMIC
The MC14007UB multi–purpose device consists of three N–channel and CASE 632
three P–channel enhancement mode devices packaged to provide access to
each device. These versatile parts are useful in inverter circuits, pulse–
shapers, linear amplifiers, high input impedance amplifiers, threshold P SUFFIX
detectors, transmission gating, and functional gating. PLASTIC
CASE 646
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
D SUFFIX
Schottky TTL Load Over the Rated Temperature Range SOIC
• Pin–for–Pin Replacement for CD4007A or CD4007UB CASE 751A
• This device has 2 outputs without ESD Protection. Anti–static

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
precautions must be taken. ORDERING INFORMATION

ÎÎÎÎ
Î ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXUBCP Plastic
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXUBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit MC14XXXUBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA
PIN ASSIGNMENT

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW D–PB 1 14 VDD
S–PB 2 13 D–PA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C
GATEB 3 12 OUTC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur. S–NB 4 11 S–PC
†Temperature Derating: D–NB 5 10 GATEC
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C GATEA 6 9 S–NC
VSS 7 8 D–NA
A A
D = DRAIN
12 9 S = SOURCE
B
1 B
2
C 3 SCHEMATIC
INPUT 14 13 2 1 11
VDD 5 4
14 C
11 6 12
13
INPUT OUTPUT CONDITION INPUT
6 8 10
1 A = C, B = OPEN
0 A = B, C = OPEN

7 VSS 7 8 3 4 5 10 9
Substrates of P–channel devices internally VDD = PIN 14
connected to VDD; substrates of N–channel VSS = PIN 7
devices internally connected to VSS.

Figure 1. Typical Application: 2–Input Analog Multiplexer

MOTOROLA CMOS LOGIC DATA MC14007UB


6–23
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ

ÎÎÎÎ
1.0

ÎÎÎ

ÎÎÎÎ
2.25

ÎÎÎ
1.0

ÎÎÎÎ

ÎÎÎ
1.0
(VO = 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VO = 13.5 Vdc)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15


2.0
2.5


4.50
6.75
2.0
2.5


2.0
2.5

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 Vdc) “1” Level VIH 5.0 4.0 — 4.0 2.75 — 4.0 — Vdc
(VO = 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
8.0

ÎÎÎÎ

ÎÎÎ
8.0

ÎÎÎÎ
5.50

ÎÎÎ

ÎÎÎÎ
8.0

ÎÎÎ

(VO = 1.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 12.5 — 12.5 8.25 — 12.5 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 5.0 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 1.0 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.5 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 10 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 1.0 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.5 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 10 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 0.25 — 0.0005 0.25 — 7.5 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 0.5 — 0.0010 0.5 — 15
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Gate) (CL = 50 pF)
ÎÎÎ
IT 5.0
10
15
IT = (0.7 µA/kHz) f + IDD/6
IT = (1.4 µA/kHz) f + IDD/6
IT = (2.2 µA/kHz) f + IDD/6
µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14007UB MOTOROLA CMOS LOGIC DATA


6–24
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise Time tTLH ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (1.2 ns/pF) CL + 30 ns 5.0 — 90 180
tTLH = (0.5 ns/pF) CL + 20 ns 10 — 45 90

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Output Fall Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tTLH = (0.4 ns/pF) CL + 15 ns

ÎÎÎÎÎÎÎ tTHL
15 — 35 70
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (1.2 ns/pF) CL + 15 ns 5.0 — 75 150

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (0.5 ns/pF) CL + 15 ns 10 — 40 80
tTHL = (0.4 ns/pF) CL + 10 ns 15 — 30 60

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
Turn–Off Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ tPLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (1.5 ns/pF) CL + 35 ns 5.0 — 60 125

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.2 ns/pF) CL + 20 ns 10 — 30 75
tPLH = (0.15 ns/pF) CL + 17.5 ns 15 — 25 55

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Turn–On Delay Time
tPHL = (1.0 ns/pF) CL + 10 ns 5.0 — 60 125

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.3 ns/pF) CL + 15 ns 10 — 30 75
tPHL = (0.2 ns/pF) CL + 15 ns 15 — 25 55
* The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD = – VGS VDD = VGS

14
IOH VDS = VOH – VDD 14
IOL VDS = VOL
7 VSS
7 VSS

All unused inputs connected to ground. All unused inputs connected to ground.

0 20
a VGS = 15 Vdc
b
c
c
IOL , DRAIN CURRENT (mAdc)
IOH , DRAIN CURRENT (mAdc)

– 4.0 16
VGS = – 5.0 Vdc b a
10 Vdc
– 8.0 a TA = – 55°C a 12
b TA = + 25°C b c
c TA = + 125°C a TA = – 55°C
c b
– 12 8.0 b TA = + 25°C
b c TA = + 125°C
c
– 10 Vdc a – 15 Vdc a
– 16 4.0
a b 5.0 Vdc
c
– 20 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 –0 0 2.0 4.0 6.0 8.0 10
VDS, DRAIN VOLTAGE (Vdc) VDS, DRAIN VOLTAGE (Vdc)

Figure 2. Typical Output Source Characteristics Figure 3. Typical Output Sink Characteristics

These typical curves are not guarantees, but are design aids.
Caution: The maximum current rating is 10 mA per pin.

MOTOROLA CMOS LOGIC DATA MC14007UB


6–25
VDD
20 ns 20 ns
0.01 µF VDD
90%
500 µF ID CERAMIC Vin 50%
10% VSS
14 tPHL tPLH
PULSE Vin VOH
Vout 90%
GENERATOR Vout 50%
7 VSS CL 10%
VOL
tTHL tTLH

Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms

APPLICATIONS

The MC14007UB dual pair plus inverter, which has access VDD
to all its elements offers a number of unique circuit applica- 14 OUT = A+B•C
tions. Figures 1, 5, and 6 are a few examples of the device
flexibility.
13
+ VDD 11 2
2
DISABLE 3
10 12 1
1 B OUTPUT
8
11

9 7
INPUT 10 12 OUTPUT 5
3
C
9 4
8
6
DISABLE 6 A
7
Substrates of P–channel devices internally connected to VDD;
Substrates of N–channel devices internally connected to VSS.
INPUT DISABLE OUTPUT
1 0 0 Figure 6. AOI Functions Using Tree Logic
0 0 1
X 1 OPEN
X = Don’t Care

Figure 5. 3–State Buffer

MC14007UB MOTOROLA CMOS LOGIC DATA


6–26
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14008B
4-Bit Full Adder
The MC14008B 4–bit full adder is constructed with MOS P–channel and L SUFFIX
CERAMIC
N–channel enhancement mode devices in a single monolithic structure. This
CASE 620
device consists of four full adders with fast internal look–ahead carry output.
It is useful in binary addition and other arithmetic applications. The fast
parallel carry output bit allows high–speed operation when used with other
adders in a system. P SUFFIX
PLASTIC
• Look–Ahead Carry Output CASE 648
• Diode Protection on All Inputs
• All Outputs Buffered
• Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX
• Capable of Driving Two Low–power TTL Loads or One Low–power SOIC
Schottky TTL Load Over the Rated Temperature Range CASE 751B
• Pin–for–Pin Replacement for CD4008B

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
± 10

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), mA
per Pin TRUTH TABLE

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
(One Stage)
PD Power Dissipation, per Package† 500 mW

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Cin B A Cout S
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
0 0 0 0 0
TL Lead Temperature (8–Second Soldering) 260 _C 0 0 1 0 1
* Maximum Ratings are those values beyond which damage to the device may occur. 0 1 0 0 1
†Temperature Derating: 0 1 1 1 0
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 1 0 0 0 1
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 1 0 1 1 0
1 1 0 1 0
BLOCK DIAGRAM 1 1 1 1 1

HIGH–SPEED
14 Cout
PARALLEL CARRY PIN ASSIGNMENT

A4 1 16 VDD
B4 15 ADDER
13 S4 B3 2 15 B4
A4 1 4
A3 3 14 Cout
C4
B3 2 B2 4 13 S4
ADDER
12 S3
A3 3 3 A2 5 12 S3

C3 B1 6 11 S2
B2 4 ADDER A1 7 10 S1
11 S2
A2 5 2 VSS 8 9 Cin
C2
B1 6 ADDER
10 S1
A1 7 1
VDD = PIN 16
Cin 9 VSS = PIN 8

MOTOROLA CMOS LOGIC DATA MC14008B


6–27
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ

ÎÎÎÎ
1.5

ÎÎÎ

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15


3.0
4.0


4.50
6.75
3.0
4.0


3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
7.0

ÎÎÎÎ

ÎÎÎ
7.0

ÎÎÎÎ
5.50

ÎÎÎ

ÎÎÎÎ
7.0

ÎÎÎ

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (1.7 µA/kHz) f + IDD
IT = (3.4 µA/kHz) f + IDD
IT = (5.0 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching)

ÎÎÎ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14008B MOTOROLA CMOS LOGIC DATA


6–28
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ
Propagation Delay Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎÎÎÎ tPLH, tPHL


15 — 40 80
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Sum in to Sum Out

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns 5.0 — 400 800
tPLH, tPHL = (0.66 ns/pF) CL + 127 ns 10 — 160 320

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 90 ns 15 — 115 230

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Sum In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 220 ns 5.0 — 305 610

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 112 ns 10 — 145 290

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 85 ns 15 — 110 220

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Carry In to Sum Out
tPLH, tPHL = (1.7 ns/pF) CL + 290 ns 5.0 — 375 750

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 122 ns 10 — 155 310

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 90 ns 15 — 115 230
Carry In to Carry Out

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 85 ns 5.0 — 170 340

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 — 75 150
tPLH, tPHL = (0.5 ns/pF) CL + 30 ns —
15 55 110
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD = – VGS Vout VDD = VGS Vout

16 16

B4 S4 B4 S4
A4 A4
B3 S3 B3 S3
A3 A3
B2 S2 B2 S2
A2 A2
B1 S1 IOH B1 S1 IOL
A1 A1
Cin Cout Cin Cout
EXTERNAL EXTERNAL
8 VSS POWER 8 VSS POWER
SUPPLY SUPPLY

Figure 1. Typical Source Current Figure 2. Typical Sink Current


Characteristics Test Circuit Characteristics Test Circuit

MOTOROLA CMOS LOGIC DATA MC14008B


6–29
VDD

16

B4 S4
A4
B3 S3
20 ns 20 ns A3
B2 S2
VDD A2
90% CL
Vin B1 S1
10% VSS CL
A1
PULSE CL
Cin Cout
GENERATOR CL
CL
8 VSS

500 µF IDD

Figure 3. Dynamic Power Dissipation Test Circuit and Waveform

VDD

16

B4 S4
A4
B3 S3
A3
B2 S2
A2
B1 S1 CL
A1 CL
PULSE CL
Cin Cout
GENERATOR CL
8 VSS CL

IDD

20 ns 20 ns
VDD
90%
Cin 50%
10% VSS
tPHL tPLH
90% VOH
S1 – S4 50%
10% VOL
tTHL tTLH
VOH
Cout 50%
VOL
tPLH tPHL

Figure 4. Switching Time Test Circuit and Waveforms

MC14008B MOTOROLA CMOS LOGIC DATA


6–30
Cout

B4

S4
A4

B3

S3
A3

B2

S2
A2

B1

S1
A1

Cin

Figure 5. Logic Diagram

MOTOROLA CMOS LOGIC DATA MC14008B


6–31
TYPICAL APPLICATION

WORD A + B INPUTS

A1 B4 A1 B4 A1 B4 A1 B4

CHIP CHIP CHIP CHIP


Cin Cout Cin Cout Cin Cout Cin Cout
1 2 3 4

S1 S4 S1 S4 S1 S4 S1 S4

SUM OUTPUTS

Calculation of 16–bit adder speed:


tP total = tP (Sum to Carry) + tP (Carry to Sum) + 2 tP (Carry to Carry)
The guaranteed 16–bit adder speed at 10 V, 25°C, CL = 50 pF is:
tp total = 290 + 310 + 300 = 900 ns

Figure 6. Using the MC14008B in a 16–Bit Adder Configuration

MC14008B MOTOROLA CMOS LOGIC DATA


6–32
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14013B
Dual Type D Flip-Flop
The MC14013B dual type D flip–flop is constructed with MOS P–channel L SUFFIX
CERAMIC
and N–channel enhancement mode devices in a single monolithic structure.
CASE 632
Each flip–flop has independent Data, (D), Direct Set, (S), Direct Reset, (R),
and Clock (C) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flip–flops for counter and
toggle applications. P SUFFIX
PLASTIC
• Static Operation CASE 646
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge–Clocked Flip–Flop Design D SUFFIX
Logic state is retained indefinitely with clock level either high or low; SOIC
information is transferred to the output only on the positive–going edge CASE 751A
of the clock pulse
• Capable of Driving Two Low–power TTL Loads or One Low–power ORDERING INFORMATION
Schottky TTL Load Over the Rated Temperature Range MC14XXXBCP Plastic
• Pin–for–Pin Replacement for CD4013B MC14XXXBCL Ceramic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V
BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA 6
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
S
PD Power Dissipation, per Package† 500 mW 5 D Q 1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
_C 3 C
R
Q 2

4
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 8

S
9 D Q 13
TRUTH TABLE
Inputs Outputs
Clock† Data Reset Set Q Q 11 C Q 12
R
0 0 0 0 1
10
1 0 0 1 0
No VDD = PIN 14
X 0 0 Q Q VSS = PIN 7
Change
X X 1 0 0 1
X X 0 1 1 0
X X 1 1 1 1
X = Don’t Care
† = Level Change

MOTOROLA CMOS LOGIC DATA MC14013B


6–33
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ

ÎÎÎÎ
1.5

ÎÎÎ

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15


3.0
4.0


4.50
6.75
3.0
4.0


3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
7.0

ÎÎÎÎ

ÎÎÎ
7.0

ÎÎÎÎ
5.50

ÎÎÎ

ÎÎÎÎ
7.0

ÎÎÎ

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 1.0 — 0.002 1.0 — 30 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 2.0 — 0.004 2.0 — 60
15 — 4.0 — 0.006 4.0 — 120

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (0.75 µA/kHz) f + IDD
IT = (1.5 µA/kHz) f + IDD
IT = (2.3 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching)

ÎÎÎ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated QA 1 14 VDD
voltages to this high-impedance circuit. For proper operation, Vin and QA 2 13 QB
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage CA 3 12 QB
level (e.g., either VSS or VDD). Unused outputs must be left open. RA 4 11 CB
DA 5 10 RB
SA 6 9 DB
VSS 7 8 SB

MC14013B MOTOROLA CMOS LOGIC DATA


6–34
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol VDD Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Q, Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns 5.0 — 175 350

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 — 75 150

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns 15 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns 5.0 — 175 350

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 — 75 150

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns 15 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns 5.0 — 225 450

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns 10 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 50 ns 15 — 75 150
Setup Times** tsu ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
5.0

ÎÎÎÎ
40

ÎÎÎÎ
20

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
10
15
20
15
10
7.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Times** th 5.0 40 20 — ns
10 20 10 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWL, tWH
15
5.0
15
250
7.5
125

— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 50 —
15 70 35 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ fcl 5.0 — 4.0 2.0 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 10 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 14 7.0
µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Rise and Fall Time tTLH 5.0 — — 15
tTHL 10 — — 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — — 4.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set and Reset Pulse Width tWL, tWH 5.0 250 125 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 50
15 70 35 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Removal Times
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ trem ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set 5 80 0 —
10 45 5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15
5
35
50
5
– 35

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 30 – 10 —
15 25 –5 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.

LOGIC DIAGRAM
(1/2 of Device Shown)
S
C C Q

C C Q
C C

C C
C C
C
R

MOTOROLA CMOS LOGIC DATA MC14013B


6–35
20 ns 20 ns
VDD
90%
D 50%
10% 20 ns 20 ns
tsu (L) VSS
tsu (H) 90% VDD
th 20 ns SET OR
VDD 50%
90% RESET 10%
C 50% VSS
10% tw trem
VSS 20 ns 20 ns
tWH tWL 90% VDD
CLOCK 50%
1 10%
VSS
fcl
tPLH tPHL tPLH tw
VOH tPHL
90%
Q 50% VOH
10% VOL Q OR Q 50%
VOL
tTLH tTHL

Inputs R and S low.

Figure 1. Dynamic Signal Waveforms Figure 2. Dynamic Signal Waveforms


(Data, Clock, and Output) (Set, Reset, Clock, and Output)

TYPICAL APPLICATIONS

n–STAGE SHIFT REGISTER


1 2 nth
D D Q D Q D Q Q

C Q C Q C Q

CLOCK

BINARY RIPPLE UP–COUNTER (Divide–by–2n)


1 2 nth
D Q D Q D Q Q

CLOCK C Q C Q C Q

T FLIP–FLOP

MODIFIED RING COUNTER (Divide–by–(n+1))


1 2 nth
D Q D Q D Q Q

C Q C Q C Q

CLOCK

MC14013B MOTOROLA CMOS LOGIC DATA


6–36
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14014B
MC14021B
8-Bit Static Shift Register
The MC14014B and MC14021B 8–bit static shift registers are constructed
with MOS P–channel and N–channel enhancement mode devices in a single
monolithic structure. These shift registers find primary use in parallel–to– L SUFFIX
serial data conversion, synchronous and asynchronous parallel input, serial CERAMIC
output data queueing; and other general purpose register applications CASE 620
requiring low power and/or high noise immunity.
• Synchronous Parallel Input/Serial Output (MC14014B)
P SUFFIX
• Asynchronous Parallel Input/Serial Output (MC14021B)
PLASTIC
• Synchronous Serial Input/Serial Output CASE 648
• Full Static Operation
• “Q” Outputs from Sixth, Seventh, and Eighth Stages
• Double Diode Input Protection D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC
• Capable of Driving Two Low–power TTL Loads or One Low–power CASE 751B
Schottky TTL Load Over the Rated Temperature Range
ORDERING INFORMATION
• MC14014B Pin–for–Pin Replacement for CD4014B
MC14XXXBCP Plastic
• MC14021B Pin–for–Pin Replacement for CD4021B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCL Ceramic
MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V TRUTH TABLE

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V SERIAL OPERATION:

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA Q6 Q7 Q8
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
t Clock DS P/S t=n+6 t=n+7 t=n+8
PD Power Dissipation, per Package† 500 mW n 0 0 0 ? ?

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature – 65 to + 150 _C
n+1 1 0 1 0 ?

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
n+2 0 0 0 1 0
TL Lead Temperature (8–Second Soldering) 260 _C n+3 1 0 1 0 1
* Maximum Ratings are those values beyond which damage to the device may occur. X 0 Q6 Q7 Q8
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C PARALLEL OPERATION:
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C Clock
MC14014B MC14021B DS P/S Pn *Qn
X X 1 0 0
X X 1 1 1
* Q6, Q7, & Q8 are available externally
LOGIC DIAGRAM X = Don’t Care

P1 P2 P3 P6 P7 P8
9 7 6 5 14 15 1
P/S

11
DS D Q D Q D Q D Q D Q D

C C C C Q C Q C Q

10
CLOCK

VDD = PIN 16 P4 = PIN 4


VSS = PIN 8 P5 = PIN 13 2 12 3
Q6 Q7 Q8

MOTOROLA CMOS LOGIC DATA MC14014B MC14021B


6–37
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ

ÎÎÎÎ
1.5

ÎÎÎ

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15


3.0
4.0


4.50
6.75
3.0
4.0


3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
7.0

ÎÎÎÎ

ÎÎÎ
7.0

ÎÎÎÎ
5.50

ÎÎÎ

ÎÎÎÎ
7.0

ÎÎÎ

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 15 — 0.015 15 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (0.75 µA/kHz) f + IDD
IT = (1.50 µA/kHz) f + IDD
IT = (2.25 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching)

ÎÎÎ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.0015.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
P8 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q6 2 15 P7
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Q8 3 14 P6
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. P4 4 13 P5
P3 5 12 Q7
P2 6 11 DS
P1 7 10 C
VSS 8 9 P/S

MC14014B MC14021B MOTOROLA CMOS LOGIC DATA


6–38
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time (Clock to Q, P/S to Q) tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL, tPLH = (1.7 ns/pF) CL + 315 ns tPHL 5.0 — 400 800
tPHL, tPLH = (0.66 ns/pF) CL + 137 ns 10 — 170 340

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL, tPLH = (0.5 ns/pF) CL + 90 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 115 230

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tWH 5.0
10
400
175
150
75


ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 135 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Frequency fcl 5.0 — 3.0 1.5 MHz
10 — 6.0 3.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Parallel/Serial Control Pulse Width tWH
15

5.0

400
8.0

150
4.0

— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 175 75 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 135 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time tsu 5.0 200 100 — ns
P/S to Clock 10 100 50 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Time ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th
15

5.0
80

20
40

– 2.5

— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to P/S 10 20 – 10 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 25 0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time tsu 5.0 350 150 — ns
Data (Parallel or Serial) to 10 80 50 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Clock or P/S

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Time ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th
15

5.0
60

45
30

0

— ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Ds 10 35 0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 35 5 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hold Time th 5.0 50 25 — ns
Clock to Pn 10 45 20 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 45 20 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Clock Rise Time tr(cl) 5.0 — — 15 µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — — 5
15 — — 4
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD Vout VDD Vout

P/S Q6 P/S Q6
PULSE PULSE
C C
GENERATOR GENERATOR
P6 Q7 P6 Q7
P7 P7
P8 IOH P8 IOL
DS Q8 DS Q8

EXTERNAL EXTERNAL
POWER POWER
SUPPLY SUPPLY

Preset output under test to a logic “1” level.

Figure 1. Output Source Current Test Circuit Figure 2. Output Sink Current Test Circuit

MOTOROLA CMOS LOGIC DATA MC14014B MC14021B


6–39
VDD

500 µF ID

0.01 µF
CERAMIC
P/S
PULSE
C Q6
GENERATOR 1
P1
P2 CL
P3
P4 Q7
P5
P6 CL
P7
PULSE P8 Q8
DS
GENERATOR 2
CL
VSS

1
f
CLOCK 50%

DATA

Figure 3. Power Dissipation Test Circuit and Waveform

SW 1
VDD
PULSE 1 VDD
GENERATOR 1 20 ns 20 ns
PARALLEL OR VDD
2 90%
P/S SERIAL DATA
50%
C Q6 INPUT 10% VSS
P1 tsu
2 2 P2
PULSE tWH tTHL
P3
GENERATOR 2 VDD
1 1 P4 Q7 CLOCK OR P/S 90%
P5 INPUT 50%
10% VSS
P6 CL tWH tWL
P7 tPLH tPHL
P8 Q8 VOH
DS Q 90%
OUTPUT 50%
SWITCH POSITION 1 = PARALLEL IN 10% VOL
SWITCH POSITION 2 = SERIAL IN VSS
SW 2
tTLH tTHL

tWL = tWH = 50% DUTY CYCLE

Figure 4. Switching Time Test Circuit and Waveforms

MC14014B MC14021B MOTOROLA CMOS LOGIC DATA


6–40
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14015B
Dual 4-Bit Static Shift Register
The MC14015B dual 4–bit static shift register is constructed with MOS L SUFFIX
CERAMIC
P–channel and N–channel enhancement mode devices in a single
CASE 620
monolithic structure. It consists of two identical, independent 4–state
serial–input/parallel–output registers. Each register has independent Clock
and Reset inputs with a single serial Data input. The register states are type
D master–slave flip–flops. Data is shifted from one stage to the next during P SUFFIX
the positive–going clock transition. Each register can be cleared when a high PLASTIC
CASE 648
level is applied on the Reset line. These complementary MOS shift registers
find primary use in buffer storage and serial–to–parallel conversion where
low power dissipation and/or noise immunity is desired.
D SUFFIX
• Diode Protection on All Inputs
SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 751B
• Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low; ORDERING INFORMATION
information is transferred to the output only on the positive going edge MC14XXXBCP Plastic
of the clock pulse. MC14XXXBCL Ceramic
• Capable of Driving Two Low–power TTL Loads or One Low–power MC14XXXBD SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range. TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit
BLOCK DIAGRAM

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Q0 5
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V 7 D

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Q1 4
lin, lout Input or Output Current (DC or Transient), ± 10 mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Pin Q2 3
9 C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW R Q3 10
_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150
6
TL Lead Temperature (8–Second Soldering) 260 _C
Q0 13
* Maximum Ratings are those values beyond which damage to the device may occur. 15 D
†Temperature Derating: Q1 12
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Q2 11
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 1 C
R Q3 2
TRUTH TABLE
14
C D R Q0 Qn VDD = PIN 16
0 0 0 Qn–1 VSS = PIN 8

1 0 1 Qn–1
X 0 No Change No Change
X X 1 0 0
X = Don’t Care
Qn = Q0, Q1, Q2, or Q3, as applicable.
Qn–1 = Output of prior stage.

MOTOROLA CMOS LOGIC DATA MC14015B


6–41
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 4.5 or .05 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
Output Drive Current ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —
mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
– 1.6
– 4.2


– 1.3
– 3.4
– 2.25
– 8.8


– 0.9
– 2.4

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0)
ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (1.2 µA/kHz)f + IDD
IT = (2.4 µA/kHz)f + IDD
IT = (3.6 µA/kHz)f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
CB 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q3B 2 15 DB
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Q2A 3 14 RB
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. Q1A 4 13 Q0B
Q0A 5 12 Q1B
RA 6 11 Q2B
DA 7 10 Q3A
VSS 8 9 CA

MC14015B MOTOROLA CMOS LOGIC DATA


6–42
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol VDD Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock, Data to Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 225 ns 5.0 — 310 750

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 92 ns 10 — 125 250

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns 15 — 90 170
Reset to Q

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 375 ns 5.0 — 460 750

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns 10 — 180 250
tPLH, tPHL = (0.5 ns/pF) CL + 95 ns 15 — 120 170

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 400 185 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 175 85 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 135 55 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 2.0 1.5 MHz
10 — 6.0 3.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 7.5 3.75

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Rise and Fall Times tTLH, tTHL 5.0 — — 15 µs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — — 5
15 — — 4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tWH 5.0 400 200 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 160 80 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 120 60 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time tsu 5.0 350 100 — ns
10 100 50 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 75 40 —
* The formulas given are for typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD
0.01 µF
PULSE 500 µF ID CERAMIC
GENERATOR VDD
2
D Q0
Q1 CL
PULSE Q2 CL
GENERATOR C Q3
CL
1 R CL

VSS

1
f
CLOCK 50%

DATA

Figure 1. Power Dissipation Test Circuit and Waveform

MOTOROLA CMOS LOGIC DATA MC14015B


6–43
tTLH tTHL
DATA VDD
90%
INPUT 50%
10% 0V
tsu
VDD tTLH t– tTHL
PULSE
GENERATOR D 90% VDD
Q0 CLOCK
2 CL 50%
Q1 INPUT 10%
SYNC CL 0V
PULSE Q2 tWH tWL
C Q3 CL tPLH tPHL
GENERATOR
1 R CL
90%
VSS 50%
Q0 10%

tWL = tWH = 50% Duty Cycle


tTLH = tTHL ≤ 20 ns tTLH tTHL

Figure 2. Switching Test Circuit and Waveforms

VDD
PULSE
CLOCK VDD
GENERATOR D Q0 50%
2 CL INPUT 0V
Q1 tsu
SYNC CL
PULSE Q2
C Q3 CL th
GENERATOR
1 R CL DATA VDD
50%
VSS INPUT 0V

Figure 3. Setup and Hold Time Test Circuit and Waveforms

MC14015B MOTOROLA CMOS LOGIC DATA


6–44
MOTOROLA CMOS LOGIC DATA

SINGLE BIT

VDD Q

RESET

CLOCK

DATA TO D OF
IN NEXT BIT

CIRCUIT SCHEMATICS
VSS

DATA INPUT BUFFER RESET INPUT BUFFER CLOCK INPUT BUFFER


VDD VDD
VDD

RESET CLOCK CLOCK


DATA DATA TO RESET
TO 4 BITS IN TO 4 BITS
IN FIRST BIT IN

VSS
MC14015B

VSS VSS
6–45
LOGIC DIAGRAMS

SINGLE BIT

C C Q
TO D OF
DATA NEXT BIT

C C C C

C C
RESET

C
C
C

COMPLETE DEVICE

5 4 3 10
Q0 Q1 Q2 Q3

DATA INPUT BUFFER


D
7 D Q D Q D Q D Q

C Q C Q C Q C Q
CLOCK INPUT BUFFER R R R R
C
9
R
6
13 12 11 2
RESET INPUT BUFFER Q0 Q1 Q2 Q3

DATA INPUT BUFFER


D
15 D Q D Q D Q D Q

C Q C Q C Q C Q
CLOCK INPUT BUFFER R R R R
C
1
VDD = PIN 16
R VSS = PIN 8
14

RESET INPUT BUFFER

MC14015B MOTOROLA CMOS LOGIC DATA


6–46
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14016B

Quad Analog Switch/Quad


Multiplexer L SUFFIX
CERAMIC
The MC14016B quad bilateral switch is constructed with MOS P–channel CASE 632
and N–channel enhancement mode devices in a single monolithic structure.
Each MC14016B consists of four independent switches capable of
controlling either digital or analog signals. The quad bilateral switch is used P SUFFIX
in signal gating, chopper, modulator, demodulator and CMOS logic PLASTIC
implementation. CASE 646

• Diode Protection on All Inputs


• Supply Voltage Range = 3.0 Vdc to 18 Vdc
D SUFFIX
• Linearized Transfer Characteristics SOIC
• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical CASE 751A
• Pin–for–Pin Replacements for CD4016B, CD4066B (Note improved
transfer characteristic design causes more parasitic coupling ORDERING INFORMATION
capacitance than CD4016) MC14XXXBCP Plastic
• For Lower RON, Use The HC4016 High–Speed CMOS Device or The MC14XXXBCL Ceramic
MC14066B MC14XXXBD SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• This Device Has Inputs and Outputs Which Do Not Have ESD TA = – 55° to 125°C for all packages.
Protection. Antistatic Precautions Must Be Taken.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎ Parameter Value Unit BLOCK DIAGRAM

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VDD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
CONTROL 1
13
2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
1 OUT 1
lin Input Current (DC or Transient), ± 10 mA IN 1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Control Pin 5
CONTROL 2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Isw Switch Through Current ± 25 mA 3
4 OUT 2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW IN 2
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 6
CONTROL 3 9
TL Lead Temperature (8–Second Soldering) 260 _C OUT 3
8
* Maximum Ratings are those values beyond which damage to the device may occur. IN 3
†Temperature Derating: 12
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C CONTROL 4 10
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C 11
OUT 4
IN 4
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must VDD = PIN 14
be taken to avoid applications of any voltage higher than maximum rated VSS = PIN 7
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage Control Switch
level (e.g., either VSS or VDD). Unused outputs must be left open.
0 = VSS Off
1 = VDD On
LOGIC DIAGRAM
(1/4 OF DEVICE SHOWN)
OUT

CONTROL

LOGIC DIAGRAM RESTRICTIONS IN


VSS ≤ Vin ≤ VDD
VSS ≤ Vout ≤ VDD

MOTOROLA CMOS LOGIC DATA MC14016B


6–47
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Figure Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Input Voltage

ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
Control Input ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
1 VIL 5.0
10






1.5
1.5
0.9
0.9




Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — — — 1.5 0.9 — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIH 5.0 — — 3.0 2.0 — — — Vdc
10 — — 8.0 6.0 — — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — — 13 11 — — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Control — Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance — Cin pF

ÎÎÎÎÎÎÎÎÎÎÎ
Control

ÎÎÎÎ
ÎÎÎ
ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ
5.0

ÎÎÎ

ÎÎÎ

ÎÎÎ

Switch Input

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Switch Output
Feed Through
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ












5.0
5.0
0.2








ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Quiescent Current

ÎÎÎ
(Per Package) ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
2,3 IDD 5.0
10


0.25
0.5


0.0005
0.0010
0.25
0.5


7.5
15
µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
“ON” Resistance 4,5,6 RON — — Ohms
(VC = VDD, RL = 10 kΩ) — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = + 5.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = ± 0.25 Vdc)
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = – 5.0 Vdc) VSS = – 5.0 Vdc
5.0



600
600
600



300
300
280
660
660
660



840
840
840

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
(Vin = + 7.5 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = ± 0.25 Vdc)
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = – 7.5 Vdc) VSS = – 7.5 Vdc


360
360


240
240
400
400


520
520

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
7.5 — 360 — 180 400 — 520
(Vin = + 10 Vdc) — 600 — 260 660 — 840

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = + 5.6 Vdc) ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
(Vin = + 0.25 Vdc) VSS = 0 Vdc

ÎÎÎ
ÎÎÎ
10


600
600


310
310
660
660


840
840

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = + 15 Vdc) — 360 — 260 400 — 520
(Vin = + 0.25 Vdc) VSS = 0 Vdc — 360 — 260 400 — 520

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = + 9.3 Vdc) 15 — 360 — 300 400 — 520

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
∆ “ON” Resistance — ∆RON Ohms

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Between any 2 circuits in a common
package

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VC = VDD)
(Vin = ± 5.0 Vdc, VSS = – 5.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0 — — — 15 — — —
(Vin = ± 7.5 Vdc, VSS = – 7.5 Vdc) 7.5 — — — 10 — — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
(VC = VSS) ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Input/Output Leakage Current

ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
— —

± 0.1 ± 0.0015 ± 0.1 ± 1.0


µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = + 7.5, Vout = – 7.5 Vdc) 7.5 — — —
(Vin = – 7.5, Vout = + 7.5 Vdc) 7.5 — ± 0.1 — ± 0.0015 ± 0.1 — ± 1.0
NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** For voltage drops across the switch (∆V switch) > 600 mV ( > 300 mV at high temperature), excessive V DD current may be drawn; i.e., the
current out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.

MC14016B MOTOROLA CMOS LOGIC DATA


6–48
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
Characteristic Figure Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time (VSS = 0 Vdc) 7 tPLH, 5.0 — 15 45 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
Vin to Vout tPHL 10 — 7.0 15
(VC = VDD, RL = 10 kΩ) 15 — 6.0 12

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Control to Output
v ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ 8 tPHZ, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
(Vin 10 Vdc, RL = 10 kΩ) tPLZ, 5.0 — 34 90
tPZH, 10 — 20 45

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎ
Crosstalk, Control to Output (VSS = 0 Vdc) 9
tPZL

15
5.0


15
30
35
— mV

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
(VC = VDD, Rin = 10 kΩ, Rout = 10 kΩ, 10 — 50 —
f = 1.0 kHz) 15 — 100 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Crosstalk between any two switches (VSS = 0 Vdc)

ÎÎÎ
— — 5.0 — – 80 — dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
(RL = 1.0 kΩ, f = 1.0 MHz,

+
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
V
crosstalk 20 log10 out1)
Vout2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Noise Voltage (VSS = 0 Vdc)
ÎÎÎÎÎÎÎ 10,11 — 5.0 — 24 — nV/√Cycle

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
(VC = VDD, f = 100 Hz) 10 — 25 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
15 — 30 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
(VC = VDD, f = 100 kHz) 5.0 — 12 —
10 — 12 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
15 — 15 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Second Harmonic Distortion (VSS = – 5.0 Vdc) — — 5.0 — 0.16 — %
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
RL = 10 kΩ, f = 1.0 kHz)
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Insertion Loss (VC = VDD, Vin = 1.77 Vdc, 12 — 5.0 dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
VSS = – 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)

+ V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
Iloss 20 log10 out) — 2.3 —
Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
(RL = 1.0 kΩ) — 0.2 —
(RL = 10 kΩ) — 0.1 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
(RL = 100 kΩ) — 0.05 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
(RL = 1.0 MΩ)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
Bandwidth (– 3.0 dB) 12,13 BW 5.0 MHz
(VC = VDD, Vin = 1.77 Vdc, VSS = – 5.0 Vdc,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
RMS centered @ 0.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
(RL = 1.0 kΩ)

ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ

ÎÎÎÎ
54 —
(RL = 10 kΩ)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(RL = 100 kΩ)
(RL = 1.0 MΩ)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ



40
38
37


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
OFF Channel Feedthrough Attenuation — — 5.0 kHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VSS = – 5.0 Vdc)
+
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ
(VC = VSS, 20 log10

ÎÎÎÎ
Vout
Vin ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
–50 dB)
— 1250 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
(RL = 1.0 kΩ)
— 140 —
(RL = 10 kΩ)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
— 18 —
(RL = 100 kΩ)
— 2.0 —
(RL = 1.0 MΩ)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

PIN ASSIGNMENT

IN 1 1 14 VDD
OUT 1 2 13 CONTROL 1
OUT 2 3 12 CONTROL 4
IN 2 4 11 IN 4
CONTROL 2 5 10 OUT 4
CONTROL 3 6 9 OUT 3
VSS 7 8 IN 3

MOTOROLA CMOS LOGIC DATA MC14016B


6–49
VC IS

Vin Vout

VIL: VC is raised from VSS until VC = VIL.


VIL: at VC = VIL: IS = ±10 µA with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS.
VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.

Figure 1. Input Voltage Test Circuit

10,000
VDD = 15 Vdc 10 Vdc

PD , POWER DISSIPATION (µW)


VDD TA = 25°C
5.0 Vdc
1000

ID
100

VDD Vout
TO ALL
10 k 10
PULSE 4 CIRCUITS CONTROL
GENERATOR INPUT
fc

VSS Vin 1.0


PD = VDD x ID 5.0 k 10 k 100 k 1.0 M 10 M 50 M
fc, FREQUENCY (Hz)

Figure 2. Quiescent Power Dissipation Figure 3. Typical Power Dissipation per Circuit
Test Circuit (1/4 of device shown)

TYPICAL RON versus INPUT VOLTAGE

700 700
RL = 10 kΩ VSS = 0 Vdc
600 TA = 25°C 600 RL = 10 kΩ
R ON, “ON” RESISTANCE (OHMS)

R ON, “ON” RESISTANCE (OHMS)

TA = 25°C
500 500

400 VC = VDD = 5.0 Vdc 400


VSS = – 5.0 Vdc VC = VDD = 10 Vdc
300 300

200 200 VC = VDD = 15 Vdc


VC = VDD = 7.5 Vdc
100 VSS = – 7.5 Vdc 100

0 0
– 10 – 8.0 – 4.0 0 4.0 8.0 10 0 2.0 6.0 10 14 18 20
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)

Figure 4. VSS = – 5.0 V and – 7.5 V Figure 5. VSS = 0 V

MC14016B MOTOROLA CMOS LOGIC DATA


6–50
Vout

RL CL

Vin

Vout 20 ns 20 ns
RL VDD
Vin 90%
VC 50% 10%
VSS
tPLH tPHL

Vout 50%
Vin

Figure 6. RON Characteristics Figure 7. Propagation Delay Test Circuit


Test Circuit and Waveforms

Vout
VC RL CL

Vin VX
20 ns
VDD Vout
90%
VC 50%
10% VC 10 k 15 pF
VSS
tPZH tPHZ
Vin = VDD
90% Vx = VSS
Vout 10% Vin
tPZL tPLZ
90% 1k
Vout Vin = VSS
10%
Vx = VDD

Figure 8. Turn–On Delay Time Test Circuit Figure 9. Crosstalk Test Circuit
and Waveforms

35

30
VDD = 15 Vdc
NOISE VOLTAGE (nV/ CYCLE)

25
10 Vdc
20
5.0 Vdc
15
OUT QUAN–TECH 10
MODEL
VC = VDD
2283
5.0
IN OR EQUIV
0
10 100 1.0 k 10 k 100 k
f, FREQUENCY (Hz)

Figure 10. Noise Voltage Test Circuit Figure 11. Typical Noise Characteristics

MOTOROLA CMOS LOGIC DATA MC14016B


6–51
2.0
RL = 1 MΩ AND 100 kΩ
TYPICAL INSERTION LOSS (dB) 0
10 kΩ
– 2.0
1.0 kΩ
– 4.0 – 3.0 dB (RL = 1.0 MΩ )
Vout
– 6.0 – 3.0 dB (RL = 10 kΩ ) RL
VC
– 3.0 dB (RL = 1.0 kΩ )
– 8.0

– 10 + 2.5 Vdc
Vin 0.0 Vdc
– 12 – 2.5 Vdc
10 k 100 k 1.0 M 10 M 100 M
fin, INPUT FREQUENCY (Hz)

Figure 12. Typical Insertion Loss/Bandwidth Figure 13. Frequency Response Test Circuit
Characteristics

ON SWITCH

CONTROL
SECTION
OF IC

LOAD
V

SOURCE

Figure 14. ∆V Across Switch

MC14016B MOTOROLA CMOS LOGIC DATA


6–52
APPLICATIONS INFORMATION

Figure A illustrates use of the Analog Switch. The 0–to–5 V The example shows a 5 V p–p signal which allows no
Digital Control signal is used to directly control a 5 V p–p ana- margin at either peak. If voltage transients above V DD and/or
log signal. below V SS are anticipated on the analog channels, external
The digital control logic levels are determined by V DD and diodes (Dx) are recommended as shown in Figure B. These
V SS. The V DD voltage is the logic high voltage; the V SS volt- diodes should be small signal types able to absorb the
age is logic low. For the example, V DD = + 5 V logic high at maximum anticipated current surges during clipping.
the control inputs; V SS = GND = 0 V logic low. The absolute maximum potential difference between V DD
The maximum analog signal level is determined by VDD and VSS is 18.0 V. Most parameters are specified up to 15 V
and V SS. The analog voltage must not swing higher than which is the recommended maximum difference between
V DD or lower than V SS. V DD and V SS.

+5 V

VDD VSS
+ 5.0 V

+5 V 5 Vp–p SWITCH
ANALOG SIGNAL IN
SWITCH 5 Vp–p
+ 2.5 V
OUT ANALOG SIGNAL
EXTERNAL
CMOS 0–TO–5 V DIGITAL
GND
DIGITAL CONTROL SIGNALS MC14016B
CIRCUITRY

Figure A. Application Example

VDD VDD

Dx Dx

SWITCH SWITCH
IN OUT
Dx Dx

VSS VSS

Figure B. External Germanium or Schottky Clipping Diodes

MOTOROLA CMOS LOGIC DATA MC14016B


6–53
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14017B
Decade Counter
The MC14017B is a five–stage Johnson decade counter with built–in code L SUFFIX
CERAMIC
converter. High speed operation and spike–free outputs are obtained by use
CASE 620
of a Johnson decade counter design. The ten decoded outputs are normally
low, and go high only at their appropriate decimal time period. The output
changes occur on the positive–going edge of the clock pulse. This part can
be used in frequency division applications as well as decade counter or P SUFFIX
decimal decode display applications. PLASTIC
CASE 648
• Fully Static Operation
• DC Clock Input Circuit Allows Slow Rise Times
• Carry Out Output for Cascading D SUFFIX
• Divide–by–N Counting SOIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 751B
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range ORDERING INFORMATION
• Pin–for–Pin Replacement for CD4017B MC14XXXBCP Plastic
MC14XXXBCL Ceramic
• Triple Diode Protection on All Inputs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V
FUNCTIONAL TRUTH TABLE

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V (Positive Logic)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA Clock Decode
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Clock Enable Reset Output=n

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW 0 X 0 n
X 1 0 n
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150
X X 1 Q0
TL Lead Temperature (8–Second Soldering) 260 _C 0 0 n+1
* Maximum Ratings are those values beyond which damage to the device may occur. X 0 n
†Temperature Derating: X 0 n
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C 1 0 n+1
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C X = Don’t Care. If n < 5 Carry = “1”,
Otherwise = “0”.
LOGIC DIAGRAM

Q5 Q1 Q7 Q3 Q9
1 2 6 7 11 BLOCK DIAGRAM

CLOCK 14 Q0 3
14 Q1 2
CLOCK Q2 4
CLOCK 12 Q3 7
ENABLE 13 C Q C Q C Q C Q C Q
CARRY
C C C C C Q4 10
D Q D Q D Q D Q D Q CLOCK
R R R R R R R R R R 13 Q5 1
15 ENABLE
RESET Q6 5
Q7 6
Q8 9
Q9 11
RESET 15 Cout 12

VDD = PIN 16
3 5 4 9 10 VSS = PIN 8
Q0 Q6 Q2 Q3 Q4

MC14017B MOTOROLA CMOS LOGIC DATA


6–54
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ

ÎÎÎÎ
1.5

ÎÎÎ

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15


3.0
4.0


4.50
6.75
3.0
4.0


3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ

ÎÎÎÎ
3.5

ÎÎÎ

(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11


7.0
11
5.50
8.25


7.0
11

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ

ÎÎÎÎ
– 1.7

ÎÎÎ

(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2



– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8



– 0.36
– 0.9
– 2.4


ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6


0.51
1.3
0.88
2.25


0.36
0.9


mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10


5.0
10


0.005
0.010
5.0
10


150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.27 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.55 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (0.83 µA/kHz) f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.0011.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
Q5 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q1 2 15 RESET
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Q0 3 14 CLOCK
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. Q2 4 13 CE
Q6 5 12 Cout
Q7 6 11 Q9
Q3 7 10 Q4
VSS 8 9 Q8

MOTOROLA CMOS LOGIC DATA MC14017B


6–55
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Decode Output tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns

ÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/PF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
5.0
10
15



500
230
175
1000
460
350

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Cout
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 142 ns
tPHL
5.0
10


400
175
800
350

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ
Propagation Delay Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 100 ns

ÎÎÎÎÎÎÎ tPLH,
15 — 125 250
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Decode Output tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns 5.0 — 500 1000

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns 10 — 230 460

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns 15 — 175 350

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Turn–Off Delay Time tPLH ns
Reset to Cout

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (1.7 ns/pF) CL + 315 ns 5.0 — 400 800

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.66 ns/pF) CL + 142 ns 10 — 175 350
tPLH = (0.5 ns/pF) CL + 100 ns 15 — 125 250

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tw(H) 5.0 250 125 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 50 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 75 35 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Frequency fcl 5.0 — 5.0 2.0 MHz
10 — 12 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 16 6.7

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tw(H) 5.0 500 250 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 250 125 —
15 190 95 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Reset Removal Time
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ trem 5.0 750 375 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 275 135 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15 210 105 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Clock Input Rise and Fall Time tTLH, 5.0 —
tTHL 10 No Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Enable Setup Time tsu 5.0 350 175 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 150 75 —
15 115 52 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
Clock Enable Removal Time
ÎÎÎÎÎÎÎÎÎÎÎ trem 5.0 420 260 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 200 100 —
15 140 70 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14017B MOTOROLA CMOS LOGIC DATA


6–56
VDD

Vout Output Output


VSS CLOCK Q0
Sink Drive Source Drive
ENABLE
Q1
Clock to
Q2 Decode desired
Q3 (S1 to A)
Outputs outputs
A Q4 (S1 to B)
VDD S1 ID
RESET Q5 Clock to 5
B Q6
VSS S1 Carry thru 9 S1 to A
Q7 (S1 to B)
Q8
VGS = VDD – VDD
Q9 EXTERNAL
CLOCK Cout POWER VDS = Vout Vout – VDD
SUPPLY
VSS

Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit

VDD

0.01 µF
500 µF ID
CERAMIC

Q0
Q1
CLOCK Q2
ENABLE Q3
Q4
RESET Q5
Q6
PULSE fc Q7
CLOCK Q8
GENERATOR
Q9
Cout
VSS CL CL CL CL CL CL CL CL CL CL CL

Figure 2. Typical Power Dissipation Test Circuit

APPLICATIONS INFORMATION

Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are se-
quential within each stage and from stage to stage, with no dead time (except propagation delay).

RESET RESET RESET


CLOCK CLOCK CLOCK
CE MC14017B CE MC14017B CE MC14017B
Q0 Q1 • • • Q8 Q9 Q0Q1 • • • Q8 Q9 Q1 • • • Q8 Q9

8 DECODED
9 DECODED 8 DECODED
OUTPUTS
OUTPUTS OUTPUTS

CLOCK
FIRST STAGE INTERMEDIATE STAGES LAST STAGE

Figure 3. Counter Expansion

MOTOROLA CMOS LOGIC DATA MC14017B


6–57
Pcp Ncp 90% VDD
CLOCK 50%
10% VSS
trem tsu 20 ns 20 ns
CLOCK VDD
ENABLE VSS
trem 20 ns 20 ns 20 ns
RESET VDD
20 ns VSS
tPHL tPLH tPLH
Q0 VOH
tTLH VOL
tPLH tPHL
90% VOH
10% 50%
Q1 VOL
tPLH tPHL tTLH tTHL
VOH
Q2 VOL
tPLH tPHL tTLH tTHL
VOH
50%
Q3 VOL
tPLH tPHL tTLH tTHL
VOH
Q4 tTHL VOL
tPLH tPHL tTLH
tPHL
VOH
Q5 VOL
tPLH tPHL tTLH tTHL
90% VOH
Q6 10% VOL
tTHL tTHL
tPLH tPHL VOH
Q7 VOL
tTHL
tPLH VOH
Q8 VOL
tTLH tTHL
tPLH tPHL
VOH
Q9 VOL
tPHL tTLH tTHL tPHL
Cout tPLH VOH
VOL
tTHL
tTLH

Figure 4. AC Measurement Definition and Functional Waveforms

MC14017B MOTOROLA CMOS LOGIC DATA


6–58
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14018B
Presettable Divide-By-N
Counter L SUFFIX
CERAMIC
The MC14018B contains five Johnson counter stages which are CASE 620
asynchronously presettable and resettable. The counters are synchronous,
and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input. Data on P SUFFIX
the Jam inputs will then be transferred to their respective Q outputs PLASTIC
(inverted). A logic 1 on the reset input will cause all Q outputs to go to a logic CASE 648
1 state.
Division by any number from 2 to 10 can be accomplished by connecting
appropriate Q outputs to the data input, as shown in the Function Selection D SUFFIX
table. Anti–lock gating is included in the MC14018B to assure proper SOIC
counting sequence. CASE 751B

• Fully Static Operation


ORDERING INFORMATION
• Schmitt Trigger on Clock Input
MC14XXXBCP Plastic
• Capable of Driving Two Low–power TTL Loads or One Low–power MC14XXXBCL Ceramic
Schottky TTL Load Over the Rated Temperature Range MC14XXXBD SOIC
• Pin–for–Pin Replacement for CD4018B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit
FUNCTIONAL TRUTH TABLE

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Preset Jam
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Clock Reset Enable Input Qn

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA 0 0 X Qn

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
per Pin 0 0 X Dn*
X 0 1 0 1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW
X 0 1 1 0
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 X 1 X X 1
TL Lead Temperature (8–Second Soldering) 260 _C * Dn is the Data input for that stage. Stage 1
has Data brought out to Pin 1.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C PIN ASSIGNMENT

Din 1 16 VDD
JAM 1 2 15 R
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must JAM 2 3 14 C
be taken to avoid applications of any voltage higher than maximum rated
Q2 4 13 Q5
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Q1 5 12 JAM 5
Unused inputs must always be tied to an appropriate logic voltage
Q3 6 11 Q4
level (e.g., either VSS or VDD). Unused outputs must be left open.
JAM 3 7 10 PE
VSS 8 9 JAM 4

MOTOROLA CMOS LOGIC DATA MC14018B


6–59
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ

ÎÎÎÎ
1.5

ÎÎÎ

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15


3.0
4.0


4.50
6.75
3.0
4.0


3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10

ÎÎÎ
7.0

ÎÎÎÎ

ÎÎÎ
7.0

ÎÎÎÎ
5.50

ÎÎÎ

ÎÎÎÎ
7.0

ÎÎÎ

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Output Drive Current
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ IOH
15 11 — 11 8.25 — 11 —

mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
(Vin = 0) ÎÎÎÎ
Input Capacitance

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Cin — — — — 5.0 7.5 — — pF

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current**†

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Dynamic plus Quiescent,
Per Package)
ÎÎÎ
IT 5.0
10
15
IT = (0.3 µA/kHz) f + IDD
IT = (0.7 µA/kHz) f + IDD
IT = (1.0 µA/kHz) f + IDD
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
buffers switching)

ÎÎÎ
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MC14018B MOTOROLA CMOS LOGIC DATA


6–60
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ All Types

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VDD
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ tTLH, tTHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.35 ns/pF) CL + 32 ns 5.0 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.6 ns/pF) CL + 20 ns 10 — 50 100
tTLH, tTHL = (0.4 ns/pF) CL + 20 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Q tPHL
tPLH, tPHL = (0.90 ns/pF) CL + 265 ns 5.0 — 310 620

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 102 ns 10 — 120 240

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 72 ns 15 — 85 170

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Q ns
tPLH = (0.90 ns/pF) CL + 325 ns 5.0 — 370 740

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.36 ns/pF) CL + 132 ns
ÎÎÎ 10 — 150 300

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.26 ns/pF) CL + 81 ns 15 — 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Preset Enable to Q ns
tPLH, tPHL = (0.90 ns/pF) CL + 325 ns 5.0 — 370 740

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 132 ns 10 — 150 300

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.26 ns/pF) CL + 81 ns 15 — 100 200

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Setup Time tsu ns
Data (Pin 1) to Clock 5.0 200 0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 0 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 80 0 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Jam Inputs to Preset Enable 5.0 200 0 — ns
10 100 0 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 80 0 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Data (Jam Inputs)–to–Preset th 5.0 540 270 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Enable Hold Time 10 500 250 —
15 480 240 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 400 200 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 200 100 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 160 80 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset or Preset Enable tWH 5.0 290 145 — ns
Pulse Width 10 130 65 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 110 55 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Clock Rise and Fall Time tTLH, tTHL 5.0 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
10 No Limit
15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 — 2.5 1.25 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 6.5 3.25
15 — 8.0 4.0
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

20 ns 20 ns
VDD
90%
ANY INPUT 50%
10% VSS

tPLH tPHL

VOH
90%
ANY OUTPUT 50%
10% VOL
tTLH tTHL

Figure 1. Switching Time Waveforms

MOTOROLA CMOS LOGIC DATA MC14018B


6–61
1
CLOCK
0
1
RESET
0
1
PRESET ENABLE
0
1
JAM 1
0
JAM 2 1
0
1
TIMING DIAGRAM JAM 3 DON’T CARE
UNTIL PRESET ENABLE 0
(Q5 Connected to Data Input) 1
GOES HIGH
JAM 4 0
1
JAM 5 0
1
Q1
0
1
Q2
0
1
Q3
0
1
Q4 0
1
Q5
0

FUNCTION SELECTION
Connect
Counter Data Input
Mode (Pin 1) to: Comments
Divide by 10 Q5
Divide by 8 Q4
No external
Divide by 6 Q3
components needed.
Divide by 4 Q2
Divide by 2 Q1
Divide by 9 Q5 • Q4 Gate package needed LOGIC DIAGRAM
Divide by 7 Q4 • Q3 to provide AND
Divide by 5 Q3 • Q2 function. Counter
JAM 1 JAM 2 JAM 3 JAM 4 JAM 5
Divide by 3 Q2 • Q1 Skips all 1’s state 2 3 7 9 12

CLOCK
CLOCK 14
SHAPER
S S S S S
DATA 1 D Q D Q D Q D Q D Q
C C C C C
Q
R P R P R P R P R P
RESET 15

PRESET ENABLE 10

VDD = PIN 16
VSS = PIN 8
5 4 6 11 13

Q1 Q2 Q3 Q4 Q5

MC14018B MOTOROLA CMOS LOGIC DATA


6–62
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14020B
14-Bit Binary Counter
The MC14020B 14–stage binary counter is constructed with MOS L SUFFIX
CERAMIC
P–channel and N–channel enhancement mode devices in a single
CASE 620
monolithic structure. This part is designed with an input wave shaping circuit
and 14 stages of ripple–carry binary counter. The device advances the count
on the negative–going edge of the clock pulse. Applications include time
delay circuits, counter controls, and frequency–dividing circuits. P SUFFIX
PLASTIC
• Fully Static Operation CASE 648
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power D SUFFIX
Schottky TTL Load Over the Rated Temperature Range SOIC
• Buffered Outputs Available from stages 1 and 4 thru 14 CASE 751B
• Common Reset Line

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Pin–for–Pin Replacement for CD4020B ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCP Plastic
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
MC14XXXBD SOIC
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TA = – 55° to 125°C for all packages.
VDD DC Supply Voltage – 0.5 to + 18.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎÎÎÎÎÎÎ
Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
lin, lout
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Input or Output Current (DC or Transient),

ÎÎÎ
per Pin
± 10 mA

Clock
TRUTH TABLE
Reset Output State

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
PD Power Dissipation, per Package† 500 mW 0 No Change

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Î ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C 0 Advance to Next State
X 1 All Outputs are Low

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
X = Don’t Care
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

LOGIC DIAGRAM

Q1 Q4 Q5 Q12 Q13 Q14


9 7 5 1 2 3

CLOCK
10 C Q C Q C Q C Q C Q C Q

C Q C Q C Q C Q C Q C
R R R R R R

RESET
11

Q6 = PIN 4 Q9 = PIN 12 VDD = PIN 16


Q7 = PIN 6 Q10 = PIN 14 VSS = PIN 8
Q8 = PIN 13 Q11 = PIN 15

MOTOROLA CMOS LOGIC DATA MC14020B


6–63
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ

ÎÎÎÎ
1.5

ÎÎÎ

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15


3.0
4.0


4.50
6.75
3.0
4.0


3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ

ÎÎÎÎ
3.5

ÎÎÎ

(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11


7.0
11
5.50
8.25


7.0
11

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ

ÎÎÎÎ
– 1.7

ÎÎÎ

(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2



– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8



– 0.36
– 0.9
– 2.4


ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6


0.51
1.3
0.88
2.25


0.36
0.9


mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10


5.0
10


0.005
0.010
5.0
10


150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.42 µA/kHz)f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.85 µA/kHz)f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (1.43 µA/kHz)f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must Q12 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q13 2 15 Q11
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Q14 3 14 Q10
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. Q6 4 13 Q8
Q5 5 12 Q9
Q7 6 11 R
Q4 7 10 C
VSS 8 9 Q1

MC14020B MOTOROLA CMOS LOGIC DATA


6–64
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, ns
tPHL

ÎÎÎÎ
Clock to Q1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPHL, tPLH = (1.7 ns/pF) CL + 175 ns

ÎÎÎÎÎÎÎ
tPHL, tPLH = (0.66 ns/pF) CL + 82 ns
tPHL, tPLH = (0.5 ns/pF) CL + 55 ns
5.0
10
15



260
115
80
520
230
160

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Q14
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tPHL, tPLH – (1.7 ns/pF) CL + 1735 ns

ÎÎÎ
tPHL, tPLH = (0.66 ns/pF) CL + 772 ns
tPHL, tPLH = (0.5 ns/pF) CL + 535 ns
5.0
10
15



1820
805
560
3900
1725
1200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Qn

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
tPHL = (1.7 ns/pF) CL + 285 ns
tPHL = (0.66 ns/pF) CL + 122 ns
ÎÎÎ
ÎÎÎ
5.0
10


370
155
740
310

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.5 ns/pF) CL + 90 ns 15 — 115 230

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 500 140 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 165 55 —
15 125 38 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ fcl 5.0 — 2.0 1.0 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 — 6.0 3.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15 — 8.0 4.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Clock Rise and Fall Time tTLH, tTHL 5.0 —
10 No Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tWL 5.0 3000 320 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 550 120 —
15 420 80 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Removal Time trem 5.0 130 65 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 50 25 —
15 30 15 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD VDD

0.01 µF
500 µF ID CERAMIC PULSE
C Q1
GENERATOR
Q4
Qn CL
PULSE R
C Q1 CL
GENERATOR CL
Q4 VSS
Qn CL
R
CL
CL 20 ns 20 ns
VSS
CLOCK 90%
50%
10%
20 ns 20 ns
VDD tWH
90% tPLH tPHL
CLOCK 50%
10% VSS Q 90%
50%
50% DUTY CYCLE 10%
tTLH tTHL

Figure 1. Power Dissipation Test Circuit Figure 2. Switching Time Test Circuit
and Waveform and Waveforms

MOTOROLA CMOS LOGIC DATA MC14020B


6–65
1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16,384
CLOCK
RESET

Q1
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14

Figure 3. Timing Diagram

MC14020B MOTOROLA CMOS LOGIC DATA


6–66
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14022B
Octal Counter
The MC14022B is a four–stage Johnson octal counter with built–in code L SUFFIX
CERAMIC
converter. High–speed operation and spike–free outputs are obtained by
CASE 620
use of a Johnson octal counter design. The eight decoded outputs are
normally low, and go high only at their appropriate octal time period. The
output changes occur on the positive–going edge of the clock pulse. This
part can be used in frequency division applications as well as octal counter P SUFFIX
or octal decode display applications. PLASTIC
CASE 648
• Fully Static Operation
• DC Clock Input Circuit Allows Slow Rise Times
• Carry Out Output for Cascading D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC
• Capable of Driving Two Low–power TTL Loads or One Low–power CASE 751B
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4022B ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Triple Diode Protection on All Inputs MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎ
Î ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBD SOIC

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TA = – 55° to 125°C for all packages.
Symbol Parameter Value Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VDD

ÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout ÎÎÎÎÎÎ
ÎÎÎ
DC Supply Voltage

ÎÎÎÎÎÎ
ÎÎÎ
Input or Output Voltage (DC or Transient)
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
V
V
FUNCTIONAL TRUTH TABLE

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), ± 10 mA (Positive Logic)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
per Pin
Clock

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation, per Package† 500 mW Clock Enable Reset Output=n

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C 0 X 0 n
X 1 0 n

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature (8–Second Soldering) 260 _C
0 0 n+1
* Maximum Ratings are those values beyond which damage to the device may occur. X 0 n
†Temperature Derating: 1 0 n+1
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C X 0 n
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C X X 1 Q0
X = Don’t Care. If n < 4 Carry = 1,
LOGIC DIAGRAM Otherwise = 0.

11 1 5 7
Q4 Q1 Q6 Q3
BLOCK DIAGRAM
CLOCK
14 Q0 2
CLOCK 14
CARRY Q1 1
13
CLOCK C Q C Q C Q C Q Q2 3
VDD 12
ENABLE C C C C Q3 7
D RQ D RQ D RQ D RQ
CLOCK
13 Q4 11
VSS ENABLE
Q5 4
15
Q6 5
RESET
Q7 10
RESET 15 Cout 12
VDD = PIN 16
VSS = PIN 8

NC = PIN 6, 9
Q0 Q5 Q2 Q7
2 4 3 10

MOTOROLA CMOS LOGIC DATA MC14022B


6–67
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ

ÎÎÎÎ
1.5

ÎÎÎ

ÎÎÎÎ
2.25

ÎÎÎ
1.5

ÎÎÎÎ

ÎÎÎ
1.5
(VO = 9.0 or 1.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15


3.0
4.0


4.50
6.75
3.0
4.0


3.0
4.0

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
3.5

ÎÎÎÎ

ÎÎÎ
3.5

ÎÎÎÎ
2.75

ÎÎÎ

ÎÎÎÎ
3.5

ÎÎÎ

(VO = 1.0 or 9.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
10
15
7.0
11


7.0
11
5.50
8.25


7.0
11

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0

ÎÎÎ
– 3.0

ÎÎÎÎ

ÎÎÎ
– 2.4

ÎÎÎÎ
– 4.2

ÎÎÎ

ÎÎÎÎ
– 1.7

ÎÎÎ

(VOH = 4.6 Vdc)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VOH = 9.5 Vdc)

ÎÎÎ
(VOH = 13.5 Vdc)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
10
15
– 0.64
– 1.6
– 4.2



– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8



– 0.36
– 0.9
– 2.4


ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VOL = 0.5 Vdc) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Sink

ÎÎÎ
IOL 5.0
10
0.64
1.6


0.51
1.3
0.88
2.25


0.36
0.9


mAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Quiescent Current

ÎÎÎ ÎÎÎ
ÎÎÎÎ
(Per Package) ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10


5.0
10


0.005
0.010
5.0
10


150
300
µAdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 20 — 0.015 20 — 600

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Total Supply Current**† IT 5.0 IT = (0.28 µA/kHz)f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (0.56 µA/kHz)f + IDD

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package)

ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
15 IT = (0.85 µA/kHz)f + IDD

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.00125.

PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
Q1 1 16 VDD
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and Q0 2 15 R
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Q2 3 14 C
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open. Q5 4 13 CE
Q6 5 12 Cout
NC 6 11 Q4
Q3 7 10 Q7
VSS 8 9 NC

NC = NO CONNECTION

MC14022B MOTOROLA CMOS LOGIC DATA


6–68
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Typ # Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH, ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Decode Output tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns

ÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
5.0
10
15



500
230
175
1000
460
350

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Propagation Delay Time

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Cout
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 315 ns
tPLH, tPHL = (0.66 ns/pF) CL + 142 ns
tPHL
5.0
10


400
175
800
350

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ
Propagation Delay Time ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 100 ns

ÎÎÎÎÎÎÎ tPLH,
15 — 125 250
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock to Decode Output tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns 5.0 — 275 1000

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns 10 — 125 460

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.5 ns/pF) CL + 150 ns 15 — 95 350

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Turn–Off Delay Time tPLH ns
Reset to Cout

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (1.7 ns/pF) CL + 315 ns 5.0 — 400 800

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.66 ns/pF) CL + 142 ns 10 — 175 350
tPLH = (0.5 ns/pF) CL + 100 ns 15 — 125 250

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWH 5.0 250 125 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 50 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 75 35 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Frequency fcl 5.0 — 5.0 2.0 MHz
10 — 12 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 — 16 6.7

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset Pulse Width tWH 5.0 500 250 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 250 125 —
15 190 95 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
Reset Removal Time
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ trem 5.0 750 375 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 275 135 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15 210 105 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Clock Input Rise and Fall Time tTLH, tTHL 5.0 —
10 No Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Enable Setup Time tsu 5.0 350 175 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 150 75 —
15 115 52 —

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
Clock Enable Removal Time
ÎÎÎÎÎÎÎÎÎÎÎ trem 5.0 420 260 — ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 200 100 —
15 140 70 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14022B


6–69
VDD

Output Output
Vout Sink Drive Source Drive
CLOCK Q0
VSS
ENABLE Q1 Clock to desired
VDD A Q2 Output
Q3 Outputs (S1 to A) (S1 to B)
RESET Q4 Clock to Q5
S1 Q5 ID Carry thru Q7 S1 to A
VSS B
Q6 (S1 to B)
Q7 VGS = VDD – VDD
CLOCK C
out
VDS = Vout Vout – VDD
EXTERNAL
VSS POWER
SUPPLY

Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit

VDD

0.01 µF
500 µF ID
CERAMIC

Q0
Q1
CLOCK Q2
ENABLE
Q3
Q4
RESET Q5
Q6
PULSE fc Q7
CLOCK Cout
GENERATOR

VSS CL CL CL CL CL CL CL CL CL

Figure 2. Typical Power Dissipation Test Circuit

APPLICATIONS INFORMATION

Figure 3 shows a technique for extending the number of decoded output states for the MC14022B. Decoded outputs are se-
quential within each stage and from stage to stage, with no dead time (except propagation delay).

R R R
C C C
CE MC14022B CE MC14022B CE MC14022B
Q0 Q1 • • • Q6 Q7 Q0 Q1 • • • Q6 Q7 Q1 • • • Q6 Q7

6 DECODED
7 DECODED 6 DECODED
OUTPUTS
OUTPUTS OUTPUTS

CLOCK
FIRST STAGE INTERMEDIATE STAGES LAST STAGE

Figure 3. Counter Expansion

MC14022B MOTOROLA CMOS LOGIC DATA


6–70
tWH
tWL 90% V
50% DD
CLOCK 10% VSS
trel tsu 20 ns
20 ns
CLOCK VDD
ENABLE VSS
trem 20 ns 20 ns 20 ns
RESET VDD
VSS
tPHL tPLH tPLH
Q0 VOH
50%
VOL
tPLH tPHL tTHL
90% 50% VOH
Q1 10% VOL
tPLH tPHL tTLH
VOH
Q2 VOL
tPLH tPHL tTLH
VOH
Q3 VOL
tPLH tPHL tTLH
VOH
Q4 VOL
tPLH tPHL tTLH tPHL
VOH
Q5 VOL
tTLH tTHL tTLH tTHL
tPLH tPHL
VOH
Q6 VOL
tPLH tPHL
VOH
Q7 VOL
tPHL tTLH tTHL tPLH
Cout tPHL VOH
VOL
tTLH tTHL

Figure 4. AC Measurement Definition and Functional Waveforms

MOTOROLA CMOS LOGIC DATA MC14022B


6–71
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA

MC14024B
7-Stage Ripple Counter
The MC14024B is a 7–stage ripple counter with short propagation delays L SUFFIX
CERAMIC
and high maximum clock rates. The Reset input has standard noise
CASE 632
immunity, however the Clock input has increased noise immunity due to
Hysteresis. The output of each counter stage is buffered.
• Diode Protection on All Inputs
P SUFFIX
• Output Transitions Occur on the Falling Edge of the Clock Pulse PLASTIC
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 646
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4024B D SUFFIX

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
SOIC
CASE 751A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit ORDERING INFORMATION

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
VDD DC Supply Voltage – 0.5 to + 18.0 V MC14XXXBCP Plastic
MC14XXXBCL Ceramic

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V MC14XXXBD SOIC
± 10

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
lin, lout Input or Output Current (DC or Transient), mA TA = – 55° to 125°C for all packages.
per Pin

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎ
Power Dissipation, per Package†

ÎÎÎÎÎÎ
ÎÎÎ
Storage Temperature
500
– 65 to + 150
mW
_C PIN ASSIGNMENT

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
TL
ÎÎÎÎÎÎ
ÎÎÎ
Lead Temperature (8–Second Soldering) 260
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
_C
CLOCK
RESET
1
2
14
13
VDD
NC
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Q7 3 12 Q1
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
Q6 4 11 Q2
Q5 5 10 NC
LOGIC DIAGRAM Q4 6 9 Q3

1 VSS 7 8 NC
CLOCK C Q C Q C Q C Q
VDD = PIN 14
VSS = PIN 7
NC = NO CONNECTION
R Q R Q R Q R Q
2
RESET

12 11 4 3
Q1 Q2 Q6 Q7

Q3 = PIN 9
Q4 = PIN 6
Q5 = PIN 5

MC14024B MOTOROLA CMOS LOGIC DATA


6–72
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ – 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
VDD
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
Output Voltage

ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin = VDD or 0 ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
“0” Level

ÎÎÎ
ÎÎÎ
VOL 5.0
10


0.05
0.05


0
0
0.05
0.05


0.05
0.05
Vdc

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
10 9.95 — 9.95 10 — 9.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ