JOURNAL OF APPLIED PHYSICS 99, 104504 共2006兲

Modeling and characterization of organic thin film transistors

for circuit design
M. Fadlallah,a兲 W. Benzarti, and G. Billiot
CEA-LETI, 17 rue des Martyrs, 38054 Grenoble, France
W. Eccleston
Department of Electrical Engineering, University of Liverpool, Liverpool L69 3GJ, United Kingdom
D. Barclay
Plastic Logic Limited, 34 Cambridge Science Park, Milton Road, Cambridge CB4 OFX, United Kingdom
共Received 15 September 2005; accepted 16 March 2006; published online 25 May 2006兲
In this paper, we develop a device model of an organic thin film transistor for a circuit design, more
specifically, for organic radio frequency identification applications. This model is based on variable
range hopping theory, i.e., a carrier may either hop over a small distance with a high activation
energy or hop over a long distance with a low activation energy. The model takes into account all
the operating regimes in direct current and transient mode; the transistor symmetry is also
considered. The model has been developed using a physical basis where the model parameters can
easily be extracted and it improves convergence in circuit simulations. It is also suitable for
computer aided design applications. © 2006 American Institute of Physics.
关DOI: 10.1063/1.2197260兴

I. INTRODUCTION gate voltage.9 In recent years several mathematical models of

Organic thin film transistors 共OTFTs兲 are currently gen-
erating a growing interest due to the low-temperature process
and low-cost production. Therefore, their potential for a wide
application, low-cost integrated circuits and large area flex-
ible electronics is increasing.1 Their possible applications are
rf identification tags, electronic paper, flexible displays, sen-
sors, etc. Furthermore, thanks to their intrinsic structure flex-
ibility, in the case of all-polymer systems, OTFTs allow the
production of flexible integrated circuits.2
Many techniques have been used in the fabrication of
organic and polymer microelectronic devices, such as lithog-
raphy spin coating, thermal evaporation, and printing. Vari-
ous printing techniques including screen printing,3,4 micro-
contact printing,5,6 and ink-jet printing7,8 共IJP兲 are of great
interest. Among these printing techniques, the IJP has been
gaining more attention because polymer devices fabricated
by the IJP technique have the advantage of simple fabrication
methods, compatibility with different substrates, low-
temperature processing, and low cost. OTFTs used in this
study were fabricated using ink-jet printing techniques.
The efficient design of complex integrated circuits based
on OTFTs requires preliminary characterization and model-
ing. To this purpose, the availability of accurate analytical
models 关simulation program for integrated circuits emphasis
共SPICE兲-like兴 is particularly attractive. With respect to
crystalline-silicon metal-oxide-semiconductor field-effect
transistors 共MOSFETs兲, the development of an analytical
model for OTFTs is complicated by the peculiar nature of the
material. In addition, OTFTs are primarily operated as accu-
mulation field-effect transistors; they normally conduct at
zero gate voltage and field-effect mobility is dependent on
a兲
FAX: ⫹33 共0兲 4 38 78 51 57; electronic mail: mouenes.fadlallah@cea.fr
the OTFTs were developed.10–13 They are mainly based on
classical MOS transistors models, slightly modified by intro-
ducing fitting empirical parameters. In this paper, we present
a direct current/alternating current 共dc/ac兲 model for OTFTs
where the charge transport mechanism is based on the vari-
able range hopping 共VRH兲 theory.14,15
The developed model should be accurate enough in de-
vice simulations but also should present a high level of con-
vergence in circuit simulations. In fact, the model has to take
into account the physical bases of the device structure and
the material specifications. At the same time, the developed
model should be easy to upgrade since the technology is not
yet mature and different parameters such as materials and
structure can be changed. It is therefore important to adopt a
physical approach in order to facilitate the upgrade of the
model. Using physical treatment including surface potential
variables introduces implicit equations into the model. This
technique will hardly degrade model convergence in circuit
simulations. In order to avoid such divergence, the model
should be developed using explicit equations. At this stage, it
is important to note that using explicit equations in a SPICE-
like approach will imply the use of if conditions which cause
discontinuities of equation derivatives. This situation may
influence the convergence of the model in circuit simula-
tions.
It is important to find the right compromise between a
physical approach and model convergence in circuit design.
A bottom-up approach going from a simple model using a
SPICE-like approach to many more modifications, other
equations, and parameters was adopted. The model perfor-
mance will be evaluated using the validation of the model
simulations towards device measurements and its conver-
gence in circuit design.

0021-8979/2006/99共10兲/104504/7/$23.00 99, 104504-1 © 2006 American Institute of Physics

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 104504-2 Fadlallah et al. J. Appl. Phys. 99, 104504 共2006兲

␮ = K3N␥−1 , 共2兲

where K1, K3, and ␥ are constants and N is the carrier num-
ber.
In order to further analyze the TFT result, the general
equation incorporates dependence of the mobility on accep-
tor concentrations, such as that of VRH, rather than bandlike
mechanism. Assuming that every carrier in the bulk repre-
sents a hole in the channel, the effective mobility ␮eff may
thus be expressed as Eq. 共3兲 assuming m = 共␥ − 1兲,
FIG. 1. Layout and cross section of the organic thin film transistor 共OTFT兲.
␮eff = K3 p␥−1 = K3 pm , 共3兲

II. MODEL STRUCTURE
The work done here is based on the cross section and the
layout of the OTFT. The model equations were also based on
the dc and ac characteristics of the device.
The layout and the cross section of the OTFT used are
shown in Fig. 1. As seen, the transistor structure uses a mul-
tifinger type, where x represents the direction parallel to the
current flow.
The basic topology of the transistor is top gate-bottom
contacts where the transistor length is located between the
where p = N. The drain current density J resulting from elec-
trical field application is expressed with Eq. 共4兲,
J = pq␮eff␰x , 共4兲
Where p is the carrier concentration, q is the electron charge,
and ␰x is the applied field between the source and drain con-
tact.
Using Gauss’s law and substituting for J = I共Wdz兲 and
␰x = dVx / dx and integrating both sides, the current equation
then becomes

冕 冕
source and the drain contacts. The transistor model repre-
senting this cross section is shown in Fig. 2.
L
K 3W C02m+1 VD
I dx = ± 共VG − Vx兲2m+1dVx ,
Rs and Rd are, respectively, the source and the drain con- 0 共2m + 1兲 共2␧0␧ pkT兲m 0
tact resistances; Cgs and Cgd are, respectively, the gate to
共5兲
source and the gate to drain capacitors; and Id is the drain
current expressing the carriers flowing between source and where C0 is the dielectric capacitor C0 = ␧d / Td, ␧d is the di-
drain for the different operating regimes of the transistor. electric permittivity, Td is the thickness of the dielectric, W is
the channel width, ␧ p is the permittivity of the organic semi-
conductor, ␧0 is the permittivity of free space, VG is the gate
III. DC MODEL IN THE DIFFERENT OPERATING voltage, and m is a mobility model parameter. Therefore, the
REGIMES general equation for the drain to source current in the linear
regime is expressed with Eq. 共6兲,
A. Linear regime
Unlike complementary metal-oxide-semiconductor K3 W C02m+1
Id,lin = ± 兵共Vgs − VT兲2m+2
共CMOS兲 standard technology, OTFT is only a drift mecha- 共2m + 1兲共2m + 2兲 L 共2␧0␧ pkT兲m
nism where the subthreshold regime and linear regime are
− 关共Vgs − VT兲 − Vd兴2m+2其, 共6兲
driven with a unique mechanism and then can be modeled
using a single equation. The equation obtained depends on where VT is the threshold voltage, Vgs is the gate to source
the universal mobility law 共UML兲.16 In the variable range voltage Vgs = VG − Vs, Vs is the source voltage, Vd is the drain
hopping 共VRH兲 model,15,16 the conductivity and thus the mo- voltage, and k and T are, respectively, Boltzmann’s constant
bility of the charge carriers increase with doping as given by and the temperature.
the empirical Eqs. 共1兲 and 共2兲, Equation 共6兲 of the current does not seem to have a
␴ = K 1N ␥ 共1兲 direct dependence on the carrier concentration p. Neverthe-
less, when m = 0 共i.e., the device is unsaturated兲, Eq. 共6兲 is
and similar to the standard conventional MOSFET equation with
K3 = ␮ and thus

Id = K3
W
L
冋
C0 共Vgs − VT兲Vd −
V d2
2
. 册 共7兲

B. Saturation regime
Based on the previous calculation, the current equation
FIG. 2. Basic model of the OTFT. in the saturation regime 共Vgs − VT ⬍ Vds兲 is given by

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 104504-3 Fadlallah et al. J. Appl. Phys. 99, 104504 共2006兲

Id,sat = 冋 K3 W C02m+1
共2m + 1兲共2m + 2兲 L 共2␧0␧ pkT兲m
共Vgs − VT兲2m+2 册 threshold voltage of the device. The total charge on the gate
electrode Qg at any gate and drain voltages may be obtained
from

冕
⫻关1 + ␭共Vd − Vgs + VT兲兴, 共8兲 L

where ␭ is the conductance parameter and Vds is the drain to Qg = − W C0共VGT − Vx兲dx, 共9兲
0
source voltage.
where 共VGT = Vg − VT , VT = VFB兲 and C0 is the dielectric ca-
pacitance per unit area. In the last step of the calculation in
IV. TRANSIENT MODEL 共6兲, this integral can be evaluated explicitly using the drain
current equation 共5兲 to relate dx to dVx and the result is given
Some of the important low frequency circuit parameters
in 共10兲,
can also be obtained from the drain current Eq. 共6兲. For ex-
ample, to calculate the drain and source capacitances, the C0WL共2m + 2兲
共VGT − Vd兲2m+3 − 共VGT − Vs兲2m+3
Qg = ,
expression C = d共Q兲 / d共V兲 can be used.15,17,18 Assuming that 共2m + 3兲关共VGT − Vd兲2m+2 − 共VGT − Vs兲2m+2兴
the polymer TFT is an accumulation mode transistor and all
共10兲
of the current is due to drift and not diffusion, then the
threshold voltage is defined as the gate voltage that results in Where L is the channel length.
an accumulation channel, i.e., the flat band voltage VFB is the The gate to source capacitance is thus

Cgs = 冏 冏⳵Qg
⳵Vgs
Vd =
共2m + 3兲
冋
− C0共2m + 2兲Vgst2m+1WL 共2m + 2兲Vgdt2m+3 − 共2m + 3兲Vgdt2m+2Vgst + Vgst2m+3
共Vgdt2m+2 − Vgst2m+2兲2
, 册 共11兲

where Vgdt = VGT − Vd and Vgst = VGT − Vs.

Similarly, the short circuit gate to drain capacitance is

Cgd = 冏 冏⳵Qg
⳵Vgd
Vgs =
共2m + 3兲
冋
− C0共2m + 2兲Vgdt2m+1WL 共2m + 2兲Vgst2m+3 − 共2m + 3兲Vgst2m+2Vgdt + Vgdt2m+3
共Vgdt2m+2 − Vgst2m+2兲2
. 册 共12兲

These equations depend on the operating regime. It is
also seen from the transistor layout and cross section that the
overlapping capacitors are important in this case since the
gate electrode covers the entire source and drain fingers.
Just like drain current equations, the capacitor model
obeys the off, linear, and saturation regimes.18 In that sense,
Cgs and Cgd depend on the polarizations applied to the struc-
ture added to the overlapping capacitance 关Eq. 共13兲兴,
Cgs = CgsovW + Cgsoff,linear,saturation ,
Cgd = CgdovW + Cgdoff,linear,saturation , 共13兲
Electrical characterization is started using I-V and C-V
characteristics with transistors having W = 10 mm and differ-
ent channel lengths.
The developed model contains only 12 parameters
共Table I兲. Most of these parameters are physical depending
on the device structure and layout.
A. Extraction of the drain current factor in the off
regime I00
As we have seen in Fig. 3, the current in off regime, i.e.,
Vgst ⬎ 0, is nearly independent of gate potential. At the same

where Cgsov and Cgdov are the overlapping capacitance of TABLE I. Parameters list and signification.
source and drain, respectively.
Lchannel Length of the channel
Wfinger Width of the channel formed of one finger
V. MODEL PARAMETER EXTRACTION Nbfinger Number of fingers or “channel” 共interdigitated
source-drain technology兲
Before starting the development of the OTFT model, full TOX Gate insulator thickness
studies in terms of electrical and technological characteriza- VT Device threshold voltage
tion are required. m Mobility parameter
Two primary sets of measurements are required for the K3 Mobility parameter
I00 Off regime drain current factor
characterization of the organic transistor: the transfer charac-
RWS Source contact resistance
teristics 共Id vs Vgs兲 that allow the effective mobility 共␮兲 and
RWD Drain contact resistance
threshold voltage 共VT兲 to be determined and the output char- CT Capacitor factor
acteristics 共Id vs Vds兲 that provide saturation and general elec- ␭ Conductance parameter
trical performance information.

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 104504-4 Fadlallah et al. J. Appl. Phys. 99, 104504 共2006兲

FIG. 5. Typical curve Log关d共Id兲 / d共Vgs兲兴 plotted against log共Vgs兲 for the
FIG. 3. Drain current Id against gate voltage Vgs for different drain voltages Id-Vgs characteristics.
Vds.

C. Extraction of the mobility parameters

time it is clear that this current is also independent of the
drain to source voltage. The model of the current in off re-
gime is given by Ioff = I00W, where I00 is the off current pa-
rameter depending on the current density in this regime
while W is the width of the transistor.
B. Extraction of the threshold voltage
The value of the threshold voltage 共VT兲 is extracted us-
ing an extrapolation method which determines where the cur-
rent starts to increase with respect to the gate voltage. The
latter is measured at low Vds to ensure that the leakage cur-
rent does not affect the value of the threshold voltage.
To extract the value of VT, the slope of the curve Id
against Vgs starting from the point corresponding to the
maximum value of the transconductance gm = d共Id兲 / d共Vgs兲 is
plotted 关Figs. 4共a兲 and 4共b兲兴, while the intercept yields the
value for VT.
The parameters K3 and m are obtained using the equa-
tion of drain current in saturation and plotting
log关d共Id,sat兲 / d共Vgst兲兴 against log共Vgst兲 共Fig. 5兲. The equation
obtained 共14兲 is in the form of Y = aX + b; the value of m can
be obtained from the gradient of the graph while the inter-
cept yields the value for K3,
log
dId,sat
d共Vgst兲
= log 冋 K3C0共2m+1兲W
共2␧0␧polykT兲mL共2m + 1兲
册
+ 共2m + 1兲log共Vgst兲. 共14兲
D. Extraction of the series resistance of source and
drain „RS and RD…
Using the Id against Vds curve for different Vgs, one can
calculate the value of the resistance in the Ohmic regime by
using the Ohmic law equation R = U / I for several gate volt-
ages 共Vgs兲 and different channel lengths 共L兲. After that, R is
plotted against L for a high Vgs 共Fig. 6兲 ensuring that the
OTFT is in the accumulation regime. The value of contact
resistance can be obtained from the gradient of the curve
while the intercept yields the value for channel resistance,
Rcontact = RS + RD, RS = RD = Rcontact/2.

FIG. 4. Drain current and the slope corresponding to the maximum of gm

plotted against the gate voltage for two channel lengths, L = 20 ␮m and FIG. 6. Resistance plotted against the channel length for gate voltage
L = 10 ␮m. Vgs = −40 V.

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 104504-5 Fadlallah et al. J. Appl. Phys. 99, 104504 共2006兲

F. Extraction of the value of the dielectric permittivity

and overlapping capacitance
The dielectric constant of the gate dielectric is extracted
from capacitance measurements on a metal-insulator-metal
共MIM兲 structure at 3 ± 0.4⫻ 10−11 F / m. The real values of W
and L are extracted via a calibrated microscope.
Concerning the extraction of the overlapping capaci-
tances Cgsov and Cgdov 共source and drain, respectively兲, the
total overlapping surfaces of the devices are calculated, are
then multiplied by the dielectric capacitance, and are finally
divided by 2.

VI. MODEL VALIDATION

FIG. 7. Linear regression of the drain current 共Id兲 against the drain voltage
共Vds兲 in saturation mode for different gate voltages 共Vgs兲.
E. Extraction of the conductance parameter ␭
The extraction of the value of the conductance parameter
␭ is obtained using the output conductance gd = d共Id兲 / d共Vds兲
as follows 共Fig. 7兲: gd = d共Id兲 / d共Vds兲 = ␭Id,sat, where Id,sat is
equal to the value of the drain current when Vds = Vgs − VT and
gd is the slope of the curve 共Id against Vds in saturation mode,
obtained by linear regression兲.
The model validation is performed using the measure-
ment data. An operation is done in dc regime for different
polarizations and transistor sizes. Nonetheless, these results
are obtained with a model using simplified equations in
order to enhance circuit simulator convergence in circuit
simulations. Figures 8共a兲 and 8共b兲 show the measurement
and simulation in dc regime of two transistor sizes
共W / L = 10 mm/ 20 ␮m and W / L = 10 mm/ 10 ␮m兲. It shows
the validity of the model with different channel lengths and
different regimes in p-type OTFT.

FIG. 8. Measurement and simulation characteristics of transistors in different dc operation regimes with two transistors sizes: 共a兲 OTFT with
W / L = 10 mm/ 20 ␮m and 共b兲 OTFT with W / L = 10 mm/ 10 ␮m. Solid lines are measurements, while crossed lines represent simulation characteristics.

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 104504-6 Fadlallah et al. J. Appl. Phys. 99, 104504 共2006兲

FIG. 9. Measurement and simulation of gate-to-channel capacitance Cgc for

low frequency 共f = 500 Hz兲 against gate voltage Vgs for drain voltage
Vds = 0 V and transistor size 共W / L = 10 mm/ 20 ␮m兲.

Even using a simple model with 12 parameters, we can

see a fair agreement in the drain current values between mea-
surements and simulations and that the model is valuable for
different transistor lengths. The developed model takes into
account the transistor symmetry when Vds changes from
negative to positive.
Another validation operation is done in the transient
regime. This validation is important for the simulation of
circuits in this regime. Thus, Fig. 9 shows the measurement
and the simulation of the gate-to-channel capacitance for
Vds = 0 V. Knowing that the circuit operation frequency is
low, the validation is made at a measurement frequency of FIG. 11. 共a兲 Simulation of a p-type OTFT inverter and 共b兲 transfer charac-
500 Hz. teristic of a p-type OTFT inverter.

convergence of the model in circuit design. Two steps are

VII. MODEL TEST IN CIRCUIT DESIGN
chosen: simulation of an inverter and simulation of a ring
oscillator.
The model is validated for device operations in static
and transient regimes. Nonetheless, it is important to test the
A. Simulation of an inverter
The simulation of an inverter 共Fig. 10兲 using a drain-gate
shortcut of the load transistor is done. The transistor sizes are
T1: W / L = 600 ␮m / 10 ␮m and the load transistor T2:
W / L = 300 ␮m / 10 ␮m. The inverter is simulated using a
Vdd = −40 V, Vss = 0 V, and an input pulse ranging between 0
and −40 V with a rise time and fall time of Tr = T f = 100 ms.
The pulse duration is Tw = 300 ms and the total period is
P = 800 ms.
The simulations are shown on Figs. 11共a兲 and 11共b兲.
While Fig. 11共a兲 shows the input and output voltages for
different cycles of inversion, Fig. 11共b兲 shows the inverter
linearity.

FIG. 10. Topology of the p-type OTFT inverter. FIG. 12. Topology of the simulated ring oscillator.

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 104504-7 Fadlallah et al. J. Appl. Phys. 99, 104504 共2006兲

erating regimes 共linear, saturation, and off兲, and in the tran-

sient regime 共capacitor behavior兲. The transistor symmetry
共Vds negative and positive and Vgs negative and positive兲 is
also taken into account in the model. The test in circuit de-
sign is also done. Simulations of inverters and ring oscilla-
tors show good characteristics and present very acceptable
simulation timing showing the good behavior of the simula-
tor convergence during circuit simulation.

ACKNOWLEDGMENTS
We would like to thank B. Eccleston from the University
of Liverpool for endless help with modeling activities. Fur-
thermore, we thank D. Barclay from Plastic Logic Limited
FIG. 13. Simulations of an OTFT ring oscillator. for providing OTFT’s measurement as well as for valuable
discussions. This work has been supported by the European
B. Simulation of a ring oscillator PolyApply project funded under the 6th EU-Framework Pro-
This step of validation was the simulation of a ring os- gramme No. 507143.
cillator. Figure 12 shows the topology of the circuit made of 1
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