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1. How do you size NMOS and PMOS transistors to increase the threshold voltage?

Ans. by increasing channel length of nmos and pmos


2. Describe the various effects of scaling

Ans. if the resistance of the std cell is R1X and capacitance is C1X then scaling by a factor
S results in..
resistance = R1X/S
capacitance= S.C1X
3.For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give
the output for a square pulse input going from 0 to VDD

Ans. As it is a pass transistor and NMOS logic design; NMOS transistors are on when
high voltage is applied to it. so it just bypasses the input 0 to VDD to the output as its
gate is connected to VDD. When gate of NMOS is hign the input at source is transferred
to the drain.
4. What happens if we increase the numberof contacts or via from one metal layer to the
next?

Ans. no. of operations that can be performed can be increased at the same time wire
congestion problem may arise
5. For CMOS logic, give the various techniques you know to minimize power consumption

Ans. Reduce the supply voltage


Reduce the operating frequency
reduce output load capacitance
reduce leakage current in standby operation
use clock gating/sleep mode
use multi threshold and multiple supply device
use efficient coding and algorithms
partition the circuit if it is mixed signal
reduce swing voltage (memory Design)
6. Explain why & how a MOSFET works

Ans. MOSFET is a metal oxide semiconductor Field effect transistor, its unidirectional device and is formed by
four terminals GATE, SOURCE, DRAIN AND SUSTRATE. GATE is the control signal. when a suitable polarity
potential is applied at gate a conducting channel will form. This conducting channel can be used for switching or
amplification. Depending upon voltage applied at gate terminal MOSFET work on three regions
saturation, cutoff and active region. active region is used for amplification, cut-off and saturation region used for
switching operation, mostly digital ckt design

7. In the design of a large inverter, why do we prefer to connect small transistors in


parallel (thus increasing effective width) rather than lay out one transistor with large
width?

Ans. There are two reasons


1. Small transistors share active areas, so total diffusion capacitance seen is less
2. Signal EM violation are bound to occur with single large transisor, with small
transistors there parallel paths
8. What happens to delay if you increase load capacitance?

Ans. Delay increases due to load capacitance effect, taking longer time to charge the
capacitor and hence stable to drive the output load.