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R

ALLIANCE
Series Software

Synopsys FPGA Express Implementation Flow
Module Generators

LogiBLOX
.V .VHD

CORE Generator

.NGC= Xilinx Binary Netlist

NGC

.VEI .VHI

.VEO .VHO

Verilog & VHDL Instantiation

State Diagram State Diagram Editor Editor
VHDL Verilog

Schematic Design Schematic Design Editor Editor
VHDL Verilog

HDL Editor HDL Editor
Xilinx XNF Macros Library

EDIF

VHDL Verilog

EDN

Functional Simulation Flow Timing Simulation Flow VHDL Verilog

Requirements

Timing

CORE Generator

LogiBLOX

VSS VSS VCS VCS or or 3rd 3rd Party Party S S II M M U U L L A A T T II O O N N
EDDIE 1999

Xilinx
I M P L E M E N T A T I O N Tools

XNF

SDF

UNIFIED Gates UniSim VITAL, Verilog, Gates SimPrim VITAL, Verilog, Gates HDL Test Bench Command File or Test Vectors

FPGAExpress
Behavioral VHDL Verilog

EDIF

NCF XNF EDIF

BIT JEDEC

EDIF for Virtex, VirtexE, Spartan II Reports User Constraints File

g

EG

Functional Simulation Flow
PN 0010416 01

com United States 1-800-245-8005 support_center@synopsys.synopsys.com United Kingdom 44 1932-820821 ukhelp@xilinx. FPGA Express will automatically analyze the HDL files. Enter constraints In the Chips window. HDL design files can be added to the project.com North America 1-800-255-7778 hotline@xilinx.1i PN 0010416 01 After optimization.com Optimize the design Click on the optimize button located next to the implement button to synthesize the design OR select the menu Synthesis Optimize Chip Place & Route XNF or EDIF file with A2.1i implementation tools with the Design Manager GUI or DOS shell based commands. Click on the implement button and specify the target die. After entering constraints. save constraints by closing the constraints window.com After creating project. Implement the design Select the top-level module/entity in the Design Sources window and the implement button will be highlighted. After adding the HDL design files.R ALLIANCE Series Software Synopsys FPGA Express Information Guide Overview Device Architecture Support FPGA Product Family Spartan Virtex XC4000X CPLD Product Family XC9500 1 2 3 4 5 6 Create a project Go to menu File New and define a new project. A window will appear where various constraints can be edited. All HDL files processed by FPGA Express must be done through a project. write out the XNF or EDIF file by clicking on the Export Netlist button next to the implement button. speed grade and package. select the implementation. Synopsys Contacts and Technical Support World Wide Web: http://www.xilinx. Right-click on the selected implementation and select Edit Constraints.com France 33 1-3463-0100 frhelp@xilinx. Strategies for synthesis can be specified during implementation. Place and Route the XNF or EDIF file using A2. Add HDL files to project and analyze HDL files Xilinx Contacts and Technical Support World Wide Web: http://www. .com Japan 81 3-3297-9163 jhotline@xilinx.