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S T E L L A R I S E R R ATA

Stellaris LM3S9B92 RevB1 Errata
This document contains known errata at the time of publication for the Stellaris LM3S9B92 microcontroller. The table below summarizes the errata and lists the affected revisions. See the data sheet for more details. See also the ARM® Cortex™-M3 errata, ARM publication number PR326-PRDC-009450 v2.0. Table 1. Revision History
Date January 2011 Revision 3.4 Description ■ Added diagram to issue “Flash corruption or device failure may occur at power on” on page 12 for industrial temperature circuits. Added issue “Special configuration considerations for PB0 and PB1 when used as GPIO” on page 17. Updated diagram for issue “Flash corruption or device failure may occur at power on” on page 12 and clarified the power-on constraints. Updated diagram for issue “Flash corruption or device failure may occur at power on” on page 12 and added clarification. Added clarification to issue “Flash Write Buffer does not function above 50 MHz” on page 12. Updated diagram for issue “Flash corruption or device failure may occur at power on” on page 12. Added issue "ROM_USBHostMode function is incorrect". Added issue "ROM_CANBitRateSet function is incorrect". Added issue “Flash corruption or device failure may occur at power on” on page 12. Added issue ???. Added issue “USB compliance test issue: USB embedded host low-speed, far-end signal compliance tests fail” on page 30. Removed the "ROM_I2CMasterErr function is incorrect" issue because the data sheet has been changed such that the ERROR bit no longer is set when the ARBLST bit is set. Additional minor clarifications and corrections. Added issue “The RTRIS bit in the UARTRIS register is only set when the interrupt is enabled” on page 25. Minor edits. Based on further examination of the "I2C arbitration may be lost when operating as a master" issue, this issue has been moved to the GPIO section and renamed as “Schmitt input feature does not function correctly” on page 16. Added issue “Encoding error in the Ethernet MAC LED Encoding (MACLED) register” on page 28. Added information about items fixed on Rev C3.

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■ December 2010 3.3 ■

November 2010

3.2

■ November 2010 October 2010 3.1 3.0 ■ ■ ■ ■ ■ ■

September 2010

2.9

■ July 2010 2.8 ■

June 2010 April 2010

2.7 2.6

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January 12, 2011/Rev. 3.4

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Stellaris LM3S9B92 RevB1 Errata

Date March 2010

Revision 2.5

Description ■ Added issue “The prescaler does not work correctly when counting up in periodic or one-shot mode” on page 22. Added issue “Snapshot must be enabled in both Timer A and B when in 32-bit snapshot mode” on page 22. Added issue “Phantom interrupts occur in Smart Card mode” on page 24. Added issue "I2C arbitration may be lost when operating as a master". Added issue “The option to force the ROM boot loader to execute at reset with an external pin does not function” on page 11. Amended the workaround for issue “A spurious DMA request is generated when the timer rolls over in Input-Edge Time mode” on page 19. Reworded description of issue “The value of the prescaler register is not readable in Edge-Count mode” on page 20. Removed "Prescaler register must have a non-zero value in 16-bit Edge-Time mode" as it has been determined this item was included erroneously. Added issue “ADC trigger and Wait-on-Trigger may assert when the timer is disabled” on page 20. Added issue “Wait-on-Trigger does not assert unless the TnOTE bit is set” on page 21 . Added issue “Do not enable match and timeout interrupts in 16-bit PWM mode” on page 21. Added issue “Do not use µDMA with 16-bit PWM mode” on page 21. Added issue “Writing the GPTMTnV register does not change the timer value when counting up” on page 22. Added issue “A spurious DMA request is generated when the timer rolls over the 16-bit boundary” on page 20. Added issue “The value of the prescaler register is not readable in Edge-Count mode” on page 20. Added issue "Prescaler register must have a non-zero value in 16-bit Edge-Time mode." Added issue “The ADCSPC register does not function” on page 23. Modified description for “The General-Purpose Timer match register does not function correctly in 32-bit mode” on page 19 to include DMA operation. Added issue “A spurious DMA request is generated when the timer rolls over in Input-Edge Time mode” on page 19. Changed workaround for “Latch-up may occur if power is applied to the VBUS pin but not to VDD” on page 29 and changed status to "Fixed in Rev C."

■ ■ Mar 2010 2.4 ■

■ ■ ■ ■ ■

Feb 2010

2.3

■ ■ ■ Jan 2010 2.2 ■

2

Texas Instruments

January 12, 2011/Rev. 3.4

Stellaris LM3S9B92 RevB1 Errata

Date Dec 2009

Revision 2.1

Description ■ The status of “The Recover Locked Device sequence does not work as expected” on page 5 has been changed to "Fixed in Rev C." "Hard Fault possible when waking from Sleep or Deep-Sleep modes and Cortex-M3 Debug Access Port (DAP) is enabled" has been removed and the content added to the LM3S9B92 data sheet. Added additional APIs to “Some ROM functions are unsupported” on page 8. “The µDMA controller fails to generate capture mode DMA requests from Timer A in the Timer modules” on page 16 has been added. "Ethernet packet count decremented before the FCS is read" has been removed and the content added to the LM3S9B92 data sheet. The status of “Latch-up may occur if power is applied to the VBUS pin but not to VDD” on page 29 has been changed to "Not fixed in Rev C."

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Nov 2009

2.0

Started tracking revision history.

Table 2. List of Errata
Erratum Number Erratum Title Module Affected Revision(s) Affected

1.1 1.2 2.1 2.2 2.3 3.1 3.2 3.3 3.4 3.5 3.6 4.1 4.2 4.3 5.1 6.1 6.2 6.3

JTAG INTEST instruction does not work

JTAG

B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1, C1 B1 B1

The Recover Locked Device sequence does not work as expected JTAG Sleep and Deep-Sleep mode not usable at higher speeds when ISRs reside in Flash memory System Control

Device Capabilities registers may not accurately reflect available System Control signals The PIOSC is not trimmed by the factory System Control

Ethernet fails to connect when using the Boot Loader software in ROM ROM Some ROM functions are unsupported ROM

ROM mapping check for the Boot loader does not function properly ROM ROM_SSIConfigSetExpClk function is incorrect ROM_USBFIFOFlush function is incorrect The option to force the ROM boot loader to execute at reset with an external pin does not function ROM ROM ROM

Cumulative page erases may introduce bit errors in Flash memory Flash Memory Flash Write Buffer does not function above 50 MHz Flash corruption or device failure may occur at power on Flash Memory Flash Memory

The µDMA controller fails to generate capture mode DMA requests µDMA from Timer A in the Timer modules Port B [1:0] pins require external pull-up resistors Schmitt input feature does not function correctly GPIO GPIO

B1, C1, C3, C5 B1 B1, C1 B1, C1, C3, C5

Special configuration considerations for PB0 and PB1 when used GPIO as GPIO

January 12, 2011/Rev. 3.4

Texas Instruments

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C3.Stellaris LM3S9B92 RevB1 Errata Erratum Number Erratum Title Module Affected Revision(s) Affected 7. C3. C1. 3. C1. C1. C3. C5 B1. C1.8 8.3 8.6 8.4 12.1 8. C1.4 8. C3.10 8.11 9. C1.2 11. C5 B1.1 13. C5 B1. C5 B1. C5 B1. C5 B1 B1 B1 B1. C3.1 7. C5 B1 B1 B1 B1 B1 A spurious DMA request is generated when the timer rolls over in General-Purpose Timers Input-Edge Time mode A spurious DMA request is generated when the timer rolls over the 16-bit boundary General-Purpose Timers The value of the prescaler register is not readable in Edge-Count General-Purpose Timers mode ADC trigger and Wait-on-Trigger may assert when the timer is disabled Wait-on-Trigger does not assert unless the TnOTE bit is set General-Purpose Timers General-Purpose Timers Do not enable match and timeout interrupts in 16-bit PWM mode General-Purpose Timers Do not use µDMA with 16-bit PWM mode Writing the GPTMTnV register does not change the timer value when counting up General-Purpose Timers General-Purpose Timers The prescaler does not work correctly when counting up in periodic General-Purpose Timers or one-shot mode Snapshot must be enabled in both Timer A and B when in 32-bit snapshot mode General-Purpose Timers Writes to Watchdog Timer 1 module WDTLOAD register sometimes Watchdog Timers fail ADC hardware averaging produces erroneous results in differential ADC mode The ADCSPC register does not function UART Smart Card (ISO 7816) mode does not function ADC UART When in IrDA mode. C1. C1. C5 B1. C3.3 8. C5 B1.1 13. C3. C5 B1. C5 B1. C5 B1. C3.4 . C3.2 8. the UnRx signal requires configuration even UART if not used Phantom interrupts occur in Smart Card mode The RTRIS bit in the UARTRIS register is only set when the interrupt is enabled An interrupt is not generated when using µDMA with the SSI module if the EOT bit is set Some bits in the I2SMCLKCFG register do not function I2S SCLK signal is inverted in certain modes UART UART SSI I2S I2S Ethernet receive packet corruption may occur when using optional Ethernet Controller auto-clock gating Ethernet packet loss with cables longer than 50 meters Ethernet Controller 4 Texas Instruments January 12.1 14. 2011/Rev.3 11. C1.5 8.9 8. C3.7 8.2 14.1 11. C3. C5 B1.1 10. C3.2 EPI dual-chip select function does not work EPI Host-Bus 16 mode does not work Clock signal in EPI General-Purpose mode is inverted The General-Purpose Timer match register does not function correctly in 32-bit mode EPI EPI EPI General-Purpose Timers B1 B1 B1 B1. C1. C3.2 7. C5 B1. C3. C1. C1 B1. C1.2 11. C1.1 10. C1.

2 16. 3. C1. 2011/Rev.4 Texas Instruments 5 . far-end signal compliance tests fail with 5 m cable USB compliance test issue: USB embedded host low-speed. Workaround: None.3 15.2 The Recover Locked Device sequence does not work as expected Description: If software configures any of the JTAG/SWD pins as GPIO or loses the ability to communicate with the debugger.3 14. After reconfiguring the JTAG/SWD pins. there is a debug sequence that can be used to recover the microcontroller.3 16. January 12.2 Ethernet PHY interrupts do not function correctly Encoding error in the Ethernet MAC LED Encoding (MACLED) register USB0ID and USB0VBUS signals are required to be connected regardless of mode Ethernet Controller Ethernet Controller USB B1 B1. C3 B1.1 16. C3 B1 B1 B1 B1 B1 B1 Latch-up may occur if power is applied to the VBUS pin but not to USB VDD USB compliance test issue: USB full-speed. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1.1 17. C5 B1 B1 B1.4 15. C1. C1.4 17.Stellaris LM3S9B92 RevB1 Errata Erratum Number Erratum Title Module Affected Revision(s) Affected 14.1 15.2 15. using the Recover Locked Device sequence does not recover the device. far-end signal compliance tests fail PWM generation is incorrect with extreme duty cycles Sync of PWM does not trigger "zero" action PWM "zero" action occurs when the PWM module is disabled PWM Enable Update register bits do not function USB USB PWM PWM PWM PWM Momentarily exceeding VIN ratings on any pin can cause latch-up Electrical Characteristics Power-on event may disrupt operation Electrical Characteristics 1 1.4 16. 1. C3. called the Recover Locked Device sequence.1 JTAG JTAG INTEST instruction does not work Description: The JTAG INTEST (Boundary Scan) instruction does not properly capture data.

follow these steps: 1. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. If Sleep or Deep-Sleep mode is used at those speeds. Power cycle the board and run the debug port unlock procedure in LM Flash Programmer. 3. but that is ok. DO NOT power cycle when LM Flash Programmer tells you to. 6 Texas Instruments January 12. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1.Stellaris LM3S9B92 RevB1 Errata Workaround: To get the device unlocked. Go to the Flash Utilities tab in LM Flash Programmer and do another mass erase operation (check "Entire Flash" and then click the Erase button). 2. Run the processor at 50 MHz. 4. Go to the Flash Utilities tab in LM Flash Programmer and do a mass erase operation (check "Entire Flash" and then click the Erase button). an invalid PC is sometimes returned for the interrupt vector address when exiting sleep mode.1 System Control Sleep and Deep-Sleep mode not usable at higher speeds when ISRs reside in Flash memory Description: Sleep and Deep-Sleep modes cannot be used when running the processor at 66 or 80 MHz when the Interrupt Service Routines (ISRs) and vector table reside in Flash memory. Power cycle the board. 2 2.4 . 2011/Rev. This erase appears to have failed. 2. Store the ISRs and vector table in the on-chip SRAM when running the processor at 66 or 80 MHz. Workaround: There are two possible workarounds for this issue: 1. 3.

2011/Rev. Silicon Revision Affected: B1 Fixed: Fixed for devices with date codes beginning 0946 (work week 46. Bits affected include DC3 [31:0].4 Texas Instruments 7 . Silicon Revision Affected: B1 January 12. 2009).Stellaris LM3S9B92 RevB1 Errata 2. This errata item affects any product with date codes prior to 0946 (work week 46. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. 2009). Do not rely on the value of these bits in system design.1 ROM Ethernet fails to connect when using the Boot Loader software in ROM Description: The Ethernet controller takes longer to connect than the Boot Loader software in ROM allows. DC4 [15:14]. and DC8 [31:0]. Workaround: None. 3. 2. Workaround: Download the Boot loader software in the on-chip Flash memory and ensure that the Ethernet connection uses MDI mode only. These bits do not always properly reflect the available signals. DC5 [27:24] and [7:0]. the PIOSC can be user calibrated. Workaround: For parts that have a Hibernation module.2 Device Capabilities registers may not accurately reflect available signals Description: Some of the Device Capabilities register bits reflect the presence of specific pins on the microcontroller. The PIOSC cannot be calibrated on parts without a Hibernation module.3 The PIOSC is not trimmed by the factory Description: The PIOSC is not trimmed by the factory prior to shipment. 3 3.

2011/Rev. 3. 3.Stellaris LM3S9B92 RevB1 Errata Fixed: Fixed in Rev C1.4 .2 Some ROM functions are unsupported Description: The following functions are unsupported in ROM: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ADCComparatorConfigure ADCComparatorRegionSet ADCComparatorReset ADCComparatorIntDisable ADCComparatorIntEnable ADCComparatorIntStatus ADCComparatorIntClear CANBitRateSet EPIIntStatus EPIModeSet EPIDividerSet EPIConfigSDRAMSet EPIConfigGPModeSet EPIConfigHB8Set EPIConfigHB16Set EPIAddressMapSet EPINonBlockingReadConfigure EPINonBlockingReadStart EPINonBlockingReadStop EPINonBlockingReadCount EPINonBlockingReadAvail EPINonBlockingReadGet32 EPINonBlockingReadGet16 EPINonBlockingReadGet8 EPIFIFOConfig EPIWriteFIFOCountGet EPIIntEnable EPIIntDisable EPIIntErrorStatus EPIIntErrorClear GPIOPinConfigure GPIOPinTypeI2S GPIOPinTypeEthernetLED GPIOPinTypeUSBAnalog I2CSlaveIntClearEx I2CSlaveIntDisableEx I2CSlaveIntEnableEx I2CSlaveIntStatusEx I2SIntClear I2SIntDisable I2SIntEnable I2SIntStatus I2SMasterClockSelect I2SRxConfigSet I2SRxDataGet 8 Texas Instruments January 12.

which can be downloaded from the website at http://www. 3.Stellaris LM3S9B92 RevB1 Errata ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ I2SRxDataGetNonBlocking I2SRxDisable I2SRxEnable I2SRxFIFOLevelGet I2SRxFIFOLimitGet I2SRxFIFOLimitSet I2STxConfigSet I2STxDataPut I2STxDataPutNonBlocking I2STxDisable I2STxEnable I2STxFIFOLevelGet I2STxFIFOLimitGet I2STxFIFOLimitSet I2STxRxConfigSet I2STxRxDisable I2STxRxEnable IntPendSet IntPendClear SSIBusy SysCtlDelay SysCtlI2SMClkSet UARTBusy UARTFIFODisable UARTFIFOEnable UARTRxErrorClear UARTRxErrorGet UARTTxIntModeGet UARTTxIntModeSet uDMAChannelSelectDefault uDMAChannelSelectSecondary USBDevEndpointConfigGet USBEndpointDataAvail USBEndpointDMAChannel USBEndpointDMADisable USBEndpointDMAEnable USBModeGet USBOTGHostRequest USBIntDisableControl USBIntEnableControl USBIntStatusControl USBIntDisableEndpoint USBIntEnableEndpoint USBIntStatusEndpoint USBHostMode Workaround: Code for these functions is included in the current version of StellarisWare.com/software_updates.ti. Silicon Revision Affected: B1 January 12.4 Texas Instruments 9 . 2011/Rev.

0008. Workaround: Use the StellarisWare SSIConfigSetExpClk function in Flash memory. 2011/Rev.3 ROM mapping check for the Boot loader does not function properly Description: Before the processor is released from the reset state. two lower bits of a clock divisor register could be corrupted. So. 3. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. the ROM is errantly mapped to zero preventing the application that is stored in Flash memory from being executed out of reset. 10 Texas Instruments January 12. 3. in situations where a valid reset vector (offset 0x0000. Rev C3 implements the boot loader process outlined in the data sheet.4 ROM_SSIConfigSetExpClk function is incorrect Description: If a non-Motorola format was specified in a call to the ROM_SSIConfigSetExpClk function. which is the NMI vector. Silicon Revision Affected: B1 Fixed: ROM boot loader does not function in Rev C1. Flash memory is mapped to address 0x0000.5 ROM_USBFIFOFlush function is incorrect Description: The ROM_USBFIFOFlush function improperly checks the state of the FIFO and does not allow the endpoint’s FIFO to be flushed. the System Control module is supposed to check offset 0x0000. the System Control module errantly checks offset 0x0000.0000.0004 of Flash memory looking for a reset vector that is not 0xFFFF. 3. This error affects all endpoints other than endpoint zero.0004) has been programmed. Workaround: Use the StellarisWare USBFIFOFlush function in Flash memory.Stellaris LM3S9B92 RevB1 Errata Fixed: Fixed in Rev C1. Workaround: Ensure that the NMI vector is always programmed. This corruption results in a small error in the actual clock rate. Currently. If an initialized reset vector is found.0000. 3.4 . otherwise ROM is mapped to address 0x0000.FFFF. but the NMI vector has not been programmed.

3. A bit error means that a bit may change from 0 to 1 or 1 to 0.FFFF. 2011/Rev. Workaround: There are two possible workarounds for this issue: 1.0004 contains 0xFFFF. C1 Fixed: Fixed in Rev C3. Minimize total page erases to less than 3000 between mass erases for the lifetime of the product.Stellaris LM3S9B92 RevB1 Errata Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. this issue would not be seen over at least 17 years. At the rate of one page erase per week.6 The option to force the ROM boot loader to execute at reset with an external pin does not function Description: The option to force the ROM boot loader to execute at reset with an external pin does not function. The two CRC functions built into ROM can assist in this. 3.4 Texas Instruments 11 . After each mass erase. Changing the PORT and PIN fields of the Boot Configuration (BOOTCFG) register has no effect. Workaround: The ROM boot loader still executes if address 0x0000. 2. A mass erase erases the entire Flash memory array (all pages). The bit error is not confined to the page being erased or the 4-KB block but could be in any page in the Flash memory. an additional 3000 page erase operations are allowed before bit errors may be introduced. Perform CRC checks on all Flash memory after page erases to increase the chances of detecting the issue. A page erase is used to erase a 1-KB page so it can be rewritten.1 Flash Memory Cumulative page erases may introduce bit errors in Flash memory Description: Cumulative page erases anywhere in the Flash memory array may introduce bit errors. Silicon Revision Affected: B1. Silicon Revision Affected: B1 January 12. indicating that the Flash memory has not been programmed. 4 4.

3 Flash corruption or device failure may occur at power on Description: There is a small risk of flash corruption or device failure on power up. The issue can occur with certain VDD and VDDC power sequences.08 V.2 V regulator has an integrated Power-OK (POK) circuit that is used to enable VDD when VDDC reaches 1. 3. the POK circuit disables the load switch if VDDC drops below 1. The 1.Stellaris LM3S9B92 RevB1 Errata Fixed: Fixed in Rev C1.4 . 12 Texas Instruments January 12. 2011/Rev.5 V. In addition. 4. ■ VDDC must reach at least 1.2 V regulator.2 V. Workaround: To eliminate the risk of flash corruption. A circuit combining an external 1. the ROM boot loader cannot be used at speeds above 50 MHz because it uses the write buffer.5 V. During power-down or transient conditions. two power-on requirements must be met: ■ The ramp of both VDD and VDDC must begin below 0. Figure 1 on page 13 details these requirements. The load switch has an internal clamp to accelerate VDD decay. 4.02 V or VDD drops below 1. Workaround: Lower the speed of the system clock to 50 MHz or less while programming the Flash memory or using the ROM boot loader.0 V before VDD rises above 1. The failure is not in the flash memory itself but in the control logic to the flash.2 Flash Write Buffer does not function above 50 MHz Description: The Flash Write Buffer does not successfully program the Flash memory at speeds above 50 MHz. Normally VDDC is supplied by the device's internal voltage regulator from the LDO output pin. however in some circuits the internal regulator may not meet this VDDC timing requirement. Three workaround circuits have been identified that meet these requirements and are described below. a voltage supervisor and a power switch can be used to ensure that this timing requirement are met. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1.

5V 0.0V when VDD ramps to 1. Figure 2 shows a small chip-scale load switch to control VDD.3V 1. VDDC and VDD Rise Time Relationships VDD 3. it is important to consider all possible power conditions for the system. a capacitor (1-3 μF) must remain connected for regulator stability.0V VDD and VDDC ramps must start ≤ 0. 3.Stellaris LM3S9B92 RevB1 Errata Figure 1. the LDO pin of the Stellaris device must be disconnected from the external 1. Although the LDO regulator output is unused in the workaround circuit.5V 1.2V When implementing this workaround. In addition.2V VDDC VDDC must be ≥ 1.2 V LDO to prevent electronic over stress of the pin. This circuit is suitable for VDD current up to 2 A peak.4 Texas Instruments 13 . All of these circuits include two jumpers which provide the option to bypass the workaround circuit for future silicon revisions. January 12. 2011/Rev. including: ■ Brown-out (momentary sags in the power source) ■ Switch and contact bounce ■ Other EMI susceptibility tests ■ Various battery and power source disturbances Three recommended circuits that eliminate the occurrence of this issue are shown below.

Figure 3.Stellaris LM3S9B92 RevB1 Errata Figure 2.4 . 2011/Rev. 3. Recommended Voltage Supply Circuit 2 14 Texas Instruments January 12. Recommended Voltage Supply Circuit 1 Figure 3 on page 14 shows a larger SOT-packaged load switch with VDD current capabilities up to 400 mA peak (both channels in parallel).

2011/Rev. Recommended Voltage Supply Circuit 3 Silicon Revision Affected: Fixed: Fixed on C5. The regulator should remain within its thermal limits while accommodating a worst-case VDDC current of 125 mA. The TPS3808G12 is a dedicated 1. SPRA953.Stellaris LM3S9B92 RevB1 Errata Figure 4 on page 15 is recommended for designs that require an industrial-temperature operating range. For more information about thermal metrics.4 V (maximum) voltage drop. Figure 4.2 V LDO voltage regulator.2 V voltage supervisor that ensures VDD is only applied once VDDC is valid.4 Texas Instruments 15 . With a 2. An important consideration is the power dissipation in the 1. see the IC Package Thermal Metrics application report. January 12. The junction temperature will be approximately 108ºC (23ºC + 85ºC) at 85ºC ambient temperature which is well within the rating of the part. The TPS79912DRV regulator has a θja of 74. 3. the power dissipation is 300 mW.2 ºC/W.

The additional transitions can cause anomalous operation in any peripherals or GPIOs that use digital inputs. Silicon Revision Affected: B1. 6. 3. As a result. Positive edges are not affected. Workaround: Use Timer B. C1. GPIOs) or that typically involve slower signals (sensor inputs). 16 Texas Instruments January 12. C3. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. Most at risk are peripherals that use pull-up resistors (I2C.1 µDMA The µDMA controller fails to generate capture mode DMA requests from Timer A in the Timer modules Description: The µDMA controller fails to generate DMA requests from Timer A in the General-Purpose Timer modules when in the Event Count and Event Time modes. a negative edge can generate several additional transitions into the microcontroller even though the input signal is still within the hysteresis band. Workaround: External pull-up resistors must be used on these two pins when they are used as GPIOs.Stellaris LM3S9B92 RevB1 Errata 5 5. 2011/Rev. C5 Fixed: Not yet fixed.1 GPIO Port B [1:0] pins require external pull-up resistors Description: The internal pull-up resistors are not effective for the Port B0 and B1 pins. 6 6. This behavior can affect the noise immunity of digital inputs.4 . If the input signal has a slew rate of less than 1V/µs.2 Schmitt input feature does not function correctly Description: The Schmitt input on digital inputs may generate spurious transitions when connected to low slew-rate signal sources. arbitration may be lost during communication when the I2C module is the master.

Stellaris LM3S9B92 RevB1 Errata Workaround: Ensure that all signals connected to digital inputs have a slew rate of at least 1V/µs. C5 Fixed: Not yet fixed. 3. Adding an external Schmitt-trigger circuit is a requirement for circuits where slow transitions are unavoidable and system noise levels are high. Silicon Revision Affected: B1. Silicon Revision Affected: B1. C3. 7 7. Note that R-C filters.3 Special configuration considerations for PB0 and PB1 when used as GPIO Description: When using PB0 and PB1 as GPIO and not as USB signals. such as low pass. C1 Fixed: Fixed in Rev C3. In some applications.4 Texas Instruments 17 . System designs should use ALE Configuration mode (CSCFG=0x0) or CSn Configuration mode (CSCFG=0x1). or if additional transitions on the falling edge can be tolerated. C1. Silicon Revision Affected: B1 January 12. 2011/Rev. on digital input signals should only be used if the slew-rate is still above 1V/µs. there may be excessive current draw on PB0 and PB1 due to an internal pull-down resistor when the USB controller is configured for Host or Device mode.1 EPI EPI dual-chip select function does not work Description: The Dual CSn Configuration mode (CSCFG=0x2) and the ALE with Dual CSn Configuration mode (CSCFG=-x3) controlled by the EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2) register do not function. reducing the resistance value of pull-up and pull-down resistors may be necessary. Workaround: Enable the USB module by setting the USB0 bit in the Run Mode Clock Gating Control Register 2 (RCGC2) register and set the DEVMODOTG bit in the USB General-Purpose Control and Status (USBGPCS) register to isolate PB0 and PB1 from the internal pull-down resistor. Workaround: None. 6.

3. During read cycles. ensure that the data meets set up and hold times for the appropriate edge as shown in the diagram above. 7.Stellaris LM3S9B92 RevB1 Errata Fixed: Fixed in Rev C1.4 .3 Clock signal in EPI General-Purpose mode is inverted Description: The clock signal that is output on the EPI0S31 signal in General-Purpose mode is inverted. 18 Texas Instruments January 12. 7. Figure 5. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. Workaround: None.2 EPI Host-Bus 16 mode does not work Description: The Host-Bus 16 mode (MODE=0x3) controlled by the EPI Configuration (EPICFG) register do not function. Timing Differences Between Rev B and Rev C Devices CLOCK (Rev B) CLOCK (Rev C) iRDY RD WR Address Data (Rev B) Data (Rev C) Data Read Write Data Data Data Workaround: Use the opposite edge for timing when designing with this interface. 2011/Rev. Figure Figure 5 on page 18 shows the timing differences between Rev B parts and Rev C parts.

Silicon Revision Affected: B1. Workaround: None. Workaround: Either ignore the spurious interrupt. Silicon Revision Affected: B1. 3. January 12. regardless of the value of the upper 16 bits. when the lower 16 bits match. C5 Fixed: Not yet fixed. if enabled. 8 8. C1. a spurious DMA request is generated.2 A spurious DMA request is generated when the timer rolls over in Input-Edge Time mode Description: When the timer is in Input-Edge Time mode and rolls over after the terminal count. or capture the edge time into a buffer via DMA.1 General-Purpose Timers The General-Purpose Timer match register does not function correctly in 32-bit mode Description: The GPTM Timer A Match (GPTMTAMATCHR) register triggers a match interrupt and a DMA request. C5 Fixed: Not yet fixed. C3. then the spurious interrupt can be detected by noting that the captured value is the same as the previous capture value.Stellaris LM3S9B92 RevB1 Errata Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. 8. C3. C1.4 Texas Instruments 19 . 2011/Rev.

Stellaris LM3S9B92 RevB1 Errata 8. Workaround: Only use DMA with a 16-bit periodic timer. Silicon Revision Affected: B1. C1. the bits [23:16] always contain the initial value of the GPTM Timer n Prescale (GPTMTnPR) register. Also.3 A spurious DMA request is generated when the timer rolls over the 16-bit boundary Description: When the timer is in 32-bit periodic or one-shot mode and is enabled to generate periodic DMA requests. C1. for the Wait-on-Trigger mode. Silicon Revision Affected: B1. C5 Fixed: Not yet fixed. enabling the ADC trigger. C3. Similarly. 20 Texas Instruments January 12. When reading the GPTM Timer n (GPTMTnR) register as a 32-bit value. the prescaler is used as an 8-bit high order extension to the 16-bit counter. that is.4 . 8.5 ADC trigger and Wait-on-Trigger may assert when the timer is disabled Description: If the value in the GPTM Timer n Match (GPTMTnMATCHR) register is equal to the value of the timer counter and the TnOTE bit in the GPTM Control (GPTMCTL) register is set. C5 Fixed: Not yet fixed. 8. enabling the Wait-on-Trigger mode. C3. Workaround: Enable the timer before setting the TnOTE bit. ensure that the timers are configured in the order in which they will be triggered. 2011/Rev. a spurious DMA request is generated when the timer rolls past 0x0000FFFF. Workaround: None. 3. the trigger fires even when the timer is disabled. if the value in the GPTMTnMATCHR register is equal to the value of the timer counter and the TnWOT bit in the GPTM Timer n Mode (GPTMTnMR) register is set. the "load" value of the 8-bit extension. the trigger fires even when the timer is disabled (the TnEN bit in the GPTMCTL register is clear).4 The value of the prescaler register is not readable in Edge-Count mode Description: In Edge-Count mode.

8. C3. C1.6 Wait-on-Trigger does not assert unless the TnOTE bit is set Description: Wait-on-Trigger does not assert unless the TnOTE bit is set in the GPTMCTL register. C5 Fixed: Not yet fixed. the ADC trigger is also enabled. C3. C5 Fixed: Not yet fixed. 3. 2011/Rev. C5 Fixed: Not yet fixed. Workaround: Ensure that any unwanted interrupts are masked in the GPTMTnMR and GPTMIMR registers.7 Do not enable match and timeout interrupts in 16-bit PWM mode Description: 16-bit PWM mode generates match and timeout interrupts in the same manner as periodic mode. the TnOTE bit must also be set in the GPTMCTL register in order for the Wait-on-Trigger to fire. Note that when the TnOTE bit is set. Silicon Revision Affected: B1. 8.Stellaris LM3S9B92 RevB1 Errata Silicon Revision Affected: B1. Workaround: If the TnWOT bit in the GPTM Timer n Mode (GPTMTnMR) register is set.8 Do not use µDMA with 16-bit PWM mode Description: 16-bit PWM mode generates match and timeout µDMA triggers in the same manner as periodic mode. 8. C1. C1. C3. Silicon Revision Affected: B1. Silicon Revision Affected: B1. C3. enabling the Wait-on-Trigger mode. C1.4 Texas Instruments 21 . C5 January 12. Workaround: Do not use µDMA to transfer data when the timer is in 16-bit PWM mode.

3. 8. Workaround: None. Silicon Revision Affected: B1.9 Writing the GPTMTnV register does not change the timer value when counting up Description: When counting up.4 . 8.10 The prescaler does not work correctly when counting up in periodic or one-shot mode Description: When counting up. C1. C3. C3. C5 22 Texas Instruments January 12. Silicon Revision Affected: B1. Silicon Revision Affected: B1. 2011/Rev. C5 Fixed: Not yet fixed. 8. C3. the prescaler does not work correctly in 16-bit periodic or snap-shot mode. Workaround: Do not use the prescaler when counting up in 16-bit periodic or snap-shot mode. Workaround: If both the TASNAPS and TBSNAPS bits are set in the GPTM Timer A Mode (GPTMTAMR) register.Stellaris LM3S9B92 RevB1 Errata Fixed: Not yet fixed. C5 Fixed: Not yet fixed. writes to the GPTM Timer n Value (GPTMTnV) register do not change the timer value.11 Snapshot must be enabled in both Timer A and B when in 32-bit snapshot mode Description: When a periodic snapshot occurs in 32-bit periodic mode. C1. the entire 32-bit snapshot value is stored in the GPTMTAR register. C1. only the lower 16-bit are stored into the GPTM Timer A (GPTMTAR) register.

10 10. 3. Instead. C3. 9 9. 10.1 ADC ADC hardware averaging produces erroneous results in differential mode Description: The implementation of the ADC averaging circuit does not work correctly when the ADC is sampling in differential mode and the difference between the voltages is approximately 0.2 The ADCSPC register does not function Description: The ADC Sample Phase Control (ADCSPC) register does not function and cannot be used. C1. C5 Fixed: Not yet fixed.4 Texas Instruments 23 . C3. C1. writes to the Watchdog Load (WDTLOAD) register may sometimes fail. Workaround: Do not use hardware averaging in differential mode.1 Watchdog Timers Writes to Watchdog Timer 1 module WDTLOAD register sometimes fail Description: Due to the independent clock domain of the Watchdog Timer 1 module. C5 Fixed: Not yet fixed. read the contents back and verify that they are correct. Silicon Revision Affected: B1.Stellaris LM3S9B92 RevB1 Errata Fixed: Not yet fixed. use the FIFO to store results and average them in software. Silicon Revision Affected: B1. 2011/Rev. Workaround: After performing a write to the WDTLOAD register. even though the WRC bit in the WDTCTL1 register is set after the write occurs. perform the write operation again.0V. If they are incorrect. January 12.

if the application does not require the use of the UnRx signal.1 UART UART Smart Card (ISO 7816) mode does not function Description: The UnTX signal does not function correctly as the bit clock in Smart Card mode. 11 11. after receiving a valid TX interrupt. the UnRx signal requires configuration even if not used Description: When in IrDA mode. 2011/Rev. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. the GPIO pin that has the UnRx signal as an alternate function must be configured as the UnRx signal and pulmac High. 24 Texas Instruments January 12. Workaround: When in IrDA mode. 3.4 . phantom parity error interrupts occur. 11. 11.Stellaris LM3S9B92 RevB1 Errata Workaround: None. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. Workaround: None.3 Phantom interrupts occur in Smart Card mode Description: In Smart Card mode. the transmitter may not function correctly if the UnRx signal is not used. even though all UARTRIS and UARTMIS bits are clear.2 When in IrDA mode.

C1 Fixed: Fixed in Rev C3. even when the PERIS and PEMIS bits are clear. 12 12. 11. 22. the RTIM bit can be set while the UART interrupt is disabled in the NVIC using the IntDisable(n) function in the StellarisWare Peripheral Driver Library. With this configuration. where n is 21.Stellaris LM3S9B92 RevB1 Errata Workaround: Make sure to always clear the parity error interrupt in the interrupt handler. regardless of the state of the RTIM enable bit in the UART Interrupt Mask (UARTIM) register.4 The RTRIS bit in the UARTRIS register is only set when the interrupt is enabled Description: The RTRIS (UART Receive Time-Out Raw Interrupt Status) bit in the UART Raw Interrupt Status (UARTRIS) register should be set when a receive time out occurs. However. or 49 depending on whether UART0. UART1 or UART2 is used. currently the RTIM bit must be set in order for the RTRIS bit to be set when a receive time out occurs. Silicon Revision Affected: B1.1 SSI An interrupt is not generated when using µDMA with the SSI module if the EOT bit is set Description: When using the primary µDMA channels with the SSI module. software can poll the RTRIS bit.4 Texas Instruments 25 . Silicon Revision Affected: B1. 2011/Rev. C5 Fixed: Not yet fixed. Workaround: Use the alternate µDMA channels for the SSI module. C1. but the interrupt is not reported to the NVIC. C3. Workaround: For applications that require polled operation. an interrupt is not generated on transmit µDMA completion if the EOT bit (bit 4 of the SSICR1 register) is enabled. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. January 12. 3.

The remaining 8 bits in each field function correctly. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. Workaround: For the transmitter. 26 Texas Instruments January 12. Ensure that the I2S0TXSCK signal leads the I2S0TXWS signal by at least 4 ns. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. so most of the possible integer input choices can be used in system design. not the falling edge. 2.1 I2S Some bits in the I2SMCLKCFG register do not function Description: The top 2 bits of the RXI and TXI bit fields in the I2SMCLKCFG register do not function (bits [29:28] of RXI and bits [13:12] of TXI).4 . Workaround: None. ensure that the CODEC is configured as the SCLK master.2 I2S SCLK signal is inverted in certain modes Description: When the I2S controller is operating as a receiver in SCLK Master mode. For the receiver. 13. when the controller is operating as a transmitter in SCLK Slave mode. The RXI and TXI fields contain the 10-bit integer input for the receive and transmit clock generator. the WS signal is latched on the rising edge of SCLK.Stellaris LM3S9B92 RevB1 Errata 13 13. 2011/Rev. and the I2S receive module is configured as the SCLK slave. there are two possible workarounds for this issue: 1. the data is launched on the rising edge of SCLK. Configure as I2S mode with DAC in Left-Justified audio format. In addition. respectively. 3. not the falling edge.

1UF C12 0.01UF RXIN 51 R1 12. PB5/EPI22 PE2/EPI24 PE3/EPI25 PD2/EPI20 PD3/EPI21 PB4/ADC10/EPI23 PB5/EPI22 PH6/EPI26 PH7/EPI27 J2 1.9 TXOP 43 R6 49. Change D3 type Add annotation for rework (2 places) Indicates factory-default jumper Drawing Title: Page Title: LM3S9B96 Developm 2 January 12. but limit cable lengths to 50 meters.3V R4 49. 3 4 5 6 14. Continue using the recommended circuit.9 C14 10pF C17 10pF 0.01UF 0.4K M+3.3V J1 +3.1UF +3.01UF 0.01UF 0.1UF R9 330 +3. See errata.1UF C15 2.4 Texas Instruments 27 B Micro.3V R60 10 12 11 3 5 4 7 6 8 2 1 9 10 +3. Recommended Center-Tap Connections PH2/EPI0S01 LED +3.3V GL GR YY+ NC GND 1CT:1 G+ G- PH0/EPI0S06 PH0/EPI06 PH1/EPI07 PH2/EPI01 PH3/EPI00 PB0/USBID JP2 B72590D0050H16 LED Ethernet 10/100baseT 1CT:1 TX+ 1 TX.3V +5V PG7/EPI31 PJ2/EPI18 PF5/EPI15 PF4/EPI12 2 PE1/EPI09 PE0/EPI08 PH5/EPI11 PH6/EPI26 +VBUS PD2/EPI20 There are two possible workarounds for this issue: PD3/EPI21 PD4/I2SRXSD PD5/I2SRXMCLK PD6 PD7 PF1/TXMCLK PC4/EPI02 PC5/EPI03 PC6/EPI04 D1 1 1 5 The microcontroller experiences some packet loss with Ethernet cables longer than 50 meters in G1 PB4/ADC10/EPI23 normal operating conditions. Add 10 Ω resistor to the center-tap of the transformer as shown in the figure.1 Ethernet Controller Ethernet receive packet corruption may occur when using optional auto-clock gating Description: Ethernet receive packets may be corrupted if the ACG bit in the Run-Mode Clock Configuration (RCC) register is set. Workaround: Do not set the ACG bit in the RCC register. 47 PF0 PF0 PF3/LED0 JP1 PB1/USBVBUS PF4/EPI12 2.2 26 27 28 29 30 31 34 35 80 79 78 77 25 24 23 22 74 75 95 96 6 5 2 1 19 18 36 14 87 39 50 52 53 54 55 64 XTLN XTALP OSC0 OSC1 17 16 48 49 PA0/U0RX PA1/U0TX PA2/SSI0CLK PA3/SSI0FSS PA4/SSI0RX PA5/SSI0TX PA6/USB0EPEN PA7/USB0PFLT PC0/TCK/SWCLK PC1/TMS/SWDIO PC2/TDI PC3/TDO/SWO PC4/EPI0S02 PC5/EPI0S03 PC6/EPI0S04 PC7/EPI0S05 PE0/EPI0S08 PE1/EPI0S09 PE2/EPI0S24 PE3/EPI0S25 PE4/ADC3 PE5/ADC2 PE6/ADC1 PE7/ADC0 PG0/EPI0S13 PG1/EPI0S14 PG7/EPI0S31 PJ0/EPI0S16 PJ1/EPI0S17 PJ2/EPI0S18 PJ3 PJ4 PJ5 PJ6 PJ7 RST_n EPI Expansion Connector Ethernet packet loss with cables longer than 50 meters Stellaris Microcontroller Description: PB0/USB0ID PB1/USB0VBUS PB2/CCP0 PB3 PB4/EPI0S23 PB5/EPI0S22 PB6/AVREF PB7/NMI PD0 PD1 PD2/EPI0S20 PD3/EPI0S21 PD4 PD5 PD6 PD7 66 67 72 65 92 91 90 89 PB0/USBID PB1/USBVBUS PB2/I2C0SCL PB3/I2C0SDA PE2/EPI24 PE3/EPI25 PD2/EPI20 PD3/EPI21 PB4/ADC10/EPI23 PB5/EPI22 PH6/EPI26 PH7/EPI27 1 2 3 4 Workaround: 10 11 12 13 97 98 99 100 61 60 59 42 41 86 85 84 PB6/TXSCK/AVREF PB7/NMI PD0/I2SRXSCK PD1/I2SRXWS +3.1UF C11 2.2UF U16 Required only for LM3S9B96 Rev B1.3V 3 C5 0.9 C13 10pF C16 10pF R8 330 C18 46 40 C19 37 R5 49.3V 0.9 R7 49.Stellaris LM3S9B92 RevB1 Errata 14 14.3V R61 10 +3. PF5/EPI15 DF12D-50DP LED2 PE2/EPI24 PE3/EPI25 PF1 PF2/LED1 PF3/LED0 PF4/EPI0S12 PF5/EPI0S15 PF2/LED1 LED1 1 2 PG0/EPI13 3 PG1/EPI14 4 PH7/EPI27 5 PJ0/EPI16 6 PD3/EPI21 7 PD2/EPI20 8 PJ6/EPI30 9 PJ5/EPI29 10 PJ4/EPI28 11 PJ3/EPI19 12 PE3/EPI25 13 PE2/EPI24 14 PB4/ADC10/EPI23 15 PB5/EPI22 16 PJ1/EPI17 17 PH0/EPI06 18 PH1/EPI07 19 PH2/EPI01 20 PH3/EPI00 21 PH4/EPI10 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 PC4/EPI02 PC5/EPI03 PC6/EPI04 PC7/EPI05 USB On-the-Go J3 USB M DD+ ID G VBUS G2 D2 2 B72590D0050H16 +VBUS JP3 OTG ID JP4 D5 1 2 PG1/EPI14 PG7/EPI31 PJ0/EPI16 PJ1/EPI17 PJ2/EPI18 PJ3/EPI19 PJ4/EPI28 PJ5/EPI29 PJ6/EPI30 PH1/EPI0S07 Figure 6. 2011/Rev. VOUT GND VIN EN PG 1 3 4 0 +5V 11 Mar 09 24 Mar 09 24 Mar 09 9 Apr 09 Initial Prototype Add Rev 0 rework changes. Silicon Revision Affected: B1 2 Fixed: Fixed in Rev C1. EPI connector Document Number: Size Date: DB-LM3S9 Sheet 4/13/2009 1 2 3 4 5 6 .6 7 8 TXON XTLN XTLP OSC0 OSC1 RXIP +3.2 RX+ 3 4 5 RX.3V C21 0.2UF History Revision Date Description U16 FAN2558S12X 5 C7 C9 0. 3. These resistors B72590D0050H160 should be replaced by a direct connection for silicon that has this item fixed.1UF 4 9 21 45 57 69 82 94 33 NC ERBIAS F VDDA GNDA GND GND GND GND GND GND GND VDD VDD VDD VDD LDO VDD25 VDD25 56 68 81 93 7 38 88 C6 C8 C10 0.

it instead only reports activity status (i. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1.4 . 15 15. Silicon Revision Affected: B1. 28 Texas Instruments January 12. C5 Fixed: Not yet fixed. 14. C1.e. 3. MAC interrupts are all functional and provide necessary operation.Stellaris LM3S9B92 RevB1 Errata Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. Workaround: None. Workaround: None. 14. C3.4 Encoding error in the Ethernet MAC LED Encoding (MACLED) register Description: Configuring the LED0 or LED1 field of the Ethernet MAC LED Encoding (MACLED) register to 0x8 should cause the corresponding LED to report a combined link + activity status. exactly the same as encoding 0x1).1 USB USB0ID and USB0VBUS signals are required to be connected regardless of mode Description: The DEVMODOTG bit in the USB General-Purpose Control and Status (USBGPCS) register does not function correctly. However. 2011/Rev. Ethernet PHY interrupts are not necessary for normal Ethernet operation.3 Ethernet PHY interrupts do not function correctly Description: The Ethernet PHY interrupts are not functional.

The compliance testing is performed using a 5 m USB certified cable between the host or device under test and the test SQiDD which is then connected to a USB compliant hub chain to the root hub.2 Latch-up may occur if power is applied to the VBUS pin but not to VDD Description: If power is applied to the VBUS pin but not to VDD.3. This resistor changes the USB VBUS signalling thresholds by approximately 8 mV which addresses the latch-up issue with no impact on USB performance. the rising edges of the USB D+/D. Workaround: Add a 100 Ω resistor (the tolerance is not critical) in series with the microcontroller's USB0VBUS signal. USB certification cannot be obtained because of this erratum. 15." is available from your local TI FAE.Stellaris LM3S9B92 RevB1 Errata Workaround: Connect the USB0VBUS input to VBUS in all modes.3.org website. "USB Far End Signal Integrity Test Results. 2011/Rev.3 USB compliance test issue: USB full-speed.6.signals begin to violate the lower right corner of the full-speed eye diagram defined by the USB specification. 15.1 Signal Integrity Test – Upstream Signal test (full speed) Compliance testing is based on the “USB Implementers Forum Full and Low Speed Electrical and Interoperability Compliance Test Procedure” Revision 1. connect the USB0ID pin to ground for Host mode operation and to VDD for Device mode operation using the DEVMOD bit in the USB General-Purpose Control and Status (USBGPCS) register. the device is unable to pass the following USB compliance tests: ■ USB Host Test B. This condition can occur if the microcontroller is unpowered and is connected as a USB device or OTG B.2 Full-speed Downstream Signal Quality Test ■ USB Device Test B. 3. In addition. Under compliance test conditions. January 12. far-end signal compliance tests fail with 5 m cable Description: While USB packet loss has not been observed.3 available from usb. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. the microcontroller may latch up and or draw excessive current. A full report on this issue.4 Texas Instruments 29 .3. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1.

setting the compare to a value of 1 or N-1 results in steady state signals instead of a PWM signal.4 USB compliance test issue: USB embedded host low-speed. C3 Fixed: Fixed in Rev C5. 16 16. Under nominal voltage and temperature conditions. The rising and falling edges of the USB D+/D. "USB Far End Signal Integrity Test Results. C1.4 ." is available from your local TI FAE. the Eye diagram compliance tests all pass with adequate margin across the voltage and temperature range of the part. C1. C3 Fixed: Fixed in Rev C5. This erratum applies only to systems defined as a USB embedded host that support low-speed devices.Stellaris LM3S9B92 RevB1 Errata Workaround: If a cable with a length of 1 m is used instead of a 5 m cable. 3. Workaround: None.3. if the user configures PWM0 as follows: ■ PWMENABLE = 0x00000001 30 Texas Instruments January 12.signals violate the lower half of the low-speed eye diagram defined by the USB specification.1 PWM PWM generation is incorrect with extreme duty cycles Description: If a PWM generator is configured for Count-Up/Down mode. Silicon Revision Affected: B1. For example. the device is unable to pass the following USB compliance test: ■ USB Host Test B.3 available from usb. A full report on this issue.3.org website. 2011/Rev. and the PWM Load (PWMnLOAD) register is set to a value N. far-end signal compliance tests fail Description: While USB packet loss has not been observed. Silicon Revision Affected: B1.1 Low-Speed Downstream Signal Quality Test USB Compliance testing is based on the “USB Implementers Forum Full and Low Speed Electrical and Interoperability Compliance Test Procedure” Revision 1. 15. USB device systems are full-speed only and thus are not affected by this erratum. USB embedded host and OTG systems that support full-speed devices only are not affected by this erratum. a cable of up to 3 m can be used and passes the eye diagram compliance tests.

the PWM0 output is a constant High value.Stellaris LM3S9B92 RevB1 Errata – PWM0 Enabled ■ PWM0CTL = 0x00000007 – Debug mode enabled – Count-Up/Down mode – Generator enabled ■ PWM0LOAD = 0x00000063 – Load is 99 (decimal). Workaround: None. so in Count-Up/Down mode the counter counts from zero to 99 and back down to zero (200 clocks per period) ■ PWM0GENA = 0x000000b0 – Output High when the counter matches comparator A while counting up – Output Low when the counter matches comparator A while counting down ■ PWM0DBCTL = 0x00000000 – Dead-band generator is disabled If the PWM0 Compare A (PWM0CMPA) value is set to 0x00000062 (N-1). 16. if the counter is cleared by setting the appropriate bit in the PWM Time Base Sync (PWMSYNC) register. the compare values must never be 1 or the PWMnLOAD value minus one (N-1). Instead. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1.2 Sync of PWM does not trigger "zero" action Description: If the PWM Generator Control (PWM0GENA) register has the ActZero field set to 0x2. the PWM0 output is a constant Low value. then the output is set to 0 when the counter reaches 0. and the output is not set to 0. PWM0 should output a 2-clock-cycle long High pulse. Silicon Revision Affected: B1 January 12. then the "zero" action is not triggered.4 Texas Instruments 31 . Instead. However. PWM0 should output a 2-clock-cycle long negative (Low) pulse. Workaround: User software must ensure that when using the PWM Count-Up/Down mode. as expected. 3. 2011/Rev. If the PWM0CMPA value is set to 0x00000001.

. WAKE. .Stellaris LM3S9B92 RevB1 Errata Fixed: Fixed in Rev C1. 17 17.) pin. as shown in Figure 8 on page 33. 16.3 PWM "zero" action occurs when the PWM module is disabled Description: The zero pulse may be asserted when the PWM module is disabled.4 . 3. The magnitude of the glitch may exceed the VIN in the maximum DC ratings table in the Electrical Characteristics chapter. 32 Texas Instruments January 12..1 Electrical Characteristics Momentarily exceeding VIN ratings on any pin can cause latch-up Description: To avoid latch-up. 16. The circuit shown in Figure 7 on page 33 typically has stray inductance and capacitance that can cause a voltage glitch when the switch transitions. enabling the PWM modules can't be synchronized.4 PWM Enable Update register bits do not function Description: The ENUPDn bits in the PWM Enable Update (PWMENUPD) register do not function. 2011/Rev. Figure 9 on page 33 shows an improved circuit that eliminates the glitch. The most common violation of the VIN electrical specification can occur when a mechanical switch or contact is connected directly to a GPIO or special function (RST. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. the maximum DC ratings of the part must be strictly enforced. Workaround: None. Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. As a result. Workaround: None.

January 12. 3. confirm that the voltage on the RST input has a curve similar to the one in Figure 10 on page 34. RS should be less than or equal to RPU/10. Excessive Undershoot Voltage on Reset 0V Voltage Time Workaround: Use a circuit as shown in Figure 9 on page 33. In this circuit. and that the VIN specification is not exceeded.Stellaris LM3S9B92 RevB1 Errata Figure 7. Incorrect Reset Circuitry VDD Stellaris® RPU RST Figure 8.4 Texas Instruments 33 .01 µF Figure 9. Typical values are: ■ RPU = 10 kΩ ■ RS = 470 Ω ■ C1 = 0. 2011/Rev. C1 should be matched to RPU to achieve a suitable tRC for the application. Recommended Reset Circuitry VDD Stellaris® RPU RST C1 RS After implementing the circuit shown in Figure 9 on page 33.

Normally VDDC is controlled by the part’s internal LDO voltage regulator. but does not solve it completely. During development. A recommended regulator is the TI TPS73101DBVR.4 . 2011/Rev. 3.2 Power-on event may disrupt operation Description: Incorrect power sequencing during power up can disrupt operation and potentially cause device failure. 34 Voltage Texas Instruments January 12. Workaround: VDDC must be applied approximately 50 µs before VDD. Recommended Voltage on Reset 0V Time Silicon Revision Affected: B1 Fixed: Fixed in Rev C1. 17.Stellaris LM3S9B92 RevB1 Errata Figure 10. the Flash memory should also be reprogrammed (using LMFlash or another programming tool) at least once a week. This fix mitigates the on-chip power issue. The workaround requires the addition of an external regulator (see Figure 11) to ensure that VDDC sequencing requirements are met (see Figure 12).

Configuration of External Regulator +5 V Existing 3. January 12.4 Texas Instruments 35 . Silicon Revision Affected: B1 Fixed: Fixed in Rev C1.3 V Regulator 3. Contact the Applications Support Team for the latest information.2 V LDO VDDC VDDC Figure 12. VDDC Sequencing Requirements VDD Default Power Sequence VDDC VDD Modified Power Sequence VDDC Detailed characterization is ongoing. 3.3 V VDD VDD VDD VDD New 1.2 V Regulator 1. 2011/Rev.Stellaris LM3S9B92 RevB1 Errata Figure 11.

ti.ti. TX 78746 http://www. Other names and brands may be claimed as the property of others.htm 36 Texas Instruments January 12.ext. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. Suite 350 Austin.com/sc/technical-support/product-information-centers.Stellaris LM3S9B92 RevB1 Errata Copyright © 2008-2011 Texas Instruments Incorporated All rights reserved. 2011/Rev.com/stellaris http://www-k. 3.4 . Texas Instruments Incorporated 108 Wild Basin. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited.