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Decoupling Capacitor Methodology

Taylor Shull
Applications Engineering Consultant Signal & Power Integrity

Goal of the PDN & Decoupling

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COMMON DECOUPLING MISTAKES

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com . Company Confidential 4 Your Initials.Decoupling Mistakes Using the IC Vendor recommendations Incorrect values Rule of thumb and guess work © 2010 Mentor Graphics Corp. Month Year www.mentor. Presentation Title.

Presentation Title.mentor. Company Confidential 5 Your Initials.Decoupling Mistakes Using the IC Vendor recommendations Incorrect values Rule of thumb and guess work The LRC of the board is not taken into account Every Plane is different Your responsible for knowing your plane parasitics © 2010 Mentor Graphics Corp.com . Month Year www.

Month Year www.Improper Decoupling Voltage Budget -10% +10% © 2010 Mentor Graphics Corp.com . Presentation Title.mentor. Company Confidential 6 Your Initials.

Company Confidential Your Initials.com . Month Year 7 www.A SIMPLE DECOUPLING STRATEGY © 2010 Mentor Graphics Corp. Presentation Title.mentor.

com .Decoupling Methodology Develop your Power Budget — DC Drop requirements — Target Impedance — Noise Budgets Develop and Analyze the stackup — Determine low & high frequency limits – First SRF & Exit Frequency – VRM Cross-over point — Locate power cavities Determine Capacitor’s — Quantities — Values — Locations © 2010 Mentor Graphics Corp. Company Confidential www.mentor.

mentor. The goal is to ensure an overall quiet plane — Noise Analysis — — — — DC Drop — — — — — — — 9 Pre-analysis: 20% Post-analysis: 80% DC Drop analysis exposes area’s of the plane that are narrow or places where voltage drop is excessive.com . Month Year www. Since it’s difficult to determine every little anti-pad and exact plane shape initially.Power Integrity Process Efforts Decoupling Capacitor Analysis — — — Pre-analysis: 80% Post-analysis: 20% Board / Plane outline that are close in pre analysis provide relatively accurate results Since the cap quantities & values are needed in the schematic. don’t try to do it. there is a lot of value for pre-analysis Pre-analysis: 60% Post-analysis: 40% The goal here is to find areas of the plane that may become noisy or have excessive overshoot/undershoot Noise analysis will not correlate to lab. stitching via quantities and overall design insight Determine what the max drop is for every rail There is a batch mode analysis that is rules driven © 2010 Mentor Graphics Corp. Presentation Title. Company Confidential Your Initials. the best place for this process is after the planes have been routed Pre-analysis can help determine needs for high current trace widths.

mentor. Presentation Title.com . Company Confidential Your Initials. Month Year 10 www.POWER BUDGETS © 2010 Mentor Graphics Corp.

mentor.2 5 0.5 2 5 5% 2. Month Year www. Company Confidential Your Initials.5% 5% 5% 22.9 2 0. Presentation Title.Power Budgets Calculate all Power needs DC Drop: — All significant parts — Max current – May be done holistically by part Target Impedance Schedule Vo lta ge (V) Pea kT ran sie nt Cu Ma rre xa nt llow (A) ed Rip ple Tar (% ge t ) Im pe da nce (m To tal Oh Po ms we ) r (w att s) — Max voltage drop — VRM’s — Voltage rail Voltage Net name 0-9vcc 1.9v 0.6 10 4.8 0.5 60 125 9 1.com .5 Excel table Decoupling & Noise (AC) — — — — 11 Voltage Allowed ripple Max Current Target impedance © 2010 Mentor Graphics Corp.9 1.8v 5v 0.

mentor.Target Impedance (Zt) Target Impedance is the first thing that must be calculated Understand the goals of the power plane (voltage rail) © 2010 Mentor Graphics Corp. Company Confidential 12 Your Initials. Month Year www. Presentation Title.com .

6 10 4.Sort the Target Impedances Lowest Target Impedance to Highest Target Impedance Schedule The lowest target impedance will be the hardest to decouple Location of the lower Zt in the stack up is critical Start your focus with the lowest Zt and work your way up Voltage Net name 0-9vcc 1. Company Confidential 13 Your Initials.8 0.9v 0.8v 5v 0. Presentation Title.mentor.5 .9 Excel table © 2010 Mentor Graphics Corp.9 1.5 60 125 9 1.2 5 0.5 2 5 5% 2. Month Year www.com Vo lta ge (V) Pea kT ran sie nt Cu Ma rre xa nt llow (A) ed Rip ple Tar (% ge t ) Im pe da nce (m To tal Oh Po ms we ) r (w att s) 2 0.5% 5% 5% 22.

STACKUP ANALYSIS AND DEVELOPMENT © 2010 Mentor Graphics Corp.mentor. Presentation Title. Month Year 14 www.com . Company Confidential Your Initials.

Presentation Title.mentor.Goal of the PDN & Decoupling Goal is to select the right amount and value of capacitors to bring the impedance profile below the target impedance.com . depending on IC package type The VRM (power supply chip) take care of power at the lower frequencies © 2010 Mentor Graphics Corp. Month Year www. The area in green is the area that can be affected by decoupling capacitors IC impedances take over anywhere between 300MHz and above. Company Confidential 15 Your Initials.

Determine proper power cavity design & stackup order Determine decoupling capacitor / PDN frequency limits (1st SRF) Finalize stackup Proper PDN Stackup Design Peak Current Determine Target Impedance Voltage Allowed Voltage Ripple 2. Import PCB Board Determine Board outline Mock Design up in HL-PI Linesim Determine Plane Pair Cavity height 3.com .mentor. Presentation Title.Power Integrity Stackup Process 1. Month Year www. Company Confidential 16 Your Initials. Determine Plane Pair location Simulate bare board Distribution Impedance Understand where Board SRF is Determine Plane Area limits Plane Pair & Location Complete © 2010 Mentor Graphics Corp.

Er = 3. Z0 = 83. Presentation Title.5 mils.3 0. Z0 = 65.35 mils.1 0. w idth = 6 mils 10 mils. TOP. Er = 4.3 0. Er = 4. Er = 4. Designer: tshull.35 mils.3 ohms. Er = 3.675 mils. VCC 10 mils.3 ohms. Er = 4.mentor. Z0 = 83.5 ohms. BOTTOM.3 1.675 mils.3 0. GND 10 mils.3 0.3 1.3 Caution on re-using old stackups — New designs may require new stackups © 2010 Mentor Graphics Corp. InnerSignal2.675 mils.5 ohms.4 mils 10 mils. HyperLynx LineSim V8. Z0 = 65.com . Company Confidential 17 Your Initials.675 mils.ffs. Er = 4. w idth = 6 mils 56. Month Year www. InnerSignal1. w idth = 6 mils 10 mils.Stackups: Start here Develop your stackup for — Power requirements — Signal Requirements — Mechanical Requirements — Cost Requirements Layer Stackup Design: Untitled. w idth = 6 mils 0.5 mils.

mentor. Month 2003 www.Stackups: Signal integrity Traces = target impedances Signal layers have symmetry Proper return paths near by Impedance planning for Differential pairs Via signal / paths analyzed Develop stackup: – Save in the modeling section – Re-use and apply for all development — Document the stackup in Hyperlynx — Save . Presentation Subject. Company Confidential 18 Initials.com .stk files for all to use — Define all Dielectric constants © 2010 Mentor Graphics Corp.

com .Stackups: Power Integrity Calculate Power Budgets — Target Impedances (Zt) identified — Lower Zt planes toward the edges (top & Bottom) Keep cavities close together — Cavity = pwr & gnd pair — Less than 4mill Analyze: — 1st SRF. Company Confidential 19 Initials. Presentation Subject.mentor. board size & Target Impedances © 2010 Mentor Graphics Corp. Month 2003 www.

PDN High Frequency Limits of the plane The first SRF is the first major dip at the bottom of the “V” This is the pure board impedance profile at a point of reference (we used 4 points in the previous example) Capacitors cannot decouple above the first SRF (The board inductance takes over) The 1st SRF will change based on different locations. Company Confidential 20 Your Initials. Month Year www. impedance © 2010 Mentor Graphics Corp.mentor. Presentation Title.com . stackup & area A Power Cavity Impedance Profile (z-parameter): freq vs.

Presentation Title.Build a Pre-Analysis board Pre PI Analysis basics — Enter the stackup details — Build out a rough estimate of the voltage plane — Something close is great to start with design Hyperlynx — Analyze different layers vs. Month Year www. Target Impedance — Understand cap locations — Find first SRF — Understand interplane capacitance & size trade-offs — Build out outline of board — Construct plane area © 2010 Mentor Graphics Corp.mentor.com . Company Confidential 21 Your Initials.

Find 1st SRF of the PDN First Self Resonant Frequency will determine the max frequency that a plane-pair can be decoupled — — — — — Defines the upper frequency limit Defines the values of the high-freq capacitors Determine the first Place down 2 to 6 IC’s as reference points Place 2 of them nearby each other (where the IC would be) for self and trans impedance values Analyze Decoupling – – – – – Pick the voltage plane & reference plane Enter your target impedance (or calculate it) Select “Distributed” Analysis Select all IC’s to be analyzed Custom – – All boxes unchecked This provides just a view of pure plane impedance Hyperlynx — – Save off the file as a name that makes sense — Results should show the first SRF (zparameter) This sets up everything for proper Capacitor selection Design — © 2010 Mentor Graphics Corp. Company Confidential 22 Your Initials.mentor. Presentation Title.com . Month Year www.

Adding in a VRM VRM’s are the IC’s that provide voltage to your plane Decoupling effects: — Reduce impedance profile at lower frequencies — Defines what needs to happen at the lower frequency decoupling caps DC Drop — This is the source of your Voltage at DC on this plane Hyperlynx: — Add in a VRM module to your plane © 2010 Mentor Graphics Corp. Company Confidential 23 Your Initials. Month Year www.mentor. Presentation Title.com .

Company Confidential 24 Your Initials.mentor. Month Year www.VRM Effects to the Impedance Profile Hyperlynx — Add VRM — Simulate just bare board w/ VRM — Distributed analysis – No Caps VRM reduces the profile at lower frequencies © 2010 Mentor Graphics Corp. Presentation Title.com .

Decoupling limits and capacitor boundaries © 2010 Mentor Graphics Corp. Presentation Title. Company Confidential 25 Your Initials.mentor.com . Month Year www.

Month 2003 www.Stackups: Vias & finalizing stackup Signal impedances Power plane placements Cavities defined Analyze: Via structures — Are signal via’s an issue to delay or quality? — Are decoupling cap & IC vias too inductive? — Stub Effects. backdrill. HDI. microvias. Company Confidential 26 Initials.mentor. blind & buried — Return path & stitching vias Can the stackup be manufactured? © 2010 Mentor Graphics Corp.com . Presentation Subject.

DECOUPLING CAPACITOR DEVELOPMENT © 2010 Mentor Graphics Corp. Month Year 27 www. Company Confidential Your Initials.com . Presentation Title.mentor.

com . Locations (approx) Decoupling Capacitor Development Determine Board outline Import PCB Board Mock Design up in HL-PI Linesim Simulate PDN LRC w/o Models Target PDN Impedance Plane SRF 2. Presentation Title. Review noise for area’s the plane needs capacitors Simulate for Lumped and Distributed Impedance Profiles Add in Capacitors Capacitor Models Determine cap Values & Quantities Capacitor Parts to schematics Schematics Determine Cap Locations Noise Analysis Analyze Noise for additional Cap locations Noise / Voltage Budget Decoupling Planning Complete © 2010 Mentor Graphics Corp. Quantity 2. Month Year www.PI: Power Integrity Process 1. Values 3. Company Confidential 28 Your Initials. Determine decoupling caps 1.mentor.

Presentation Title. Month Year www. VRM & Board all define the Power Distribution Network (PDN) © 2010 Mentor Graphics Corp. Company Confidential 29 Your Initials.com .mentor.Capacitor development needs Add Capacitors to reduce the board impedance profile — Different values & Quantities will be utilized — Higher freq caps need to be more localized to the power pins — Lower freq caps can be located anywhere The caps.

com . Company Confidential 30 Your Initials. Month Year www. Supposed to only have intrinsic ESL values Yellow (C4) — 0603 – Note double dip © 2010 Mentor Graphics Corp.Differences in Capacitor Models 4 identical values & mounting — 0.1uf — ESL’s were all a little different — Pick a model that doesn’t have mounting ESL (or one that has just intrinsic ESL) Red & Purple (C1 & C2) — Hyperlynx Calculated ESL’s (intrinsic) Green (C3) — 00603. Presentation Title.mentor.

and overall. via size.mentor. Company Confidential 31 Your Initials.com .Capacitor Mounting Capacitor mounting will affect your ESL. etc Use ESL calculator for guidelines on cap mounting location © 2010 Mentor Graphics Corp. Month Year www. your frequency response of your capacitor Analyzing basic mounting structures in Linesim is worth doing — Don’t over do it — Look for best design practices — Look for top or bottom based mounting — Use the mounting editor for a better understanding of complex mounting schemes — You may stitch all grounds together here — Explore via to via width. Presentation Title.

Month Year www. © 2010 Mentor Graphics Corp.mentor.com .Capacitor Mounting Effects Mounting (or any other type of inductance) will shift the waveform left Red line is generic capacitors (no board or mounting effects) Purple line is the same caps with their mounting inductances included. Company Confidential 32 Your Initials. Presentation Title.

PI: Adding decoupling caps The Approach — Start with small sets – Higher frequencies will require more caps – Lower Frequencies will require less caps – Target Impedance will determine how many and what quantities — Don’t select caps that go above the 1st SRF frequency — Take mounting into effect — Place small arrays (10 at a time?) Place caps in small groups — Copy and place groups to quickly add more.mentor.com . Analyze in Lumped analysis — Note the new SRF follows the calculated resonance of the caps we selected © 2010 Mentor Graphics Corp. Month Year www. Company Confidential 33 Your Initials. Presentation Title.

com . Presentation Title. Company Confidential 34 Your Initials.PI: Shaping the PDN Impedance Profile Yellow: Bare board Profile — Simulated in Distributed Target Zo: 90 mohms Red: Added 10x15nf caps — Simulated lumped Green: Added 10x1uf caps (Meets Target Impedance!) — Simulated lumped © 2010 Mentor Graphics Corp. Month Year www.mentor.

mentor. preferable pins that are close together — Profile looks good — Check Exit frequency — Check Decoupling cap mounting Surround IC’s with caps Dist analysis trans impedance Optimization — Could get by with less 1uf caps — Could try a few more higher freq caps Capacitor Mounting (Green) effects © 2010 Mentor Graphics Corp.PI: Shaping the PDN Impedance Profile Surround the IC pins with the caps Simulate Distributed — Look at the transimpedance (from one pin to another). Month Year www. Presentation Title.com . Company Confidential 35 Your Initials.

com . Presentation Title. Company Confidential Your Initials. Month Year 36 www.DECOUPLING CAPACITOR DEVELOPMENT REVIEW © 2010 Mentor Graphics Corp.mentor.

Company Confidential www.com .mentor.Decoupling Methodology Develop your Power Budget — DC Drop requirements — Target Impedance — Noise Budgets Develop and Analyze the stackup — Determine low & high frequency limits – First SRF & Exit Frequency – VRM Cross-over point — Locate power cavities Determine Capacitor — Quantities — Values — Locations © 2010 Mentor Graphics Corp.

com . Company Confidential 38 Your Initials.Goal of the PDN & Decoupling © 2010 Mentor Graphics Corp. Presentation Title.mentor. Month Year www.

Month 2003 www. Company Confidential 39 Initials. Presentation Subject.com .Thank you © 2010 Mentor Graphics Corp.mentor.