Timing Closure REL Script

V12.1

1- Hello, and welcome to this recorded e-learning module for designers trying to
understand FPGA timing closure. My name is Frank Nelson and I will be your
instructor for this module. This module is about how to gain timing closure.
While this topic is very large we are going to try to give you a high-level view of
how you can get your design to meet your timing needs.

2- If you would like to print out this slide presentation and a copy of the script,
please feel free to do so, now. You can pause the recording and download both
by clicking on the Attachments link you see in the upper right-hand corner of this
gui.

3- Regardless of your experience, this module will help you reduce your learning
curve and get productive faster.

<Read slide>

In fact, timing closure is such a large and important topic, that many customers
attend our live courses, just so they can get a handle on the topic. We
recommend that, you take the time to attend both of these courses, to learn all of
the critical design considerations you must make when targeting any FPGA
device.

4- After completing this module…

<read slide>

5- Well, this flow diagram pretty much describes how to gain timing closure. We are
going to touch on all of these topics (although briefly) in this REL. This diagram
shows you the things you must consider from the very beginning of the design
process (that starts at 1, obviously).

<click1> The first thing you have to understand is what is a reasonable

expectation of performance. This is strictly dependent on your chosen device
family and as you know they are each different. Each has its own dedicated set
of hardware resources and each has slightly different performance. Well, when
we talk about performance, we are really talking about how your internal logic
maps to CLB resources (that is to say LUTs and registers). For this sake of
discussion we are not concerned about Block RAMs, DSP slices, or dedicated
processors or gigabit transceivers. We are talking about how you get your
generic HDL code to map to LUTs and registers, and then meet your system
timing needs. To do that you first have to choose an appropriate device family
that can meet your performance needs.

<click2> The next topic is planning a good pin layout. This will directly affect
your input and output delays, so its important to follow some good guidelines.

<click3> HDL coding is perhaps the most important topic. And as you can see it
comes up very early in the design process (#3). This implies that the more effort
you put into building a better design will actually help you be successful much
sooner, rather than later.
<click4> Next is making appropriate timing constraints for your design. As you
may or may not know, the implementation tools use timing constraints to
determine if you are happy with your results. So in affect if you don’t write timing
constraints, you are telling the tools you don’t care about speed. This means that
writing effective timing constraints is pretty much always done by every user,
even if their performance expectations are modest.

<click5> Finally, before synthesizing, it is recommended that you choose a

“Design Strategy and Goal”. This is an automatic way to guide the
implementation and synthesis tools (that is the place and route tools and XST,
Xilinx’s synthesis tool). This will enable algorithms and software operations that
will help you meet your objective.

<click6> After considering all of these first few steps, most customers would
have a pretty good design that is not a waste of time to synthesize and
implement. Although many experienced customers might not wait this long (and
in fact skip some steps), we are guiding you through this process in the most
thorough way so that you understand our guidance correctly.

<click7> The first yellow triangle you see here is guiding you to review your
synthesis tools timing estimates and hopefully this will give you confidence that
you can meet your system timing goals. If you are way off, then we recommend
changing your code or at least changing your synthesis tool settings to hopefully
generate a more useful netlist.

<click8> Next you implement your design and use the static timing analyzer
utility to determine if you actually met your timing goals. Till this point the only
timing information you had was an estimate, since completing implementation is
required to know the design’s routing delays.

<click9> This may then require you to make a HDL coding change, make a path
specific constraint, evaluate the placement of your logic (change tool settings), or
make a design change (such as replicating a piece of logic to reduce a net delay).
But no matter what it is, if the timing analyzer tells you that you did not meet
timing, you will need to make a change. But if you met timing, your done and can
now generate a bitstream for programming and do other things.

<click10> Sometimes, to change the tool settings, designers use the

SmartXplorer or XploreAhead (a utility that is part of PlanAhead) to generate
different implementation results.

<click11> If that still does not help to meet timing, then users can consider
making area constraints with the PlanAhead software. PlanAhead makes it easy
to evaluate the placement of your logic and find a better place and route solution.

<click12> After that another implementation can be completed, and if you still
have not met timing, you can try running the tools differently…

<click13> Your last option is to migrate to a faster speed grade, larger device, or
faster device family, or…
 <click14> …re-architect your design. This might mean inserting additional
pipeline stages, or getting another designer to evaluate your HDL code and find
out why you have too many logic levels in your timing critical path.

So as you can see this is rather methodical, but the key is that the sooner you
evaluate your HDL code and optimize your design to use the FPGA dedicated
hardware resources, the sooner your device will meet timing.

6- <read slide>

7- After you have built your design you can get a timing estimate in a couple ways.
You can calculate a manual estimate, which is pretty good. You can synthesize a
timing estimate, which is pretty good, but will require you to code the design.

Or you can synthesize and run the design through Map to get a timing estimate.
This will require a little more time than the synthesis estimate.

<read slide>

8- <read slide>
9- <read slide>

10- So as I mentioned, PlanAhead and IO Planner are included with the ISE software.
The IO planner can be launched from the Project Navigator.

On this slide, we see the IO Planner has been opened and a design has been
loaded. Note that no logic is highlighted in the Device View, just pins. That’s
because the HDL code has yet to be associated or synthesized. However, the
pins have been assigned. We can see a number of pins color coded.

Other key features include a very elegant cross probing that allows you to see the
group of pins associated with each clock region. In this case, a clock region is
selected in the Device View and the associate pins become highlighted as well in
the Package View.

But what you must remember is that you are going to use this to evaluate the
routing delays from your source or destination logic to your pins.
11- This slide shows an example of a design that was layed out early. In this case, we
have selected a component and are showing all of its pin connections. As you
can see the green lines show the effective (not the actual routing) from a
component to its output pins.

The component (in yellow) is a considerably large component using about 20% of
the device resources.

So do you see anything wrong with this pin layout? Yep. Its bad. This is the case
because we have prohibitively long routes to/from the chosen IO pins.

It would have been better if the designer had anticipated placing the necessary IO
pins in associated groups, rather than spreading them across the die. To fix this,
it will take the tools a lot of implementation time and effort, but the better
solution would be to move the poorly assigned IO pins, which may or may not be
possible depending where you are in your design flow.

12- The next step, after improving your pin layout is to make certain that you have
used a good HDL coding style.

<read slide>

13- You should also know that using the dedicated hardware resources are critical to
obtaining peak performance.

<read slide>

14- Next, you should use timing constraints. On the left, in this example, we see a
design that has been implemented just with pin assignments. Note how the logic
is effectively grouped, by default. In this case the timing achieved was
reasonable.

But when we used global timing constraints, that is the Period, Offset In, and
Offset Out timing constraints, obtain a different layout that improved the speed
by 20%. And note that the pin assignments were maintained.

15- <read slide>

16- <read slide>

17- We also wanted to show you an easy way to set your XST synthesis and Place and
Route software options. Xilinx provides you with preset software options in the
Design Goals and Strategies.

This is an easy way to run both synthesis and implementation without knowing
how the software works. This is helpful is someone does not want to understand
the various options and when they can improve your timing results.

<read slide>
18- This slide is intended to point out the next phase of timing closure, which is the
most powerful synthesis options that are included with all of the high-end FPGA
design software.

<read slide>

While discussing these options is important, they are covered in the Synthesis
Options REL. We also describe the XST synthesis options which covers additional
synthesis utilities offered with the ISE software. We encourage you to learn more
about these options.

19- After synthesis, the implementation tools include several options that can
manipulate the place and route solution found. These options are covered as part
of the Design for Performance course, but the best ones are…

<read slide>

20- Understanding your system performance and locating any timing critical paths is
critical to deciding how to improve your timing. These timing reports are made
with the Timing Analyzer. The functions of this tool and the reports it generates
are covered as part of the Designing for Performance course.

But in this case, we wanted to point out a few things about a simple example…

<read slide>

By seeing the detail reported, it is easy to understand why this information is so

important, but understanding what you should do based on the report is also
critical. And that is one of the biggest reasons customers attend the Designing
for Performance course.

21- In this example, we see a simple path being reported.

<read slide>

22- Another software utility is the SmartXplorer included with the ISE software.

<read slide>

23- And here we can see the different iterations that could have been attempted.

<read slide>

24- Similarly, the PlanAhead software (that’s the area constraint tool that is included
with the ISE software) includes a similar functionality called XploreAhead.

<read slide>
25- As we work further through the timing closure flow diagram, I described earlier,
we have pretty much used all the easy solutions to gaining timing closure. Now if
we need more speed, we will have to get into making area constraints with
PlanAhead, which is actually not that hard. But the key is have you fixed your
code, have you synthesized as best you can, and have you given the
implementation tool options a chance to help you. If the answer is yes, and you
still need more speed, then you can consider making Area Constraints.

To learn more about Area Constraints, we encourage our customers to attend one
of our PlanAhead software courses. This will teach all of the basics and all of the
advanced features of PlanAhead. You could also listen to the Area Constraints
REL.

In this example…

<read slide>

26- This slide shows you an example use of PlanAhead. In this case, we see…

<read slide>

27- Now, I am not going to torment you with trying to review all of the details of
timing closure again. So if you are wondering how all the details of the slides I
just covered went into this, just replay this recording and note that I took you
through this whole diagram and described all of the possible solutions to gaining
timing closure.

Note that I did not describe the last option. Buying a faster part. Trust me, if you
get to this phase it is not usually fun. But it does happen, and I will just say that
we appreciate your business. The tools are not designed to recommend this
option, but I will say that if you have an idea of how fast your device can operate
and good HDL experience, then you should not have to do this. In the end, most
customers would say I made this mistake while I was learning.

28- In summary, <read slide>

29- Well, there are lots of places to learn more about FPGAs and they all start at
support.xilinx.com.

30- <read slide>

31- If you would like to see what other courses we offer, or what other Free RELs are
available go to the Xilinx Education link you see here.

But whatever you do, please take a second and let us know what you thought of
this REL. Just click on this icon on the next page and tell us what you think.
 My name is Frank Nelson. You have been listening to the Timing Closure REL
module. Thanks for listening.

32- (nothing said)