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A Multiple-valuedSingle-Electron SRAM by the PADOX Process
Hiroshi Inokawa, Akira Fujiwara, and Yasuo Takahashi hTT Basic Research Laboratories, hTT Corporation 3-1 Morinosato Wakamiya,Arsugi-shi,Kanagawa P&, 243-0198 Japan Email: inokawa@aecl.ntt.co.jp
Abstract
(b) 3-terminal Id-VgP

Multiple-valued static memory consisting of a single-electron transistor (SET) and a MOSFET is proposed. The.memory operation is verified by using transistors fabricated by the CMOScompatible pattemdependent oxidation (PADOX) process. The results indicate that a dramatic increase of CMOS memory density can be attained by the use of a SET with multiple-valued capability. Introduction singleelectron memories, such as nanocrystal memories [1-5], static memories feature a fast simple write operation and stable retention while the power is on. Thus we believe that the static type will have a wide range of applications different from those of the floating-gate type. Multiple-valued operation has been reported for floating-gate singleelectron memories [SI,but is not exclusive,to that type of memory. We propose here a multiple-valued static memory comprised of a single-electron transistor (SET) and a MOSFET and demonstrate its characteristics using transistors fabricated by the pattemdependent oxidation (PADOX) [6-81 the same silicon-on-insulator (SO0 on wafer. Principle of Operation Figure l(a) is a schematic of the proposed multiple-valued static memory. The source of a MOSFET with fixed gate bias V is connected to the , drain of a SET. As illusmted in Fig. l(b), the SET' drain current I,+increases and decreases periodically as a function of the gate voltage V , [9-111. However, the Id has such large dependence on the drain voltage V , that the peak current is almost proportional to the V, , and the valley current increases more rapidly when the Coulomb-blockade condition breaks. The MOSFET c o ~ e ~ t eto the SET eliminates this large V d , dependence of the SET characteristics by keeping the V , nearly constant around V=-V&. where V is the , threshold voltage of the MOSFET. This V- , ,V is set

In contrast to floating-gate

I-vcharacteristics of the combined SET-MOSFET circuit with
the SET gate shorted to the MOSFET drain.

Fig. 1 (a) Schematic of the proposed multiple-valued memory. (b) 3-terminal IcV, characteristics of a SET. (c) 2-terminal

Fig. 2 (a) A possible layout of the integrated SET and MOSFET. (b) Circuit diagram corresponding to the layout above. (c) Potential profile along the length of the narrow wr ie where, a SET is created [8].
low enough to sustain the Coulomb-blockade condition. By connecting the SET gate to the MOSFET drain, the multipeak negative differential resistance characteristics shown in Fig. l(c) are obtained as 2-terrninal I-V characteristics. If a constantarrent source I,, is connected to the SET-MOSFET circuit, the periodic nature of the I-V characteristics results in a number of stability points, and this enables the multiple-valued memory operation.

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0-7803-6520-8/01/$10.000 2001 IEEE.

7 aF. 12 pm and 90 nm. Since the areas outside the wire can easily be used for MOSFETs. 6. stability point b can be reached. characteristics of the SET (Fig. Figure 4 shows the subthreshold characteristics of a MOSFET fabricated on the same SO1wafer for drain voltages of 5 V and 10 mV. The SET is creiited in a narrow wire region by pattemdependent oxidation (PADOX) [6-81. .measured at 27 K. The gate length. Figure 5 shows the I-V characteristics of the combined SET-MOSFET circuit. 2(a) and (b).4 T 3 106 10-10 10-12 0. cell area and operating speed. This creates two tunnel barriers and an island sandwiched between them. characteristics of a MOSFET fabricated same SO1 wafer for the above SET. which are shown in Fig. 3 I. The device exhibits a sharp cutoff and a small shift due to the drain voltage. . 4 IcV. which are suitable for the proposed application. 3). sourcddrain capacitance. width and the gate oxide thickness are 14 pm.2. This is an amactive feature of the device.206 71 1 30 Y ' 4 p . Discussion Here we discuss the two major issues in large-scale' memory applications.respectively. Other stability points. PADOX is highly compatible with the CMOSprocess. l(r 10. % 20 T 10 n 2 3 4 I 5 v o 2 "1 3 "w 4 0 Fig. reflecting the 2. and tunnel resistance were calculated to be 0. Note that stability point f cannot be attained by this current-mode operation. . 2(c)] [8]. EXpehents Both the SET and the MOSFET were fabricated on a thin silicon-on-insulator (SOI) layer. From this figure and a Coulomb diamond plot. (3-terminal) characteristics of a SET fabricated by PADOX [ I M measured at 27 K and 10 mV of V .5 "9 e 2 2. Figure 3 shows the IKVp characteristics of a SET. 5) is lower than the previous one.5 1 1. The current increases and decreases periodically. respectively. Stability points (a-f) expected for f. 5 I-V (2-tenninal) characteristics of the proposed circuit measured at 1. stability to ~ points a-f should appear.5 nA are also shown. V the current load of 4.27 aF.5 nA is C O M W ~ ~ the circuit. and is not available in other negative-resistance device like resonant-tunnelingdiodes (RTDs) [12-14] Memory operation was confirmed by current sweep measurements. the voltage jumps when the current exceeds the second peak in the I-V characteristics (Fig.V. Periodic draincurrent peaks are clearly seen along with the effect of tunnel resistance modulation by the gate voltage. V. but in the middle of the wire the high compressive stress generated by the oxidation reduces the bandgap pig. i. 5).5 3 the 0 OR Fig. c-e. Note that these multipeak characteristics originate from the characteristics of a single SET. because the last peak in the I-V characteristics (Fig. If the current sweep is reversed at this moment. and the number of peaks is infinite in principle. gate capacitance. Direct access to any stability point can be made by the voltage-mode operation exemplified in FCEl memory devices [12]. which constitute a SET. Fig. can also be reached by choosing higher current-sweep reversal points. If a current source of 4. A possible layout and the corresponding circuit diagram of the integrated SET and MOSFET are shown in Figs. The quantum size effect raises the potential in the wire. and 80-220 kn.e.08 V o . If the current starts from stability point a and increases.

Thus this cell not only has a multiple-valued function. we considered two . any stability point can be directly reached by this voltage-mode operation. 5. with its gate and source shorted serves as a current source. 7(a)] is slow. 7 (a) A multiple-valued singleelectron SRAM cell with two depletion-mode MOSFETs (M1 and M 2 ) and one enhancement-mcde MOSFET (M3). and that associated with the SET is very small (-aF). where F is half the minimum wiring pitch. Table 1 Comparison of cell shuchues to improve the operating speed of the multiple-valuedSRAM. Multlplevalued Flash but is much smaller than an ordinary 6-transistor SRAM cell. and is quantized to a stability point after M3 is cut off.207 5 4 WL 1 - E3 s 2 1 BL 2 4 I (nN 6 8 Fig. (b) An example of the SRAM layout. It has an area of 31. WL wl storage capacttor 5 I I wl readout Trs. To improve the read-out speed. Figure 7(b) shows an example of the cell layout.Another depletion-mode MOSFET. As described in the previous section. If we assume the bit line capacitance of 100 f and F a voltage swing of one volt. The write-in speed of the proposed SRAM should be fast since the capacitance connected to the memory node (the crossing point of the three MOSFET terminals) is comparable to that of the ordinary SRAM. as can be understood from Fig. 6 I I I Destrudlve Nobdestrudlve Multlplevalued DRAM Figure 7(a) shows a four-transistor memory cell as a practical design. because the current that can be supplied to the without deseoying the memory status is bit line (BL) less than a nanoampere. A depletion-mode grounded-gate MOSFET M1 is used to sustain the SET drain voltage around the absolute threshold voltage of M1. M2. In write operation. and pass-transistor M3 controls the access to the cell. The read-out speed of the original cell [Fig.19. Fig. 6 current Sweep n m ~ ~ ~ m ofn B PrOPO~ The complianceof the curient source is 5 v. e the memory. the voltage applied to the bit line (BL) is transferred through M3. the read-out speed becomes of the order of 100 p.

T. Jpn. Appl. Japan. Baba.. h. M. Although this cell structure enables nondesauctive read-out. Appl.R. 1743 (1997). Tsai. Phys. [9] T. and K.. Waho and M. Fujiwara. Seabaugh. 22th Intl.. and of course the proposed SRAM does not require periodic refreshing. 1997) p. Len.1628 (1994). Kawaura.C. Kao. H. Isbikuro. Hashimoto. 41. Rev.A. Takahashi. Yano. [I31 T. Nagase. Ish& T. Phys. . Tiwari. 18. 13. Phys. Hartstein. Horiguchi. 35. F. J.425 (1999). 74.C. Phys. IEEE Trans. to the memory node as shown in the center column of Table 1. Murai. Yuan. Chan. 44’97 (1997). Sunamura. Intel Technology Journal. Murotani. Conclusions References [I] K. on Multiple-valued Logic (Sendai. Proc.By using a special read-out scheme. K. We have devised a novel multiple-valued SRAM comprised of a SET and a MOSFET.70. Mills. Discussion o the f SRAM cell design and its operating speed revealed that the area should be much smaller than. Another way to improve the speed is to add MOSFETs specialized for read+ut operation (See the right column of Table 1). Appl. [lo] J. Phys. since the area above the storage node is open in the proposed cell Fig.. H. 27th Intl.850 (1997). Murase. 37. S i K. Seki. Hanafi. K. Electron Devices. Len. Guo.A. Mod. Bauer. Len. the cell area is sacrificed considerably due to the increased number of transistors. Also note that the area penalty due to the storage capacitor is negligible. Kageshima.. E. [14] L. [8] S . 849 [121 A. Although the read-out operation is destructive. speed comparable to that of multiple-valued flash memory [16. Symp. and S. Kurihara. A. and verified the basic operation using devices fabricated by silicon-based PADOX technology. Namatsu.. M4 converts voltages at the memory node to current levels. and K. and H. [I71 A. Appl.J. If we add a storage capacitor C. Micheel. IEEE J. (1992).4399 (1992). Symp. and K. IEEE Trans. 40. [I51 T. J. c n be driven out to the BL in a short time. D. 72. Okuda and T.J. H. Y. Fazio. [4] Y. Atwood. 109 (1987). E.. Kurihara. Crabbe. 3257 (1998). Nakamura. H. Dolan. 68. Q4’97 (1997). Leobandung.1213 (1996). Hiramoto. Rev. Namatsu. 32. Solid-state Cir-cuirs. 7co)i. Phys. on Multble-Valued Logic (Nova Scotia. T. M. [3] L. Shiraishi. Y. [6] Y. Yukinori Ono for helpful discussions. Fazio and M . Nagase. and K. Takahashi. 43. The speed should be comparable to that of multiple-valued DRAM [15]. [ I l l M. K. Tucker. Takahashi. such as parallel charge sensing.-T. Saito. L29 (2001). 1377 (1996). Canada. [5] H. Electron Devices. Acknowledgments We thank Dr. J. H. Murase. and K. Yamamoto. 1992) p. E Rana. the data can be refreshed immediately by the sense amplifier.Y. Kastner. Jpn. [7] A.17] should be attainable. Iwadate. and B. The small voltage difference on the BL is read by a sense amplifier.. Y. and the speed should be comparable to that of conventional memories.479 (1992). [2] S . Phys.208 additional cell structures (Table 1). A.S. Jpn. Len..3555 (1999). Chou. and T. J. Intel Technology Journal. H. Fulton and G. 59. 64. Reaves. and T. Appl. Kobayashi. Murase. T. The results open up the possibility o f dramatically increasing the memory density of future scaled-down CMOS. [I61 G. the a charges stored in C. Appl.. IEEE Electron Device Le#. 38. Phys. Appl.F. Y. Sakamoto. and M5 controls the access from the sense line (SL). and technical advice in electrical measurements. Proc. Phys. K.