ASHAY S. CHITNIS, PH.D.

5362, Hollister Avenue, Apt # 16

Santa Barbara, CA 93111
Phone: 805-636-2031
Cell no: 805-696-8850
Curriculum Vitae
HONORS
WHO'S WHO IN WORLD
WHO'S WHO IN AMERICA
WHO'S WHO IN SCIENCE AND ENGINEERING
EDUCATION AND CREDENTIALS
Doctor of Electrical Engineering (3.85 GPA), December 2002 - The University of S
outh Carolina, Columbia, South Carolina.
Advisor: Prof. M. Asif Khan.
Bachelor in Electronics Engineering (3.91 GPA), August 1998- The University of P
une, Pune, India
PROFESSIONAL EXPERIENCE
Research Scientist, CREE Santa Barbara Technology Center (A division of Cree, I
nc) - 09/04-03/10
Conducted pioneering research in solid state lighting - leading to new products/
processes and/or advancement in performance of existing products;
* Assessment of Glass materials in Light Emitting Diodes (10/09 - 03/10).
Objective: Determine feasibility of glass materials in LED technology.
Accomplishments:
* Selected glass materials based on optical, thermal, mechanical properties.
* Glass encapsulation of LEDs - process development.
* Generated preliminary process specifications.
* Generated preliminary tool specifications.
* Submitted new concept designs of glass + phosphor composite LEDs.
* Generated 18 possible invention disclosures.
* Color control of white LEDs - (10/07- ongoing).
Objective: Produce/manufacture color controlled LEDs with target bin yield ] 90%
.
Accomplishment:
* Successfully generated empirical model for color point prediction of cool whi
te LEDs. Model served as a basis to generate advanced LED designs.
* Contract development at prospective vendor for - a) model validation, b) gene
rated tool/process specifications for manufacturability, c) Comprehensive perfor
mance testing of these advanced LED designs.
* Preliminary REL assessment and Failure Analysis of color controlled cool-whit
e LEDs.
* Several patents published and/or under review.
* White LED for solid state lighting - (9/06 - 05/08).
Project objective: Low cost white LED product development.
* Concept definition and demonstration at lab scale.
* Assisting in commercialization - cool white LEDs. Collaborated as and when re
quired for product ramp at Corporate Headquarters in Durham, NC. This involved p
rocess development, generating process/tool specifications, materials selection,
equipment selection, contract development at vendor-site, regular vendor intera
ction for equipment procurement, generating DOEs, personnel training.
* Several patents awarded and/or in process.
* Warm white LEDs process development.
* IC-LED - (06/05 - 09/06)
Project objective: Demonstrate wafer level packaging.
Accomplishment:
* Approach 1: Wafer level alignment bonding.
* Approach 2: Non-alignment wafer level technology.
* Conceptualized novel approaches to realize cost-effective IC LED. Successful
proof of concept demonstration.
* Low cost permanent wafer level bonding (10/04 - 05/05).
Objective: Develop low cost permanent wafer level bonding with thermally and ele
ctrically conducting bond medium.
* Theoretical modeling to asses stress in bonding of wafers of different materi
als.
* Successful demonstration of III-Nitride LED wafer bonding to low cost substra
tes.
* $350K equipment procurement for in-house process development - ramp effort in
ternally.
* Bonding qualification - SAM characterization, dicing.
* Wafer bonder equipment ownership and personnel training for various projects.
* 20+ patents published and/or under review. Includes equipment inventions.
ACADEMIC EXPERIENCE
Research Assistant Professor, Photonics/Microelectronics Laboratory (PML) - 04/0
4-08/04
In April 2004, I was promoted to the position of Research Assistant Professor. T
his involved joint collaboration with an Associate Professor from Department of
Mechanical Engineering, to establish a thermal packaging sub-team to address the
rmal issues in III-Nitride devices particularly deep UV emitters.
Post Doctoral Research Associate, Photonics/Microelectronics Laboratory (PML) 01
/03-03/04
Responsible for establishing and managing all aspects of the packaging laborator
y at PML, including,
selecting and purchasing equipment and providing exceptional leadership and guid
ance to maintain an environment focused on development and innovation of packagi
ng of III-Nitride optoelectronic and electronic devices.
Overall, my research work was focused on development of robust packaging technol
ogy to realize high-power III-Nitride Multi-Quantum-Well (MQW) based light emitt
ers for optical communications, solid-state lighting and several other key indus
trial and defense applications. With the self-established packaging technology,
was able to reduce the thermal resistance for a packaged deep UV LED to 30 (C/W
from 400 (C/W. With this approach, record power performance of UV LEDs with peak
emission at 340 nm, 325 nm and 280 nm was achieved. Some of the key areas of re
search include;
* Thermal Packaging of III-Nitride Deep UV Light Emitting Diodes.
* Development of high-power packaged UV LED modules for Non-Line-of-Sight (NLOS
) communication.
* Electrical, optical and thermal characterization of Deep UV LEDs.
* Generating scholarly material for reports and presentation.
* Further optimization of flip-chip technology in terms of reliability performa
nce.
Graduate Research Associate, PML 1998-2002
Performed comprehensive research in fabrication, characterization, and testing o
f III-Nitride microelectronic devices. Created simulations, analyzed data, and p
repared presentations and publications. Gained extensive LED characterization ex
perience.
* Performed Hall and Capacitance-Voltage measurements on III-Nitride epilayers
on sapphire and SiC substrates.
* Fabricated and tested blue LEDs and laser diodes on sapphire and SiC substrat
es.
* Developed low contact resistivity ohmic contacts to n and p type GaN.
* Fabricated world's first III-Nitride blue LED on silicon substrate.
* Developed electro and electro-less deposition of thick Au metallization for u
se in packaging applications.
* Designed and implemented gold stud bump thermo-compression and eutectic Au/Sn
flip-chip bonding technology for III-Nitride devices on sapphire substrates.
* Thermal management study of III-Nitride packaged devices.
* Established an inclusive laboratory for researching III-Nitride device packag
ing; initiated purchasing of $500,000 in equipment.
* Participated in developing low-temperature electro-optical characterization t
echnique used to study carrier transport and emission properties of III-Nitride
optoelectronic devices at elevated and cryo-temperatures.
* Non-polar LED fabrication process development.
INSTRUMENTATION AND SOFTWARE SKILLS
Proficient in the use of LED device simulator (APSYS). Polarization effects were
taken into account while simulating band-diagrams, emission spectra, current di
stribution, etc.
Study of light extraction from packaged Optoelectronic devices was carried out u
sing Lightools (Ray Tracing Simulator).
Proficient in Microsoft office tools, JMP.
Extensive clean-room fabrication experience. Broad knowledge of Mask Aligner, RI
E/PECVD, EBEAM metal deposition system, thermal evaporation system, and sputter
system.
Extensive expertise with semiconductor packaging equipments; semi-automatic dici
ng saw, semi-automatic flip-chip bonder, wire bonder, thermal evaporator, UV and
temperature cure ovens, etc.
AWARDS
* Doctoral Thesis: " Enhanced Performance of Ultra Violet Emitters by Flip-chip
Packaging
Technique."
* Nominated in Dean's List of Outstanding Graduate Students (2002)
* Poet of Merit Award (2002)
PUBLICATIONS
Principal author and co-author of numerous articles on semiconductor devices. Wo
rk has been published in international journals and referred to as a basis for f
urther research. Authored and co-authored research methodologies and findings in
many conference proceedings. Over 200 citations in reputed scientific journal.
PERSONAL INFORMATION
* US permanent resident.
* Fluent in English with basic knowledge of German.
* Hobbies include music, reading, poetry, and trekking.