Internship Report

(Carried out in Intel India Technology Pvt. Ltd. Bangalore)

ELECTRICAL VALIDATION FOR

DDR IO INTERFACE

submitted by

DIPAK PRAKASH BANKAR

Roll No.: 09VL07F

Under the Guidance of

Prof. M. S. Bhat Bhide Amruta A

NITK Surathkal Intel India Tech. Pvt. Ltd.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
NATIONAL INSTITUTE OF TECHNOLOGY
KARNATAKA,SURATHKAL
June-November, 2010
ELECTRICAL VALIDATION FOR DDR IO
INTERFACE

November 30, 2010

Contents

1 Imporatance Of Silicon Validation 12

1.1 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2 Classification Of Validation on Silicon . . . . . . . . . . . . . . . . 12
1.2.1 Pre-Silicon Validation . . . . . . . . . . . . . . . . . . . . 13
1.2.2 Post-Silicon Validation Methods . . . . . . . . . . . . . . . 13
1.2.3 Post-Silicon Validation Challenges . . . . . . . . . . . . . . 15
1.2.4 Necessity For Post-Silicon Validation. . . . . . . . . . . . . 15

2 Introduction To DUAL DATA RATE (DDR) Interface 16

2.1 DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.1 DDR1 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.2 DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.3 DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 DDR3 Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.1 Signal Functionality . . . . . . . . . . . . . . . . . . . . . 19
2.3 Comparision of Different DDR Generations . . . . . . . . . . . . . 20

3 Delay Locked Loop In Integrated Circuit 21

3.1 DLL Application In Integrated Circuit . . . . . . . . . . . . . . . . 21
3.2 DLL Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1 Voltage Controlled Delay Line (VCDL) . . . . . . . . . . . 24
3.2.2 Phase Detector (PD) . . . . . . . . . . . . . . . . . . . . . 24
3.2.3 Loop filter (LF) . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.4 Phase Interpolator (PI) . . . . . . . . . . . . . . . . . . . . 25
3.3 Characterization of Delay Locked Loop on Test chip . . . . . . . . 26
3.3.1 Delay per PI code . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.2 INL and DNL Analysis . . . . . . . . . . . . . . . . . . . . 26

4 Signal Integrity 28
4.1 Typical Silicon Problem . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1.1 Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1
 4.1.2 Frequency Dependent Loss . . . . . . . . . . . . . . . . . . 30
4.1.3 Need of proper Termination . . . . . . . . . . . . . . . . . 32
4.1.4 Reflections . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.5 Jitter in High Speed Serial Link . . . . . . . . . . . . . . . 33

5 JEDEC Specifications 34
5.1 Setup and Hold Times: . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.1 DQ/DQS: . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.2 Clk/Cntl: . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.3 Clk/Cmd: . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2 Clock Jitter: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3 Clock Vix: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.4 tDQSS (DQS latching rising transitions to associated clock edges) : 36

6 Tools Used For Post Silicon Validation 37

6.1 Validation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2 Measuring Instruments-Digital Storage Oscilloscope (DSO) . . . . 37
6.3 Probes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4 Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.4.1 Jitter Analysis Application Tool . . . . . . . . . . . . . . . 38
6.4.2 Memory Stress Tool . . . . . . . . . . . . . . . . . . . . . 38
6.4.3 INFINISCAN . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.4.4 ITP (In Target Probe) . . . . . . . . . . . . . . . . . . . . . 38
6.4.5 Internal Post processing tool . . . . . . . . . . . . . . . . . 39
6.4.6 Cadence-Allegro Physical Viewer . . . . . . . . . . . . . . 39

7 Results 40
7.1 DLL Characterization . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.1.1 Delay range and Step Size . . . . . . . . . . . . . . . . . . 40
7.1.2 Code Vs. Delay . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1.3 Integral Nonlinearity . . . . . . . . . . . . . . . . . . . . . 42
7.1.4 Differential Non Linearity. . . . . . . . . . . . . . . . . . . 42
7.2 Signal Integrity Validation . . . . . . . . . . . . . . . . . . . . . . 43
7.2.1 DQ-DQS setup and hold time measurement . . . . . . . . . 43
7.2.2 Clock-Command setup and hold time measurement . . . . . 45
7.2.3 Clock-Control setup and hold time measurement . . . . . . 47
7.2.4 TDQSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.2.5 Clock Vix . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.2.6 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2
List of Figures

2.1 DDR1 clocking Routing. . . . . . . . . . . . . . . . . . . . . . . . 17

2.2 DDR2 clocking Routing. . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 DDR3 clocking Routing. . . . . . . . . . . . . . . . . . . . . . . . 19

3.1 Phase Relationship between DQ-DQS. . . . . . . . . . . . . . . . . 22

3.2 Timing relation of clock and DQS. . . . . . . . . . . . . . . . . . . 22
3.3 DLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Delay Locked Loop Location in the IC. . . . . . . . . . . . . . . . 23
3.5 DLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 Phase Interpolator Design.. . . . . . . . . . . . . . . . . . . . . . . 25

4.1 Ideal and Real waveforms at receiving end. . . . . . . . . . . . . . 29

4.2 Reflections and Ground Bounce. . . . . . . . . . . . . . . . . . . . 29
4.3 Graph for Cross talk. . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.4 Crosstalk representation . . . . . . . . . . . . . . . . . . . . . . . . 31
4.5 Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.6 TDR impedance profile. . . . . . . . . . . . . . . . . . . . . . . . . 33
4.7 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1 Code Vs Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2 Integral Nonlinearity. . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.3 Differential Non Linearity. . . . . . . . . . . . . . . . . . . . . . . 42
7.4 Setup and Hold Time of DQ-DQS at 800 MHz. . . . . . . . . . . . 43
7.5 Setup and Hold Time of DQ-DQS at 1066 MHz. . . . . . . . . . . . 44
7.6 Setup and Hold Time of Clock-Command at 800 MHz. . . . . . . . 45
7.7 Setup and Hold Time of Clock-Command at 1066 MHz. . . . . . . 46
7.8 Setup and Hold Time of Clock-Control at 800 MHz. . . . . . . . . . 47
7.9 Setup and Hold Time of Clock-Control at 1066 MHz. . . . . . . . . 48
7.10 Tdqss(Clock-DQS) at 800 MHz. . . . . . . . . . . . . . . . . . . . 49
7.11 Tdqss(Clock-DQS) at 1066 MHz. . . . . . . . . . . . . . . . . . . 50
7.12 Clock Vix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.13 Clock Vix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3
7.14 Clock Jitter at 800MHz. . . . . . . . . . . . . . . . . . . . . . . . . 52
7.15 Clock Jitter at 1066MHz. . . . . . . . . . . . . . . . . . . . . . . . 52

4
SYNOPSIS

The latest trend in mobile computing and media computing platforms is to integrate
chipsets and micro processor in to a single chip solution or System-on-chip (SOC).
Increasing the performance of memory interfaces with minimal power is one of the
major challenges faced by chipset designs. As a result of this new DDR memory
standards like DDR2 and DDR3 evolved. This revolution leads to complex design
which imposes severe validation requirements, pre-silicon validation and postsili-
con validation. But complete system level verification of a complex SoC at 45nm
or below is not feasible in pre-silicon, in system at-speed post-silicon validation has
become an essential step in design in verification and optimization of the design
before the product is shipped to the customer. Using Bench setup with high-speed
oscilloscope and advanced probing techniques, the signal are captured and signal
integrity timing and quality checks are done. Debug is done by the appropriate soft-
ware tools and scripts specified by Intel.
Ten years ago a typical Intel chipset had about 50 thousand gates. Today, these core
platform components have as many as 4 million gates with increase in Intel desktop
processors transistor numbers from about 3 million to over 40 million As the pro-
cessor complexity has grown, the bugs found in Post-Silicon have increased. The
complexity of creating the conditions to cause the bugs to appear and the complexity
of debugging them have increased as well.
The project dealt with Post-Silicon validation by devising new ways of acquiring
the required signals under stress conditions across Process, Voltage and Tempera-
ture usually indicate as PVT corners. The complexity to acquire the required signals
increases with advancements in the process technology. The latest 45nm (nanome-
ter) technologies posses great challenge to the Post-Silicon validation team as the
new generation processors and chipsets have more functions, operate at faster fre-
quencies and must be compatible with far more hardware devices and software com-
ponents than ever before with even reduced number of observation pins.

5
Internship Details

Group: Atom SOC Development Group.

This group is a part of Intel Architecture Group(IAG) within Intel and works towards
the enabling of System on Chip for next generation mobile computers based on
Atom processor.

Team: HIP-EV-DDR
This team works on Electrical Validation of DDR Interface.

Role:
Masters Intern in HIP-EV-DDR team.

Responsibilities:
• To understand SOC architecture of mobile computer platforms.

• To study the DDR

• To understand and perform SIV on DDR

• To debug the validation issues

My Activities from June2010-November2010

• Studied Intel mobile Platform Architectures

• Ramped up on DDR Arch and configurations

• Ramped up on SIV and BDV procedures

6
• Worked on various debug activities

• Prepared ITP Scripts for debugging

• Automated procedures

• Received 2 recognition awards.

7
Company Profile

Intel Technology India Pvt. Ltd., Bangalore

About Intel
Intel pushes the boundaries of innovation so our work can make people’s lives more
exciting, fulfilling, and manageable. And our work never stops. We at Intel, never
stop looking for the next leap ahead in technology, education, culture, manufactur-
ing, and social responsibility. And we never stop striving to deliver solutions with
greater benefits for everyone. - INTEL

Founded in : 18th July, 1968

Number of employees : 83,500
Headquarters : Santa Clara, California, U.S.
Revenues : $35.127 billion
Assets : $53.095 billion
Fortune 500 ranking : 62
Stock Symbol : INTC

For past 40 years, Intel Corporation has developed technology enabling the com-
puter and Internet revolution that has changed the world. Founded in 1968 by
Robert Noyce and Gordon Moore to build semiconductor memory products, In-
tel introduced the world’s first microprocessor in 1971. Initial mission was to de-
sign and manufacture complex integrated circuits or silicon chips. The company

8
was first called NM Electronics and later became INTEL (for INTegrated ELectron-
ics). Today, Intel supplies the computing and communications industries with chips,
boards, systems, and software building blocks that are the ”ingredients” of comput-
ers, servers and networking and communications products. These products are used
by industry members to create advanced computing and communications systems.
Intel’s mission is to do a great job for our customers, employees, and stockholders
by being the pre-eminent building block supplier to the worldwide digital economy.
Intel, the world’s largest chip maker, is also a leading manufacturer of computer, net-
working, and communications products. Intel’s Web site serves geographies around
the globe localized content including product information, solutions and strategies,
programs, and support. Main areas of operation include Software and Hardware
Design and Development, Sales and Marketing, Venture Capital (a strategic in-
vestment initiative to support related technology enterprise) and Intel Innovation
in Education. Today, the Bangalore center has the distinction of housing a number
of mission critical projects for the company. Design of the next generation 32-bit
server and Intels 100% e-corporation initiative support are especially significant in
this regard. The design center, which houses the cream of the companys knowledge
workers, boasts of the highest software quality within Intel and has more than 250
invention disclosures and 335 patent filings (2004) to its credit. Donation, Spon-
sorship, and Grant Information, Intel receives many requests to help support very
worthy and important causes. In order to focus our giving and maximize the results
achieved, Intel established a set of criteria to guide donations, grants, and sponsor-
ship commitments. These criteria generally emphasize math and science education,
and technology literacy programs. Intel is also involved in community volunteering
program that coordinates a variety of employee volunteer programs in support of
education, environmental stewardship and safety, youth development, and commu-
nity service. Its goal is to be a great asset to the community; by being a responsible
corporate citizen. Some of the programs include blood donation camps, eco-watch
for improving the environment in our communities through energy conservation and
biodiversity projects, projects to build awareness in health, hygiene, nutrition, life
skills among underprivileged people and many more such activities.
• Architecture and Silicon Technology
In the age of Moore’s Law, Intel has delivered architecture and silicon tech-
nology with amazing transistor counts as many as two billion and growing.
With steady gains in energy efficient performance, and innovative uses of new
materials, our innovations continue to enable industry leading firsts.
• Micro-architectures
By continuously introducing new micro-architectures, Intel is creating great
leaps in energy efficient performance that enable new form factors at home,
in the office, and on the go.

9
• Silicon Technology
Transforming the way we experience computing at the silicon level, Intel is
developing new technologies that use innovative materials for ever smaller,
faster, and more energy efficient processors and processor technology.

• Multi-core Technology
Developing new levels of system intelligence, energy efficiency, and process-
ing performance, Intel multi-core technology enables improved computing
experiences while paving the way for the evolution of Tera-scale computing.

• Product Technologies
Intel’s leading edge notebook and desktop products range from processor to
processor technologies that are designed to work together to deliver a great
computing experience for home, business, and on the go. Discover your next
great technology experience with Intel inside.

• Revolutionary Mobile Technologies

As our future becomes increasingly connected, Intel is developing advanced
technologies that are enabling an entirely new line of laptops, Mobile Internet
Devices (MIDs), and more.

• Powering Business and High performance

Providing advanced manageability, security, and energy efficient performance,
Intel’s business optimized technologies address business challenges and op-
portunities and pushing the limits of computing, these technologies help en-
able high performance.

• Graphics and chipsets

Advanced graphics and chipset technologies from Intel help enable revolu-
tionary graphics in gaming and multimedia, while unleashing performance in
HD video and audio.

• I/O and accelerators

In collaboration with industry leaders, Intel is driving expansive I/O capabili-
ties with a range of breakthrough technologies.

• Manufacturing
Operating 24/7 in plants around the world, Intel’s manufacturing processes are
precision tuned to perform with maximum efficiency and quality to produce
fast, smart, and more energy efficient technologies.

• Fab
With 15 wafer fabrication plants (fabs) worldwide, Intel’s manufacturing pro-

10
 cesses employ exceptional flexibility on a global and virtual network. By de-
sign, these facilities are consistently sharing information to improve product
performance while further fine tuning the manufacturing process.

• Making performance packed microprocessors

From revolutionary hafnium based 45nm Intel process technology, to 32nm
and beyond, Intel’s state-of-the-art manufacturing processes are designed for
massive volumes delivering breakthrough transistor counts and performance
in smaller, more energy efficient packages.

• Reducing environmental impact

Environmental innovation is at the heart of Intel’s manufacturing processes.
Utilizing an extensive network of engineers, Intel is consistently developing
new technologies that deliver responsible product design along with sustain-
able and eco-focused programs.

11
Chapter 1

Imporatance Of Silicon Validation

To ensure leading performance, reliability and compatibility of processors and chipsets

incorporating millions of transistors with dozens of operating systems, hundreds of
platform components and thousands of hardware devices and software, component
and platform validation are absolutely pivotal in nature.

1.1 Problem Statement

Electrical issues are found too late in the validation cycle or after customer ship-
ments leading to costly delays or recalls.
• Products are often shipped with known signal abnormalities because no fail-
ures have been reported. A better method to assess risk is required.
• Platform design guide driven by simulations only, with no empirical data on
electrical margins.
• Customers can implement their platform in many different ways while adher-
ing to the recommended guidelines. Reliable operation must be ensured for
the whole solution space.
• Limited time available to complete validation. Otherwise will miss market
window.
The Post-Silicon validation plays crucial role in limited time frame.

1.2 Classification Of Validation on Silicon

Validation techniques may be broadly classified as Pre-Silicon and Post-Silicon val-
idation. Intels validation process begins during the first stages of component de-

12
sign and continues throughout as Pre-Silicon and Post-Silicon validation. With any
semiconductor device, Pre-Silicon design verification and Post-Silicon validation
are critical to the functional and operational quality of the finished product. This sit-
uation holds especially true for SOC (System-On-Chip) devices, in which a single
defect in any one function could necessitate a re spin. The term bug has been used to
describe design problems. There are three categories of bugs: functional, electrical,
and manufacturing/yield.
• Functional bugs, or logic bugs, are where the logic of a design is improperly
implemented.
• Electrical bugs are where the functional behavior of the circuit is correct, but
it fails to operate correctly in some part of the specified operating region (i.e.
at some voltage, temperature or frequency).
Manufacturing/yield bugs occur when a circuit is sensitive to some variable in the
manufacturing process and changes its operation as a result of manufacturing varia-
tions.

1.2.1 Pre-Silicon Validation

Pre-silicon validation is generally performed at a chip, multi-chip or system level.
The objective of pre-silicon validation is to verify the correctness and sufficiency of
the design. This approach typically requires modeling the complete system. The
model of the Design Under Test (DUT) may be Registry Transfer language (RTL),
and other components of the system may be behavioral or bus functional models.
The goal is to subject the DUT to real-world-like input stimuli.

1.2.2 Post-Silicon Validation Methods

Post-silicon validation and debug is the last step in the development of a semicon-
ductor integrated circuit which starts the moment first silicon gets into lab from
foundries [5]. Need for a powerful Post-Silicon methodology capable of detecting
problems with processors and chip sets becomes more pronounced as more com-
plex processors are designed and deployed. Different methodologies in Post-Silicon
validation are
1. System Validation (SV) for the Chipset and the CPU
2. Circuit Marginality Validation (CMV)
3. Analog Validation (AnV) or Electrical Validation (EV)
4. Platform Compatibility Validation (CV)

13
System Validation (SV) Methodology
The purpose of the System validation is to perform
• Chipset logic functionality validation.
• Validate and stress Chipset specific features using synthetic testing
validation board custom designed for SV use that include debug hooks for all inter-
faces. In addition it uses
• Special test cards designed specifically for SV tests
• AGP, PCI, USB, LPC, LAN, AC97
• Internally developed SV software running under DOS
• Memory Stress tests
• The two key benefits of this approach are:
• Controllability of tests and test coverage.
• Lack of dependency on internal or external drivers for O/S specific support.

Circuit Marginality Validation (CMV)

The purpose of the CMV is to
• Identify circuit marginalities in the CPU:
• Characterize the part beyond normal operating conditions (Shmoo Freq, Vcc,
temp).

Analog Validation (AnV) (OR) Electrical Validation (EV)

Analog or Electrical Validation is defined as test covering signal quality ,voltage and
clock timing margins, circuit characterization and buffer modeling added as a vali-
dation discipline executed in parallel with SV/CV and following similar milestones
and schedule. Its purpose is as follows,
• Develop and deploy methodology to maximize electrical analog test coverage
across the platform from pre production tape out and till customer.
• Verify that a motherboard designed according to the design guide will have
adequate electrical margin under worst case operating conditions on EV board
and at least one Original Equipment Manufacturer (OEM) board.

14
1.2.3 Post-Silicon Validation Challenges
The challenges faced in Post-Silicon validation are:

• Signal Integrity.

• Design Complexity.

• Power and thermal management.

These challenges have to be addressed thoroughly in Post-Silicon validation.

1.2.4 Necessity For Post-Silicon Validation.

The ever increasing System-On-Chip complexity, product time-to-market pressure
and the automotive industry stringent requirements have led to a new approach in
performing the validation activity at the post-silicon stage. The following activities
cannot be easily reproduced during RTL verification environment.

• Involve Physical Constraints, for example temperature variation or electrical

tests on the device.

• Involve system level integration where some components are not ready at Pre-
Silicon stage, for example system level stress test on the device where the test
involves multiple peripheral transactions which increase over a time.

• Combination of above, for example, running system level stress test on the
device at different temperature variation and verify if there is any flash data
retention issue observed.

One of the initial stages of validation is actual mechanical probing, where a very
small mechanical probe is used to measure a signal on the device. This is a very
time consuming and error-prone activity due to the incredibly small dimensions in-
volved in todays devices. It is possible to determine when voltage transitions occur
on a given node and provide oscilloscope traces of individual signals relative to each
other which are extremely useful in debugging timing-related failures. This is useful
to allow debug of either functional or electrical failures through the reconstruction
of signal waveforms on a device for further comparison to simulation and data col-
lected through scan and clock manipulation.

15
Chapter 2

Introduction To DUAL DATA RATE

(DDR) Interface

Double data rate (DDR) or double pumped, dual-pumped, and double transition is
used in applications where fast data transmission is needed, such as memory access
and first-in first-out (FIFO) memory structures. DDR stands for Dual Data Rate.
Dual data rate means data is sampled at both the rising and falling edge of the clock.
Its an interface that connects between MCH and system memory. In mobile it started
off from DDR, gave birth to DDR2 and now the latest DDR3. DDR uses both edges
of a clock to transmit data, which facilitates data transmission at twice the rate of
a Single Data Rate (SDR) architecture using the same clock speed by transferring
data on both rising and falling edges of the clock signal This method also reduces
the number of I/O pins required to transmit data.

2.1 DDR SDRAM

DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Mem-
ory) is a class of memory integrated circuit used in computers. It achieves nearly
twice the bandwidth of the preceding (Single Data Rate) SDRAM by double without
increasing the clock frequency.

2.1.1 DDR1 SDRAM

One of the most significant changes introduced in DDR1 was the step away from re-
lying on a central clock scheme used in SDR, to introducing a Source-Synchronous
or Strobing design.
The benefit of which was a requirement for higher performance. The introduc-
tion of a single-ended Data Strobe (DQS) architecture creates an additional tracking

16
layer between the Data and the centralised System Clock (CLK).
DDR1s Single-ended Data Strobe refers to the characteristic of having only a
single rising and falling signal wave. This single-ended Data Strobe is tracked by the
Data (DQ) for more effective signalling it has greater fundamental strength in toler-
ating Process-Voltage-Temperature (PVT) variation and issues caused by crosstalks,
echoes and signal reflection, which tend to distort the waveform or induce timing
inaccuracy.

Figure 2.1: DDR1 clocking Routing.

2.1.2 DDR2 SDRAM

DDR2 SDRAM or double-data-rate two uses same clock speed as DDR but operates
the external data bus twice as fast as DDR SDRAM achieved by improved bus sig-
naling, and by operating the memory cells at half the clock rate (one quarter of the
data transfer rate), rather than at the clock rate as in the original DDR but markedly
higher latency providing worse performance.

17
 Figure 2.2: DDR2 clocking Routing.

2.1.3 DDR3 SDRAM

DDR3 is the latest technology implemented in Dual Data Rate (DDR) memory
technology working at a lower voltage rail as compared to its predecessor DDR2.
Though DDR3 has a disadvantage of higher latencies when compared with DDR2,
the disadvantage is overcome by the fact that it offers higher bandwidth with re-
duced power consumption owing to the reduced operating voltage. DDR3 transfers
I/O data at eight times the data rate of the memory cells it contains and allows for
chip capacities of 512 megabits to 8 gigabits with a power consumption reduction of
30% compared to current commercial DDR2 modules due to DDR3’s 1.5 V supply
voltage, compared to DDR2’s 1.8 V or DDR’s 2.5 V with the effective clock rate of
8001600 MHz using both rising and falling edges of a 400800 MHz I/O clock. Only
DDR3 was used throughout the project for all platforms during validation process.

2.2 DDR3 Signal Groupings

The DDR memory consists of over 130 signals. These signals can be divided into
several signal groups. These groups are clocks, data, command/address, control and
power as follows:

• Clock: CK/CK#. Differential clock..

• Data group: DQ[0:63], DQS/DQS#[0:7], and DM[0:7].

18
 Figure 2.3: DDR3 clocking Routing.

• Control Group: CKE, ODT, Chip select CS#.

• Command Group: Address[0:15], Bank Address[0:1], WE#, RAS#,CAS#.

2.2.1 Signal Functionality

• CK/CK# :- The system clock inputs driven from the MPLL (memory PLL).
The setup and hold times for control and command is wrt clock.

• DQ[63:0] :- Single ended data lines.

• DQS/DQS# [7:0] :- Differential strobes required to latch the data. Each strobe
validate 7 data lines. Data setup and hold is wrt strobe.

• DM[7:0] :- Data mask, associated with one byte of data.

• CKE :- Clock enable for enabling/disabling memory clock, mainly used dur-
ing power down mode or the self refresh mode.

• CS :- Chip select signal. These are used for selecting the rank of the DIMM.

19
 • ODT :- On Die Termination. Used to improve signal integrity.( overshoot
undershoot etc). ODT is asserted for DQ, DM, DQS.

• A[15:0] :- Address lines. Row and Column address lines are multiplexed.

• BA[2:0] :-Bank address used to select a particular SDRAM internal banks.

• WE# :- Write enable asserted by the controller during memory write cycle.

• RAS#:- Row address strobe used to latch row address.

• CAS# :- Column address strobe used to latch column address.

2.3 Comparision of Different DDR Generations

Comparision between the different DDR generations is as in Table

Parameter DDR DDR2 DDR3

Frequency 200, 266,333, 400, 533,667, 800,1067,1333,
400MHz 800MHz 1600MHz
Voltage 2.5 V 1.8 V 1.5 V
Package TSOP BGA BGA
No. of pins 184 240 240
Strobes Single-ended Differential differential
DRAM density less than 1Gbit less than 4Gbit less than 8Gbit

20
Chapter 3

Delay Locked Loop In Integrated

Circuit

The Delay Locked Loop (DLL) is a feed back control system like Phase Locked
Loop (PLL) and is employed in high speed phase alignment circuits such as mi-
croprocessor and SDRAMs i.e., memory ICs in order to cancel the on-chip clock
amplication and buffering delays and improve the I/O timing margins. The supply
and substrate noise resulting from the switching of digital circuits affects the PLL
or DLL operation and results in output clock jitter which subtracts from the I/O tim-
ing margins. With shrinking margins for jitter, DLLs are becoming substitutes for
PLLs based on Voltage Controlled Oscillators (VCO) where no clock synthesis is
required.

3.1 DLL Application In Integrated Circuit

Consider the DQ-DQS phase-relationship management during write operation, DDR
SDRAMs rely on a data strobe signal (DQS) to achieve high-speed operation. DQS
is a non-continuous-running strobe used for clocking data on the DQ lines. It’s
transmitted externally along with the data signals (DQ) to ensure that they track
each other with temperature and voltage changes. The DDR SDRAM uses on-chip
Delay Locked Loops (DLLs) to output DQS relative to the corresponding DQS Fig-
ure /refwr. Due to Fly-by topology of DDR3, the Clock signal gets skewed, hence
accordingly DQS signal should be moved to satisfy the JEDEC specification known
as Tdqss Figure /refdqs.
When writing to the DRAM, the memory controller in the Field-Programmable
Gate Array (FPGA) must generate a DQS signal that’s center-aligned within the
DQ data signals. When reading from the memory device, the DQS coming into
the FPGA is edge-aligned with respect to the DQ signals. Upon receiving the DQS

21
 Figure 3.1: Phase Relationship between DQ-DQS.

Figure 3.2: Timing relation of clock and DQS.

signal, the memory controller must phase-shift it to be center-aligned with the DQ

signals. The amount of time that the DQS must be delayed is governed by board-
induced skew between the DQS and DQ groups, the resulting data-valid window at
the controller, and the sampling-window requirements at the controller input reg-
isters. This is one of the most challenging requirements for DRAM controller de-
signs. Memory-interface designers can employ one of several techniques to align
the DQS to the center of the data-valid window with on-chip Delay Locked Loops
(DLLs), or phase-locked loops (PLLs). DLL and PLL block diagrams are shown in
figure /refdll.
Delay Locked Loop (DLL) is a circuit that uses feedback to equalize the phase
of one clock signal with respect to a second clock signal that is derived from the
same clock source. DLL can be used to synchronize the phase of the clock that is
distributed by the clock tree in an Integrated Circuit (IC) to the clock inputs of all
flip-flips within the core of the IC (i.e., the buffered leaf node outputs of the clock

22
 Figure 3.3: DLL Block Diagram.

tree), with the phase of the clock signal (CLK IN) just inside the clock input pad as
shown in figure /refdllic.

Figure 3.4: Delay Locked Loop Location in the IC.

The clock signal from the clock input pad is usually the most convenient clock
for latching data signals just inside the data input pads. Without active synchroniza-
tion, the phase of the two clocks will likely be different due to the uncertain and IC
specific propagation delay through the clock tree buffer network. The role of the
DLL is to adjust the output tap of a programmable digital delay line at the root of
the clock tree so that the phase at the leaf nodes of within ASIC are synchronized at
all the flip-flip inputs.

23
3.2 DLL Functional Blocks
DLL block diagram is shown in figure /refbd.

Figure 3.5: DLL Block Diagram.

Delay-Locked Loop functional blocks consists of three major components: A

controlled delay line, a phase detector and a low-pass filter.

3.2.1 Voltage Controlled Delay Line (VCDL)

The controlled delay line can be either voltage controlled, in which case it will be
called a Voltage Controlled Delay Line (VCDL), or Current Controlled Delay Line
(CCDL), in which case it will be called Current Controlled Delay Line. The delay
line delays the input signal by an amount D that it is dependent on the control voltage
or current.

3.2.2 Phase Detector (PD)

Compares the phase of the signal at the input and output of the VCDL. Depending
on the type, produces an error signal that is proportional to the phase difference
between the input and output phases, it just gives an indication on the sign of the
phase error (bang-bang detector).

3.2.3 Loop filter (LF)

Eliminates the high frequency components of the error signal: It can be implemented
as:

• An RC low-pass filter

• An active low pass filter

24
 • A charge-pump and a capacitor

The charge-pump capacitor is the most favored for integrated implementations

due to its simple implementation, its shows almost ideal behavior that its DC gain is
infinite results in zero phase error when the loop is locked. The behavior of the full
loop is that the phase detector measures the phase difference between the delay line
input and output creating an error signal. The error signal is then low pass filtered
and used to control the delay line propagation delay. If the output signal was early
then the filtered error signal should change in such a direction as to increase the
delay. Vice versa, a late phase at the output must result in a filtered error signal such
that the delay line propagation delay decreases.

3.2.4 Phase Interpolator (PI)

Phase Interpolator design is shown in figure /refpi.

Figure 3.6: Phase Interpolator Design..

PI design is a dual input differential buffer which uses the same symmetric loads
as all the core. The current sources of the two differential pairs are thermometer
controlled elements. The thermometer codes are generated by a X bit long up/down
shift register which is controlled by the peripheral loop FSM. By changing the ther-
mometer code, the FSM adjusts in a complementary fashion the currents of the two
input differential pairs resulting in a mixing of the two input clock phases.

25
3.3 Characterization of Delay Locked Loop on Test
chip
3.3.1 Delay per PI code
To find delay per PI, consider the below calculation The code given to Finite State
Machine (FSM) when incremented by one produces a delay of (1/8)* 45 degrees,
in other words it produces T/64 seconds of delay per PI where T is the Time period
of DIMM clock. For 800 MHz DIMM frequency, time period (T) is (1/800) which
equals 1.25 ms Thus the delay per PI code should be 1.25 ms / 64 equal to 19.53
ps (pico seconds).That is each code increment delays the DIMM clock by 19.53
pico seconds As per above case the output clock will be delayed by 19.53 pico
seconds with respect to input reference clock (RefCLK). Similarly for 1066 and
1333 MHz the delay per PI code equals 14.65 ps and 11.7 ps respectively. During the
DLL validation process, the DLLs are also checked for per code delay consistency.
Because of the earlier mentioned capacitive capacitance of the differential pair input
transistors in the Phase Interpolators, delay produced in non linear with code.

3.3.2 INL and DNL Analysis

Integral non-linearity and Differential Non-linearity are two secondary parameters.

Integral Non-Linearity (INL)

Integral non-linearity (INL) is a term describing the maximum deviation between
the ideal output of a Digital to Analog Convertor (DAC) and the actual output level.
The term is often used as an important specification for measuring error in a DAC.
The transfer function of a DAC should ideally be a line and the INL measurement
depends on the line selected. Two often used lines are the best fit line, which is the
line that minimizes the INL result and the endpoint line which is a line that passes
through the points on the transfer function corresponding to the lowest and highest
input code. In all cases, the INL is the maximum distance between the ideal line
selected and the actual transfer function.

Differential Non-Linearity DNL

A Differential Non-linearity (DNL) is a term describing the deviation between two
adjacent points (two adjacent PI codes). The term also used as an important spec-
ification for measuring error in a Digital-to-analog converter (DAC), the accuracy
of a DAC is mainly determined by this specification. Ideally, any two adjacent dig-
ital codes correspond to output analog voltages that are exactly one LSB apart or

26
one code apart. Differential non-linearity is a measure of the worst case deviation
from the ideal one code step. The INL and DNL deviations from ideal case are also
computed for all modules across all PVT corners.

27
Chapter 4

Signal Integrity

The term Signal Integrity (SI) addresses two concerns in the electrical design aspects
the timing and the quality of the signal. Does the signal reach its destination when
it is supposed to? And also, when it gets there, is it in good condition? The goal
of signal integrity analysis is to ensure reliable high-speed data transmission. In a
digital system, a signal is transmitted from one component to another in the form
of logic 1 or 0, which is actually at certain reference voltage levels. At the input
gate of a receiver, voltage above the reference value Vih is considered as logic high,
while voltage below the reference value Vil is considered as logic low shows the
ideal voltage waveform in the perfect logic world, whereas figure 4.2 shows how
signal will look like in a real system.
More complex data, composed of a string of bit 1 and 0s, are actually continuous
voltage waveforms. The receiving component needs to sample the waveform in
order to obtain the binary encoded information. The data sampling process is usually
triggered by the rising edge or the falling edge of a clock signal. It is clear from the
diagram that the data must arrive at the receiving gate on time and settle down to
a non-ambiguous logic state when the receiving component starts to latch in. Any
delay of the data or distortion of the data waveform will result in a failure of the
data transmission. Imagine if the signal waveform in Figure 4.2 exhibits excessive
ringing into the logic gray zone while the sampling occurs, then the logic level
cannot be reliably detected.

4.1 Typical Silicon Problem

Timing is everything in a high-speed system. Signal timing depends on the delay
caused by the physical length that the signal must propagate. It also depends on the
shape of the waveform when the threshold is reached. Signal waveform distortions
can be caused by different mechanisms. But there are three mostly concerned noise

28
 Figure 4.1: Ideal and Real waveforms at receiving end.

problems:

• Reflection Noise
Due to impedance mismatch, stubs, vias and other interconnect discontinu-
ities.

• Crosstalk Noise
Due to electromagnetic coupling between signal traces and vias.

• Power/Ground Noise
Due to parasitics of the power/ground delivery system during drivers simul-
taneous switching output (SSO). It is sometimes also called Ground Bounce,
Delta-I Noise or Simultaneous Switching Noise (SSN).

Figure 4.2: Reflections and Ground Bounce.

Besides these three kinds of SI problems, there are other Electromagnetic Com-
patibility or Electromagnetic Interference (EMC/EMI) problems that may contribute

29
to the signal waveform distortions. When SI problems happen and the system noise
margin requirements are not satisfied the input to a switching receiver makes an
inflection below Vih minimum or above Vil maximum; the input to a quiet receiver
rises above Vil maximum or falls below Vih minimum; power/ground voltage fluc-
tuations disturb the data in the latch, then logic error, data drop, false switching, or
even system failure may occur. These types of noise faults are extremely difficult to
diagnose and solve after the system is built or prototyped. Understanding and solv-
ing these problems before they occur will eliminate having to deal with them further
into the project cycle, and will in turn cut down the development cycle and reduce
the cost. In the later part of this chapter, we will have further investigations on the
physical behavior of these noise phenomena, their causes, their electrical models for
analysis and simulation, and the ways to avoid them.

4.1.1 Crosstalk
Crosstalk is the coupling of energy from one line to another via:

• Mutual capacitance (electric field)

• Mutual inductance (magnetic field)

Crosstalk is caused by a transformation of energy from one signal trace to an-

other, resulting in a change in the voltage measured at the receivers pins. Backward
crosstalk appears at the driver, and can affect signal integrity by forcing the driver
out of its normal I/V operating area. Backward crosstalk is more important when
impedance discontinuities occur near the driver end of the interconnect. Forward
crosstalk appears at the receiver and is manifested as a change in the effective r of
the dielectric.

• The mutual inductance will induce current on the victim line opposite of the
driving current (Lenzs Law).

• The mutual capacitance will pass current through the mutual capacitance that
flows in both directions on the victim line.

4.1.2 Frequency Dependent Loss

Frequency Dependent Loss is due to primarily two factors: copper loss and dielectric
loss. Signal available at the receiver is often described in terms of eye opening.

30
 Figure 4.3: Graph for Cross talk.

Figure 4.4: Crosstalk representation .

Copper Loss:
Copper has resistive loss as does any conductor. At high frequencies, the internal
inductance of conductors pushes the current to the outer surfaces. This effect is
called skin effect.
This phenomenon decreases the effective area available for current flow and so
increases the effective resistance. It is as is there is only a thin layer on the surface
of the conductor that is involved in high-frequency current flow, and the thickness
of this layer is called skin depth.

Dielectric Loss:
In dielectric the relative dielectric constant is thought to be due to such things as
the physical distortion of molecules, the reorientation of molecules, the changing

31
of the scope of electron orbits, etc. each case has a stimulus and response. When
calculating response of the system to fields through dielectric, the imaginary part of
the dielectric constant shows up as a loss.

4.1.3 Need of proper Termination

• Termination keeps energy from bouncing around
• In current-mode signaling voltage is developed across the terminator
• Quality of termination can limit system performance.

Figure 4.5: Terminations.

4.1.4 Reflections
The mismatches between transmission line segments are caused by manufacturing
tolerances, connectors, vias and other factors. Reflections adversely affect signal
integrity in two ways:
• Wave reflections cause less energy to propagate forward to the receiver.
• Wave reflections can cause the equivalent of multi-path distortion, whereby
the reflected signal arrives at the receiver some time later than the main signal.
Sources of Reflections: Z - Discontinuities
• PCB Zs
• Connector Zs
• Vias (through) Zs
• Package Zs
• Termination Zs
The best way to control wave reflections is to minimize impedance discontinu-
ities between the driver and receiver.

32
 Figure 4.6: TDR impedance profile.

4.1.5 Jitter in High Speed Serial Link

Jitter is defined as the short term variations of digital signal significant instants from
their ideal positions in time. In other words ideally, an edge should always land at
the same position on the time axis, but in the real world, the edge is sometimes a
little early or sometimes a little late as shown in Figure 4.7. In a digital signal the
significant instances are the transition points. When data rate increase, the Jitter
magnitude and signal amplitude noise need to decrease proportionally in order to
maintain an acceptable BER. At the data rates in excess of 1 Gbps, a slight increase
in jitter or amplitude noise will have a much more pronounced effect on the BER
than at lower data rates.

Figure 4.7: Jitter.

33
Chapter 5

JEDEC Specifications

JEDEC Solid State Technology Association, formerly known as Joint Electron De-
vice Engineering Council (JEDEC) or Joint Electron Device Engineering Councils,
is the semiconductor engineering standardization body of the Electronic Industries
Alliance (EIA), a trade association that represents all areas of the electronics in-
dustry in the United States. JEDEC is the leading developer of standards for the
solid-state industry. Almost 3,300 participants, appointed by some 295 companies
work together in 50 JEDEC committees to meet the needs of every segment of the
industry, manufacturers and consumers alike. The publications and standards that
they generate are accepted throughout the world. All JEDEC standards are avail-
able online, at no charge. JEDEC was founded in 1958 as a joint activity between
EIA and NEMA to develop standards for semiconductor devices. This early work
began as a part numbering system for devices which became quite popular in the
’60s. For example, the 1N4001 rectifier diode and 2N2222 transistor part numbers
came from JEDEC. These part numbers are still popular today. JEDEC later devel-
oped a numbering system for integrated circuits, but this did not gain acceptance
in the semiconductor industry. JEDEC’s adoption of open industry standards (i.e.,
standards that permit any and all interested companies to freely manufacture in com-
pliance with adopted standards) serves several vital functions for the advancement
of electronic technologies. First and foremost, such standards allow for interoper-
ability between different electrical components. JEDEC standards do not protect
members from normal patent obligations. The designated representatives of JEDEC
member companies are required to disclose patents and patent applications of which
they personally are aware (assuming that this information is not considered propri-
etary). JEDEC patent policy requires that standards found to contain patents, whose
owners will not sign a standard JEDEC patent letter, be withdrawn. Thus the penalty
for a failure to disclose patents is retraction of the standard. Typically, standards will
not be adopted to cover technology that will be subject to patent protection. In rare
circumstances, standards covered by a patent may be adopted, but only on the under-

34
standing that the patent owner will not enforce such patent rights or, at a minimum,
that the patent owner will provide a reasonable and non-discriminatory license to
the patented technology.

JEDEC Specs for Various DDR2/3 Signal Groups:

5.1 Setup and Hold Times:
Setup Time: It is the time interval for which the input signal must be stable prior
to the sampling event of the clock for the input signal to be recognized correctly.
Hold Time: It is the minimum time interval for which the input signal must be
stable following the sampling event of the clock for the input signal to be recognized
correctly.

5.1.1 DQ/DQS:

Setup tDS min (ps) Hold tDH min(ps)

DDR2-667 100 175
DDR2-800 50 125
DDR3-800 75 150
DDR3-1066 25 100

5.1.2 Clk/Cntl:

Setup tIS min (ps) Hold tIH min(ps)

DDR2-667 200 275
DDR2-800 175 250
DDR3-800 200 275
DDR3-1066 125 200

5.1.3 Clk/Cmd:

Setup tIS min (ps) Hold tIH min(ps)

DDR2-667 200 275
DDR2-800 175 250
DDR3-800 200 275
DDR3-1066 125 200

35
5.2 Clock Jitter:

Tjit- per Tjit - cc terr (2per) terr (5per)

DDR2-667 125ps 250ps 175ps 250ps
DDR2-800 100ps 200ps 150ps 200ps
DDR3 - 800 100ps 200ps 150ps 200ps
DDR31066 90ps 180ps 132ps 188ps

5.3 Clock Vix:

Min Max
DDR2 0.5xVDD - 0.175 0.5xVDD + 0.175
DDR3 0.5xVDD - 0.175 0.5xVDD + 0.175

5.4 tDQSS (DQS latching rising transitions to associ-

ated clock edges) :

Min Max
DDR2-667 -0.25 times of tCK (avg) 0.25 times of tCK (avg)
DDR2-800 -0.25 times of tCK (avg) 0.25 times of tCK (avg)
DDR3-800 -0.25 times of tCK (avg) 0.25 times of tCK (avg)
DDR3-1066 -0.25 times of tCK (avg) 0.25 times of tCK (avg)

36
Chapter 6

Tools Used For Post Silicon

Validation

6.1 Validation Board

Validation board is the motherboard which is assembled for testing. Three vari-
ants of the boards is manufactured by altering the track impedance namely (a) Hi-
impedence (b) Low-impedence and (c) Typical. These boards are used for evaluating
the chipsets.

6.2 Measuring Instruments-Digital Storage Oscillo-

scope (DSO)
An instrument that digitizes electrical signals and post processes the data to con-
struct a displayed waveform. To solve signal integrity problems, digital designers
need to step into the analog domain. And to take that step, they need tools that can
show them how digital and analog signals interact. Digital errors often have their
roots in analog signal integrity problems. To track down the cause of the digital
fault, its often necessary to turn to an oscilloscope, which can display waveform de-
tails, edges and noise; can detect and display transients; and can help you precisely
measure timing relationships such as setup and hold times.

6.3 Probes:
Differential probes are required to measure the Differential signals and single ended
signals as well. These probes should be chosen according to the BW requirement.

37
6.4 Software Tools
6.4.1 Jitter Analysis Application Tool
The Jitter measurement application consists of two products: Jitter Analysis Ad-
vanced and Jitter Analysis Essentials. These products are applications that enhance
basic capabilities of some Windows-based oscilloscopes from Agilent. These jitter
analysis applications include the following features:
• Select and configure multiple measurements on more than one waveform
• Display statistical results for up to six measurements
• Perform random and deterministic jitter analysis including
• Show results as plots
• Save statistical results to a data log file
• Save individual data points to a measurement results file
• Save the worst case waveforms to .wfm files

6.4.2 Memory Stress Tool

Memory Stress Tool is used to stress the primary memory. Tool, randomly write the
data to the memory and read it back. If it finds any mismatch in the data that has
been written and the data received back it reports memory error which can be seen
in log file generated by the tool.

6.4.3 INFINISCAN
With the help of infiniscan zones on the oscilloscope can be defined such that the
signal waveforms crossing that particular zone can be completely eliminated from
the screen. This helps in generating write eye, read signals from the screen can be
eliminated so that their appearance should not disturb write eye.

6.4.4 ITP (In Target Probe)

This ITP tool is used to program the register content of the GMCH. This is connected
to the Customer reference board through XDP port. The memory register content
can be directly readable as well as writable using the In Target probe by writing
scripts. This is mainly used to enable the ports, display protocols and change the
register settings.

38
6.4.5 Internal Post processing tool
This is the tool that is used to capture waveforms from oscilloscope for use on other
post processing applications. Featuring an easy to use interface, this makes it simple
to transfer waveform data from Tektronix or Agilent oscilloscope to PC. This will
take through the steps of capturing first set of data. The first step involves getting
system and oscilloscope to talk to each other. The second step involves tuning the
signals display on the oscilloscope to get the maximum wave resolution for tool
to analyze. Finally the third step is to use tool to transfer the waveforms over the
destination.

6.4.6 Cadence-Allegro Physical Viewer

Cadence-Allegro physical viewer is used to view the board file and to find the vari-
ous nets, symbols, reference designators etc on the customer reference board which
intern used to find the probing points for measurement and debugging.

39
Chapter 7

Results

7.1 DLL Characterization

7.1.1 Delay range and Step Size

fequency Delay Range(pS) Step Size(pS)

Ideal Actual Ideal Actual
800 1250 1237 19.52 11.58-27.33
1066 938 927 14.65 8.42-20.67
1600 625 616 9.76 5.4-13.2

40
7.1.2 Code Vs. Delay

Figure 7.1: Code Vs Delay.

For this Code Vs. Delay Characterization, code is varied from 0 to 63 and the
corresponding delay is recorded from the scope. The above graph shows one of the
finding.

41
7.1.3 Integral Nonlinearity

Figure 7.2: Integral Nonlinearity.

7.1.4 Differential Non Linearity.

Figure 7.3: Differential Non Linearity.

42
7.2 Signal Integrity Validation
7.2.1 DQ-DQS setup and hold time measurement

Figure 7.4: Setup and Hold Time of DQ-DQS at 800 MHz.

43
 Figure 7.5: Setup and Hold Time of DQ-DQS at 1066 MHz.

According to DDR write protocol, DQ should be center alligned with respect

to DQS. For this measurement the DQS is probed differentially and DQ is probed
single ended with respect to ground. Above figure shows one of Eye for DQ-DQS
setup and hold margines, if its not above the JEDEC specication the failure occures
and DQ is pulled or pushed by using programmable delay element known as DLL
so as make it center alligned so that failure will not occure.

44
7.2.2 Clock-Command setup and hold time measurement

Figure 7.6: Setup and Hold Time of Clock-Command at 800 MHz.

45
 Figure 7.7: Setup and Hold Time of Clock-Command at 1066 MHz.

For this measurement clock is probed differentially and command(WE) is probed

single ended with respect to ground. If set up and hold margines are not above the
JEDEC specification, WE is pushed or pulled so as to meet the specification.

46
7.2.3 Clock-Control setup and hold time measurement

Figure 7.8: Setup and Hold Time of Clock-Control at 800 MHz.

47
 Figure 7.9: Setup and Hold Time of Clock-Control at 1066 MHz.

For this measurement clock is probed differentially and control(CS) is probed

single ended with respect to ground. If set up and hold margines are not above the
JEDEC specification, CS is pushed or pulled so as to meet the specification.

48
7.2.4 TDQSS

Figure 7.10: Tdqss(Clock-DQS) at 800 MHz.

49
 Figure 7.11: Tdqss(Clock-DQS) at 1066 MHz.

According to specification the clk and DQS should be exactly alligned. TDqss
is the delta between Clk and DQS, it should be within the JEDEC specification. For
this measurement Clk and DQS are probed differentially.

50
7.2.5 Clock Vix

Figure 7.12: Clock Vix.

Figure 7.13: Clock Vix.

This defines the measure of the crossover of the Clock and Clockbar signal(Clock
is a differential signal). For this measurement clock is probed single ended with re-
spect to ground.

51
7.2.6 Jitter

Figure 7.14: Clock Jitter at 800MHz.

Figure 7.15: Clock Jitter at 1066MHz.

For this measurement the Clock signals are probed differentialy, and the inbuilt
jitter tool from the Agilent is used.

52
Bibliography

53