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Izak Nel 209 324 067 DIT101T JK Flip-Flop

alter J and K values to every possible combination and note changes in JK configuration in reference to the clock pulse. display all the functions and ascertain the full intimate knowledge of internal functioning and application of the flip flop. Multi meter 4. Connect flip flop to pulse. Rubber anti static mat 2. Side cutter 10. Needle nose pliers 9. Oscilloscope 6. Continuity tester 5. Terminal screwdriver set 7. Magnifying glass + light 3. Breadboard 8. 1.Illustrate the working of a JK flip flop with a negative edge trigger. Wire stripper .

SPDT Switch 9. Red LED s 2. 4 channel/4 input dip switch 10. 9V Duracell Battery 4.1. 7805 Voltage Regulator 7. Ethernet cable cores ( jumper wires ) 3. 74LS00 NAND Gate 5. Assorted Resistors 8. 9 v two pole battery connecter . 74LS112 Negative-Edge-Triggered Master-Slave J-K Flip-Flop 6.

Logic Diagram .

one per channel.y y y y y y y y y y y y y y y y y Set up regulated 5 volt supply Fit SPDT switch Fit IC across breadboard isolator channel Connect Vcc and GND Connect two 5k7 resistors to the two selected switch channels (A. Parallel one resistor/switch junction to input A of NAND 1 Parallel the other resistor/switch junction with input B of NAND 2 Connect NAND 1 Output input A of NAND 2 Connect NAND 2 Output to input B of NAND 1 Connect 100 resistor and LED in series with NAND 1 Output to ground Connect 100 resistor and LED in series with NAND 2 Output to ground Fits and connect IC 74LS112 Connect two 5k7 resistors to the two selected dip switch channels in series with pins 2 and 3 separately Ground opposite side pins of dipswitches Parallel pins 4 and 13 and connect to Vcc Connect pin 8 of 74LS00 to pin 1 of 74LS112 Connect two 100 ohm resistor in series with two LED s to pins 5 and 6 separately .e.B) i.

The JK flip flop also has two additional inputs i. Only when the complimentary part of the latch receives its input that allows it to give a high output does the original output change.e. Preset and Clear.e.also known as the trailing edge this means that if the inputs change states and they allow for a condition change of Q but the input edge of the clock pulse is Positive the output will not change states. Example of switch bounce comes to mind. . When One of these inputs receive a low input (active low functioning) the will Set or Clear the output regardless of the edge state concerning the input clock pulse. BUT the JK Flip flop only changes states when the input clock pulse is on a negative edge of its input clock pulse . it has a set and clear function that once latched does not change its output even when the inputs have been removed i.The JK flip flop functions in a very similar fashion than that of the RS Latch.

1027 watts = 102. c) Power consumption of the instrument 20.7 mW .a) Physical size of instrument Instrument built on a standard issue breadboard that has a dimension spec of 150 mm x 5 mm x 10 mm b) Supply voltage to the instrument 9 volt battery enters a 7805 voltage regulator and delivers a 5 volt Parallel output to the IC.02055 x 5 = 0.55 mA at 5 volts 0.

The lone T input is in fact the CLK input for other types of flip-flops. after which this latch will not change again.) We can use this characteristic to advantage in a number of ways. the enabled input can change the state of the master latch once. there are some important differences. Instead. the JK flip-flop behaves just like the RS flip-flop.In most ways. the T flip-flop must also be edge triggered. This was not true of the RS flip-flop. this is the only way to ensure that the flip-flop will change state only once on any given clock pulse. For both types. If both the J and K inputs are held at logic 1 and the CLK signal continues to change. The Q and Qc outputs will only change state on the falling edge of the CLK signal. the master latch cannot change state back and forth while the CLK input is at logic 1. . (The master latch circuit will change state with each rising edge of CLK. Since one of the two logic inputs is always disabled according to the output state of the overall flip-flop. For the same reason. The JK flip-flop must be edge triggered in this manner. Any level-triggered JK latch circuit will oscillate rapidly if all three inputs are held at logic 1. However. and the J and K inputs will control the future output state pretty much as before. This is not very useful. the Q and Q' outputs will simply change state with each falling edge of the CLK signal. A flip-flop built specifically to operate this way is typically designated as a T (for Toggle) flip-flop.

Timing Diagram Clock J 0 0 1 1 K 0 1 0 1 Q Qc NC NC 0 1 1 0 Toggle Truth Table .

frequency dividers and many other arbitrary and novel hobby applications. It can perform the functions of the set/reset flip-flop and has the advantage that there are no ambiguous states. traditionally labelled J and K. If J and K are both high at the clock edge then the output will toggle from one state to the other. It can also act as a T flip-flop to accomplish toggling action if J and K are tied together. frequency counters. This toggle application finds extensive use in binary counters. This Flip Flop is truly a giant in the industry and finds application in almost any digital system conceivable it is used in counters. shift registers. The J-K flip-flop is the most versatile of the basic flip-flops. .The Objective was achieved. It has the inputfollowing character of the clocked D flip-flop but has two inputs. If J and K are different then the output Q takes the value of J at the next clock edge. examined and understood. the internal workings of a JK flip-Flop were investigated. If J and K are both low then no change occurs.