15” TFT TV SERVICE MANUAL

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TABLE OF CONTENTS
1. 2. 3. 4. 5. 6. 7. INTRODUCTION................................................................................................................................... 1 TUNER .................................................................................................................................................. 1 TDA988X ............................................................................................................................................... 1 MULTI STANDARD SOUND PROCESSOR ........................................................................................ 1 AUDIO AMPLIFIER STAGE WITH TDA7299 ....................................................................................... 1 POWER................................................................................................................................................. 2 MICROCONTROLLER SDA55XX ........................................................................................................ 2 7.1. General Features............................................................................................................................... 2 7.2. External Crystal and Programmable Clock Speed ............................................................................ 2 7.3. Microcontroller Features .................................................................................................................... 2 7.4. Memory.............................................................................................................................................. 2 7.5. Display Features................................................................................................................................ 2 7.6. ROM Characters................................................................................................................................ 2 7.7. Acquisition Features .......................................................................................................................... 3 7.8. Ports .................................................................................................................................................. 3 8. SERIAL ACCESS CMOS 16K (2048*8) EEPROM ST24C16 .............................................................. 3 9. CLASS AB STEREO HEADPHONE DRIVER TDA1308 ...................................................................... 3 10. SAW FILTERS ...................................................................................................................................... 3 11. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM .................................................................... 4 11.1. TEA5114A...................................................................................................................................... 4 11.1.1. General description .............................................................................................................. 4 11.1.2. Features ................................................................................................................................. 4 11.1.3. Pin Connections ................................................................................................................... 4 11.2. MC34167........................................................................................................................................ 5 11.2.1. General Description.............................................................................................................. 5 11.2.2. Features ................................................................................................................................. 5 11.3. LM7808 .......................................................................................................................................... 5 11.3.1. Description ............................................................................................................................ 5 11.3.2. Features ................................................................................................................................. 5 11.4. SDA55XX ....................................................................................................................................... 6 11.4.1. General description .............................................................................................................. 6 11.5. TFMS5360 ..................................................................................................................................... 6 11.5.1. Description ............................................................................................................................ 6 11.5.2. Features ................................................................................................................................. 6 11.6. SST37VF040.................................................................................................................................. 7 11.6.1. Description ............................................................................................................................ 7 11.6.2. Features ................................................................................................................................. 7 11.6.3. Pin Description ..................................................................................................................... 7 11.7. ST24LC21 ...................................................................................................................................... 8 11.7.1. Description ............................................................................................................................ 8 11.7.2. Features ................................................................................................................................. 8 11.7.3. Pin connections .................................................................................................................... 8 11.8. VPC3230D ..................................................................................................................................... 9 11.8.1. General Description.............................................................................................................. 9 11.8.2. Pin Connections and Short Descriptions........................................................................... 9 11.9. AL300........................................................................................................................................... 11 11.9.1. General Description............................................................................................................ 11 11.9.2. Features ............................................................................................................................... 11 11.9.3. Pin Definition and Description .......................................................................................... 11 11.10. LM1086 ........................................................................................................................................ 14 11.10.1. Description .......................................................................................................................... 14 11.10.2. Features ............................................................................................................................... 14 11.10.3. Applications ........................................................................................................................ 14 11.10.4. Connection Diagrams......................................................................................................... 14 11.11. LM1117 ........................................................................................................................................ 15 11.11.1. General Description............................................................................................................ 15 11.11.2. Features ............................................................................................................................... 15 i 15” TFT TV Service Manual 24/10/2003

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11.11.3. Applications ........................................................................................................................ 15 11.11.4. Connection Diagrams......................................................................................................... 15 11.12. TDA7299 ...................................................................................................................................... 16 11.12.1. Description .......................................................................................................................... 16 11.12.2. Features ............................................................................................................................... 16 11.12.3. Pin Connection ................................................................................................................... 16 11.13. DS90C385.................................................................................................................................... 17 11.13.1. General Description............................................................................................................ 17 11.13.2. Features ............................................................................................................................... 17 11.13.3. Pin Description ................................................................................................................... 17 11.14. TDA1308 ...................................................................................................................................... 18 11.14.1. General Description............................................................................................................ 18 11.14.2. Features ............................................................................................................................... 18 11.14.3. Pinning................................................................................................................................. 18 11.15. TL431 ........................................................................................................................................... 19 11.15.1. Description .......................................................................................................................... 19 11.15.2. Features ............................................................................................................................... 19 11.15.3. Pin Configurations.............................................................................................................. 19 11.16. 24C16........................................................................................................................................... 20 11.16.1. Description .......................................................................................................................... 20 11.16.2. Features ............................................................................................................................... 20 11.16.3. Pin Configuration................................................................................................................ 20 11.16.4. Pin Description ................................................................................................................... 20 11.17. AL875........................................................................................................................................... 21 11.17.1. General Description............................................................................................................ 21 11.17.2. General Features ................................................................................................................ 21 11.17.3. Pin Definition and Description .......................................................................................... 21 11.18. 74HC244A.................................................................................................................................... 23 11.18.1. Description .......................................................................................................................... 23 11.18.2. General Features ................................................................................................................ 23 11.18.3. Pin Description ................................................................................................................... 23 11.19. ICS1523 ....................................................................................................................................... 24 11.19.1. Description .......................................................................................................................... 24 11.19.2. Features ............................................................................................................................... 24 11.20. MC34063...................................................................................................................................... 25 11.20.1. Description .......................................................................................................................... 25 11.20.2. Features ............................................................................................................................... 25 11.20.3. Pin connections .................................................................................................................. 25 11.21. TDA9885/86 ................................................................................................................................. 26 11.21.1. General description ............................................................................................................ 26 11.21.2. 13.13.2.Features .................................................................................................................. 26 11.21.3. 13.13.3.Pinning.................................................................................................................... 26 11.22. MSP34X0G .................................................................................................................................. 27 11.22.1. Introduction ......................................................................................................................... 27 11.22.2. Features ............................................................................................................................... 27 11.22.3. Pin connections .................................................................................................................. 28 11.23. SAA3010T.................................................................................................................................... 30 11.23.1. 14.22.1.Description ............................................................................................................. 30 11.23.2. 14.22.2.Features .................................................................................................................. 30 11.23.3. 14.22.3.Pinning.................................................................................................................... 30 12. SERVICE MENU SETTINGS.............................................................................................................. 31 12.1. ADJUST MENU SETTINGS ........................................................................................................ 31 OPTIONS MENU SETTINGS..................................................................................................................... 33 12.2. APS WSS TEST MENU............................................................................................................... 38 13. BLOCK DIAGRAM .............................................................................................................................. 39 14. CIRCUIT DIAGRAMS ......................................................................................................................... 40

ii 15” TFT TV Service Manual 24/10/2003

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1. INTRODUCTION
TFT TV is a progressive scan flicker free colour television with PC input, driving a XGA panel with 4:3 aspect ratio. The chassis is capable of operation in PAL, SECAM, NTSC (playback) colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L´. Sound system output is supplying 2x2W (10%THD) for left and right outputs of 8Ω speakers. The chassis is equipped with one full SCART, one front-AV, one SVHS, one D-Sub 15 (PC) input and one line out (left and right) and one HP outputs.

2. TUNER
The hardware and software of the TV is suitable for tuners, supplied by different companies, which are selected from the Service Menu. These tuners can be combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L´, I/I´, and D/K. The tuning is available through the digitally controlled I 2C bus (PLL). Below you will find info on one of the Tuners in use. General description of UV1316: The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient. Features of UV1316: 1. Member of the UV1300 family small sized UHF/VHF tuners 2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K 3. Digitally controlled (PLL) tuning via I2C-bus 4. Off-air channels, S-cable channels and Hyperband 5. World standardised mechanical dimensions and world standard pinning 6. Compact size 7. Complies to “CENELEC EN55020” and “EN55013” Pinning: 1. Gain control voltage (AGC) 2. Tuning voltage 3. I²C-bus address select 4. I²C-bus serial clock 5. I²C-bus serial data 6. Not connected 7. PLL supply voltage 8. ADC input 9. Tuner supply voltage 10. Symmetrical IF output 1 11. Symmetrical IF output 2

: : : : : :

4.0V, Max: 4.5V Max: 5.5V Min:-0.3V, Max: 5.5V Min:-0.3V, Max: 5.5V 5.0V, Min: 4.75V, Max: 5.5V 33V, Min: 30V, Max: 35V

3. TDA988X
The TDA9885 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL. The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL demodulator for positive and negative modulation including sound AM and FM processing. Both devices can be used for TV, VTR, PC and set-top box applications.

4. MULTI STANDARD SOUND PROCESSOR
The MSP 34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Signal conforming to the standard by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, MICRONAS Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.

5. AUDIO AMPLIFIER STAGE WITH TDA7299
The TDA7299 is an audio class-AB amplifier assembled in SO package specially designed for sound cards application. By utilizing two TDA7299, chassis operates as a stereo TV set. TDA7299 has stand-by feature

1 15” TFT TV Service Manual 24/10/2003

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for low stand-by power consumption by using pin #3. It can deliver 2W without clipping at 12V/8Ω applications.

6. POWER
MC34167 is a power switch regulator, which can output 5V from 12V up to 5A. Utilising a power MOSFET inside works at a very high efficiency without producing excessive heat. This IC is the main supply for the voltages used in the main board. Using the pin 5 (stand-by) of IC, TFT TV can have low stand-by power consumption.

7. MICROCONTROLLER SDA55XX
7.1. General Features • Feature selection via special function register • Simultaneous reception of TTX, VPS, PDC, and WSS (line 23) • Supply Voltage 2.5 and 3.3 V • ROM version is used. 7.2. External Crystal and Programmable Clock Speed • Single external 6MHz crystal, all necessary clocks are generated internally • CPU clock speed selectable via special function registers. • Normal Mode 33.33 MHz CPU clock, Power Save mode 8.33 MHz 7.3. Microcontroller Features • 8bit 8051 instruction set compatible CPU. • 33.33-MHz internal clock (max.) • 0.360 ms (min.) instruction cycle • Two 16-bit timers • Watchdog timer • Capture compare timer for infrared remote control decoding • Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit) • ADC (4 channels, 8 bit) • UART(rxd,txd) 7.4. Memory • Up to 128 Kilobyte on Chip Program ROM • Eight 16-bit data pointer registers (DPTR) • 256-bytes on-chip Processor Internal RAM (IRAM) • 128bytes extended stack memory. • Display RAM and TXT/VPS/PDC/WSS-Acquisition-Buffer directly accessible via MOVX • UP to 16KByte on Chip Extended RAM (XRAM) consisting of; - 1 Kilobyte on-chip ACQ-buffer-RAM (access via MOVX) - 1 Kilobyte on-chip extended-RAM (XRAM, access via MOVX) for user software - 3 Kilobyte Display Memory 7.5. Display Features • ROM Character set supports all East and West European Languages in single device • Mosaic Graphic Character Set • Parallel Display Attributes • Single/Double Width/Height of Characters • Variable Flash Rate • Programmable Screen Size (25 Rows x 33...64 Columns) • Flexible Character Matrixes (HxV) 12 x 9...16 • Up to 256 Dynamical Redefinable Characters in standard mode; 1024 Dynamical Redefinable Characters in Enhanced Mode • CLUT with up to 4096 colour combinations • Up to 16 Colours per DRCS Character • One out of 8 Colours for Foreground and Background Colours for 1-bit DRCS and ROM Characters 7.6. ROM Characters • Shadowing 2 15” TFT TV Service Manual 24/10/2003

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4. 4.0. CC. 9.7) • One 4-bit I/O-port with secondary function (P4. which uses a bidirectional data bus and serial clock. Supported standards are B/G. D/K. SAW FILTERS K3953M is an IF Filter for Video Applications. I. WSS.1. The memory is compatible with the I²C standard. The memory carries a built-in 4 bit. Ports • One 8-bit I/O-port with open drain output and optional I 2 C Bus emulation support (Port0) • Two 8-bit multifunction I/O-ports (Port1. L/L’.8. • 3 X 4Bits RGB-DACs On-Chip • Free Programmable Pixel Clock from 10 MHz to 32MHz • Pixel Clock Independent from CPU Clock • Multinorm H/V-Display Synchronisation in Master or Slave Mode 7. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications. G+) • Four Different Framing Codes Available • Data Caption only limited by available Memory • Programmable VBI-buffer • Full Channel Data Slicing Supported • Fully Digital Signal Processing • Noise Measurement and Controlled Noise Compensation • Attenuation Measurement and Compensation • Group Delay Measurement and Compensation • Exact Decoding of Echo Disturbed Signals 7. Supported standards are B/G. two wire serial interface. This is used together with 1 chip enable input (E) so that up to 2*8K devices may be attached to the I²C bus and selected individually. VPS. SERIAL ACCESS CMOS 16K (2048*8) EEPROM ST24C16 The ST24C16 is an 16Kbit electrically erasable programmable memory (EEPROM).2. 10. 3 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. The package is SIP5K.7.4) (Not available in P-SDIP 52) 8.com . Acquisition Features • Multistandard Digital Data Slicer • Parallel Multi-norm Slicing (TTX.3. Port3) • One 4-bit port working as digital or analogue inputs for the ADC (Port2) • One 2-bit I/O port with secondary function (P4.pdffactory. 4.• Contrast Reduction • Pixel by Pixel Shiftable Cursor With up to 4 Different Colours • Support of Progressive Scan and 100 Hz. L/L’. unique device identification code (1010) corresponding to the I²C bus definition. K9656M is an IF Filter for Audio Applications. I. D/K. organised as 8 blocks of 256*8 bits. The package is SIP5K. CLASS AB STEREO HEADPHONE DRIVER TDA1308 The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package. 4.

IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM TEA5114A MC34167 LM7808 SDA55XX TFMS5360 SST37VF040 ST24LC21 VPC3230D AL300 LM1086 LM1117 TDA7299 DS90C385 TDA1308T TL431 24C16 AL875 74HC244A ICS1523 MC34063 TDA9885/86 MSP3400G SAA3010T 11. The input signal black level is tied to the same reference voltage on each input in order to have no differential voltage when switching two RGB generators.2. Pin Connections 4 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.3. TEA5114A 11.1.com . An AC output signal higher than 2 Vpp makes gain going slowly down to 0dBto protect the TV set video amplifier from saturation. Fast blanking output is a logical OR between FB1 (Pin 8) and FB2 (Pin 10).1.11. General description This integrated circuit provides RGB switching allowing connections between peri TV plug. 11. internal RGB generator and video processor in a TV set.1.pdffactory.1.1. Features • 25MHz Bandwidth • Crosstalk : 55dB • Short circuit to ground or VCC protected • Anti saturation gain changing • Video switching 11.

11. 9.2.3.5. and thermal shutdown.5 V to 40 V • Standby Mode Reduces Power Supply Current to 36 mA • Economical 5–Lead TO–220 Package with Two Optional Leadforms • Also Available in Surface Mount D 2 PAK Package • Moisture Sensitivity Level (MSL) Equals 1 11. MC34167 11. Protective features consist of cycle–by–cycle current limiting. 8. Although designed primarily as fixed voltage regulators.2. General Description The MC34167.1. thermal shutdown and safe area protection. fixed frequency oscillator with on–chip timing components. 15.2. latching pulse width modulator for single pulse metering.3. LM7808 11. making it useful in a wide range of applications. high gain error amplifier. Description The L7800 series of three-terminal positive regulators is available in TO-220 TO-220FP TO-3 and D 2 PAK packages and several fixed output voltages. these devices can be used with external components to obtain adjustable voltages and currents. and a high current output switch.11. 6. 24V • Thermal Over load protection • Short Circuit Protection • Output Transition SOA Protection 5 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.2. eliminating the distribution problems associated with single point regulation. 8. making it essentially indestructible.0 A • Fixed Frequency Oscillator (72 kHz) with On–Chip Timing • Provides 5. 12. 5.pdffactory. MC33167 series are high performance fixed frequency power switching regulators that contain the primary functions required for dc–to–dc converters.2. This series was specifically designed to be incorporated in step–down and voltage–inverting configurations with a minimum number of external components and can also be used cost effectively in step–up applications. 11.5 A • Output Voltages of 5. Each type employs internal current limiting. Features • Output Switch Current in Excess of 5.2. These regulators can provide local on-card regulation. 18. under voltage lockout. If adequate heat sinking is provided. Features • Output Current Up To 1.com .3. they can deliver over 1A output current.05 V Output without External Resistor Divider • Precision 2% Reference • 0% to 95% Output Duty Cycle • Cycle–by–Cycle Current Limiting • Under voltage Lockout with Hysteresis • Internal Thermal Shutdown • Operation from 7. Also included is a low power standby mode that reduces power supply current to 36 mA. These devices consist of an internal temperature compensated reference.1.

5 V supply voltage and 3.3 V I/O (TTL compatible). WSS. NTSC and contains a digital slicer for VPS. Device has an internal ROM of up to 128 KBytes.2. The device also supports Closed caption acquisition and decoding. ROMless versions can access up to 1 MByte of external RAM and ROM. Additionally. transfers data to/from external memory interface and receives/ transmits data via I2C-firmware user-interface. fully 8051-compatible Microcontroller with television specific hardware features. data pointers. General description The SDA55XX is a single chip teletext decoder for decoding World System Teletext data as well as Video Programming System (VPS).1.5. 11. SDA 55XX is realized in 0. SDA55XX 11. The software and hardware development environment (TEAM) is available to simplify and speed up the development of the software and On Screen Display. and Pixel oriented characters (DRCS). page search and evaluation of header control bits) once per field. an accelerating acquisition hardware module.5. and Wide Screen Signalling (WSS) data used for PAL plus transmissions (Line 23). TOP and list-pages. – Modular and open tool chain. Internal XRAM consists of up to16 Kbytes. It improves the TV controller software quality in following aspects: – Shorter time to market – Re-usability – Target independent development – Verification and validation before targeting – General test concept – Graphical interface design requiring minimum programming and controller know how.25 micron technology with 2.1. cycle time (min. the firmware can provide high-end Teletext features like Packet-26-handling. The on-chip display unit for displaying Level 1.4.). TEAM stands for TVT Expert Application Maker.11. The device provides an integrated general-purpose. The slicer combined with dedicated hardware stores TTX data in a VBI buffer of 1 Kilobyte. The interface to user software is optimized for minimal overhead. • 36 KHZ • Pin diode and preamp • IR filter. The Microcontroller firmware performs all the acquisition tasks (hamming and parity-checks. configurable by customer. Microcontroller has been enhanced to provide powerful features such as memory banking. The 8-bit Microcontroller runs at 360 ns.4. 11. a display generator for Level 1. Features • Photo detector and preamplifier in one. and additional interrupts etc.5 TTX data and powerful On screen Display capabilities based on parallel attributes. Program Delivery Control (PDC). Controller with dedicated hardware does most of the internal TTX acquisition processing. FLOF. TFMS5360 11.pdffactory.com . 6 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. Description The TFMS5360 is a miniature receiver for infrared remote control systems. The SDA 55XX supports a wide range of standards including PAL.5. TTX and Closed Caption. PDC.5 teletext data can also be used for customer defined on screen displays.

Symbol 1 AMS -A0 DQ7-DQ0 CE# WE# OE# VDD VSS NC Pin Description Functions To provide memory addresses.6.3.7-3. AMS = Most significant address AMS = A15 for SST37VF512. The SST37VF512/010/020/040 can be electrically erased and programmed at least 1000 times using an external programmer. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the SST37VF512/010/020/040 provide a typical Byte-Pro-gram time of 10 µs.. Description The SST37VF512/010/020/040 devices are 64K x8 / 128Kx8 / 256K x8 / 512K x8 CMOS.6.g. A17 for SST37VF020. To output data during Read cycles and receive input data during Program cycles. SST37VF040 11. OTPs. Features • Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8 • 2. To program or erase (WE# = VIL pulse during Program or Erase) To gate the data output buffers during Read operation when low To provide 3. Designed. Many-Time Programmable (MTP). Pin name Address Inputs Data Input/output Chip Enable Write Enable Output Enable Power Supply Ground No Connection 1.6V) Unconnected pins.8 seconds (typical) for SST37VF040 • Electrical Erase Using Programmer – Does not require UV source – Chip-Erase Time: 100 ms (typical) • CMOS I/O Compatibility • JEDEC Standard Byte-wide Flash EEPROM Pinouts • Packages Available – 32-lead PLCC – 32-lead TSOP (8mm x 14mm) – 32-pin PDIP 11.6. These devices will improve flexibility.2. efficiency and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs.6V Read Operation • Superior Reliability – Endurance: At least 1000 Cycles – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 10 mA (typical) – Standby Current: 2 µA (typical) • Fast Read Access Time: – 70 ns.11.7-3.6 seconds (typical) for SST37VF512 1. The outputs are in tri-state when OE# or CE# is high. The SST37VF512/010/020/040 have to be erased prior to programming. The SST37VF512/010/020/040 are suited for applications that require infrequent writes and low power nonvolatile storage.0V supply (2. 11. low cost flash. and mask ROMs.pdffactory.1.6. These devices conform to JEDEC standard pinouts for byte-wide flash memories. and tested for a wide spectrum of applications.com . Featuring high performance Byte-Program. manufactured with SST’s proprietary. and A18 for SST37VF040 7 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.4 seconds (typical) for SST37VF020 4. manufactured. e. A16 for SST37VF010.2 seconds (typical) for SST37VF010 2. these devices are offered with an endurance of at least 1000 cycles. to change the contents of devices in inventory. To activate the device when CE# is low. high performance CMOS SuperFlash technology. 90 ns • Latched Address and Data • Fast Byte-Program Operation: – Byte-Program Time: 10 µs (typical) – Chip Program Time: 0. Data retention is rated at greater than 100 years.

Pin connections CO Pin connections DIP Pin connections NC: Not connected Signal names SDA SCL Vcc Vss VCLK Serial data Address Input/Output Serial Clock (I2C mode) Supply voltage Ground Clock transmit only mode 8 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.2.com . organized by 8 bits. The ST24LC21 can not switch from the I2C bidirectional mode to the Transmit Only mode (except when the power supply is removed).5V. The device will switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL pin.3.5V single supply voltage • 400k Hz compatibility over the full range of supply voltage • Two wire serial interface I2C bus compatible • Page Write (Up To 8 Bytes) • Byte. the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK.11. 11.7.pdffactory. Both Plastic Dual-in-Line and Plastic Small Outline packages are available. Features • 1 million Erase/Write cycles • 40 years data retention • 2.7. The device operates with a power supply value as low as 2.5V To 5. This device can operate in two modes: Transmit Only mode and I 2C bidirectional mode. Description The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM).7. When powered. random and sequential read modes • Self timed programming cycle • Automatic address incrementing • Enhanced ESD/Latch up • Performances 11. ST24LC21 11.1.7.

SUPPLYD = 3.25 MHz Pad Decoupling Circuitry GND Pad Decoupling Circuitry Supply Voltage Double Clock Output Clock Output 9 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.1. data and sync.45 V Pin No.11. 50/60-Hz and 100/120 Hz TV sets.25-MHz crystal.. leave vacant X = obligatory. Digital Circuitry Digital Decoupling Circuitry GND 2 I C Bus Clock 2 I C Bus Data Reset Input. one Fast Blank (FB) input • integrated high-quality A/D converters and associated clamp and AGC circuits • multi-standard sync processing • linear horizontal scaling (0. General Description The VPC 323xD is a high-quality.2. Active Low FIFO Input Enable FIFO Write Enable FIFO Reset Write/Read FIFO Read Enable FIFO Output Enable Main Clock output 20.. It can be combined with other members of the DIGIT3000 IC family (such as DDP 331x) and/or it can be used with 3rd-party products.com . which is targeted for 4:3 and 16:9.8. contrast. or 656-output interface • peaking. Digital Circuitry Ground.8.. Active Low Test Pin. 1/16 or 1/36 of normal size) with 8-bit resolution • 15 predefined PIP display configurations and expert mode (fully programmable) • control interface for external field memory • I2C-bus interface • one 20.8.25 V. single-chip video front-end... VPC3230D 11. connect as described in circuit diagram SUPPLYA = 4. The main features of the VPC 323xD are • high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking • multi-standard colour decoder PAL/NTSC/SECAM including all substandards • four CVBS. PQFP 80-pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name Type Connection (if not used) VREF VREF VREF VREF VREF VREF X LV or GNDD X X X X X X X GNDD GNDD GNDD LV LV LV LV LV LV X X LV LV Short Description B1/CB1IN G1/Y1IN R1/CR1IN B2/CB2IN G2/Y2IN R2/CR2IN ASGF FFRSTWIN VSUPCAP VSUPD GNDD GNDCAP SCL SDA RESQ TEST VGAV YCOEQ FFIE FFWE FFRSTW FFRE FFOE CLK20 GNDPA VSUPPA LLC2 LLC1 IN IN IN IN IN IN IN OUT SUPPLYD SUPPLYD OUT IN/OUT IN/OUT IN IN IN IN OUT OUT OUT OUT OUT IN/OUT OUT OUT OUT IN/OUT Blue1/Cb1 Analog Component Input Green1/Y1 Analog Component Input Read1/Cr1 Analog Component Input Blue2/Cb2 Analog Component Input Green2/Y2 Analog Component Input Read2/Cr2 Analog Component Input Analog Shield GNDF FIFO Reset Write Input Digital Decoupling Circuitry Supply Voltage Supply Voltage. 4).. one CVBS output • two RGB/YCr Cb component inputs.75.3. Pin Connections and Short Descriptions NC = not connected LV = if not used. brightness. color saturation and tint for RGB/ YC r C b and CVBS/ S-VHS • high-quality soft mixer controlled by Fast Blank • PIP processing for four picture sizes (1/4.15. few external components • 80-pin PQFP package 11. 1/9.5. as well as non-linear horizontal scaling ‘Panorama-vision’ • PAL+ preprocessing • line-locked clock.pdffactory. one S-VHS input.25 . connect to GNDD VGAV Input Y/C Output Enable Input.

connect to GNDAI 10 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. LLC Circuitry Picture Bus Luma (MSB) Picture Bus Luma Picture Bus Luma Picture Bus Luma Ground.pdffactory. Analog Front-End Analog Video Output Chroma/Analog Video 5 Input Video 1 Analog Input Video 2 Analog Input Video 3 Analog Input Video 4 Analog Input Supply Voltage. LLC Circuitry Ground. Analog Component Inputs Front-End Reference Voltage Top. Luma Output Circuitry Picture Bus Luma Picture Bus Luma Picture Bus Luma Picture Bus Luma (LSB) Picture Bus Chroma (MSB) Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Supply Voltage. Luma Output Circuitry Supply Voltage. Analog Component Inputs Front-End Ground. Chroma Output Circuitry Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma (LSB) Ground Sync Pad Circuitry Supply Voltage.com . connect to GNDF Supply Voltage.29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VSUPLLC GNDLLC Y7 Y6 Y5 Y4 GNDY VSUPY Y3 Y2 Y1 Y0 C7 C6 C5 C4 VSUPC GNDC C3 C2 C1 C0 GNDSY VSUPSY INTLC AVO FSY/HC/HSYA MSY/HS VS FPDAT/VSYA VSTBYY CLK5 NC XTAL1 XTAL2 ASGF GNDF VRT I2CSEL ISGND VSUPF VOUT CIN VIN1 VIN2 VIN3 VIN4 VSUPAI GNDAI VREF FB1IN AISGND SUPPLYD SUPPLYD OUT OUT OUT OUT SUPPLYD SUPPLYD OUT OUT OUT OUT OUT OUT OUT OUT SUPPLYD SUPPLYD OUT OUT OUT OUT SUPPLYD SUPPLYD OUT OUT OUT IN/OUT OUT IN/OUT SUPPLYA OUT IN OUT SUPPLYA OUTPUT IN SUPPLYA SUPPLYA OUT IN IN IN IN IN SUPPLYA SUPPLYA OUTPUT IN SUPPLYA X X GNDY GNDY GNDY GNDY X X GNDY GNDY GNDY GNDY GNDC GNDC GNDC GNDC X X GNDC GNDC GNDC GNDC X X LV LV LV LV LV LV X LV LV or GNDD X X X X X X X X LV LV VRT VRT VRT VRT X X X VREF X Supply Voltage. Analog Front-End Reference Voltage Top. Sync Pad Circuitry Interlace Output Active Video Output Front Sync/ Horizontal Clamp Pulse/Front-End Horizontal Sync Output Main Sync/Horizontal Sync Pulse Vertical Sync Pulse Front End/Back-End Data/Front-End Vertical Sync Output Standby Supply Voltage CCU 5 MHz Clock Output Not Connected Analog Crystal Input Analog Crystal Output Analog Shield GNDF Ground. Chroma Output Circuitry Ground. Analog 2 I C Bus Address Select Signal Ground for Analog Input. Analog Component Inputs Front-End Fast Blank Input Signal Ground for Analog Component Inputs.

regardless of the resolution of the incoming signal.9. Blue Input When in RGB Mode Cr Input When in CCIR601 444 Mode Refer to register #1Bh for details. text.9.11. control menu.9.com . OSD bitmaps of up to 8K pixels are supported. The AL300 also provides de -interlacing. Two integrated On Screen Display (OSD) windows provide overlay of a control menu. The input video can be linearly and independently zoomed in the x and y directions. It provides LCD/PDP monitor and projector manufacturers with a low-cost. 100-pin QFP). easy solution to bring TV or PC video to LCD panels. The AL300 is equipped with a high quality zoom engine that automatically maintains full screen output display. Video Vertical Sync Signal Video Horizontal Sync Signal Graphic Vertical Sync Signal Graphic Horizontal Sync Signal Graphic Horizontal Active Data Reference Graphic Input Clock Red Input When in RGB Mode Y Input When in CCIR601 422 and 444 Modes Green Input When in RGB Mode CbCr Input When in CCIR601 422 Mode Cb Input When in CCIR601 444 Mode Refer to register #1Bh for details. Buffered Output of the Clock Input for Host Interface such as a Pin Name Type Video Interface TVCLK IN (CMOSd) TVHREF IN (CMOSd) TVVS IN (CMOSs) TVHS IN (CMOSs) Graphic Interface GVS IN (CMOSs) GVH IN (CMOSs) GHREF IN (CMOS) GCLK IN (CMOSd) R/YIN<7:0> IN (CMOS) G/UVIN<7:0> IN (CMOS) BIN<7:0> IN (CMOS) 29-36 Host Interface HOSTCLK OUT (CMOS) 38 11 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.1. filtering. the AL300 (in 160pin QFP) offers the best cost-performance and total solution for LCD monitors or projectors. Pin Definition and Description Pin # 1 2 3 4 6 7 8 9 11-18 20-27 Note Video Clock from Video Source Video Horizontal Active Data Reference This signal is used to indicate valid data of the YUV input. or other display information. virtually all languages and fonts are supported.pdffactory. With the internal OSD RAM. and scaling support for interlaced video to be displayed on a LCD panel. or caption on the output display. Used with an AL875 (high speed 3-channel ADC with PLL. Features • Converts PC’s or TV’s signals for flat panel dis plays • Supports active matrix up to 1280x1024 resolution • De-interlacing support for video inputs • Automatic screen positioning support • Fully programmable zoom ratios • Independent linear zoom in H and V directions • Supports single and dual pixel per clock panels • Dithering logic to enhance color resolution for 12-bit or 18-bit panels • Built-in high speed PLL • User-definable font table supporting different languages and font sizes • Two built-in OSD windows 2 • I C programmable • No external memory required • Single 3.9.3. With optional external userdefined font table ROM. General Description The AL300 is designed to enable simple connection from PC’s or video devices to flat panel displays.2. 11. AL300 11. or other flat panel devices.3 volt power with 5 volt tolerant I/O • 160-pin 28x28 mm PQFP package 11. the AL300 OSD functionality is very flexible with font size and display location. Special OSD effects such as translucency and blinking offer the manufacturer a unique and vivid way of presenting monitor status.

data are output every SCLK. used to indicate active output pixels (HDE). RGB Format Video Input 1. virtual IHSREF can be I2CADDR IN (CMOSd) 47 YUVIN IN (CMOSd) 48 Test1 IN (CMOSd) Test2 IN (CMOSd) Panel/Display Interface RB<7:0> OUT (CMOS) 49 50 52-55. Panel/Display Display Enable. 107-110 BA<7:0> OUT (CMOS) 112-115. the frequency provided is for I C sampling and for output reference timing when input sync signals are missing or undetectable. read address = 71 1. 97-100 GA<7:0> OUT (CMOS) 102-105. write address = 72. Right Pixel of Interleaved Green Output in Dual Pixel Mode Valid when Register 0x43 bit4 = ‘1’. the B data lag A data by 90° (half SCLK). Connected to Register 0x1B bit 3 General Purpose Output. Default PCLKB lags PCLKA by 180° (one SCLK). 117-120 PLL (Phase Lock Loop) Interface IHSREF OUT (CMOS) 123 12 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. A and B data are aligned. Blue Data Output When Register 0x43 bit4 = ‘0’. Polarity is programmable. Can be programmed to either polarity. Data are output with PCLKB. B. write address = 70. Display Pixel Clock (for single pixel per clock mode) Panel/Display Hsync. When Register 0x43 bit4 = ‘1’. When Register 0x43 bit4 = ‘1’. CCIR YUV Format Video Input Refer to RIN. read address = 73 YUV Input 0. For AL300 ver. A. 67-70 BB<7:0> OUT (CMOS) 72-75. the left pixel of interleaved red data are output with PCLKA. B. Connected to Register 0x1B bit 2 General Purpose Output. Green Data Output When Register 0x43 bit4 = ‘0’. Right Pixel of Interleaved Blue Output in Dual Pixel Mode Valid when Register 0x43 bit4 = ‘1’. For AL300 ver. Can be programmed to either polarity. When no input HSYNC is present. A. BIN pins Test Pin Test Pin Right Pixel of Interleaved Red Output in Dual Pixel Mode Valid when Register 0x43 bit4 = ‘1’. Usually in the range of 10~50MHz. B. the B data lag A data by 90° (half SCLK). A and B data are aligned. 57-60 GB<7:0> OUT (CMOS) 62-65. For AL300 ver.com . A. the left pixel of interleaved red data are output with PCLKA. Can be programmed to either polarity. active high 2 I C Serial Clock Input 2 I C Serial Data Input/Output General Purpose Output. the left pixel of interleaved red data are output with PCLKA. Connected to Register 0x1B bit 1 Power Down 0. usually for input PLL to regenerate input pixel clock. 77-80 PCLKA PCLKB OUT (CMOS) OUT (CMOS) 84 85 SCLK PHS PVS PDSPEN RA<7:0> OUT (CMOS) OUT (CMOS) OUT (CMOS) OUT (CMOS) OUT (CMOS) 86 88 89 90 92-95. GIN. data are output every SCLK. For AL300 ver. Data are output with PCLKB. Input Hsync Reference. A and B data are aligned. Interrupt Request. Data are output with PCLKB. Red Data Output When Register 0x43 bit4 = ‘0’. data are output every SCLK.pdffactory. the B data lag A data by 90° (half SCLK). Leading Pixel Clock of Interleaved Video Output for Right data in Dual Pixel Mode. When Register 0x43 bit4 = ‘1’.XOUT XIN OUT (CMOS) IN (CMOS) 39 40 IREQ SCL SDA GOUT1 GOUT2 GOUT3 Configuration PWRDN OUT (CMOS) IN (CMOSs) INOUT (COMSsu) OUT (CMOS) OUT (CMOS) OUT (CMOS) IN (CMOSd) 41 42 43 81 82 83 46 Micro-controller Crystal Output 2 Crystal Input. Normal Operation 1. Polarity is programmable Lagging Pixel Clock of Interleaved Video Output for Right data in Dual Pixel Mode. buffered and polarity adjusted. Panel/Display Vsync. For AL300 ver. For AL300 ver. Power Down 2 I C Bus Slave Address Select 0. Always positive polarity.

45. 71. OHSREF is either equivalent to IHSREF or the equally divided IHSREF. 3. 10h~13h. 61. Always positive polarity.3V GND of Internal PLL Digital VCC. Reset RESETB IN (CMOS) PLLVCC POWER PLLGND GROUND VCC POWER Reset. Refer to registers 03h. 121. 10. 96. connected to OPLLCLK when internal PLL is used. 137-140 160-157. 116. 106. 87. 51. 101. 111. 150-147.pdffactory. 151 5. 146. active low VCC of Internal PLL. 131. 155-152. 136. 28. 141. connected to external PLL clock output when external PLL is used Recovered Output Clock generated by the internal PLL PLL External VCO Filter Circuit Input OSD ROM Data OSD ROM Address Power. Output PLL Feedback.com . 145-142 122 128 130 19. 156 44 OPLLCLK OUT (CMOS) VCOIN IN OSD ROM Interface ROMDATA IN (CMOSd) <7:0> ROMADDR OUT (CMOS) <15:0> generated by programming registers 41h & 42h Output Hsync Reference.3V GND GROUND Digital Ground NC No connection Remarks: CMOSd : CMOS with internal pull-down CMOSs : CMOS with Schmitt trigger CMOSsu : CMOS with Schmitt trigger and internal pull-up 13 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. works with OHSREF to generate output pixel clock Output Clock. 66. 37. 76. for output PLL to generate output pixel clock.OHSREF OUT (CMOS) 124 OHSFB OCLK OUT (CMOS) IN (CMOSd) 125 126 127 129 132-135. Ground. 3. 56. 91.

3. 2.85V. Applications SCSI-2 Active Terminator High Efficiency Linear Regulators Battery Charger Post Regulation for Switching Supplies Constant Current Regulator Microprocessor Supply 11.10. Description The LM1086 is a series of low dropout positive voltage regulators with a maximum dropout of 1.pdffactory.3.5V. Features Available in 2.1% (typical) 11. which can set the output voltage with only two external resistors.10. 5V and Adjustabl e Versions Current Limiting and Thermal Protection Output Current 1. The LM1086 is available in an adjustable version.45V.0V.4. It has the same pin-out as National Semiconductor’s industry standard LM317. The fixed versions integrate the adjust resistors.5V. 3. It is also available in five fixed voltages: 2.10. The LM1086 circuit includes a zener trimmed band-gap reference.2.5V at 1. 3. Connection Diagrams 14 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.5A Line Regulation 0.1.015% (typical) Load Regulation 0. LM1086 11.10.3V.com .85V. 3. current limiting and thermal shutdown.10. 2.5A of load current.11. 11.3V.45V and 5.

it is also available in five fixed voltages.com .2. and 5V. and Adjustable Versions • Space Saving SOT-223 Package • Current Limiting and Thermal Protection • Output Current 800mA • Line Regulation 0.3V.11. In addition.1.11.85V.11. The LM1117 series is available in SOT-223. which can set the output voltage from 1. TO-220. 5V. General Description The LM1117 is a series of low dropout voltage regulators with a dropout of 1. 11.4.3V. Applications • 2.11. 2.25V to 13. 1.3.8V with only two external resistors.11. The LM1117 is available in an adjustable version.2% (Max) • Load Regulation 0.11. LM1117 11. 2. 2.85V.5V. 2.4% (Max) • Temperature Range — LM1117 0°C to 125°C — LM1117I -40°C to 125°C 11.2V at 800mA of load current. A minimum of 10µF tantalum capacitor is required at the output to improve the transient response and stability. The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage accuracy to within ±1%. 3.pdffactory.8V.8V. and TO-252 D-PAK packages.5V. Connection Diagrams 15 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. 3. It has the same pin-out as National Semiconductor’s industry standard LM317.85V Model for SCSI-2 Active Termination • Post Regulator for Switching DC/DC Converter • High Efficiency Linear Regulators • Battery Charger • Battery Powered Instrumentation 11. Features • Available in 1.

12.11.1.12. Features Can deliver 2W without clipping at 12V/8Ω Internal fixed gain 20dB No boucherot cell Thermal protection AC short circuit protection SVR capacitor for better ripple Rejection Low turn-on/off pop Stand-by mode 11. Pin Connection 16 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. TDA7299 11. Thanks to the fully complementary output configuration the device delivers a rail voltage swing without need of boostrap capacitors.2.pdffactory.3.com .12.12. 11. Description The device TDA7299 is a new technology Mono Audio Amplifier in SO package specially designed for 12V sound cards application.

General Description The DS90C385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. The DS90C385 is also offered in a 64 ball. 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE. Negative LVDS differential data output.11.2. Using an 85 MHz clock. Ground pins for LVDS outputs. • Narrow bus reduces cable size and cost • Up to 2.5 Megabytes/sec bandwidth • 345 mV (typ) swing LVDS devices for low EMI • PLL requires no external components • Compatible with TIA/EIA-644 LVDS standard • Low profile 56-lead or 48-lead TSSOP package • DS90C385 also available in a 64 ball.13. FPFRAME. 17 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. Pin Description DS90C385 MTD56 (TSSOP) Package Pin Description-FPD Link Transmitter Pin Name TxIN TxOUT+ TxOUTTxCLKIN R_FB TxCLK OUT+ TxCLK OUTPWR DOWN Vcc GND PLL Vcc PLL GND LVDS Vcc LVDS GND I/O I O O I I O O I I I I I I I No. SVGA. 0. 8 Green. Pin name TxCLK IN. TTL level input. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.8mm fine pitch ball grid array (FBGA) package 11. Features • 20 to 85 MHz shift clock support • Best–in–Class Set & Hold Times on TxINPUTs • Tx power consumption <130 mW (typ) @85MHz Grayscale • Tx Power-down mode <200µW (max) • Supports VGA. 11. VSYNC. 8 Blue.38 Gbps throughput • Up to 297. Power supply pins for TTL inputs.13.pdffactory. Power supply pin for PLL. Programmable strobe select Positive LVDS differential clock output. 28 4 4 1 1 1 1 1 3 4 1 2 1 3 Description TTL level input. Power supply pin for LVDS outputs.1.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the TSSOP package.13. FPFRAME and DRDY (also referred to as HSYNC.5 Mbytes/sec. This includes: 8 Red.13. Data Enable). and 4 control lines —FPLINE. TTL Ievel clock input. 0. This chipset is an ideal means to solve EMI and cable size problems associated with wide. At a transmit clock frequency of 85 MHz. DS90C385 11. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386/DS90CF366) without any translation logic. Positive LVDS differentiaI data output. Ground pins for TTL inputs. Ground pins for PLL. Also available is the DS90C365 that converts 21 bits of LVCMOS/LVTTL data into three LVDS (Low Voltage Differential Signaling) data streams. Negative LVDS differential clock output. ensuring low current at power down. Both transmitters can be programmed for Rising edge strobe or falling edge strobe through a dedicated pin. DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Assertion (low input) TRI-STATES the outputs. high-speed TTL interfaces. XGA and Dual Pixel SXGA.com . the data throughput is 297.3.

Negative LVDS differential clock output.14. Ground pins for TTL inputs. Max : 4.0V.14. Positive LVDS differentiaI data output.3. Positive LVDS differential clock output. Pin name TxCLK IN.5V Vo(clip) : Min : 1400mVrms Min : 0. Ground pins for PLL. Pins not connected. TTL Ievel clock input.75V. General Description The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic package. Min : 3. Power supply pin for LVDS outputs. Power supply pins for TTL inputs.com . Pinning SYMBOL OUTA INA(neg) INA(pos) VSS INB(pos) INB(neg) OUTB VDD PIN 1 2 3 4 5 6 7 8 DESCRIPTION Output A (Voltage swing) Inverting input A Non-inverting input A Negative supply Non-inverting input B Inverting input B Output B (Voltage swing) Positive supply PIN VALUE Min : 0. 11. Max : 7. LOW = falling edge. TTL level input.DS90C385SLC SLC64A Package Pin Description-FPD Link Transmitter Pin Name TxIN TxOUT+ TxOUTTxCLKIN R_FB TxCLK OUT+ TxCLK OUTPWR DOWN Vcc GND PLL Vcc PLL GND LVDS Vcc LVDS GND NC I/O I O O I I O O I I I I I I I No. 28 4 4 1 1 1 1 1 3 5 1 2 2 4 6 Description TTL level input. Negative LVDS differential data output. HIGH = rising edge. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications. TDA1308 11.14. Max : 4. Assertion (low input) TRI-STATES the outputs. ensuring low current at power down.1. Programmable strobe select.75V. Ground pins for LVDS outputs.14.pdffactory. Features • Wide temperature range • No switch ON/OFF clicks • Excellent power supply ripple rejection • Low power consumption • Short-circuit resistant • High performance • high signal-to-noise ratio • High slew rate • Low distortion • Large output voltage swing. The rising edge acts as data strobe.25V 5V. 11.25V Vo(clip) : Min : 1400mVrms 2.5V 0V 2. Power supply pin for PLL.0V 18 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.2. 11.

15. SO-8.5V temperature compensation reference. Pin Configurations 19 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. wide operating current (150mA) and temperature range (0. TL431 acts as an open-loop error amplifier with a 2. °C to 105. The TL431 thermal stability. SOT-89 and SOT23-5 packages.15. The TL431 is operating in full industrial temperature range of 0°C to 105°C.11.to 105.°C • Low Temperature Coefficient 30 ppm /°C • Offered in TO-92.makes it suitable for all variety of application that are looking for a low cost solution with high performance. SOT-23-5 • Improved Replacement in Performance for TL431 • Low Cost Solution 11.1. The TL431 is available in TO-92. SOT-89.3.15. SOIC. The output voltage may be adjusted to any value between VREF and 36 volts with two external resistors.com .15. Description The TL431 is a 3-terminal adjustable shunt voltage regulator providing a highly accurate 1 % band gap reference. Features • Trimmed Band gap to 1% • Wide Operating Current 1mA to 150mA • Extended Temperature Range 0.pdffactory. 11.2. TL431 11.

512 x 8 (4K). The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. the entire family is available in 5. The AT24C16 does not use the device address pins. 20 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.16.7V (2. The Write Protect pin allows normal read/write operations when connected to ground (GND). Pin Configuration Pin Name A0 . 2. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. Filtered Inputs for Noise Suppression • Bi-directional Data Transfer Protocol • 100 kHz (1. Description The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/ 1024/2048 words of 8 bits each. 2.5V to 5. 1024 x 8 (8K) or 2048 x 8 (16K) • 2-wire Serial Interface • Schmitt Trigger. The A0 and A1 pins are no connects. (AT24C01A/02/04/08/16).5V to 5. 2. which limits the number of devices on a single bus to one. the write protection feature is enabled and operates as shown in the following table. The AT24C01A/02/04/08/16 is available in space-saving 8-pin PDIP. A1. The device is optimized for use in many industrial and commercial applications where low-power and lowvoltage operation are essential.5V to 5. 8K.8V. Features • Low-voltage and Standard-voltage Operation – 5. The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. 8-pin PDIP and 8-lead TSSOP Packages 11.com . 2. The A0. In addition.8V to 5.2. The A0 pin is a no connect.7 (V CC = 2.5V) – 2.16. As many as eight 1K/2K devices may be addressed on a single bus system.8V (1. 2K).5V (2. DEVICE/PAGE ADDRESSES (A2.16.16.5V) • Internally Organized 128 x 8 (1K). 16-byte Page (4K.11.5V).5V) – 1.7V to 5.1.7V) and 400 kHz (5V) Compatibility • Write Protect Pin for Hardware Data Protection • 8-byte Page (1K. WRITE PROTECT (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides hardware data protection. 24C16 11.8V to 5.16.5V). 11. 256 x 8 (2K). A1 and A2 pins are no connects.5V. When the Write Protect pin is connected to VCC. 16K) Write Modes • Partial Page Writes are Allowed • Self-timed Write Cycle (10 ms max) • High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years • Automotive Grade and Extended Temperature Devices Available • 8-lead JEDEC SOIC.5 (V CC = 2. 8-lead TSSOP (AT24C01A/02/04/08/16) and 8-lead JEDEC SOIC (AT24C01A/ 02/04/08/16) packages and is accessed via a 2-wire serial interface. A0): The A2.8 (V CC = 1.0 (V CC = 4. A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02.7V to 5.4.pdffactory.5V) – 2.5V) and 1.5V) versions.3.A2 SDA SCL WP NC Function Address Inputs Serial Data Serial Clock Input Write Protect No Connect 11.5V to 5.0V (4.

to be pulled up. pulled down for normal operation. 21 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. Through an I C interface. In addition.6~2. 110MHz) • 0.3V power with 5V tolerant I/O and low power dissipation. General Features • High speed 8-bit ADC up to 110MHz conversion rate • Support display resolution up to 1280x1024 at 60Hz refresh rate • Low power dissipation (0.3 volt power with 5 volt tolerant I/O • 100-pin 14x20 mm PQFP package 11. The sampling clock is provided by an external clock source. the input active horizontal and vertical starting and ending positions can be detected to ensure that the whole picture fits into the displayable region of the 2 screen.pdffactory. the AL875 is fully programmable to support various graphic resolution s. Pin Definition and Description AL875 TESTIN3 TESTIN2 TESTIN1 TESTIN0 VDD VRBR VNR VRTR NC NC VDDAR RIN GNDAR VRBG VNG VRTG NC NC VDDAG GIN GNDAG VRBB VNB VRTB NC NC VDDAB BIN GNDAB ADTEST3 CKINTEN Type IN (CMOS) IN (CMOS) IN (CMOS) IN (CMOS) POWER IN IN IN --POWER IN GROUND IN IN IN --POWER IN GROUND IN IN IN --POWER IN GROUND IN (CMOSu) IN (CMOSd) Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Description Test signal input 3.17.3. The AL875 uses 3. Test pin.6~2. Its 110 MHz conversion rate can support display resolution of up to 1280x1024 at 60Hz refresh rate.0V p-p analog input range • 10k~1MHz CKREF locking range 2 • Full programmability via I C interface • Automatic screen position support • Programmable clock phase adjustment • TTL compatible digital inputs and outputs • High impedance tri-state output • Power-down mode • Single 3.3V. AL875 11. can be left open. The AL875 provides a programmable PLL divider up to 4096. Test signal input 0. can be left open. which multiplies the frequency of the input reference clock (usually a HSYNC signal) to generate the sampling clock.com . General Description The AL875 is a high-speed triple 8-bit monolithic analog-to-digital converter (ADC) designed for digitizing RGB graphics/video signal or other applications. can be left open. The AL875 accepts 0. Digital power supply Red channel bottom voltage reference Red channel comparator voltage reference Red channel top voltage reference Not connected Not connected Red channel analog power supply Red channel analog input Red channel analog ground Green channel bottom voltage reference Green channel comparator voltage reference Green channel top voltage reference Not connected Not connected Green channel analog power supply Green channel analog input Green channel analog ground Blue channel bottom voltage reference Blue channel comparator voltage reference Blue channel top voltage reference Not connected Not connected Blue channel analog power supply Blue channel analog input Blue channel analog ground Internal ADC test pin 3. can be left open. usually a PLL. 11.2.9W typical at 3.11. Test signal input 2.1.17.0V analog input range without using pre-amplifiers which may reduce the overall S/N ratio.17.17. Test signal input 1. Digitized data is piped at the full clock rate to the 24-bit output port.

Internal ADC test pin 2. Used with optional external PLL Horizontal sync input The invert control of the ADC sampling clock External clock input 22 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.pdffactory. Reserved for AL876 PLL digital ground. to be pulled down. to be pulled down. Reserved for AL876 PLL digital power supply. HI: internal PLL clock) NC I2C address control input 1 I2C address control input 2 Internal ADC test pin 1. to be pulled up Reset pin (active LOW) Red channel ADC output overflow Green channel ADC output overflow Blue channel ADC output overflow Blue channel ADC output ground Blue channel ADC output bit 0 Not connected Not connected Blue channel ADC output bit 1 Blue channel ADC output bit 2 Blue channel ADC output bit 3 Blue channel ADC output bit 4 Blue channel ADC output bit 5 Blue channel ADC output bit 6 Blue channel ADC output bit 7 Blue channel ADC output power supply Green channel ADC output ground Green channel ADC output bit 0 Green channel ADC output bit 1 Green channel ADC output bit 2 Green channel ADC output bit 3 Green channel ADC output bit 4 Green channel ADC output bit 5 Green channel ADC output bit 6 Green channel ADC output bit 7 Green channel ADC output power supply Red channel ADC output ground Red channel ADC output bit 0 Red channel ADC output bit 1 Red channel ADC output bit 2 Red channel ADC output bit 3 Red channel ADC output bit 4 Red channel ADC output bit 5 Red channel ADC output bit 6 Red channel ADC output bit 7 Red channel ADC output power supply PLL Reference clock output with phase adjustment from CKREF. Not connected Not connected I2C serial data input/output Logic digital power supply Logic digital ground I2C serial clock input Test signal input 4. the outputs are in HI-Z) Power-Down control (Active HIGH) Clock feedback divider output. Output clock A (in phase with the internal digital logic clock) Digital ground. Output clock B (with phase adjustment) ADC sampling clock (in phase with the ADC sampling clock) Digital power supply.com . Suggested to be separated from the other VDD pins with a ferrite bead for AL876 compatibility Digital ground Output enable (when OE is HIGH. Usually used for external PLL reference input.RCLAMP ADDR1 ADDR2 ADTEST1 ADTEST2 NC NC SDA VDD GND SCL TESTIN4 /RESET ROF GOF BOF GNDB BOUT0 GCLAMP BCLAMP BOUT1 BOUT2 BOUT3 BOUT4 BOUT5 BOUT6 BOUT7 VDDB GNDG GOUT0 GOUT1 GOUT2 GOUT3 GOUT4 GOUT5 GOUT6 GOUT7 VDDG GNDR ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 ROUT6 ROUT7 VDDR CKREFO CKAO GNDPLL CKBO CKADCO VDDPLL OUT (CMOSt) IN (CMOSd) IN (CMOSd) IN (CMOSd) IN (CMOSd) --INOUT (CMOSsu) POWER GROUND IN (CMOSs) IN (CMOSd) IN (CMOSu) OUT (CMOS) OUT (CMOS) OUT (CMOS) GROUND OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) POWER GROUND OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) POWER GROUND OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) OUT (CMOSt) POWER OUT (CMOS) OUT (CMOS) GROUND OUT (CMOS) OUT (CMOS) POWER 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 GND /OE PWRDN HSFB HSYNC INV CKEXT GROUND IN (CMOS) IN (CMOSd) OUT (CMOS) IN (CMOS) IN (CMOSd) IN (CMOS) 86 87 88 89 90 91 92 Reserved for AL876 internal clock enable (LO: external clock.

18.3. 16. 11. Reserved for AL876 PLL analog power supply. Reserved for AL876 PLL analog ground. General Features • High speed: t PD = 10ns (typ. Pin Description Pin no 1 2.VSYNC CKREF VDD GNDAPLL CP NC VDDAPLL IN (CMOS) IN (CMOS) POWER GROUND IN -POWER 93 94 95 96 97 98 99 GND GROUND 100 Vertical sync input PLL reference clock input Digital power supply Analog ground. This device is designed to be used with 3 state memory address drivers. etc. Description The 74HC244 is an advanced high-speed CMOS OCTAL BUS BUFFER (3-STATE) fabricated with silicon gate C2MOS technology.1. 15. 17 18. G control input governs four BUS BUFFERs.18.) • Symmetrical output impedance: |I OH |=IOL = 6mA (min) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating voltage range: VCC(Opr) = 2V to 6V • Pin and function compatible with 74 series 244 11. Reserved for AL876 PLL filter input. 14. Suggested to be separated from the other VDD pins with a ferrite bead for AL876 compatibility Digital ground 11.2.com . 8 9. 74HC244A 11. Not connected Analog power supply. 6. All inputs are equipped with protection circuits against static discharge and transient excess voltage.18. 12 19 10 20 Symbol 1G 1A1 to 1A4 2Y1 to 2Y4 2A1 to 2A4 1Y1 to 1Y4 2G GND VCC Name and function Output Enable Input Data Inputs Data Outputs Data Inputs Data Outputs Output Enable Input Ground (0V) Positive Supply Voltage 23 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. 5. Internal compensation pin.18. 4. 7. 13. Please follow the reference design for external RC filter circuitry. 3 11.) at VCC =6V • Low power dissipation: ICC =4μA (max) at TA =25°C • High noise immunity: V NIH =VNIL =28%VCC (min.pdffactory.

2.1. ICS1523 11. Features • Pixel clock frequencies up to 250 MHz • Very low jitter • Dynamic Phase Adjust (DPA) for clock outputs • Balanced PECL differential outputs • Single-ended SSTL_3 clock outputs • Double-buffered PLL/DPA control registers • Independent software reset for PLL/DPA • External or internal loop filter selection • Uses 3.19. Inputs are 5 V-tolerant.com .3 Vdc. Using ICS ’s advanced low-voltage CMOS mixed-mode technology. The advanced PLL uses either its internal programmable feedback divider or an external divider. the ICS 1523 is an effective clock solution for video projectors and displays at resolutions from VGA to beyond UXGA. Dynamic Phase Adjust™ circuitry allows user control of the pixel clock phase relative to the recovered sync signal. 2 • I C-bus™ serial interface can run at either low speed (100 kHz) or high speed (400 kHz). The ICS 1523 offers pixel clock outputs in both differential (to 250 MHz) and single-ended (to 150 MHz) formats. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output or a re-synchronized and sharpened input HSYNC. • Lock detection • 24-pin 300-mil SOIC package 24 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.19. A second differential output at half the pixel clock rate enables deMUXing of multiplexed analog-to-digital converters. 11.pdffactory. The device is programmed by a standard I 2C-bus™ serial interface and is available in a 24-pin small-outline integrated circuit (SOIC) package.11. Description The ICS 1523 is a low-cost but very high-performance frequency generator for line-locked and genlocked high-resolution video applications.19.

Pin connections 25 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. 11. driver and high current output switch. These devices consist of an internal temperature compensated reference.20.com . This series was specifically designed to be incorporated in Step–Down and Step–Up and Voltage–Inverting applications with a minimum number of external components.20. comparator. controlled duty cycle oscillator with an active current limit circuit.11. MC34063 11.20.20.5 A • Output Voltage Adjustable • Frequency Operation to 100 kHz • Precision 2% Reference 11.1. Description The MC34063A Series is a monolithic control circuit containing the primary functions required for DC–to– DC converters.0 V to 40 V Input • Low Standby Current • Current Limiting • Output Switch Current to 1.pdffactory. Features • Operation from 3.3.2.

9.0 and 6.9. PC and set-top box applications. 11. The TDA9886 is an alignment-free multistandard (PAL. AFC bits 2 via I C -bus readable 2 • TakeOver Point (TOP) adjustable via I C-bus or alternatively with potentiometer • Fully integrated sound carrier trap for 4.4. 13. TAGC REF VAGC CVBS AGND VPLL VP AFC OP2 SIF1 SIF2 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESCRIPTION VIF differential input 1 VIF differential input 2 output 1 (open-collector) FM-PLL for loop filter de-emphasis output for capacitor AF decoupling input for capacitor digital ground audio output tuner AGC TakeOver Point (TOP) 2 I C-bus data input/output I2C-bus clock input sound intercarrier output and MAD select not connected tuner AGC output 4 MHz crystal or reference input VIF-AGC for capacitor (Not connected for TDA9885) video output analog ground VIF-PLL for loop filter supply voltage (+5 V) AFC output output 2 (open-collector) SIF differential input 1 SIF differential input 2 26 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.com . reduced harmonics. 45. 13. switchable via I 2C-bus • AM demodulator without extra reference circuit • Alignment-free selective FM-PLL demodulator with high linearity and low noise • I2C-bus control for all functions • I2C-bus transceiver with pin programmable Module Address (MAD). operating as peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals • Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analog converter. alignment-free.21.Features • 5 V supply voltage • Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled) • Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation. frequencies switchable for all 2 negative and positive modulated standards via I C-bus • Digital acquisition help. single reference QSS mixer able to operate in high performance single reference QSS mode and in intercarrier mode.2. 5.75 and 58.Pinning SYMBOL VIF1 VIF2 OP1 FMPLL DEEM AFD DGND AUD TOP SDA SCL SIOMA n.3.pdffactory.13. VTR.5. Both devices can be used for TV. General description The TDA9885 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL. 38. controlled by FM-PLL oscillator • Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL controlled) • SIF AGC for gain controlled SIF amplifier.75 MHz • 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating as crystal oscillator • VIF Automatic Gain Control (AGC) detector for gain control.21. 38.13.2. good intermodulation figures.3.5 MHz. 6.0. excellent pulse response) • Gated phase detector for L/L accent standard • Fully integrated VIF Voltage Controlled Oscillator (VCO). VIF frequencies of 33. TDA9885/86 11. 33.c.1.11.5.21. 11.21. SECAM and NTSC) vision and sound IF signal PLL demodulator for positive and negative modulation including sound AM and FM processing.

1. I2S_WS: The I2S_WS word strobe line defines the left and right sample. no I²C interaction is necessary (Automatic Sound Selection). I2S_CL: Gives the timing for the transmission of I S serial data (1. This new generation of TV sound processing ICs now includes versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC).22. loudness • AVC: Automatic Volume Correction 27 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. The full TV sound processing. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard. The MSP 34x0G further simplifies controlling software. The MSP 34x0G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). All MSP 34x0G versions are pin and software downward compatible to the MSP 34x0D.pdffactory. MSP34X0G MSP3400G Multistandard Sound Processor Family 11.com . The DBX noise reduction. I2S_DA_IN1.22. is performed on a single chip. MICRONAS Noise Reduction (MNR) is performed alignment free. Figure shows a simplified functional block diagram of the MSP 34x0G. balance. 2*16 bits) per sampling cycle (32 kHz) are transmitted. new registers MODUS. Source Select 2 I S bus interface consists of five pins: 1. down to processed analog AF-out.11. starting with analog sound IF signal-in. 2 3.22. Features 2 • Standard Selection with single I C transmission • Automatic Standard Detection of terrestrial TV standards • Automatic Sound Selection (mono/stereo/bilingual). Introduction The MSP 34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide. 2. as well as the NICAM digital sound standards. I2S_DA_OUT: For output. or alternatively. Furthermore. four channels (two channels per line.024 MHz). The MSP 34x0G has optimum stereo performance without any adjustments. 11. I2S_DA_IN2: For input. Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. treble. Standard selection requires a single I²C transmission only. bass.2. pilot levels and identification signals can be evaluated internally with subsequent switching between mono/stereo/bilingual. 4. two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted. STATUS • Two selectable sound IF (SIF) inputs • Automatic Carrier Mute function • Interrupt output programmable (indicating status change) • Loudspeaker / Headphone channel with volume.

22. left Analog Shield Ground 1 SCART 2 input. one Mono input. Pin connections NC = not connected. leave vacant LV = if not used. PLCC 68-pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 PSDIP 64-pin 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 60 PSDIP 52-pin 14 13 12 11 10 9 8 7 6 5 4 3 2 1 52 51 50 49 PQFP 80-pin 9 8 7 6 5 4 3 2 1 80 79 78 77 76 75 74 73 72 71 70 69 PLQFP 64-pin 8 7 6 5 4 3 2 1 64 63 62 61 60 59 58 57 56 55 54 53 52 Pin Name Type Connection (if not used) Short Description ADR_WS NC ADR_DA I2S_DA_IN1 I2S_DA_OUT I2S_WS I2S_CL I2C_DA I2C_CL NC STANDBYQ ADR_SEL D_CTR_I/O_0 D_CTR_I/O_1 NC NC NC AUD_CL_OUT TP XTAL_OUT XTAL_IN TESTEN ANA_IN2+ OUT OUT IN OUT IN/OUT IN/OUT IN/OUT IN/OUT IN IN IN/OUT IN/OUT LV LV LV LV LV LV LV OBL OBL LV OBL OBL LV LV LV LV LV LV LV OBL OBL OBL AVSS via 56 pF/LV AVSS via 56 pF/LV LV OBL OBL LV LV OBL OBL LV LV OBL OUT OUT IN IN IN 24 25 26 27 28 29 30 31 32 33 59 58 57 56 55 54 53 52 51 50 48 47 46 45 44 43 42 41 40 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 51 50 49 48 47 46 45 44 43 42 ANA_INANA_IN1+ AVSUP AVSUP NC NC AVSS AVSS MONO_IN NC VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R IN IN IN IN IN IN LV LV AHVSS LV ADR word strobe Not connected ADR Data Output I2S1 data input I2S data output I2S word strobe I2S clock I2C data I2C clock Not connected Stand-by (low-active) I2C bus address select D_CTR_I/O_0 D_CTR_I/O_1 Not connected Not connected Not connected Audio clock output (18. leave vacant OBL = obligatory. right 28 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.pdffactory. two Stereo SCART outputs • Complete SCART in/out switching matrix • Two I2S inputs. only if IF input 1 is also not in use) IF input 1 Analog power supply 5V Analog power supply 5V Not connected Not connected Analog ground Analog ground Mono input Not connected Reference voltage IF A/D converter SCART 1 input. right SCART 1 input. acc. to ASTRA specification) • ASTRA Digital Radio (ADR) together with DRP 3510A • All NICAM standards • Korean FM-Stereo A2 standard 11. one I 2S output • Dolby Pro Logic with DPL 351xA coprocessor • All analog FM-Stereo A2 and satellite standards. AM-SECAM L standard • Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM • Adaptive deemphasis for satellite (Wegener-Panda.• Subwoofer output with programmable low-pass and complementary high-pass filter • 5-band graphic equalizer for loudspeaker channel • Spatial effect for loudspeaker channel • Four Stereo SCART (line) inputs. connect to DVSS AHVSS: connect to AHVSS Pin No.3.432 MHz) Test pin Crystal oscillator Crystal oscillator Test pin IF Input 2 (can be left vacant. connect as described in circuit diagram DVSS: if not used.com . only if IF input 1 is also not in use) IF common (can be left vacant.

right Reference ground 2 Headphone out.34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SC2_IN_L ASG2 SC3_IN_R SC3_IN_L ASG4 SC4_IN_R SC4_IN_L NC AGNDC AHVSS AHVSS NC NC CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L DACA_R NC NC RESETQ NC NC NC I2S_DA_IN2 DVSS DVSS DVSS DVSUP DVSUP DVSUP ADR_CL IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT IN IN OUT LV AHVSS LV LV AHVSS LV LV LV or AHVSS OBL OBL OBL LV LV OBL OBL OBL LV LV OBL LV LV LV LV LV LV LV LV OBL LV LV LV LV OBL LV LV LV LV OBL OBL OBL OBL OBL OBL LV SCART 2 input. left Headphone out. left Analog Shield Ground 4 SCART 4 input. left Not connected Analog reference voltage Analog ground Analog ground Not connected Not connected Volume capacitor MAIN Analog power supply 8V Volume capacitor AUX SCART output 1. left Analog Shield Ground 2 SCART 3 input. right SCART 4 input. left Loudspeaker out. left SCART output 2. right Not connected Not connected Power-on-reset Not connected Not connected Not connected I2S2-data input Digital ground Digital ground Digital ground Digital power supply 5V Digital power supply 5V Digital power supply 5V ADR clock 29 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. left SCART output 1. right SCART 3 input.com . right Not connected Not connected Subwoofer output Not connected Loudspeaker out. right Reference ground 1 SCART output 2.pdffactory.

1. (ODN): output with open drain n-channel transistor (OD3): output 3-state 30 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. 14.22.22.3.23. 14.23. SAA3010T 11.2.23. The device can generate 2048 different commands and utilizes a keyboard with a single pole switch for each key. each system containing 64 different commands. (IPU): input with p-channel pull-up transistor. The commands are arranged so that 32 systems can be addressed.2. 11. The circuit response to legal (one key pressed at a time) and illegal (more than one key pressed at a time) keyboard operation is specified in the section “Keyboard operation”.Pinning Pin 1 2 3 7 8 9-13 14 15-17 18 19 20 21-27 28 Mnemonic X7 (IPU) SSM (I) Z0-Z3 (IPU) MDATA (OP3) DATA (OP3) DR7-DR3 (ODN) VSS DR-2-DR0 (ODN) OSC (I) TP2 (I) TP1 (I) X0-X6 (IPU) VDD(I) Function sense input from key matrix sense mode selection input sense inputs from key matrix generated output data modulated with 1/12 the oscillator frequency at a 25% duty factor generated output information Scan drivers Ground (0V) Scan drivers Oscillator input test point 2 Test point 1 Sense inputs from key matrix Voltage supply Note: (I): Input.23.1.Description The SAA3010 is intended as a general purpose (RC-5) infrared remote control system for use where a low voltage supply and a large debounce time are expected.3.11. 14.22.Features Low voltage requirement Biphase transmission technique Single pin oscillator Test mode facility 11.pdffactory.com .

Position: Vertical Position Adjusts the vertical positon of the screen.12. Before starting the production mode alignments. Value: 0000 Max. move the cursor to Adjust… parameter by pressing “P+/P-“ buttons in Service Menu and press “VOL+/VOL-“ button. Position Vert. Service Adjust. Min. Value: 0063 Recommended Value: 0009 Vert . The following menu appears on the screen.. Value: Recommended Value: 0000 0063 0063 31 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www.. Value: 0020 Max. SERVICE MENU SETTINGS All system.buttons remaining items can be seen.1. make sure that all manual adjustments are done correctly. The following menu appears on the screen. To start production mode alignments enter the MAIN MENU and then press the digits 4. you can access its items by pressing “P+/P-“ buttons. In order to enter selected menu. Horiz. Adjust.0.. Entire service menu parameters of TFT TV are listed below.12. Aps Wss Test LCDTFT33 4. Horiz . Using VOL+/VOL. Value: 0242 Recommended Value: 0167 Active Width Adjusts the width of the screen. Border Vert. but 10 of them are seen when you first enter the menu. 12. Options. Position Active Width Active Height Horiz.com . Total Horiz. use “VOL+/VOL-“ buttons.. geometry and white balance alignments are performed in production service mode. 7. Value: Max. Min.pdffactory. Border Hsync Phase Auto Position Resolution 0028 There are 14 items in the ADJUST menu. After entering the Service menu. 2 and 5 respectively. Min.. Position: Horizontal Position Adjusts the horizontal positon of the screen. ADJUST MENU SETTINGS In order to enter Adjust menu. To exit the service menu press “MENU” button..

Border: Horizontal Border Adjusts the thickness of the horizontal border. Total: Horizontal Total Min. Store Stores the entered adjust menu values.Active Height Adjusts the height of the screen. Min. Horiz. Value: Recommended Value: Auto Position Resolution Value: Total Value: Adjust. Value: Recommended Value: Horiz . Border Hsync Phase Auto Position Resolution Total V Freq Reset Store 0000 0015 0000 - 1024*0236 1142*0262 0028 V Freq Value: Reset Resets the adjust menu values. Border: Vertical Border Adjusts the thickness of the vertical border. Value: Max. Value: 0255 Recommended Value: 0000 Hsync Phase Min. Value: Recommended Value: 0000 0063 0063 0000 0063 0028 Horiz . Border Vert.. Value: Max. Min.com . Min. Value: Max. Value: 0000 Max. 0060 32 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. Value: 0000 Max.. Value: 0255 Recommended Value: 0000 Vert .pdffactory. Total Horiz.

.S. Headphone Vsr DBE Subwoofer Lineout Dolby prologic Equalizer 000: On There are 50 items in the OPTIONS menu.. but 10 of them are seen when you first enter the menu.OPTIONS MENU SETTINGS In order to enter Options menu. Hue First APS A. Set ON Headphone On/Off enable/disable the usage of the HP and HP related items in sound menu. Options. Set OFF Equalizer On/Off enable/disable equalizer system. Set OFF 33 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. Set ON Dolby prologic On/Off enable/disable dolby prologic system.pdffactory. Set OFF Subwoofer On/Off enable/disable Subwoofer. Set OFF Lineout On/Off enable/disable Lineout. move the cursor to Options… parameter by pressing “P+/P-“ buttons in Service Menu and press “VOL+/VOL-“ button. Using P+/P. Set OFF A. Set OFF DBE On/Off enable/disable DBE. Set ON Vsr On/Off enable/disable Vsr.P. Hue Set ON On/Off First APS On/Off If ON. Set ON DK On/Off enable/disable DK Standard.com . TV starts with APS menu at Start-up. The following menu appears on the screen.S On/Off enable/disable Automatic Programming System.buttons remaining items can be seen. Set ON BG On/Off enable/disable BG Standard.P.

Set OFF NM On/Off enable/disable M Standard.0 Equ Coe. Equalizer BG DK I L L’ M N NM FM Prs Avl On 009: On I On/Off enable/disable I Standard. Value: 0000 00000 Max.pdffactory. Value: 00FF 00255 Recommended Value: 000F 00015: for 4 ohm Recommended Value: 0011 00017: for 8 ohm Options.. FM Prs Avl On Nicam Prs Avl On Scart Prs Avl On Scart Volume Avl On FM Prs Avl Off Nicam Prs Avl Off Scart Prs Avl Off Scart Volume Avl Off Equ Coe.. Set OFF M On/Off enable/disable M Standard. Set OFF FM Prs Avl On Adjusts the FM Prescaler value. Set OFF L/L’ On/Off enable/disable L/L’ Standard..1 018: 000F 00015 34 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. Set OFF N On/Off enable/disable N Standard.Options.com .. when Automatic Volume Levelling is On Min.

Value: 00FF 00255 Recommended Value: 0008 00008: for 4 ohm Recommended Value: 000A 00010: for 8 ohm Nicam Prs Avl Off Adjusts the Nicam Prescaler value. when Automatic Volume Levelling is On Min. Value: Max. Value: 0000 00000 Max.com . when Automatic Volume Levelling is Off Min. Value: 00FF 00255 Recommended Value: 0035 00053: for 4 ohm Recommended Value: 0035 00053: for 8 ohm Equ Coe. Value: 00FF 00255 Recommended Value: 0013 00019: for 4 ohm Recommended Value: 0017 00023: for 8 ohm Scart Prs Avl Off Adjusts the Scart Prescaler value. Value: Recommended Value: 0000 FFFF FFFF 00000 65535 65535 0000 FFFF FFFF 00000 65535 65535 35 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. when Automatic Volume Levelling is On Min. Value: Recommended Value: Equ Coe. when Automatic Volume Levelling is Off Min. Value: 0000 00000 Max. Value: 00FF 00255 Recommended Value: 0008 00008: for 4 ohm Recommended Value: 0009 00009: for 8 ohm Scart Volume Avl Off Adjusts the Scart Volume value. Value: 00FF 00255 Recommended Value: 0022 00034: for 4 ohm Recommended Value: 0028 00040: for 8 ohm Scart Prs Avl On Adjusts the Scart Prescaler value. Value: 0000 00000 Max. Value: 00FF 00255 Recommended Value: 0035 00053: for 4 ohm Recommended Value: 0035 00053: for 8 ohm FM Prs Avl Off Adjusts the FM Prescaler value. when Automatic Volume Levelling is Off Min. when Automatic Volume Levelling is Off Min. when Automatic Volume Levelling is On Min.0 Min.Nicam Prs Avl On Adjusts the Nicam Prescaler value. Value: 00FF 00255 Recommended Value: 000F 00015: for 4 ohm Recommended Value: 0010 00016: for 8 ohm Scart Volume Avl On Adjusts the Scart Volume value. Value: 0000 00000 Max.pdffactory. Value: 0000 00000 Max.1 Min. Value: 0000 00000 Max. Value: 0000 00000 Max. Value: Max.

3 Min.2 Equ Coe. Set ON Top TXT On/Off enable/disable Top TXT.pdffactory. Set ON Carrier On/Off enable/disable Carrier. Set ON.. Value: Max. Value: Recommended Value: Equ Coe. Set ON 0000 00FF 0000 00000 00255 00000 36 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. Value: Max. Value: 0000 00000 Max.2 Min. Value: Max. Set ON RC_1541 On/Off Enables/disables Remote control usage for Service menu. Value: Recommended Value: Sound On/Off enable/disable Sound. Value: 0004 00004 Recommended Value: 0000 00000 IF Freq Adjusts the IF Frequency Min.Options. Equ Coe.. Value: Recommended Value: 0000 FFFF FFFF 00000 65535 65535 0000 FFFF FFFF 00000 65535 65535 Avl On/Off enable/disable Automatic Volume Levelling System. Set ON TXT Lang Switches between Teletext Language Groups Min. Set OFF Fast TXT On/Off enable/disable Fast TXT.com .3 Avl Top TXT Fast TXT TXT Lang IF Freq Sound Carrier 027: FFFF 65535 Equ Coe. AV-1 On/Off enable/disable AV-1.1 Equ Coe.

Set OFF. Set ON S-VHS On/Off enable/disable S-VHS. Value: Max. Set ON RGB On/Off enable/disable RGB.com . Set ON PC On/Off enable/disable PC.. S-VHS RGB MENU CB BV1 BV3 BU V1-V3 V3_U AGC 050: FFFF 65535 MENU On/Off enable/disable semi-transparent MENU.Options. CB Min..pdffactory. Value: Recommended Value: BV1 Min. Value: Recommended Value: 00000000 11111111 00001101 00000000 11111111 00001101 37 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. Carrier RC_1541 AV-1 AV-2 PC S-VHS RGB MENU CB BV1 036: On AV-2 On/Off enable/disable AV-2. Value: Max.. Set ON Options..

Min. Value: Recommended Value: V3_U Min. The following menu appears on the screen. Value: 001F 00031 Recommended Value: 000A 00010 12.pdffactory. Programme Search VPS Pdc Format 1 Pdc Format 2 Name Wss 38 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. Value: Recommended Value: 00000000 11111111 00001101 00000000 11111111 00001101 0000 FFFF 0D0D 00000 65535 03341 0000 FFFF 0D0D 00000 65535 03341 AGC Adjusts the Automatic Gain Control value. Value: Max. Aps Wss Test Programme Search VPS Pdc Format 1 Pdc Format 2 Name Wss P 08 CNN S 04 BG 463 There are 7 items in the Aps Wss Test menu.button. Value: Recommended Value: BU Min. APS WSS TEST MENU In order to enter Aps Wss Test menu. Value: Recommended Value: V1-V3 Min. move the cursor to Aps Wss Test parameter by pressing P+/Pbuttons in Service Menu and press VOL+/VOL. Value: Max.2. Value: Max. Value: 0000 00000 Max.com .BV3 Min. Value: Max.

pdffactory.13. Hsync Vsync PLL IC ICS 1523 ICS SDA SCL SDA5555 MCU Micronas I2C DDC IC 24LC21 ST Graphics RGB VGA PC Graphics Option 39 15” TFT TV Service Manual 24/10/2003 PDF created with FinePrint pdfFactory trial version http://www. ST TDA7299 Audio Amp. BLOCK DIAGRAM Audio_L QSS Scart_Audio_In AV_Audio In Audio_Out MSP3410G Audio Processor Micronas TDA7299 Audio Amp. FB Micronas 24-bit RGB 4:4:4 AL 300 LCD Cont. FB Selected Video AL 875 Triple ADC Averlogic RGB. ST Audio_R Tuner UV1316 Philips IF IC TDA988X Philips CVBS_IF CVBS_scart CVBS_FAV VPC 3230 16-bit YUV 4:2:2 S-Video Video Pro. Averlogic 3x8 bit RGB 90C385 LVDS Tx National LVDS 15”TFT PANEL Text RGB.com . RGB. FB Video Output Text RGB.

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