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Logic Delay

Peter Kogge Joseph Nahas

University of Notre Dame Fall 2010 Modified and rearranged from original 2008 slides by Jay Brockman Based on lecture slides by David Harris, Harvey Mudd College http://www.cmosvlsi.com/coursematerials.html

CMOS VLSI Design

Capacitance Effective Resistance RC Delay Inverter Delay The Elmore Model Effect of Load Capacitance

Logic Delay

Slide 2

CMOS R and C

Gate Capacitance

Source/Drain Capacitance

Channel On-Resistance

Req

A A

Logic Delay CMOS VLSI Design

Slide 3

Capacitance

Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion

Logic Delay

Slide 4

Gate Capacitance

Approximate channel as connected to source Cgs = oxWL/tox = CoxWL = CpermicronW proportional to width Cpermicron = ox(L/tox) typically ~2 fF/m of gate width L and tox both scale with process Often just Cg

polysilicon gate W tox n+ L p-type body

Logic Delay CMOS VLSI Design Slide 5

Cgs

n+

Diffusion Capacitance

Csb, Cdb = source/drain to bulk Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Comparable to Cg for contacted diff Cg for uncontacted Cdb Varies with process Cdb Often just Cd

Csb Cdb Csb Cdb Csb

Logic Delay

Slide 6

RC Delay Model

Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width k Resistance inversely proportional to width k

d R/k g kC s kC kC d k s kC kC d

CMOS VLSI Design Slide 7

kC 2R/k

d k s

Logic Delay

NMOS

NMOS

Logic Delay

Output of 1st gate sees aggregate input capacitance of 2nd Termed Load Capacitance CL

CMOS VLSI Design

Slide 8

Between Cells

Rp A Rn A CL

Logic Delay

Slide 9

Vin Rp Vout

Rn

CL

Logic Delay

Slide 10

Vin Rp Vout

Rn

CL

Logic Delay

Slide 11

Vin Rp Vout

Rn

CL

Logic Delay

Slide 12

Vin Rp Vout

Rn

CL

Logic Delay

Slide 13

Solving

How long does it take to discharge the output from starting voltage V0 to voltage V1?

Kirchhoffs current law at output

Rp V IR Rn IC CL

Logic Delay CMOS VLSI Design Slide 14

Definitions

Waveform Rise time tr = time to rise from 20% of Vdd to crossing 80% of Vdd Fall time tf = time fall from 80% of Vdd to crossing 20% of Vdd Edge Rate trf = (tr + tf)/2 Logic gate input to output Propagation delay tpd = max time from input crossing 50% of Vdd to output crossing 50% of Vdd tpdr = delay when input is rising

tpHL = delay when output goes from High to Low

tpLH = delay when output goes from Low to High

Delay tp = (tpHL + tpLH)/2 Contamination delay tpd = min time from input crossing 50% of Vdd to output crossing 50% of Vdd

Logic Delay

Slide 15

Delay Definitions

Vin Vin

Propagation delay input waveform

50%

Vout

tp = (tpHL + tpLH)/2 t

80% 50% 20%

tpHL Vout

output waveform

tpLH

signal slopes

tf

Logic Delay CMOS VLSI Design

tr

t

Slide 16

Vin Vout

Vin

Vout

V0 = Vdd V1 = Vdd/2 t t0

Logic Delay

t1

CMOS VLSI Design Slide 17

Effective Resistance

Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace Ids(Vds, Vgs) with effective resistance R Ids = Vds/R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay

Logic Delay

Slide 18

Switching Voltages

Vgs

Vds

Vgs

Vds

Slide 19

Logic Delay

2.5 2

X 10-4

VDD/2

3VDD/4

VDD

VGS = 2.5V

ID (A)

R2

Req

R1

VGS = 2.0V VGS = 1.5V VGS = 1.0V

1.5

2.5

VDS (V)

Slide 20

Logic Delay

Approximating RON

Logic Delay

Slide 21

RC Values

Capacitance C Cg Csb Cdb 2 fF/m of gate width Values similar across many processes for minimal gate length. VDD Resistance 0.6 m: 5 V 0.35 m: IDsat 550 A/m 0.25 m: VDD 0.18 m: Req 0.75 VDD/Idsat 130 nm: 90 nm: 1.2 V Req 7 K*m in 0.6 m process Req 2 K*m in 90 nm process Unit transistors May refer to minimum contacted device (4/2 ) Or maybe 1 m wide device Doesnt matter as long as you are consistent

Logic Delay CMOS VLSI Design Slide 22

Estimate the delay of a fanout-of-1 inverter

2 Y 1

2 1

Logic Delay

Slide 23

Assume input going Low to High

2C R 2C 2C Y 1 R C C

2 Y 1

Logic Delay

Slide 24

Estimate the delay of a fanout-of-1 inverter

2C R 2C 2C Y 1 R C R C C C 2C 2C

2 Y 1

Logic Delay

Slide 25

Estimate the delay of a fanout-of-1 inverter

2C R 2C 2C Y 1 R C R C C C 2C 2C

2 Y 1

What is Aggregate C?

d 6RC

Logic Delay CMOS VLSI Design Slide 26

Estimate the delay of a fanout-of-1 inverter

2C R 2C 2C Y 1 R C R C C C 2C 2C

2 Y 1

Logic Delay CMOS VLSI Design Slide 27

1 2 3

In

54

In

1 27

Out

2 1

6 3

18 9

54

Out

27

4 2

8 4

16 8

32 16

54

In

1 27

Out

Logic Delay CMOS VLSI Design Slide 28

Delay Case 1

54C

27C

d = 84 RC

Logic Delay

Slide 29

Delay Case 2

6C 6C R/3 3C 3C 9C R/9 18C 18C 9C 27C 54C

d1 = 12 RC

d2 = 36/3 RC = 12 RC

d2 = 108/9 RC = 12 RC

d = d1 + d2 + d3 = 36 RC << 84 RC Note the geometric progression in size! 3X per stage. The delay for each stage is the same

Logic Delay CMOS VLSI Design Slide 30

Delay Case 3

4C 4C R/2 2C 2C 4C R/16 8C 32C 16C 27C 54C

d1 = 9 RC

d5 = 129/16 RC = 8.1 RC

d = d1 + d2 + d3 + d4 + d5 = 44.1 RC Case 2 = 36 RC < Case 3 = 44 RC < Case 1 = 84 RC You can have too much of a good thing!

Logic Delay CMOS VLSI Design Slide 31

Some Review

k: transistors width is k times unit width On resistance is 1/k times unit transistor Cg is capacitance of gate to body Cg-k is k times Cg-unit of unit transistor Cdiff is capacitance to body from a contacted source or drain Approximately = Cg Diffusion capacitance of uncontacted source or drain is less but approx as same

k Cg

Cdiff

Logic Delay

Slide 32

3 Input NAND

Logic Delay

Slide 33

Vout

i i=1 j=1

Logic Delay

Slide 34

Vout

Delay = R1*Ci

In reality, C2, CN shielded by Rs (dont have to charge all way to voltage at Y) Thus a conservative estimate

Logic Delay CMOS VLSI Design Slide 35

Assume not driving any other gates This is called the Parasitic Delay Fall Delay = (R/3)3C + (2R/3)3C + (3R/3)9C = 12RC Rise time = R*(9C + 3C + 3C) Why is this worst case?

Logic Delay

Slide 36

Assuming: gate size is indicated as # in each transistor gate capacitance of unit transistor 1 Cg = C

Logic Delay CMOS VLSI Design Slide 37

Estimate worst-case rising and falling delay of 2input NAND driving h identical gates.

2 A B

2 2 2x

Y

h copies

Logic Delay

Slide 38

Assume driving h identical 2in NANS Only 1 pmos on for slowest case Assume int node charged

Rise delay

Fall delay

Size 2 because in series Elmore delays: Worst Case Rise = R(6+4h)C = (6+4h)RC Worst Case Fall = (R/2)(2C) + R*(6+4h)C = (7+4h)RC

Logic Delay CMOS VLSI Design Slide 39

=h copies

What is the load on Y? What is the fall time? What is the rise time?

Logic Delay

Slide 40

Contamination Delay

Contamination = min possible On fall, best if both bottom NMOS Ts on Diffusion cap already drained Only R effective left Delay = On rise, best when ALL 3 PMOS turn on Resistances in parallel Delay =

Logic Delay

Slide 41

Logic Delay

Slide 42

24/12 Inverter

Total cap = 9C

Logic Delay

Slide 43

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