VERILOG SOURCE CODE

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Module processor(data,reset,w,f,clk,rx,ry,done,buswires); Input[7:0}data; Input reset,w,clk; Input[1:0]F,RX,RY; Input reg[7:0]buswires; Out reg done; Reg[7:0]sum; Reg[0:3]rin,rout; Reg extern,ain,gin,gout,addsub; Wire[3:0]t; Integer k; Wire[1:0]count; Wire[3:0]I; Wire[0:3]xreg; Wire[0:3]y; Wire[7:0]R1,R2,R3A,G; Wire[1:6]func,func Reg,sel; Wire clear=reset|done|(~w&~count[1]&~count[0]); Upcount counter(clear,clk,count); Assign func={F,RX,Ry}; Wire F rin=w&~count[1]&~count[0]; Rgn functionreg(func,frin,clk,funcreg);

Defparam functionreg.n=6; Assign I=funcReg[1:2]; Dec2to4 decX(func Reg[3:4],1 b1,Y); Dec2to4 decY(func reg[5:6],1,b1,Y); always@(count,1,Xreg,y) begin extern=1 b0; done=1 b0; ain=1,b0; gin=1 b0; gout=1 b0; addsub=1 b0; rin=4 b0; rout=4 b0; case(count) 2 b00:; 2 b01: Case(I) 2 b00:begin\\load Extern=1 b1; Rin=xreg; Done=1,b1; End 2 b01:begin\\move Rout=y;

Rin=xreg; Done=1 b1; End Default:begin\\add,sub Rout=Xreg; Ain=1 b1; End End case Endcase End

\\regctrl always@(I,T,Xreg,Y) begin for(k=0;k<4;k=k+1) begin rin[k]=((I[0]|i[1])&T[1]&xreg[k])|(I[2]|I[3])&t[3]&Xreg[0]); end end trin tri_ext(data,extern,buswires); regn reg_0(buswires,rin1[0],clk,r0); regn reg_1(buswires,rin[1],clk,r1); regn reg_2(buswires,rin[2],clk,r2);

regn reg_3(buswires,rin[3],clk,r3); trin tri_0(R0,Rout[0],buswires); trin tri_0(R1,Rout[1],buswires); trin tri_0(R2,Rout[2],buswires); trin tri_0(R3,Rout[3],buswires); regn reg_A(buswires,Ain,Clk,A); \\alu always@(addsub,A,buswires) begin if(!Addsub) sum=A+buswires; else sum=a-buswires; regn reg-G(sum,gin,clk,g); trin tri_g(g,gout,buswires); endmodule module regn(R,Rin,clk,Q); parameter n=8; input[n-1:0]Q; always@(posedge clk) if(rin) Q<=R; End module Module trin(Y,E,F); Parameter n==8;

Input[n-1:0]y; Input E; Output wire[n-1:0]F; Assign F=E?Y: bz; Endmodule Module upcounter(clear,clk,Q); Input clear,clk; Output reg[1:0]Q; always@(posedge clk) if(clear) Q<=0; Else Q<=Q+1; Endmodule

Module upcounter(clear,clk,Q); Input clear,clk; Output reg[1:0]Q; ays if(clear) Q<=0; Else Q<=Q+1; Endmodule

Module dec2to4(w,Y,EN); Input[1:0]w; Input En; Output[0:3]y; Reg[0:3]y; always@(w,En) begin if(en==0) y=4 b0000; else case(w) 0:Y=4 b1000; 1:Y=4 b0100; 2:Y=4 b0010; 3:y=4 b0001; Endcase End Endmodule

VHDL SOURCE CODE Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_ARITH.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL; Entity proc is

Port(data:in std_logic_vector(7 downto 0); Reset,w,clock:in std_logic; F,rx,ry:in std_logic_vector(1 downto 0; Done:buffer std_logic; Buswires:inout std_logic_vector(7 downto 0)); End proc;

Architecture behavioral of proc is Signal X,Y,rin,rout:std_logic_vector(0 to3); Signal clear,high,addsub:std_logic; Signal extern,ain,gin,gout,frin:std_logic; Signal count,zero,t,i:std_logic_vector(1 downto 0); Signal r0,r1,r2,r3:std_logic_vector(7 downto 0); Signal a,sum,g:std_logic_vector_vector(7 downto 0); Signal s,funcreg,sel:std_logic_vector(1 to 6); Begin Zero<= 00 ;high<= 1 ; Clear<=reset or done or((not w)and (not t(1))and (not t(0))); Counter:upcount port map (clear,clock,count); T<=count; Func<=f&rx&ry; Frin<=w and (not (1)) and (not t(0)); Functionreg:regn generic map(n=>6) port map(func,frin,clock,funcreg); I<=funcreg(1to2); Decx;dec2to4 port map (funcreg(3to4),high,x);

Decy:dec2to4 port map(funcreg(3to4),high,y);

Controlsignals:process(t,I,x,y) Begin Extern<= 0 ; done<= 0 ;ain<= 0 ;gin<= 0 ; Gout<= 0 ;addsub<= 0 ;rin<= 0000 ;rout<= 0000 ; Case t is When 00 =>--no signals asserted in time step t0 When 01 =>--define signals asserted in time step t1 Case I is When 00 =>-- load Extern<= 1 ; rin<=x; done<= 1 ; When 01 =>--add,sub Rout<=x;ain<= 1 ; End case ; When 10 =>--define signals asserted in time step t2 Case I is When 10 =>--add Rout<=y;gin<= 1 ; When 11 =>--sub Rout<=y; addsub<= 1 ;gin<= 1 ; When others=>--load,move Rout<=x;ain<= 1 ; End case; Whentime others=>-- define signals asserted in time step t3

Case I is When 00 =>--load When 01 =>--move When others=>--add,sub Gout<= 1 ;rin<=x;done<= 1 ; End case; End case; End process; Reg0:regn port map(bus wires,rin(0),clock,r0); Reg1:regn port map(bus wires, rin(1),clock,r1); Reg2:regn port map(bus wires,rin(2),clock,r2); Reg3:regn port map(buswires,rin(30,clock,r3); Rega:regn port map(buswires,ain,clock,a); Alu:with addsub select Sum<=a+buswires when 0 ,a-buswires when others; Regg:regn port map(sum,gin,clock,a); Alu:with addsub select Sum<=a+buswires when 0 ,a-buswires when others; Regg:regn port map(sum,gin,clock,g); Sel<=rout&gout&extern; With sel select Buswires<=r0 when 100000 , R1 when 010000 , R2 when 001000 , R3 when 000100 ,

G when others Data when others; End behavioral;

DECODER 2 TO 4 Entity dec 2to4 is Port(w:in std_logic_vector(1 downto 0); En:in std _logic; Y:out std_logic_vector(0to3)); End dec2to4; Architecture behavioral of dec2to4 is Signal enw:std_logic_vector(2 downto 0); Begin With enw select Y<= 1000 when 100 , 0100 when 101 0010 when 110 0001 when 111 0000 when others; End behavioral;

REGN Entity regn is Generic(n:integer:=8);

Rin,clock: in std _logic; q:out std _logic_vector(n-1 downto 0)); end regn;

ARCHITECTURE BEHAVIORAL OF REGN IS Begin Process Begin Wait until clock event and clock= 1 ; If rin= 1 then Q<=r; End if; End process; End behavioral;

UPCOUNT Library IEEE; Use IEEE.std_logic_1164.all; Use IEEE.std_logic_ARITH.ALL; Use IEEE.STD-logic_UNSIGNED.ALL; Entity upcount is Port(clear,clock:in std_logic; Q:buffer std_logic_vector(1 downto 0));

End upcount:process(clock) Begin If(clock event and clock= 1 )then If clear= 1 then Q<= 00 ; Else Q<=q+ 1 ; End if; End cross; End behavioral;

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