# UNIT I – BOOLEAN ALGEBRA AND LOGIC GATES Boolean Variables & Truth Tables Boolean algebra differs in a major way

from ordinary algebra in that Boolean constants and variables are allowed to have only two possible values, 0 or 1. Boolean 0 and 1 do not represent actual numbers but instead represent the state of a voltage variable, or what is called its logic level. Some common representation of 0 and 1 is shown in the following diagram. In Boolean algebra, there are three basic logic operations: AND ,OR, and NOT. These logic gates are digital circuits constructed from diodes, transistors, and resistors connected in such a way that the circuit output is the result of a basic logic operation (OR, AND, NOT) performed on the inputs. Truth Table A truth table is a means for describing how a logic circuit's output depends on the logic levels present at the circuit's inputs. In the following two-input logic circuit, the table lists all possible combinations of logic levels present at inputs A and B along with the corresponding output level X.

When either input A OR B is 1, the output X is 1. Therefore the "?" in the box is an OR gate. OR Operation The expression X = A + B reads as "X equals A OR B". The + sign stands for the OR operation, not for ordinary addition. The OR operation produces a result of 1 when any of the input variable is 1. The OR operation produces a result of 0 only when all the input variables are 0.

Mrs.A.Umaamaheshvari / ECE / SSEC 1

An example of three input OR gate and its truth table is as follows:

With the OR operation, 1 + 1 = 1, 1+ 1 + 1 = 1 and so on. AND Operation The expression X = A * B reads as "X equals A AND B". The multiplication sign stands for the AND operation, same for ordinary multiplication of 1s and 0s.The AND operation produces a result of 1 occurs only for the single case when all of the input variables are 1.The output is 0 for any case where one or more inputs are 0

Mrs.A.Umaamaheshvari / ECE / SSEC 2

An example of three input AND gate and its truth table is as follows:

With the AND operation, 1*1 = 1, 1*1*1 = 1 and so on. NOT Operation The NOT operation is unlike the OR and AND operations in that it can be performed on a single input variable. For example, if the variable A is subjected to the NOT operation, the result x can be expressed as x = A' where the prime (') represents the NOT operation. This expression is read as: x equals NOT A x equals the inverse of A x equals the complement of A

Mrs.A.Umaamaheshvari / ECE / SSEC 3

Each of these is in common usage and all indicate that the logic value of x = A' is o pposite to the logic value of A. The truth table of the NOT operation is as follows:

1'=0 0' = 1

because NOT because NOT 0 is 1

1

is

0

The NOT operation is also referred to as inversion or complementation, and these terms are used interchangeably. NOR Operation NOR and NAND gates are used extensively in digital circuitry. These gates combine the basic operations AND, OR and NOT, which make it relatively easy to describe then using Boolean algebra. NOR gate symbol is the same as the OR gate symbol except that it has a small circle on the output. This small circle represents the inversion operation. Therefore the output expression of the two input NOR gate is: X = (A + B)'

Mrs.A.Umaamaheshvari / ECE / SSEC 4

An example of three inputs OR gate can be constructed by a NOR gate plus a NOT gate:

NAND Operation NAND gate symbol is the same as the AND gate symbol except that it has a small circle on the output. This small circle represents the inversion operation. Therefore the output expression of the two input NAND gate is: X = (AB)'

Describing Logic Circuits Algebraically Mrs.A.Umaamaheshvari / ECE / SSEC 5

A. its output expression is simply equal to the input expression with a prime (') over it. and NOT circuit are the basic building blocks of digital systems. the output logic level can be determined for any set of input levels. C=1. AND gate. the AND operations are performed first (X=AB+C: AB is performed first). in which case the operation inside the parentheses is to be performed first (X= (A+B) +C: A+B is performed first).
Evaluating Logic Circuit Outputs Once the Boolean expression for a circuit output has been obtained. no matter how complex.Any logic circuit. D=1 X = A'BC (A+D)' = 0'*1*1* (0+1)' = 1 *1*1* (1)' = 1 *1*1* 0 Mrs. may be completely described using the Boolean operations. because the OR gate. B=1.Umaamaheshvari / ECE / SSEC 6
. This is an example of the circuit using Boolean expression:
If an expression contains both AND and OR operations. unless there are parentheses in the expression. Circuits containing Inverters Whenever an INVERTER is present in a logic-circuit diagram. These are two examples of the evaluating logic circuit output: Let A=0.

2. 4. perform the operations of the expression first and then invert the result. that is. If an expression has a bar over it.A. 0 = 1 or 1 = 0. Determining Output Level from a Diagram The output logic level for given input levels can also be determined directly from the circuit diagram without using the Boolean expression.
Implementing Circuits from Boolean Expression
Mrs. First. 3. perform all inversions of single terms. Then perform all operations within parentheses. Perform an AND operation before an OR operation unless parentheses indicate otherwise.Umaamaheshvari / ECE / SSEC 7
. C=1. the following rules must always be followed when evaluating a Boolean expression: 1. B=0. D=1.=0 Let A=0. E=1 X = [D+ ((A+B)C)'] * E = [1 + ((0+0)1 )'] * 1 = [1 + (0*1)'] * 1 = [1+ 0'] *1 = [1+ 1 ] * 1 =1
In general.

respectively. This tells us that a three-input OR gate is required with inputs that are equal to AC. This Boolean expression contains three terms (AC. Each OR-gate input is an AND product term. which means that an AND gate with appropriate inputs can be used to generate each of these terms. BC'.A. Note the use of INVERTERs to produce the A' and C' terms required in the expression. Suppose that we wanted to construct a circuit whose output is y = AC+BC' + A'BC. BC'. a logic-circuit diagram can he implemented directly from that expression.
Mrs.If the operation of a circuit is defined by a Boolean expression. which are ORed together. A'BC).
Boolean Theorems Investigating the various Boolean theorems (rules) can help us to simplify logic expressions and logic circuits. and A'BC.Umaamaheshvari / ECE / SSEC 8
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A. The two theorems are: (16) (x+y)' = x' * y' Mrs.Multivariable Theorems The theorems presented below involve more than one variable: (9) (10) (11) (12) (13a) (13b) (14) (15) Proof of (14) x + xy = x (1+y) = x * 1 [using theorem (6)] = x [using theorem (2)] x + y = y + x (commutative law) x * y = y * x (commutative law) x+ (y+z) = (x+y) +z = x+y+z (associative law) x (yz) = (xy) z = xyz (associative law) x (y+z) = xy + xz (w+x)(y+z) = wy + xy + wz + xz x + xy = x [proof see below] x + x'y = x + y
DeMorgan's Theorem DeMorgan's theorems are extremely useful in simplifying expressions in which a product or sum of variables is inverted.Umaamaheshvari / ECE / SSEC 9
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A. this is the same as inverting each variable individually and then ORing them.Umaamaheshvari / ECE / SSEC 10
. this is the same as inverting each variable individually and then ANDing these inverted variables.
(17) (x*y)' = x' + y' Theorem (17) says that when the AND product of two variables is inverted.
Mrs.Theorem (16) says that when the OR sum of two variables is inverted.

Mrs. AND. can be used to perform each of the Boolean operations OR.A.Example X = [(A'+C) * (B+D')]' = (A'+C)' + (B+D')' [by theorem (17)] = (A''*C') + (B'+D'') [by theorem (16)] = AC' + B'D
Three Variables DeMorgan's Theorem (18) (x+y+z)' = x' * y' * z' (19) (xyz)' = x' + y' + z' Universality of NAND & NOR Gates It is possible to implement any logic expression using only NAND gates and no other type of gate. and INVERT. This is because NAND gates.Umaamaheshvari / ECE / SSEC 11
. in the proper combination.

and the right side shows the alternate symbol.A. and by removing bubbles that are already there. (In the special case of the INVERTER. it can be shown that NOR gates can be arranged to implement any of the Boolean operations. This is done by adding bubbles (small circles) on input and output lines that do not have bubbles.
Alternate Logic Gate Representations The left side of the illustration shows the standard symbol for each logic gate. The alternate symbol for each gate is obtained from the standard symbol by doing the following: 1. the operation symbol is not changed.Umaamaheshvari / ECE / SSEC 12
. Invert each input and output of the standard symbol. 2.) Mrs. or from OR to AND. Change the operation symbol from AND to OR.In a similar manner.

3. that line is said to be active-LOW. Concept of Active Logic Levels: When an input or output line on a logic circuit symbol has no bubble on it.Umaamaheshvari / ECE / SSEC 13
. When an input or output line does have a bubble on it. and so the alternate symbols for each will have bubbles on both inputs and output. None of the standard symbols have bubbles on their inputs. and so both the standard and alternate symbols for each will have a bubble on either the input or the output. The equivalences are valid for gates with any number of inputs.A. AND and OR gates are noninverting gates. NAND and NOR gates are inverting gates. The standard and alternate symbols for each gate represent the same physical circuit: there is no difference in the circuits represented by the two symbols. that line is said to be active-HIGH. and is used to interpret the circuit operation. The presence or absence of a bubble. and all the alternate symbols do.Several points should be stressed regarding the logic symbol equivalences: 1. then.
Mrs. determines the active-HIGH/active-LOW status of a circuit's inputs and output. 2. 4.

g. (a +b) • (c+d’) The parentheses precedence is the same as in normal algebra Boolean Function Truth Table Boolean function can be represented by truth table as well.Boolean Function A Boolean function is an algebraic expression consists of binary variables. c+d’. and the Boolean operators. y and z The function is 1 if x and y are both 1 or if x is 1 and z is 0.Umaamaheshvari / ECE / SSEC 14
.If the function has n variables. Parentheses 2. its truth table will have 2n rows e. f = x • y + x • z’ f has 3 variables so 23 combinations
Mrs. f = x • y + x • z’ Precedence: z’. the constants 0 & 1.g. d’. Otherwise. NOT 3.A. x • y + x • z’ e. x • y.g. f = (a +b) • (c+d’) Precedence: a+b. the function is evaluated to either 0 or 1 e. f = 0 Operator Precedence The operator precedence is: 1. AND 4.For a set of given values of the variables. x • z’. f = x • y + x • z’ The Boolean function f has 3 binaryvariables x. OR e.g.

g.g.
Minterm In a Boolean function. x+y. Minterms and Maxterms for 3 Variables
Mrs. x•y’ & x•y Each of the 4 product terms is called a MINTERM or STANDARD PRODUCT By definition.A. y andz: x’yz’ is a minterm but xy’ is NOT a minterm Maxterm Consider 2 binary variables x and y and an OR operation. e.Each of the 4 sum terms is called a MAXTERM or STANDARD SUM.Consider 2 binary variables x and y and an AND operation. a Minterm is a product which consists of all the variables in the normal form or the complement form but NOT BOTH. a Maxterm is a sum in which each variable appears once and only once either in its normal form or its complement form but NOT BOTH.Umaamaheshvari / ECE / SSEC 15
. x’•y. for a function with 2 variables x and y: x•y’ is a minterm but x’ is NOT a minterm e. x’+y. x+y’. there are 4 and only 4 possible combinations: x’+y’. there are 4 and only 4 possible combinations: x’•y’.By definition.f is 1 when the expression is evaluated to 1 otherwise it is 0. for a function with 3 variables x. a binary variable (x) may appear either in its normal form (x) or in its complement form (x’).

7) f2 = M0•M1•M3•M5 = Π M(0.z) = m1 + m4 + m6 = Σm(1. e. 5. 5)
Mrs. 1.z) = m2 + m4 + m6+ m7 = Σm(2. 2.f1’ = x’y’z’+x’yz’+x’yz+xy’z+xyz f1 = (x’y’z’+x’yz’+x’yz+xy’z+xyz)’ = (x+y+z)(x+y’+z)(x+y’+z’)(x’+y+z’)(x’+y’+z’) = M0•M2•M3•M5•M7 = Π M(0.y.A.g. 7)
Maxterm Boolean Expression Boolean functions can also be expressed with maxterms.f1(x. e. 6) f2(x.y.Minterm Boolean Expression Boolean functions can be expressed with minterms. 3.Umaamaheshvari / ECE / SSEC 16
. 4. 6. 4.g. 3.

the 2 variables (b.A. without changing its functionality .b. each minterm must have 3 literals Neither a’ nor bc’ are minterms.b.Literal A Literal is a variable in a product or sum term xy’ is a 2-literal product term x’yz has 3 literals x’ + xy’ + x’yz is an expression of sum of products with 3 product terms. a Boolean function can be converted to an expression in product of maxterms e.The 3 product terms have 1. therefore.g.ab’c is a minterm Conversion to Minterms e.b.The 3 sum terms have 1. they can be converted to minterms e.g. f(a. f(a.c) = a’ + bc’ + ab’c Function f has 3 variables. c) must be added.g.They can be converted to minterm.c) = a’+bc’ = (a’+b)(a’+c’) {not maxterms} = (a’+b+cc’)(a’+c’+bb’) {cc’=0} = (a’+b+c)(a’+b+c’)(a’+c’+b)(a’+c’+b’) = (a’+b+c)(a’+b+c’)(a’+c’+b’) Mrs. 2 and 3 literals respectively x’(x+y’)(x’+y+z) is an expression of product of sums. a’b = a’b(c + c’) = a’bc + a’bc’ and a’b’ = a’b’(c+c’) = a’b’c + a’b’c’ bc’ = bc’(a+a’) = abc’ + a’bc’ f = a’bc+a’bc’+a’b’c+a’b’c’+abc’+a’bc’+ab’c Express Boolean Functions in Maxterms By using the Distribution Law: x+yz = (x+y)(x+z).Since a’=a’•1 & 1 = b+b’. a’= a’(b + b’) = a’b + a’b’ Similarly.c) = a’ + bc’ + ab’c To convert a’ to a minterm.Umaamaheshvari / ECE / SSEC 17
. 2 and 3 literals Express Boolean Functions in Minterms If product terms in a Boolean function are not minterms. f(a.

Umaamaheshvari / ECE / SSEC 18
. Each time a number is found in one group which is the same as a number in the group below except for one digit. fewer logic gates Boolean Function Manipulation Example f = xy’ + xyz + x’z = x(y’ + yz) + x’z {common factor} = x[(y’+y)(y’+z)] + x’z {Distribution law} = x(y’+z) + x’z {y’ + y = 1} = xy’ + xz + x’z {Distribution law} = xy’ + (x + x’)z {common factor} = xy’ + z {x + x’ = 1} Simplify f1=abc+a’b+abc’ and f2=(a+b)’(a’+b’) to the minimum literals f1 = abc+a’b+abc’ = ab(c+c’) + a’b = ab + a’b = (a+a’)b = b f2 =(a+b)’(a’+b’) = a’b’(a’+b’) {DeMorgan} = a’b’a’+a’b’b’ = a’b’ + a’b’ = a’b’ QUINE-McCLUSKEY MINIMIZATION Quine-McCluskey minimization method uses the same theorem to produce the solution as the K-map method. Begin with the minimization procedure.A. The next step is to identify the essential prime implicants. The numbers are converted into binary form. Mrs.e. Where a prime implicant covers a minterm. hence. This composite number has the same number of digits as the numbers in the pair except the digit different which is replaced by an "x". -> These prime implicants must be in the final answer. the numbers pair is ticked and a new composite is created.Manipulation can transform logic expressions.Boolean Function Manipulation Boolean functions can be manipulated with Boolean algebra. the intersection of the corresponding row and column is marked with a cross. The function is converted into numeric notation. easier to be implemented in hardware. namely X(Y+Y')=X Minimization Technique
• • • • • • • • • • • •
The expression is represented in the canonical SOP form if not already in that form. The minterms are arranged in a column divided into groups. Those columns with only one cross identify the essential prime implicants. but still keep the same logic functionality. The above procedure is repeated on the second column to generate a third column. Each minterm of one group is compared with each minterm in the group immediately below. which can be done using a prime implicant chart. i.Manipulation can reduce the complexity.

If any non-essential prime implicant has all its crosses circled. The above binary representations are grouped into a number of sections in terms of the number of 1's as shown in the table below. One generally would take those prime implicants which cover the greatest number of crosses on their row.15). If all the crosses in one row also occur on another row which includes further crosses.8. Once one cross on a column is circled. using Quine-McCluskey method. all the crosses on that column can be circled since the minterm is now covered. Firstly these minterms are represented in the binary form as shown in the table below. then the latter is said to dominate the former and can be selected.
Example Find the minimal sum of products for the Boolean expression. a selection must be made from the remaining nonessential prime implicants.10. The dominated prime implicant can then be deleted.14. f= (1. the prime implicant is redundant and need not be considered further.7.A. Next. by considering how the non-circled crosses can be covered best.11. Binary representation of minterms Minterms 1 2 3 7 8 9 10 11 14 15 U 0 0 0 0 1 1 1 1 1 1 V 0 0 0 1 0 0 0 0 1 1 W 0 1 1 1 0 0 1 1 1 1 X 1 0 1 1 0 1 0 1 0 1
Group of minterms for different number of 1's No of 1's 1 1 1 2 Minterms 1 2 8 3 U 0 0 1 0 V 0 0 0 0 W 0 1 0 1 X 1 0 0 1
Mrs.2.3.9.Umaamaheshvari / ECE / SSEC 19
.•
• • • • • •
The single crosses on a column are circled and all the crosses on the same row are also circled. indicating that these crosses are covered by the prime implicants selected.

14. to get 2-cell combination.15) (11.11). one variable and dash in the same position can be combined to form 4-cell combinations as shown in the figure below.15) (14.A.11.3) (2.7.11) (3.9) (2.15) U 1 1 V 0 0 0 W 1 1 1 X 1 1 -
The cells (1.15) (10. Mrs. From above 4-cell combination table.7) (3.3) and (9.11) (10.3.Umaamaheshvari / ECE / SSEC 20
.9) (8.9.2 2 3 3 3 4
9 10 7 11 14 15
1 1 0 1 1 1
0 0 1 0 1 1
0 1 1 1 1 1
1 0 1 1 0 1
Any two numbers in these groups which differ from each other by only one variable can be chosen and combined.10.11) (2. as shown in the table below.11).9.14) (7. 2-Cell combinations Combinations (1. the prime implicants table can be plotted as shown in table below.10) (8.11) (10.15) U 0 0 1 1 0 1 1 1 1 1 V 0 0 0 0 0 0 0 0 0 1 1 W 0 1 1 0 1 1 1 1 1 1 1 X 1 1 0 0 1 1 1 0 1 1 -
From the 2-cell combinations.3) (1. Thus the (1.9. Combinations (1.3.9.9) and (3.11) (8.10.11) (9.3.11) form the same 4-cell combination as the cells (1.10) (3.11) combination could be written as (1.11.3. The order in which the cells are placed in a combination does not have any effect.

11) (3.9.10.10. b) The outputs are 1-bit sum (s) & 1-bit carry (c)
The logic is:
Mrs. Sequential logic blocks have the outputs depending on the current inputs as well as any previous inputs.Umaamaheshvari / ECE / SSEC 21
.3.11) (2.9.A. A yellow cross is used against every essential prime implicant. Y = V'X + V'W + UV' + WX + UW Logic Combinational logic blocks have the outputs depending on the combinations of the current inputs.7. Binary Adder Binary Adder is for binary number addition Logic Circuit to be discussed: Half Adder Full Adder Ripple Adder Carry Look Ahead Adder Half Adder o o o o Half adder is for addition of 2 single bits It has two 1-bit inputs and two 1-bit outputs The inputs are the 2 bits to be added (a. The prime implicants sum gives the function in its minimal SOP form.Prime Implicants Table Prime Implicants (1.11.3.11) (8.15) 1 X X 2 X X 3 X X 7 X 8 X X 9 X X 10 X X X 11 X X X X 14 X X 15 X -
The columns having only one cross mark correspond to essential prime implicants.

the adder needs to take in 3 inputs: a. b and the carry from the previous bit. Full Adder To carry the addition.Umaamaheshvari / ECE / SSEC 22
. b and ci) and produces 2 outputs (s. A Full Adder takes in 3 inputs (a.Binary Addition The half adder adds 2 single-bit inputs It cannot complete a full addition
To complete a full addition.A. co) a & b are the 2 bits to be added. an adder with 3 inputs is required. ci is the carry input (carry over from the previous bit) and co is the carry output (to the next bit)
Mrs.

Circuit-SUM
Mrs. instead of using XOR gates.Logic for Full Adder Logic equations derived from the truth table:
s = a ⊕ b ⊕ ci co = ab + bci + aci Full Adder The below implementation shows implementing the full adder with AND-OR gates. The basis of the circuit below is from the above Kmap.Umaamaheshvari / ECE / SSEC 23
.A.

Umaamaheshvari / ECE / SSEC 24
.Circuit-CARRY
Full adder can be built from 2 half adders s = a ⊕ b ⊕ ci co = ab+bci+aci = ab+(a’bci+abci)+(abci+ab’ci) = ab + abci + ci (a’b+ab’) = ab + ci (a ⊕ b)
n-bit Ripple Adder To perform an addition of 2 n-bit numbers An-1…A1A0 & Bn-1…B1B0.A. where An1 & Bn-1 are theMSB & A0B0 are the LSB. we need a n-bit adder.which can be built from ‘n ‘fulladders Mrs.

carry_in(i-1) For a four-bit adder the carry-outs are calculated as follows carry_out0 = G0 + P0 .Ripple Adder: Carry ripples through the chain
Carry-Look-Ahead Adder The delay generated by an N-bit adder is proportional to the length N of the two numbers X and Y that are added because the carry signals have to propagate from one full-adder to the next. the carry bit is received from the less significant elementary addition and is propagated further to the more significant elementary addition. Once these bits are available to the rest of the circuit. the delay becomes unacceptably large so that a special solution needs to be adopted to accelerate the calculation of the carry bits. For each input bits pair these functions are defined as: Gi = Xi . carry_out0 = G1 + P1G0 + P1P0 . carry_in0 carry_out1 = G1 + P1 . Therefore. each individual three-bit addition (X i+Yi+carry-ini) is implemented by a simple 3-input XOR gate. carry_in0
Mrs.Umaamaheshvari / ECE / SSEC 25
. In the first case. carry_in0 carry_out3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1 . In the second. the carry bit is activated by the local conditions (the values of Xi and Yi). carry_in0 carry_out2 = G2 + P2G1 + P2P1G0 + P2P1P0 .A. The design of the look-ahead carry generator involves two Boolean functions named Generate and Propagate. the carry_out bit corresponding to a pair of bits Xi and Yi is calculated according to the equation: carry_out(i) = Gi + Pi. For large values of N. Yi Pi = Xi + Yi The carry bit c-out(i) generated when adding two bits Xi and Yi is '1' if the corresponding function Gi is '1' or if the c-out(i-1)='1' and the function Pi = '1' simultaneously. This solution involves a "look-ahead carry generator" which is a block that simultaneously calculates all the carry bits involved.

A.Umaamaheshvari / ECE / SSEC 26
.The set of equations above are implemented by the circuit below and a complete adder with a look-ahead carry generator is next. The input signals need to propagate through a maximum of 4 logic gate in such an adder as opposed to 8 and 12 logic gates in its counterparts illustrated earlier.
Pi is called Carry Propagate Gi is called Carry Generate With Pi and Gi. we obtain the sum & carry for the full adder:
Ci+1= Gi + PiCi C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0 C3 = G2 + P2C2 = G2 + P2(G1 + P1G0 + P1P0C0) = G2 + P2G1 + P2P1G0 + P2P1P0C0 Carry no longer depend on its previous stage Look-Ahead Carry Generator
Mrs.

A. sum_out0 = X 0 Y0 carry_out0
Mrs.Speed: 2 gate delays for all carry Cost: more gates
Sums can be calculated from the following equations. where carryout is taken from the carry calculated in the above circuit.Umaamaheshvari / ECE / SSEC 27
.

e.sum_out1 = X 1 sum_out2 = X 2 sum_out3 = X 3
Y1 Y2 Y3
carry_out1 carry_out2 carry_out3
MSI Adder Adders are available in Medium Scale Integration (MSI) devices Both TTL and CMOS are available.A. 74183: TTL 1-bit Full Adder 7482: TTL 4-bit Carry-Look-Ahead Adder Mrs.g.Umaamaheshvari / ECE / SSEC 28
.

Similar to adders.Umaamaheshvari / ECE / SSEC 29
.4008: CMOS 4-bit Carry-Look-Ahead Adder 74182: 4-bit Look-Ahead Carry Generator 4-bit Addition To add 2 4-bit numbers: Z = X + Y
8-bit Addition To add 2 8-bit numbers: Z = X + Y
Subtractor Subtractor circuits take two binary numbers as input and subtract one binary number input from the other binary number input.A.
• •
Half Subtractor Full Subtractor Mrs. it gives out two outputs. difference and borrow (carry-in the case of Adder). There are two types of subtractors.

It has two inputs.A. Symbol
Truth Table X 0 0 1 1 Y 0 1 0 1 D 0 1 1 0 B 0 1 0 0
From the above table we can draw the Kmap as shown below for "difference" and " borrow". The boolean expression for the difference and Borrow can be written.Umaamaheshvari / ECE / SSEC 30
. The logic symbol and truth table are shown below.
Mrs. X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).Half Subtractor The half-subtractor is a combinational circuit which is used to perform subtraction of two bits.

Umaamaheshvari / ECE / SSEC 31
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Full Subtractor A full subtractor is a combinational circuit that performs subtraction involving three bits.A. namely minuend. The logic symbol and truth table are shown below. and borrow-in.From the equation we can draw the half-subtractor as shown in the figure below.
Mrs. subtrahend. Symbol
Truth Table X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Bin 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 Bout 0 1 1 1 0 0 0 1
From above table we can draw the Kmap as shown below for "difference" and "borrow".

Bin + Y.Y + X'.The boolean expression for difference and borrow can be written as D = X'Y'Bin + X'YBin' + XY'Bin' + XYBin = (X'Y' + XY)Bin + (X'Y + XY')Bin' = (X =X Y)'Bin + (X Y Bin Y)Bin'
Bout = X'.Bin From the equation we can draw the full-subtractor as shown in figure below.
Mrs.
Full-subtractor circuit is more or less same as a full-adder with slight modification.A.Umaamaheshvari / ECE / SSEC 32
.

A. Implementation and associated problems are those of a parallel binary adder. seen before in parallel binary adder section. It has 4-bit difference output D3D2D1D0 with borrow output Bout. The subtrahend is stored in the Y register and must be 2's complemented before it is added to the minuend stored in the X register. The circuit for a 4-bit serial subtractor using full-adder is shown in the figure below. Below is the block level representation of a 4-bit parallel binary subtractor.Parallel Binary Subtractor Parallel binary subtractor can be implemented by cascading several full-subtractors.Umaamaheshvari / ECE / SSEC 33
. which subtracts 4-bit Y3Y2Y1Y0 from 4-bit X3X2X1X0.
Mrs.
A serial subtractor can be obtained by converting the serial adder using the 2's complement system.

Y A<B. A3B3 is 10 and A2A1A0 & B2B1B0 can be anything: A=1xxx. there are 4 cases: 1. let: Si = AiBi + Ai’Bi’ = (AiBi’ + Ai’Bi)’ Si is true when Ai = Bi For A = B. B=0xxx 2.A. Y A=B = S3•S2•S1•S0 136 Logic For A > B For A > B.Comparator Comparator compares binary numbers. B=00xx Mrs. Y A=B For each bit. A3=B3 and A2B2 is 10 and A1A0 & B1B0 can be anything: A=11xx. Logic comparing 2 bits: a and b
Magnitude Comparator Comparator compares binary numbers 4-bit Magnitude Comparator: Inputs: A3A2A1A0 & B3B2B1B0 Outputs: Y A>B. B=10xx or A=01xx. we must have: A3=B3 and A2=B2 and A1=B1 and A0=B0 Hence.Umaamaheshvari / ECE / SSEC 34
.

1. A=0xxx. A=011x. B=1001 Y A<B=A3 ’B3+S3A2 ’B2+S3S2A1 ’ B1+S3S2S1A0 ’ B0 4-bit Comparator Logic Circuit
MSI: 7485 4-bit Magnitude Comparator
Mrs.g. B=111x 4) A3=B3 and A2=B2 and A1=B1 and A0B0 is 01: e.A. B=01xx 3) A3=B3 and A2=B2 and A1B1=01 and A0B0 is xx: e.g.g. A=1000.g. B=1xxx 2) A3=B3 and A2B2 is 01 and A1A0 & B1B0 can be 1. anything: A=10xx. A3=B3 and A2=B2 and A1B1=10 and A0B0 is xx: e. B=010x 4.3. A3=B3 and A2=B2 and A1=B1 and A0B0 is 10: e. 1.Umaamaheshvari / ECE / SSEC 35
. B=11xx or A=00xx. A=110x. there are also 4 cases: 1) A3B3 is 01 and A2A1A0 & B2B1B0 can be anything: 1. B=1010 Y A>B=A3B3’+S3A2B2’+S3S2A1B1’+S3S2S1A0B0’ Logic For A < B For A < B. A=1011.

A.Umaamaheshvari / ECE / SSEC 36
.Comparison of 4-bit Numbers
Comparison of 8 .bit Numbers
Mrs.

A.
A binary decoder has n inputs and 2n outputs. 7 segment display and memory address decoding.Binary Decoder has n inputs and 2noutputs also called as n-to-2n decoder. where the input and output codes are different. Only one output is active at any one time. Figure below shows a representation of Binary n-to-2n decoder
Mrs. otherwise its outputs assume a single "disabled" output code word. corresponding to the input value.Decoder A decoder is a multiple-input. Figure below shows the pseudo block of a decoder.Decoding is necessary in applications such as data multiplexing. multiple-output logic circuit that converts coded inputs into coded outputs. Inputs have all the 2n combinations and the corresponding output will be activated for each input combinations.Umaamaheshvari / ECE / SSEC 37
. Enable inputs must be on for the decoder to function.

A. 3-to-8 decoder has 3 inputs and 8 outputs 3-to-8 Decoder Function Table
3-to-8 Decoder Logic Circuit
Mrs.g.
e.Umaamaheshvari / ECE / SSEC 38
.

Mrs. The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate.Umaamaheshvari / ECE / SSEC 39
. Any combinational circuit with n inputs and m outputs can be implemented with an nto-2n decoder with m OR gates. and an OR gate to form the sum. in canonical sum-of-minterms form can be implemented using a single n-to-2n decoder to generate the minterms.2-to-4 Decoder with Output Enable
Implement Logic Function with Decoder
•
• •
Any n-variable logic function.A.

y.7) (3.5.4. Thus we have the equation as shown above and a circuit can be drawn as shown below from the equation derived.7)
Truth Table
X 0 0 0 0 1 1 1 1
Y 0 0 1 1 0 0 1 1
Z 0 1 0 1 0 1 0 1
C 0 0 0 1 0 1 1 1
S 0 1 1 0 1 0 0 1
From the truth table we know the values for which the sum (s) is active and also the carry (c) is active.
Use a 3-to-8 decoder to implement: f = x’y’z + xy’z + xyz (m1 + m5 + m7) Mrs.Suitable when a circuit has many outputs.A. y.2. z) = (1. (Ex) Full adder using decoder S(x. and each output function is expressed with few minterms.Umaamaheshvari / ECE / SSEC 40
.6. z) = C(x.

2-to-4 Decoder 2. G2A and G2B are enable pins Logic Symbol
Mrs. BCD-to-Decimal Decoder 5. 3-to-8 Decoder 3.MSI Decoders 1. 4-to-16 Decoder 4. Low Power Schottky TTL: 74LS138 3-to-8 Decoder where G1.g.A.Umaamaheshvari / ECE / SSEC 41
. BCD-to-Seven-Segment Decoder e.

Umaamaheshvari / ECE / SSEC 42
.A.74LS138 3-to-8 Decoder
Implement Logic Function with74LS138 Use a 3-to-8 decoder to implement: f = x’y’z + xy’z + xyz (m1 + m5 + m7)
Mrs.

A. top decoder is enabled When D = 1.Umaamaheshvari / ECE / SSEC 43
. A Outputs: Y0 – Y15 When D = 0.4-to-16 Decoder Use 2 3-to-8 decoders Inputs: D.bottom decoderis enabled En’ is enable
Binary Encoders Mrs. C. B.

g. the device is usually called an encoder. only one input line has a value of 1.An encoder is a combinational circuit that performs the inverse operation of a decoder. 2n-to-n. Truth Table I0 1 0 0 0 0 I1 0 1 0 0 0 I2 0 0 1 0 0 I3 0 0 0 1 0 I4 0 0 0 0 1 I5 0 0 0 0 0 I6 0 0 0 0 0 I7 0 0 0 0 0 Y2 0 0 0 0 1 Y1 0 0 1 1 0 Y0 0 1 0 1 0
Mrs. where it has only one of 2n inputs = 1 and the output is the n-bit binary number corresponding to the active input.g. It can be built from OR gates
e.Umaamaheshvari / ECE / SSEC 44
.A. priority encoders. At any one time. e. The figure below shows the truth table of an Octal-to-binary encoder. 4-to-2 Encoder
Octal-to-Binary Encoder Octal-to-Binary take 8 inputs and provides 3 outputs. The simplest encoder is a 2n-to-n binary encoder. thus doing the opposite of what the 3-to-8 decoder does. If a device output code has fewer bits than the input code has.

the input having the highest priority will take precedence. The operation of the priority encoder is such that if two or more inputs are active at the same time. we can draw the circuit as shown below
Priority Encoder If more then two inputs are active simultaneously.This ambiguity is resolved if priority is established so that only one input is encoded.A. e. The priority encoder includes a priority function.0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 0 0
0 1 0
0 0 1
1 1 1
0 1 1
1 0 1
For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are: Y0 = I1 + I3 + I5 + I7 Y1= I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 +I7 Based on the above equations. 4-to-2 PriorityEncoder A3 has the highest priority A0 has the lower priority
Mrs. the output is unpredictable or rather it is not what we expect it to be. no matter how many inputs are active at a given point of time.Umaamaheshvari / ECE / SSEC 45
.g.

74148 8-to-3 Priority Encoder
16-to-4 Priority Encoder Cascade two 74148 8-to-3 priority encoders.Umaamaheshvari / ECE / SSEC 46
.A. A number of select inputs determine which data source is connected to the Mrs. The Input 15 has highest priority
Multiplexer A multiplexer (MUX) is a digital switch which connects data from one of n sources to the output.

This rotary switch can touch any of the inputs.Umaamaheshvari / ECE / SSEC 47
. The operation of a multiplexer can be better explained using a mechanical switch as shown in the figure below.
2x1 MUX A 2 to 1 line multiplexer is shown in figure below. At any given point of time only one input gets selected and is connected to output. The truth table for the 2:1 mux is given in the table below. each 2 input lines A to B is applied to one input of an AND gate. Selection lines S are decoded to select a particular AND gate. The block diagram of MUX with n data sources of b bits wide and s bits wide select line is shown in below figure. which is connected to the output.A.output.
Mrs.
MUX acts like a digitally controlled multi-position switch where the binary code applied to the select inputs controls the input source that will be switched on to the output as shown in the figure below. As you can see at any given point of time only one input gets transferred to output. based on the select input signal.

S Truth Table B 0 0 0 0 1 1 1 Kmap A 0 0 1 1 0 0 1 1 S 0 1 0 1 0 1 0 1 Y 0 0 1 0 0 1 1 1
Mrs. And once we have the truth table.Design of a 2:1 Mux To derive the gate level implementation of 2:1 mux we need to have truth table as s hown in figure.A. we can drive the output y as shown below Y = A.Umaamaheshvari / ECE / SSEC 48
.S’ + B. Combining the two 1' as shown in figure. we can draw the K-map as shown in figure for all the cases when Y is equal to '1'.

A.Umaamaheshvari / ECE / SSEC 49
.Circuit
MSI MUX 74150: 16-to-1 74153: Dual 4-to-1 74157: Quad 2-to-1 74151: 8-to-1
Mrs.

16-to-1 MUX Use two 74151 D = 0 enables top MUX D = 1 enables bottom MUX W = Y’ = (Y1+Y2)’ = (W1’+W2’)’ = W1W2
Mrs.A.Umaamaheshvari / ECE / SSEC 50
.

A. 8-to-1 multiplexer from Smaller MUX
Mrs. An 8-to-1 multiplexer can be constructed from smaller multiplexers as shown below.Umaamaheshvari / ECE / SSEC 51
.Larger Multiplexers Larger multiplexers can be constructed from smaller ones.

the whole group of 4 bits goes to the output
Mrs.A.Umaamaheshvari / ECE / SSEC 52
.16-to-1 multiplexer from 4:1 mux
Quadruple 2-to-1 MUX It is 2-to-1 MUX with 4 bits for each input There is 1 output of 4 bits There is 1 select signal When 1 input is selected.

g 4-to-1 mux to implement 3 variable functions) as follows.e select lines as most significant inputs).Quad 2-to-1 MUX
Implementing Functions Multiplexers Any n-variable logic function can be implemented using a smaller 2 n-1-to-1 multiplexer and a single inverter (e.Umaamaheshvari / ECE / SSEC 53
.A. but grouping inputs by selection line values (i. Mrs. Construct the truth table for the function. Choose n-1 variables as inputs to mux select lines. Express function in canonical sum-of-minterms form.

3.Determine multiplexer input line i values by comparing the remaining input variable and the function F for the corresponding selection lines value i.5.Umaamaheshvari / ECE / SSEC 54
. 2. Connect the input variables X. We have four possible mux input line i values:
• • • •
Connect to 0 if the function is 0 for both values of remaining variable. Truth Table
Select i 0 0 1 1
X 0 0 0 0
Y 0 0 1 1
Z 0 1 0 1
F 1 1 0 1
Mux Input i 1 1 Z Z
Mrs.3. Y as mux select lines. Mux data input lines 1.1.3.A. The remaining mux data input lines 0. Connect to the inverted remaining variable if the function is equal to the remaining variable inverted
3-variable Function Using 8-to-1 mux Implement the function F(X. Y.Y.Z) = S(1. 6 that correspond to the function minterms are connected to 1. We choose the two most significant inputs X. 7 are connected to 0.Z) = S(0. Z to mux select lines. Connect to remaining variable if function is equal to the remaining variable.6) using an 8-to-1 mux. Connect to 1 if the function is 1 for both values of remaining variable. 5.6) using a single 4-to-1 mux and an inverter. 4.Y.
3-variable Function Using 4-to-1 mux Implement the function F(X.

Umaamaheshvari / ECE / SSEC 55
. Z=1) thus mux input2 = 0 when XY=11 the function F is Z' thus mux input3 = Z'
Mrs.2 2 3 3
1 1 1 1
0 0 1 1
0 1 0 1
0 0 1 0
0 0 Z' Z'
We determine multiplexer input line i values by comparing the remaining variable Z and the function F for the corresponding selection lines value i
• • • •
input
when XY=00 the function F is 1 (for both Z=0. Z=1) thus mux input0 = 1 when XY=01 the function F is Z thus mux input1 = Z when XY=10 the function F is 0 (for both Z=0.A.

Umaamaheshvari / ECE / SSEC 56
.Example for logic function implementation using MUX
Mrs.A.

De-multiplexers They are digital switches which connect data from one input source to one of n outputs.Umaamaheshvari / ECE / SSEC 57
.Usually implemented by using n-to-2n binary decoders where the decoder enable line is used for data input of the de-multiplexer. one b-bits-wide data input and n b-bits-wide outputs. This rotary switch can touch any of the outputs.
The operation of a de-multiplexer can be better explained using a mechanical switch as shown in the figure below. which Mrs.A.The figure below shows a demultiplexer block diagram which has got s-bits-wide select input.

Umaamaheshvari / ECE / SSEC 58
.A. As you can see at any given point of time only one output gets connected to input.
1-to-4 De-multiplexer
Truth Table S1 0 0 1 1 S0 0 1 0 1 F0 D 0 0 0 F1 0 D 0 0 F2 0 0 D 0 F3 0 0 0 D
Mrs.is connected to the input.