PEDS2009

Analysis of ZVS/ZCS Soft-Switching Dual-Resonant Converter
1
1

J. J. Chenand 2B. R. Lin

Graduate School of Engineering Science and Technology 2 Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 640, Taiwan
Abstract - A soft-switching converter with dual resonant structures is presented in this paper. The dual resonant tanks are composed by the leakage inductors and resonant capacitors to achieve zero-current-switching (ZCS) turn-off mechanism for diodes at the secondary side of transformer. Moreover, the voltage stresses of power switches are clamped by the active clamp circuit at the primary side of transformer. The active clamp circuit is not only absorbed the energy stored in the leakage inductor but also create zero-voltage-switching (ZVS) turn-on feature for power switches. Hence, the reverse-recovery problem can be eliminated. The operational principles, design consideration and realization are discussed. Finally, experimental results from a 400W prototype are presented to confirm the effectiveness of the proposed converter.

I.

INTRODUCTION

Nowadays, the various flat panel display (FPD) has become popular for large screen TVs. Among them, the plasma display panel (PDP) have been regarded the better choice for larger area display applications because its noteworthy benefits that include light weight, thinness, long lifetime and wide viewing angle, etc. For these purpose, the PDP power supply unit has to provide higher power density and smaller size. As we know, raising switching frequency is preferred to reduce the volume of switching mode power supply. However, the switching losses of power semiconductor devices and electromagnetic interference (EMI) will be increased proportional to switching frequency. For driving PDP, many literatures have been investigated in [1]-[3]. The power factor correction (PFC) pre-regulator is adopted at the input stage and the second power stage including sustaining power module, addressing power module, resetting module and scanning power module are demanded. Among these power modules, the sustaining power module requires higher power rating due to the PDP cells emitting the extreme light and the desired images [1]. Thus, increasing the efficiency of the sustaining power module is significantly important to improve the overall power unit efficiency. To solve these problems, many literatures have been proposed to realize zero voltage switching (ZVS) or / and zero current switching (ZCS) [1]-[3]. Among them, the ZVS forward and flyback converter using active clamp circuit in [4]-[8] is attractive topology as compared to the full-bridge converter for simple control scheme. Nevertheless, the high voltage low current output application causes larger size of output inductor, appreciable duty loss, higher voltage stress and serious reverse-recovery problem on output diodes. In this paper, a soft-switching converter using active clamp circuit and dual resonant structures is presented.

The proposed converter combines an active clamp circuit and dual resonant circuit. As shown in Fig. 1, the active clamp circuit includes auxiliary switch S2 and clamp capacitor Cc which is connected in parallel with main switch S1. By using asymmetrical PWM scheme, the active clamp circuit causes not only recycle the energy stored in the leakage inductor but also limit the voltage stresses of switches; and further, it creates ZVS turn-on condition for all switches. The dual resonant actions are based on the leakage inductors of transformer Llk1, Llk2 and capacitors C1, C2 which generate the ZCS turn-off mechanism for diodes D1, D2 and release the reverse-recovery problem on diodes. This study is mainly arranged into five sections. Following the introduction, the operation principles and design considerations are represented in Section II and Ⅲ, respectively. Section Ⅳ and Ⅴ present a 400W design example and experimental results to verify the effectiveness of the proposed converter. Finally, some conclusions are described in Section Ⅵ. II. OPERATIONAL PRINCIPLES

The circuit configuration of the proposed converter is depicted in Fig. 1. Main switch S1 and auxiliary switch S2 are operated by asymmetrical PWM scheme with a short dead time td. In order to simplify the analysis, the power transformer T is represented by an ideal transformer with the magnetizing inductor Lm in primary side and the leakage inductors Llk1, Llk2 connected in series with each secondary winding ns. In addition, the other assumptions are made as follows. 1) Power switches are ideal expect for their body diodes and output capacitors. 2) The conductive voltage drops of diodes are neglected at secondary side of transformer. 3) The ripple voltage of clamp capacitor CC is neglected due to the clamp capacitance is large enough. 4) The magnetizing inductor Lm is much larger than leakage inductors Llk1 and Llk2. The key waveforms and equivalent circuit for each stages of the proposed converter are shown in Fig. 2 and Fig. 3, respectively. One switching cycle is divided into eight stages. Prior to stage 1, the auxiliary switch S2 is in the ON-state. Since the secondary current isec is zero, hence the primary current ipri is a negative value, which is equal to magnetizing current iLm. Stage 1(t0 ~ t1): This stage begins at t0 when auxiliary switch S2 is turned off. According to the reflected negative voltage across the secondary winding of the transformer, diode D1 is reverse-biased and diode D2 is still forward-based. During this stage, the negative primary

411

Stage 6(t5 ~ t6): When the voltage across auxiliary switch S2 arrives at zero. the angular resonant L lk1 (C1 + C 2 ) and the resonant impedance Z r1 is L lk1 (C1 + C 2 ) . The leakage inductor current iLlk2. To facilitate ZVS for S2. Stage 3(t2 ~ t3): At time t = t2. From (1) and (2). The magnetizing current can be obtained as V i Lm ( t ) = i Lm ( t 1 ) + in ( t − t 1 ) (1) Lm In the secondary side of transformer. moreover. the current through the diode D2 is zero even though it remains to be turned on. Owing to the capacitances of Cr1 and Cr2 are very small. This stage is finished when vCr1 is charged to vCc and vCr2 is discharged to zero. therefore the primary current ipri and the magnetizing current iLm maintain as a constant value. the reverse-recovery problem of D2 can be removed. the main switch current iS1 now increase at a linear rate determined by the input voltage. Because of this. Stage 2(t1 ~ t2): At time t = t1. The magnetizing current can be written as V − Vin i Lm ( t ) = i Lm ( t 5 ) − Cc (t − t 5 ) (6) Lm In the secondary side of transformer. Circuit configuration of the proposed converter. n 2 Vin − nv C1 ( t 1 ) Vin (t − t1 ) + sin[ω r1 ( t − t 1 )] (5) Lm Z r1 Fig. the voltage across main switch S1 becomes zero. the primary current ipri conducts through the body diode of S2 into clamp capacitor Cc. where the primary current ipri still remains negative value. In the primary side of transformer. hence the interval of this mode is very short. diode D2 turns on due to the voltage across primary winding of transformer has increased to the point where the reflected voltage across secondary winding of transformer is sufficient to forward bias diode D2. Key waveforms for stage analysis. The primary current ipri charges the parasitic capacitor Cr1 of S1 from zero to VCc and discharges the parasitic capacitor Cr2 of S2 from VCc to zero. the secondary current isec and the capacitor voltages vC1. Therefore. the primary current ipri and the magnetizing current iLm are almost constant. As long as S1 is turned on before the primary current ipri becomes positive value. main switch S1 is turned on. Thus the ZVS operation of S1 is achieved. 1. since the diode D2 turns on.PEDS2009 current ipri discharges the parasitical capacitor of main switch and charges the parasitical capacitor of auxiliary switch. The leakage inductor Llk1 and the capacitors C1. the primary current ipri equals the sum of the magnetizing current and the reflected current of secondary current isec. The leakage inductor current iLlk1. 2. the main switch S1 is turned off. vC2 are calculated as follows: n (VCc − Vin ) − v C 2 ( t 5 ) sin[ω r 2 ( t − t 5 )] (7) i Llk 2 ( t ) = Z r2 412 . respectively. the leakage inductor Llk2 and the capacitors C1. the magnetizing inductor current iLm increases in an approximately linear manner. Thus. C2 resonate like Mode 2 until the secondary current isec becomes zero. In this interval. Owing to the magnetizing inductor Lm is being charged by input power source Vin. the secondary current isec and the capacitor voltages vC1. the main switch current iS1 can be calculated as (5). the current through secondary winding isec has become zero. i pri ( t ) = i Lm ( t 1 ) + Fig. There are no current through primary winding during this stage due to the secondary windings are reverse polarity. the leakage inductor Llk1 and the capacitors C1. the primary current ipri begins to flow through the body diode of S1. The magnetizing inductor Lm is discharged linearly by clamp capacitor CC. C2 resonate similar to stage2. respectively. S1 can be operated on ZVS operation. the switch has to turn on before current reverses. vC2 are calculated as i Llk1 ( t ) = i D1 ( t ) = i sec ( t ) = nVin − v C1 ( t 1 ) sin[ω r1 ( t − t 1 )] (2) Z r1 v C1 ( t ) = [ v C1 ( t 1 ) − nVin ] cos[ω r1 ( t − t 1 )] v C 2 ( t ) = Vo − [ v C1 ( t 1 ) − nVin ] cos[ω r1 ( t − t 1 )] where the turn ratio frequency ω r1 is 1 (3) (4) n is ns n p . Stage 4(t3 ~ t4): At time t = t3. Stage 5(t4 ~ t5): At time t = t4. C2 begin to resonate. The time interval of this stage is very brief due to small parasitical capacitances.

(d) (e) (a) (f) (b) (g) 413 . the sequence of topologies is then repeated. Stage 7(t6 ~ t7): At time t = t6. the auxiliary switch current iS2 equals the sum of the magnetizing current and the reflected current of secondary current isec. When the auxiliary switch S2 is turned off at time t = t0. Stage 8(t7 ~ t0): At time t = t7. the leakage inductor Llk2 and the capacitors C1. Due to diode D1 can be turned off with zero current. C2 resonate similar to stage 6 until the secondary current isec returns to zero at time t = t7. In this interval. the auxiliary switch S2 is triggered under the condition of ZVS. Under the assumption of an infinite value of clamp capacitor. the primary current ipri is equal the magnetizing current iLm and decreases at a linear rate determined by input voltage plus clamp capacitor voltage. since the positive primary current ipri still flows through the body diode of S2 to charge the clamp capacitor Cc. the reverse-recovery problem is solved. the reflected secondary current becomes zero.PEDS2009 (8) v C1 ( t ) = [ v C 2 ( t 5 ) − n (VCc − Vin )] cos[ω r 2 ( t − t 5 )] v C2 ( t ) = Vo − [ v C2 ( t 5 ) − n (VCc − Vin )] cos[ω r 2 ( t − t 5 )] (9) From (8) and (11). V i pri ( t ) = i Lm ( t 5 ) + in ( t − t 5 ) Lm (10) 2 n (VCc − Vin ) − nv C 2 ( t 5 ) + sin[ω r 2 ( t − t 5 )] Zr2 where 1 the angular resonant frequency ωr 2 (c) is L lk 2 (C1 + C 2 ) and the resonant impedance Z r 2 is L lk 2 (C1 + C 2 ) .

stress = VCc. D (1 − D max ) 2 Ts Vo L m < max (31) 2n 2 I o. C2.peak ≈ I o Ts 2 L lk 2 (C1 + C 2 ) (25) ( C1 + C 2 ) < (1 − D max ) 2 DTs = n (VCc − Vin )(1 − D)Ts n 2Lm (12) (1 − D)Ts (13) n 2 L m + L lk 2 where Ts is the time period of switching cycle and D is the duty cycle of the main switch S1. the ZVS mechanism of auxiliary switch S2 is alike a linear charging manner. The series resonant phenomenon occurs in the secondary side by capacitors C1.rms ≈ 2 I D1. πf s ω r1 > (20) D min On the other hand. πf s ωr2 > (21) 1 − D max From (20) and (21). Operation stages of the proposed converter III. one half of the resonant period must be shorter than the minimum on time of main switch S1. For the ZVS condition of main switch S1. thus the average current of main switch equals the magnetizing inductor 414 . C2 and leakage inductors Llk1 resonant when main switch S1 is turned off in Stage 6 and 7. where the wave is similar to a sinusoidal wave.PEDS2009 ZCS operation of diode D2. DESIGN CONSIDERATIONS By utilizing the volt-second balance rule on the magnetizing inductor Lm. 3. leakage inductor Llk1.peak 2 2 I D 2.stress = VS2. As long as the primary current ipri is a positive value at time t = t5.max The switches S1 and S2 are operated on complementary pulse width modulation scheme. the input power is transferred to the output terminal through transformer T. the capacitors C1.av = ( )I o (30) nL m nL m 1− D From (29) and (30). and capacitors C1. peak ≈ VD 2.max = Vin (32) 1− D Owing to the average values of secondary current and auxiliary switch current are zero. the average current of magnetizing inductor equals input current. n 2 L m + L lk1 n 2 L m + L lk 2 D + i Lm. the output voltage Vo equals the sum of the capacitor voltage VC1 and VC2. Thus the peak current and root mean square current of diodes D1 and D2 can be approximately expressed as I o Ts I D1.peak ≈ (24) 2 L lk1 (C1 + C 2 ) I D 2. diode D1. the steady state equation can be obtained as Vin DTs = VCc (1 − D)Ts (11) VC1 n 2Lm n L m + L lk1 2 (23) π 2 f s2 L lk 2 From Kirchoff’s Current Law. VC1 and VC2 can be expressed as D VCc = Vin (14) 1− D n 2 L m + L lk1 VC1 = Vin (15) nL m n 2 L m + L lk 2 D Vin (16) nL m 1− D For Llk1 and Llk2 << Lm. i pri ( t 1 ) = i Lm ( t 1 ) < 0 (29) Since the average currents of the secondary side isec and auxiliary switch iS2 are zero. the capacitor voltages VCc. the secondary side current of transformer isec is the sum of two diode currents iD1 and iD2. the primary current ipri has to achieve a negative value at time t = t1. the ZVS operation of S2 can be easily achieved. the sum of capacitances C1 and C2 must satisfy the following relations to achieve the ZCS of all diodes.peak ≈ nVin + VC1 ≈ nVin (28) 1− D 1− D According to Mode 5 in section Ⅱ. C2 and leakage inductors Llk1. main switch S1. therefore the voltage stresses on switches S1 and S2 are 1 VS1. the magnetizing inductance Lm has to satisfy the following relation. (15) and (16) can be rewritten as D Vin VC1 = n (17) 1− D VC 2 = nVin (18) From (15) and (18).peak 2 π L lk1 (C1 + C 2 ) Ts π L lk 2 (C1 + C 2 ) Ts (26) (27) The voltage stresses of diodes D1 and D2 can be expressed as D 1 VD1. One half of the resonant period has to short than the maximum off time of main switch S1 to achieve VC 2 = nVin DTs = VC 2 I D1. n Vin Vo = VC1 + VC 2 ≈ (19) 1− D In Stage 2 and 3. To ensure the ZCS condition for diode D1.rms ≈ I D 2. D2 min (C1 + C 2 ) < 2 2 (22) π f s L lk1 (h) Fig.

(b) auxiliary switch S2.7μH. the current slopes of main switch and auxiliary switch are approximately equal to the current slope of magnetizing inductor since the secondary side current is quite low. the main switch S1 and the auxiliary switch S2 can be operated at ZVS turn-on under different output power condition and the drain voltage VS1. 5. thus the reverse-recovery problems of diode are completely removed. D2: HFA30PA60C(600V/15A).max = i Lm ( t 4 ) ≈ (34) nL m Table 1. 4 and Fig. Vo = 190VDC. Ae = 1. EXPERIMENTAL RESULTS (a) (b) Fig. fs = 90 kHz.max = i S2. 5. By observing Fig.PEDS2009 current iLm. RDS(ON). n Io (33) (1 − D) The maximum current of switches equals the maximum current of magnetizing inductor which can be approximately expressed as D(1 − D)Ts Vo i S1. 7 shows the experimental waveforms for primary side currents and secondary side currents of the transformer.av = i Lm. Llk2 = 1. EER-42 core. Parameters and components of the prototype circuit. S2: FS14SM-16A(800V/14A. The experimental waveforms of switches voltages and currents under 15% output power and rated output power are depicted in Fig.ds. Fig. 6 shows the voltages and currents of diodes D1. VS2. 4 Experimental waveforms for the ZVS turn on of the switches under 15% output power. (a) Capacitors Switches Diodes (b) Fig.7mm. 7(a). Cc = 0. D1.ds are clamped about 630V by active clamp circuit. fr1 = 139 kHz. The prototype circuit was experimental and tested to verify the performance of the adopted circuit. the 415 . Two diode currents decrease to zero before these turn off.47μF. From Fig.94 cm2. 6(a). The components and parameters of the prototype circuit were shown in Table 1. (a) main switch S1. Fig.av ≈ Input voltage Output voltage Output power Switching frequency Resonant frequency Transformer Vin = 380VDC.47μF. (a) main switch S1. C2 = 0. (b) auxiliary switch S2. 4. S1. C1 = 0. IV. 5 Experimental waveforms for the ZVS turn on of the switches under rated output power. In addition. D2 at secondary side under rated output power. I S1. 4 and Fig.5mm. fr2 = 126kHz. As can be seen from Fig. Po = 400W. Cin = 470μF/450V.47μF. Lm = 320μH. C2 and leakage inductor Llk2. C2 and leakage inductor Llk1 generated half-wave diode current iD1. Co = 820μF/250V.4μH. the resonant tank including capacitors C1. Secondary 15 turns of litz wire winding: 2×0. Form Fig. Llk1 = 1. Primary 46 turns of litz wire winding: 2×0. the diode current iD2 was generated by capacitors C1.max = 520 mΩ).

K. Kim. a laboratory prototype has been built to verify the effectiveness of the proposed converter and the maximum efficiency was measured to exceed 93%. vol. R. D2 are achieved. Youn. Lee. M. Jun. no. W. K. CONCLUSION (a) A soft-switching converter with dual resonant structures has been proposed. K. 53. Moon and M. vol. “New Cost-Effective PWM Single-Switch Isolated Converter. B. 19. H. E.” IEEE Trans. Circuits Syst.” IEEE Trans. 6 Experimental waveforms for the ZVS turn on of the diodes under rated output power. design and implementation of an active clamp forward converter with synchronous rectifier. Wang. 1715–1720. J. B. “Novel zero-voltage-transition PWM DC-DC converters.” IEEE Trans. (b) Fig. vol. no. (b) Fig. Y. “Analysis and implementation of a ZVS-PWM Converter With Series-Connected Transformers. I. Kim. E. The active clamp circuit has been employed to limit the voltage stress of power switches and provided the ZVS feature. 699–710. 53.. J. pp. Chiang and C. G. pp. “A Step-Up DC-DC Converter with a Resonant Voltage Doubler. respectively. Kwon. Kwon. (b) diode D2. vol. 1. 3267–3275. Electron. which resonant frequencies are almost as 139 kHz and 126kHz. Feb. S2 and ZCS turn-off feature for diodes D1. H. Oct. IEEE PESC. Theory Appl. (b) secondary side. “Dual Series-Resonant Active-Clamp Converter. On the secondary side of transformer. Finally. Conf. Park. Mar. 54. 917–921. pp.. “New Multi-Output LLC Resonant Converter for High Efficiency and Low Cost PDP Power Module. B. B. 2004. 7 Experimental waveforms for primary side currents and secondary side currents of the transformer. W.. Moon and M. 7(b). E. M. C. Ind. Lin. C2. the resonant tanks composed by the leakage inductors Llk1. K. 10. vol. Electron. Owing to the ZVS turn-on feature for power switches S1. Kim and B. J. no. Youn. Express Briefs. vol. Ind. Huang and D. no. R. Kwon. 2007. 254–262. 2006.” IEEE Trans. 411–419. (a) diode D1. 6. 1–7. “Analysis and Design of Phase Shift Full Bridge Converter With Series-Connected Two Transformers. J. J. According to Fig. J. Chen. 2008. G. Llk2 and capacitors C1. Moon and J.. V. the switching losses and reverse-recovery losses could be reduced. iD2 are generated by the leakage inductors Llk1. no. G. 2. Electron. Y. Llk2 and capacitors C1. Circuits Syst. Lin.” IEEE Trans. C. Feb. REFERENCES [1] C. pp. (a) Primary side. 2006. Fundam. therefore the maximum efficiency is over 93%. 1310–1319. pp. K. W. Power Electron. 2007.” in Rec. Park. C. pp. Koo.. no. D2. H. II.” IEEE Trans. Dec. pp. IEEE PESC. the diode currents iD1. [2] [3] [4] [5] [6] [7] [8] (a) 416 ..” in Rec. B. pp. 55. Chio and B. 6. Operation principle. Yoon. G. Lee. 2006. Conf. Therefore. design consideration and realization have also been presented. Ind. 54. 2. Wang. C2 which generated half-wave diode currents and created the ZCS turn-off mechanism for diodes D1. 2007.PEDS2009 primary current is the sum of main switch current iS1 and auxiliary switch iS2. “Analysis. H. W.