# Assignment No 1

Designing using basic digital electronics & Register Transfer and Micro operations Course No. CSE211 Course Title: Computer Organization and Architecture Q1. Enable bit plays an important role in decoder expansions. How is this justified in designing (a) 3X8 line decoder using two 2X4 line decoders (b) 5X32 line decoder using four 3X8 and one 2X4 line decoders Q2. Discuss the basic logic behind counters i.e. how will you obtain 1000(8) from 0111(7)? How will you implement the same? How many flip flops will be complemented in a 10 bit binary counter to reach the next count after 1001100111? Q3. What will happen if buffer gate in the clock input of the register is removed? What is the role of clear and load signals in designing register with parallel load? Q4. The content of a four bit register is initially 1101. The register is shifted six times to the right with the serial input being 101101. What is the content of the register after each shift? Q5. Draw the block diagram to implement following register transfer statement yT2 : R2←R1, R1←R2 Q6. Register A holds the 8 bit binary 11011001. Determine the B operand and the logic microoperation to be performed in order to change the value in A to (a) 01101101 (b) 11111101 Q7. Design one stage of arithmetic logic shift unit. Q8. Identify at least two application areas (discuss their roles also) for (a) Encoder/Decoder (b) Multiplexers/Demultiplexer (c) Flip Flops

CSE211 Course Title: Computer Organization and Architecture Q1. Q6. How are data. address and control buses involved in data transfer to and from memory? Consider a computer system with 16 registers of 32 bit each and RAM of 1GB. . (b) Find out register size of registers in Pentium Processor. Draw timing diagram for D3T4: SC ← 0 Q4. Q7. address and control buses involved in data transfer to and from memory? Consider a computer system with 16 registers of 32 bit each and RAM of 1GB. Fetching and decoding of any instruction takes three clock cycles. How many clock cycles are needed to execute (a) LDA and STA (b) BUN and BSA (c) ISZ (d) AND and ADD Q2. Calculate the size of data bus and address bus required for the same. (a) How are data. Demonstrate the execution of interrupt cycle with the help of an example. How? Q3. Calculate the size of data bus and address bus required for the same. Why is micro programmed control better than hardwired? Identify some situations when hardwired is preferred. Q8. How is I bit useful in determining the type of instruction? Q5.Assignment No 2 Basic Computer Organization & Design and Instruction Cycle and Memory Reference Instruction Course No.

Indicate whether the following constitute a control. Give five examples of external interrupts and five examples of internal interrupts? What is the difference between a software interrupt and a sub routine call? Q8. status or a data transfer command: (a) Skip next instruction if flag is set (b) Seek a given record on magnetic disk (c) Check if I/O device is ready (d) Move printer paper to the beginning of next page (e) Read interface status register Q7. 11111 (multiplicand) and 10101(multiplier). A. 10100011 by 1011. Perform BCD addition and subtraction of 1254 and 456. Q4. Q and SC during the process of division of two binary numbers. Show the contents of E. Write the RISC 1 instructions in assembly language that will cause a jump to address 3200 if the Z(zero) status bit is equal to 1. A. Q and SC during the process of multiplication of two binary numbers. Q2. Show that adding B after A+B+1 restores the original value of A. What should be done with end carry? Q5. Perform the same multiplication using Booth Algorithm Q3. Show the contents of E.Assignment No 3 Central Processing Unit and Computer Arithmetic Course No. (a) Using immediate mode (b) Usng a relative address mode (assume that PC=3400) . CSE211 Course Title: Computer Organization and Architecture Q1. Q6.

Explain how a priority can be established in the interrupt service program? Q7. CPU. “Strobe control mechanism for asynchronous data transfer does not ensure whether the data transmitted by source unit is accepted by destination unit. What role does an interface play in resolving these differences? Q2. RAM. Q5. Design the architecture of DMA mode of operation and illustrate how various components namely. CSE211 Course Title: Computer Organization and Architecture Q1. How many characters per second can be transmitted over a 1200-baud line in each of the following modes? (Assume a character code of eight bits). Q6.” Suggest possible enhancement(s) to this mechanism to overcome this limitation? Q4. Design parallel priority interrupt hardware for a system with eight interrupt resources. Consider a computer with priority interrupt hardware. Q8 Why does DMA have priority over the CPU when both request a memory transfer? . (c) Asynchronous serial transmission with one stop bits. Enlist major differences that exist between central computer and the peripheral devices. (a) Synchronous serial transmission (b) Asynchronous serial transmission with two stop bits. Q3.Assignment No 4 I/O Organization and DMA Controller Course No. Any one of many sources can interrupt the computer and any interrupt request results in storing the return address and branching to a common interrupt routine. DMA Controller and I/O Peripheral interface each other. Quote some practical references to demonstrate isolated v/s Memory-mapped I/O.