Modified
Booth
Encoding
Radix-4 8-bit
Multiplier
Final Project Report

Da Huang, Afsaneh Nassery

 

 

Table of Contents
Table of Contents ...................................................................................................................... 2
Abstract: .................................................................................................................................... 3
System Diagram:............................................................................................................... 3
Performance Estimation: ................................................................................................... 5
Transistor number and Area estimation .................................................................... 5
Time Delay:............................................................................................................... 6
Power Consumption: ................................................................................................. 6
Project Floor plane: ........................................................................................................... 7
Sub circuit Design ..................................................................................................................... 8
Encoder Circuit ............................................................... Error! Bookmark not defined.
Decoder Circuit ............................................................... Error! Bookmark not defined.
12 Bit Adder circuit......................................................................................................... 12
Full System Design ................................................................................................................. 13
Test simulations………………………………………………………………………… 16
Summary ................................................................................. Error! Bookmark not defined.
Reference ................................................................................................................................ 20

Page 2 of 20 

 
 

Encoder.5um CMOS technology. Booth multiplication allows for smaller. Each unit schematic is shown below: For 8-bit Multiplicand. In this project. which is also a standard technique used in chip design. and provides significant improvements by reducing the number of partial product to half over “long multiplication” techniques. System Diagram: Y[7:0] 8 X[7:0] 8 8 8 8 “0” X[-1] X[0] X[1] Encode X[1] X[2] X[3] Encode 3 9 bit DECODE 3 7 9 bit DECODE 2 9 X[3] X[4] X[5] Encode 3 9 bit DECODE 12-BIT ADDER 9 X[5] X[6] X[7] Encode 3 7 9 bit DECODE 12-BIT ADDER 9 2 7 2 12-BIT ADDER 9 OUTPUT: P[15]p[14]P[13]P[12]P[11]P[10]P[9]P[8]P[7]P[6] P[5]P[4] P[3]P[2] P[1]P[0] System Architecture We applied three basic unit cells in this design: Encoder. we demonstrate an extendable system diagram for 8-bit radix-4 MBE algorithm.  Abstract: In this project. we have the following structure: Page 3 of 20      . and 12-bit Adder. we are building up a Modified Booth Encoding Radix-4 8-bit Multiplier using 0. Decoder. faster multiplication circuits through encoding the signed numbers to 2’s complement. decoder and Carry Look Ahead Adder (CLA) are presented in this system.

  Y[7:0] X[2i-1] X[2i] X[2i+1] ENCODER DECODER DECODER DECODER DECODER DECODER DECODER DECODER DECODER 12-bit Adder We use 3 4-bit CLA units to build up our 12bit adder circuit. The diagram is shown below. 4-bit CLA Adder: Page 4 of 20      .

  Performance Estimation: Transistor number and Area estimation T Num of Number Transisto Area for Area needed Gate(um Est.5 35805 NOR2 4 32 128 315 10080 XNOR 8 32 256 1147. 2) XOR2 8 30 240 885 26550 OR3 8 18 144 612.5 36720 2 r Est.5 11025 AND3 8 21217. 30 240 707. ype of Transisto Gate r And2 6 134 804 595 79730 OR2 6 62 372 577.25 Total 2184 Total 0.265 Area mm2 Transist 5 or Page 5 of 20      .

887 mW / MHz + 0.  Time Delay: From the system diagram.2092mW ( f = 100MHz ) Page 6 of 20      . Including the encoder. decoder and 3 adder. Power Consumption: Ptotal = Pstatic + Pdynamic = 1.205mW = 0. we have 38gate delay. each adder will give a 10 gate delay time. we can see the critical path is as below: For the 12-bit adder.

  Project Floor plane: Page 7 of 20      .

1 shows the schematic and the layout of 1 bit decoder block. This is the logic for the encoder block: M i = X1 . (a) (b) Decoder Block The decoder block generates the partial product from the selector signals that they are generated in encoder block. Fig. We design the 9 bit decoder using 9 blocks of 1bit decoder that their selector signals are the same and 9 blocks of half adder is used to make the partial product in the 2’s complement form in the negative cases. This is the logic for the 1bit decoder that generates 1 bit of the partial product: PPij =(YjXX 2 +Yj-1 XX 2 ) ⊕ M i Fig. X 2 = X1X 0 X -1 +X1 X 0 X -1 Here the schematic and the layout of the encoder. Page 8 of 20      . X=X 0 ⊕ X -1 .2 and 3 shows the schematic and the layout of 9 bit decoder block.  Sub circuit Design Encoder Block The encoder block generates the selector signals for each 3 bits of multiplicand.

3 9bit Decoder Block schematic Fig.1 1bit decoder block schematic and layout Fig.  Fig.3 9bit Decoder Block layout Page 9 of 20      .

The 4bit CLA contains 4 PFA units and one CLL unit. Block Diagram: Schematic 4bit Look Ahead ADDER Page 10 of 20      .  12 Bit Adder circuit Logic We use three 4bit Carry Look Ahead (CLA) Adder to make up the 12bit adder. which will increase the computation time.

  12bit Look ahead ADDER Page 11 of 20      .

  Layout 4bit Look Ahead ADDER layout 12bit Look ahead ADDER Page 12 of 20      .

we apply the highest partial product bit rather than the multiplicand bit. We finish this target at the generation partial product. This difference maybe come from we take a different approach to add sign bit.  Full System Design Logic Here we will show how the signed multiplier works. which is the 2’s complement result of partial products. Here is the sign extension for 16 bit x 16 bit. and also we extend 9bit result to 12bit. There are 3 or 2 bit sign extension for each partial product. Ei = Mi ⊕ PPi [8] This sign bit extension is different from the book and reference value. The book and reference paper all take the same way to put sign bit add at adder part. and how to extend the sign bit. We get the 9bit output from Decoder. Here shift two bit for each partial product. Except the highest bit set to be 0. Page 13 of 20      . Our 9bit decoder schematic carefully shows how this works.

  Here is the schematic and layout of the multiplier: Schematic Page 14 of 20      .

sign extension: We have sign extension on each partial product before they goes into 12 bit adder.  Encoder circuit: Decoder and bit shift. Page 15 of 20      .

and the lowest 2 bit goes to output directly. Page 16 of 20      . For each output of 12 bit adder. the highest 10 bits go to next adder.  Connection between adder blocks.

  Multiplier Layout Page 17 of 20      .

  Here is our DRC and LVS check results: Page 18 of 20      .

  Test Simulations: Digital Simulation Result: In order to make sure about the multiplication procedure we wrote the verilog code for all the blocks and check our multiplier with digital simulation. The table shows our simulation result: A[7:0] B[7:0] Output 00000001 00000001 0000000000000001 00001111 00000010 0000000000011110 00001111 00000100 0000000000111100 00001111 00001111 0000000000110001 10000001 00000100 1111111000000100 10110111 01011010 1110011001010110 Eldo Simulation Result: 12 bit CLA adder Eldo Simulation Result: Page 19 of 20      .

Stanford University. Ming-Tsai Chan. Thesis. Eduardo. Oklobdziji. C. Neil H. [5]: Vojin G. [3]: Leonardo L. David Harris [2]:G. Design of a Novel Radix-4 Booth Multiplier Page 20 of 20      .  Reference [1]: CMOS VLSI Design: A Circuits and Systems Perspective.de Oliveira. High-Speed VLSI Arithmetic Units: Adders and Multipliers [4 ]:Hsin-Lei Lin. Array Hybrid Multiplier versus Modified Booth Multiplier: Comparing Area and Power Consumption of Layout Implementations of Signed Radix-4 Architectures. Chang. 1994.E. Weste. Bewick. Thrid Edition. Fast Multiplication: Algorithm and Implementation PhD. Robert C. Sergio B.