VHDL

1. In VHDL, a port is A. a type of entity B. a type of architecture C. an input or output D. a type of variable

2. A VHDL component A. can be used once in each program B. is a predefined description of a logic function C. can be used in multiple times in a program D. is part of a data flow description E. answers (B) and (C) 3. A component is called for use in a program by using a A. signal B. variable C. component instantiation D. architecture declaration

4. Which of the following is the most accurate statement about VHDL entities and architectures? A. A component can have many entity declarations and many architectures. B. A component can have many entity declarations but only one architecture. C. A component can have only one entity declaration and many alternative architectures. D. A component can have only one entity declaration and only one architecture.

5. With reference to the VHDL behavioral model code segment below, which of the following statements is most accurate? ARCHITECTURE test_behav OF test IS VARIABLE x : BIT := ‘1’ ; BEGIN PROCESS ( in_sig, y)

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Data Flow Specification C. END test_behav. A. Y <= in_sig XOR x . A. attributes 2 . Structural Specification 7. The following fragment of code illustrates the use of what VHDL construct? IF clock’event AND clock = ‘1’ THEN output <= input +1 END IF. Structural model (because components can be easily added and removed) B. Mixture of all three methods (because the appropriate level of abstraction can be chosen which is best suited for our design) 8. A VHDL Model which uses abstract constructs (such as If-Then-Else) most likely represents which of the following styles of VHDL model? A. Which style of VHDL Model is most appropriate for use during the early stages of a design? A. D. BEGIN X := in_sig XOR y. A variable (x) is incorrectly declared in the process declaration section A signal (y) is incorrectly defined in the architecture declaration section Both the Variable and Signal declarations are incorrect. END PROCESS. Behavioral Specification B. C. Data Flow (RTL) model (because logic equations can be easily manipulated for design modifications) C. B. The code segment is error free 6. Behavioral model (because it is implementation independent) D.SIGNAL y : BIT := ‘0’.

B. END test. clocks C.B. 10. comments D. D. wire 3 . Which of the following is not a VHDL data object A. ARCHITECTURE example OF test IS BEGIN a <= y AND z AND clock. Signals y and z are incorrectly used as inputs within the architecture Signals a and b are incorrectly assigned values within the architecture Both (a) and (b) Code is error free. y. B. C. identifiers 9. z: OUT BIT. All VHDL processes execute concurrently Concurrent signal assignment statements are one-line processes Statements in a process execute sequentially All of the above 11. Which of the following statements most accurately identifies any errors in the VHDL Code fragment below? ENTITY test is PORT (a. b: IN BIT. D. variable C. clock: INOUT BIT). b <= y NOR z AND clock. signal B. Which of the following statements are true? A. END example. C. A. clock <= NOT clock.

Designing a combinational circuit requires state minimization. Structural Specification 13. TRUE / FALSE 14. Behavioral Specification B. Designing a sequential circuit requires the use of a feedback path. Data Flow Specification C. constant 12. Designing a combinational circuit requires the use of a flip-flop or memory element. TRUE / FALSE 15.D. A VHDL Model that exclusively uses concurrent signal assignment statements to describe the functionality of the design most likely represents which of the following styles of VHDL model? A. TRUE / FALSE 4 .