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/Contents/ 1. An Overview <#overview> 2. Different types of Synchronous Counters <#diff> * Binary UP Counters <#bc> * Binary Down Counters <#down> * Binary Up/Down Counters <#updown> * MOD-N/Divide-by-N Counters <#mod> * BCD Counters <#bcd> * Ring Counters <#ring> * Johnson/Twisted-Ring Counters <#johnson> * Loadable/Presettable Counters <#load> 3. A Comparison between Synchronous and Asynchronous Counters <#compare> 4. Synchronous Counter Design <#design> * Multiplexer <#mux> * Read-Only Memory <#rom> * Programmable Logic Array <#pla> 5. Making Fast Counters <#fast> * Where speed is a concern... <#speed> * General Structure of a Synchronous Binary Counter <#struct> * Prescaling <#prescaling> * Pipelining <#pipelining> * Fast Counters From Xilinx <#xilinx> 6. Referennces <#ref> /An Overview/ The purpose of the survey is to collate information on */Digital Synchronous Counters. /*Particular emphasis was placed on the following areas : 1. 2. 3. 4. *//**/Types of Synchronous Counters and How they work /* */Fast Counter Techniques /* */Fast Counters from Xilinx /* */Implementation of Counters : Dedicated Hardware and Alternative Devices /*

The material is presented in a manner suitable for a teaching tool. It seeks to enlighten and to spark off interest in the design of counters. As R.S.S Obermann remarks "....design of counters has, in my experience, always been an excellent proving ground for anyone who has mastered Boolean algebra... Have fun reading !!!!! /Different types of Synchronous Counters / /*Binary Up Counters*/ A synchronous binary counter counts from 0 to 2^N -1, where N is the number of bits/flip-flops in the counter. Each flip-flop is used to represent one bit. The flip-flop in the lowest-order position is complemented/toggled with every clock pulse and a flip-flop in any other position is complemented on the next clock pulse provided all the bits in the lower-order positions are equal to 1.

. . There are many variations to the basic binary counter. the output of the first flip-flop will have to drive 10 gates (called fan-out. . Besides the up counter.Take for example A_4 A_3 A_2 A_1 = 0011. A_3 A_2 A_1 = 011. . The diagram below shows the implementation of a 4-bit synchronous up-counter. A_1 . use the first method. But A_4 is not complemented the lower-order positions. . we can organise it into 3 groups of 4. we can feed the outputs from the flip-flops directly to a many-input AND gate as follows : /4-bit Synchronous Binary Up Counter using speedup technique/ This method does overcomes the problem of additive propagation delay but introduces some other problem of its own. we will need to have : 1 * 15-input AND gate. A_2 is complemented because all the lower-order positions (A_1 only in this case) are 1's. there is the binary down counter. In the second method. Not only that. On the next count. This method obviously usus a lot more resources than the first method. 1 * 14-input AND gate. A_4 A_3 A_2 A_1 = 0100. we have a propagation delay through the AND gates which add up to give an overall propagation delay which is proportional to the number of bits of the counter. the output from each flip-flop is only used as an input to one AND gate. A_3 is also complemented because all the lower-order positions. the output from each flip-flop is used as an input to all the higher-order bits. in the first method. From the diagram above. If we have a counter that counts to for example 16 bits. we need a flip-flop for every bit and an AND gate for every bit except the first and the last bit. The "solution" to this is to use a compromise between the two methods. Within each group of 4. ------------------------------------------------------------------------ . . . . /4-bit Synchronous Binary Up-Counter / From the diagram above. the binary up/down counter. we can see that the third flip-flop gets its J-K input from the output of a 2-input AND gate and the fourth flip-flop gets its input from a 3-input AND gate and so on. do not give an all 1 condition. is always complemented. 1 * 3-input AND gate and 1 * 2-input AND gate. The one described above is the binary up counter (counts upwards). To implment a synchronous counter. we can see that although the counter is synchronous and is supposed to change simultaneously. If we have a 12-bit counter. To overcome this problem. Any counter that counts in binary is called a binary counter. The output from the flip-flop may not have the power to do this. we only have an overall gate propagation delay and a maximum fan-out of 3 instead of 10 using the first and second method respectively. binary-coded-decimal (BCD) counter etc. This way. A_2 and A_1 are 1's. Say we have a 12-bit counter. we use the second method and between the 3 groups. . the lowest-order bit.

If neither is at logic level 1.1. with the NAND gate. all the bits of the counter toggle at every clock pulse. Without the NAND gate. A_3 is also complemented because all the lower-order positions. In some cases. we use two AND gates for each flip-flop to "choose" which of the output to use. On the next count. where N is the number od bits/flip-flops in the counter. the normal output or the inverted one. That is. is always complemented. A_2 and A_1 are 0's. This can be done by allowing the counter to skip states that are normally part of the counting sequence. . /3-bit Synchronous Binary Up/Down Counter/ From the diagram. The OR gate allows either of the two outputs which have been enabled to be fed into the next flip-flop. the output from the NAND gate is connected to the asynchronous CLEAR inputs of each flip-flop. One of the most common methods is to use the CLEAR input on the flip-flops. The opposite is true for binary down counters./*Binary Down Counters*/ In a binary up counter. the lowest-order bit. -----------------------------------------------------------------------/*Binary Up/Down Counters*/ The similarities between the implementation of a binary up counter and a binary down counter leads to the possibility of a binary up/down counter. A_3 A_2 A_1 = 011. the speed up techniques apply. As with the binary up and binary down counter. a particular bit. Now. the counter doesn't count and if both are at logic level 1. /3-bit Synchronous Binary MOD-6 Counter / In the example above. The inputs to the NAND gate are the outputs of the B and C flip-flops. which is a binary up counter and a binary down counter combined into one.1. except for the first bit. we can see that COUNT-UP and COUNT-DOWN are used as control inputs to determine whether the normal flip-flop outputs or the inverted ones are fed into the J-K inputs of the following flip-flops. But A_4 is not complemented the lower-order positions. All the methods used improve a binary up counter can be similarly applied here. Taking an example. /4-bit Synchronous Binary Down Counter / The implementation of a synchronous binary down counter is exactly the same as that of a synchronous binary up counter except that the inverted output from each flip-flop is used. it is a MOD-8 counter. -----------------------------------------------------------------------/*MOD-N/Divide-by-N Counters*/ Normal binary counter counts from 0 to 2^N . toggles if all the lower-order bits are 1's. we have a MOD-6 counter. a particular bit toggles if all the lower-order bits are 0's and the first bit toggles on every pulse. A_1 . do not give an all 0 condition. A_4 A_3 A_2 A_1 = 0011. Since the difference is only in which output of the flip-flop to use. we want it to count to numbers other than 2^N . There are a few methods of doing this. A_2 is complemented because all the lower-order positions (A_1 only in this case) are 0's. A_4 A_3 A_2 A_1 = 0100.

We don't have to worry about this here because even if the system does go to the 111 state. We can essentially say that the counter skips 110 and 111 so that it goes only six different states. a valid state) on the next clock pulse. 0001. At the first pulse. the NAND output will immediately clear the counter to state 000. The counter will therefore count from 000 to 101. In a state machine with unused states. be in state 110 before the counter is cleared. hence the name ring counter. we need to make sure that the unused states do not cause the system to hang. At the fourth pulse. all the flip-flops will be cleared when B = C = 1 (110_2 = 6_10 ). it is a MOD-6 counter. This state is called the temporary state and the counter usually only remains in a temporary state for a few nanoseconds. A ring counter requires more flip-flops than a binary counter for the same MOD number. -----------------------------------------------------------------------/*Binary Coded Decimal (BCD) Counters*/ The BCD counter is just a special case of the MOD-N counter (N = 10). a MOD-8 ring counter requires 8 flip-flops while a MOD-8 binary counter only requires 3 (2^3 = 8). it will go to state 000. and one MOD-2 counter (for the first digit of the hour). The ring counter above functions as a MOD-4 counter since it has four distinct states and each flip-flop output waveform has a frequency equal to one-fourth of the clock frequency. When the counter goess from state 101 to state 110. This glitch is very narrow and will not normally be a problem unless it is used to drive other circuitry outside the counter. The next pulse produces the 0010 state and the third. and for a very short period of time. -----------------------------------------------------------------------/*Ring Counters*/ Ring counters are implemented using shift registers. thus. assuming a starting state of Q_3 = 1 and Q_2 = Q_1 = Q_0 = 0. why do we still need ring counters? One main reason is because . we need 3 BCD counters (for the second digit of the hour. ie. minute and second for example. BCD counters are very commonly used because most human beings count in decimal. A MOD-N ring counter will require N flip-flops connected in the arrangement as the diagram above. There is usually only a single 1 circulating in the register. The 111 state is the unused state here. Once the flip-flops have been cleared.So. To make a digital clock which can tell the hour. It is essentially a circulating shift register connected so that the last flip-flop shifts its value into the first flip-flop. the 1 shifts from Q_3 to Q_2 and the counter is in the 0100 state. A ring counter can be constructed for any MOD number. as long as clock pulses are applied. two MOD-6 counters (for the first digit of the minute and second). the 1 at Q_0 is transferred back to Q_3 . So if a ring counter is less efficient in the use of flip-flops than a binary counter. resulting in the 1000 state. For example. the B = C = 1 condition no longer exists and the NAND output goes back to high. Subsequent pulses will cause the sequence to repeat. no way to get out of the state. We also have to note that the temporary state causes a spike or glitch on the output waveform of B. minute and second). which is the initial state. /4-bit Synchronous Ring Counter / In the diagram above.

On the first clock pulse. at the count of 0. In the example above. we will get the states 001 and 000. two of the N flip-flops used will be in a unique combination of states. As with the binary counter. also known as the twisted-ring counter. it sometimes represents a logical choice for certain applications. an AND gate with inputs (not Q_2 ) and (not Q_2 ) can be used to decode for this state. So for a given MOD number. Thus. using the same reasoning. regardless of the number of flip-flops in the counter. the combination Q_2 = Q_1 = 0 occurs only once in the counting sequence. it must start with only one flip-flop in the 1 state and all the others at 0. The MOD number of a Johnson counter is twice the number of flip-flops. a Johnson counter requires only half the number of flip-flops needed for a ring counter. 110. The reason for this is that for each state. -----------------------------------------------------------------------/*Johnson/Twisted-Ring Counters*/ The Johnson counter. On the third clock pulse. 100. it is necessary to preset the counter to the required starting state before the clock pulses are applied. is exactly the same as the ring counter except that the inverted output of the last flip-flop is connected to the input of the first flip-flop. /4-bit Synchronous Johnson Counter / The Johnson counter works in the following way : Take the initial state of the counter to be 000. one logic gate (AND gate) is required to decode each state. In fact. giving the state 011. which is the initial state again. the inverse of the last flip-flop. However. ring counters can be decoded without the use of logic gates. Note that we are comparing with the binary counter using the speed up technique discussed above. A Johnson counter requires fewer flip-flops than a ring counter but generally more than a binary counter. three flip-flops were used to create the MOD-6 Johnson counter. In the example above. will be shifted to the first flip-flop. Thus. a Johnson counter requires decoding gates whereas a ring counter doesn't. 011 and 001. The decoding signal is obtained at the output of its corresponding flip-flop. On the second clock pulse. One way to do this is to apply a pulse to the PRESET input of one of the flip-flops and the CLEAR inputs of all the others. On the fourth clock pulse. Thus this is a MOD-6 Johnson counter. On the fifth and sixth clock pulse. For the ring counter to operate properly. producing the state 100. Hence. this Johnson counter has six distinct states : 000. since the last flip-flop is still at level 0. the inverse of the last flip-flop will be fed into the first flip-flop. but with the Johnson counter. giving the state 110. it has more decoding circuitry than a ring counter but less than a binary counter. another 1 will be fed into the first flip-flop. now a 0. A Johnson counters represent a middle ground between ring counters and binary counters. 111. Since it is not possible to expect the counter to come up to this state when power is first applied to the circuit. This will place a single 1 in the ring counter. .ring counters are much easier to decode. and the sequence is repeated so long as there is input pulse. each gate requires only two inputs. the state 111 is produced. The state 010 does not occur. The same characteristic is shared by all the other states in the sequence.

/4-bit Ripple Counter / It can be seen that a ripple counter requires less circuitry than a synchronous counter. This means that they can be preset to any desired starting value. This will asynchronously transfer P_2 . P_1 and P_0 and a LOW pulse is applied to the PARALLEL LOAD input. This can be done either asynchronously (independent of the clock signal or synchronously (on the active transition of the clock signal). This transfer occurs independently of the J. the J. starting from the number that was loaded into the counter. the propagation delays of the flip-flops add together to produce the overall delay. P_1 = 0. /A comparison between Synchronous and Asynchronous Counters/ Asynchronous counters. these inputs have no effect. there are certain "risks" when using an asynchronous counter. and the external event is used to produce a pulse which is synchronised with this internal clock. The flip-flops in an asynchronous counter is usually clocked by the output pulse of the preceding flip-flop. For the example above. The counter is loaded by applying the desired binary number to the inputs P_2 . are not clocked by a common pulse and hence every flip-flop in the counter changes at different times. In a synchronous counter. not(PL). When not(PL) is high. the asynchronous counter is slow. The asynchronous PRESET and CLEAR inputs are used to perform the asynchronous presetting. The counter will then continue counting from 101. The counter will perform normal count-up operations if there are clock pulses. the slower it will be. The first flip-flop is clocked by an external event. hence the name loadable counter. P_1 and P_0 into the flip-flops. First of all. This will produce LOW states at the CLEAR input of Q_1 . No logic gates are used at all in the example above. /3-bit Synchronous Binary Presettable Counter/ In the diagram above. Q_1 = 1 and Q_0 = 0. K.-----------------------------------------------------------------------/*Loadable/Presettable Counters*/ Many synchronous counters available as ICs are designed to be presettable. the counter resumes counting. This will make the counter go to state 101 regardless of what is occuring at the CLK input. . the more bits or number of flip-flops in an asynchronous counter. and CLK inputs. and the PRESET inputs of Q_2 and Q_0 . This presetting operation is also known as loading. As long as not(PL) remains in the LOW state. Hence. and P_0 = 1. After not(PL) returns to high. The diagram below shows a 3-bit asynchronously presettable synchronous up counter. it has some major disadvantages over the synchronous counter. has an internal clock. all the flip-flops will change states simultaneously while for an asynchronous counter. also known as ripple counters. Now let's say that not(PL) goes low at Q_2 = 0. say that P_2 = 1. Although the asynchronous counter is easier to construct. The diagram of an ripple counter is shown below. The counter will remain at state 101 until not(PL) goes back to HIGH. Secondly. the CLK input has no effect on the flip-flop. K and CLK inputs are wired the same way as a synchronous up counter. A synchronous counter however.

there is a small chance that it will occur near a clock transition. or 65. Using logic gates is the traditional method of implementing combinational logic and has been applied for decades. No wiring change is necessary. and all the words stored in these have to be decoded. However there are other methods of implementing combinational logic which offers other advantages.doc. When used as a combinational logic device.In a complex system. The PLA only decodes a small percentage of the minterms. it can also be used to implement combinational logic. A ROM with 16 input address lines must have 2^16 . 2^n input lines and 1 output line (and usually also a complement of the output). also called the data selector.536 storage locations. As with the MUX. This intermingling of transitions often causes erroneous operations.html>. More information on these devices are given in article 2 of cwl3 <http://www-dse. -----------------------------------------------------------------------/*Read-Only Memory*/ The ROM is usually used as a storage unit for fixed programs in a computer. a different ROM producing this function can be plugged into the circuit. And the worse this is that these problems are difficult to forsee and test for because of the random time difference between the events. each input line is used to represent a variable and the 2^n locations represent the minterms. Some of the alternative methods which are discussed here are: multiplexers (MUX). The ROM has n input lines pointing to 2^n locations within the ROM that store words of M bits. However. The PLA is sometimes used to produce a system with a small number of chips in a minimum time. it is still a popular approach. When a different function is required. -----------------------------------------------------------------------/*Programmable Logic Array*/ The PLA is very similar to the ROM. many state changes occur on each clock edge and some ICs respond faster than others. The 2^n possible combinations of the select inputs connects one of the input lines to the output. . /Synchronous Counter Design/ A synchronous counter usually consists of two parts: the memory element and the combinational element.ic. the n select inputs represent n variables and the 2^n input lines represent all the minterms of the n variables.ac. read-only memory (ROM) and programmable logic array (PLA). Since this method often results in minimum component cost for many combinational systems.uk/~nd/surprise_96/journal/vol2/cwl3/article2. The memory element is implemented using flip-flops while the combinational element can be implemented in a number of ways. If an external event is allowed to affect a system whenever it occurs (unsynchronised). after some IC's have responded. but before others have. it has n select inputs. It is useful for systems requiring changeable functions. -----------------------------------------------------------------------/*Multiplexer*/ The multiplexer. It can be thought of as a ROM with a large percentage of its locations deleted.

B. The /T/ implies a /T/ flip-flop. It becomes a problem when the counter . only the propagation delay of 1 AND gate has to be considered.. From the diagrams. C). the parallel synchronous carry counter operates at a greater maximum frequency. In applications that require speed. Therefore. From the diagrams. The output current of a flip-flop may not be large enough to drive that many gates. The signals are propagated serially and in parallel (to each AND gate) in the first and second case respectively. it can be seen that the least significant bit Q0 toggles on every clock pulse. These two counters are illustrated as follows : /Series Carry Synchronous Counter/ /Parallel Carry Synchronous Counter/ Both counters depicted above are /binary-up counters/. We will be looking at some technique commonly used to improve the speed of a counter. the /series carry synchronous counter / and the /parallel carry synchronous counter/. (see diagrams above) In the series carry scheme. This structure does have limitations. some commercial counters (by Xilinx) will be considered. the time to propagate the change in /Q0/must take into account the propagation delays of the 3 AND gates (A. The parallel carry scheme results in a much faster counter. it can be seen that a single flip-flop output(consider /Q0/) has to drive a number of subsequent AND gates. To reinforce. These are... This is illustrated by the /highlighted paths/. In the parallel carry scheme. this scheme is commonly used. the concepts presented. To illustrate the worst case delay in both cases. For example./Making Fast Counters/ */Where speed is a concern./* In certain application. counters used in communication and certain instrumentation applications are necessarily fast. namely. speed is an important factor affecting the choice of a counter. and subsequent bits toggle when preceding bits are high. -----------------------------------------------------------------------/*General Structure of a Synchronous Binary Counter */ There are two common ways in which a synchronous binary counter is structured. The important distinction between the two counters is the way the /EN/ signals propagate from Q0 to Q3. This difference in speed is accounted for by the delay encountered during the propagation of the /EN/ signals. Thus. the /minimum clock period/ of the parallel scheme is shorter. The flip-flop complements/toggles its output on the rising edge of a clock pulse provided its enable (/EN/) input is high. we consider a /change in Q0 from 0 to 1/. This structure is believed to be the fastest synchronous binary counter structure.

The prescaling stage is sometimes provided by a dedicated prescaling device known as the /Prescaler/. Its speed can be improved by using some form of /Prescaling/. however. it does not suffer the same drawback as the parallel carry scheme. a carry is also generated (/UC/ and /TC/) . The reader does not have to concern himself or herself with the implementation of the prescaler. How exactly this tree will look like is an engineering choice. This makes it a suitable basis for making big counters. The reader should. a tree of AND gates is usually used. This device/circuit is designed primarily using /Emitter Coupled Logic (ECL) /. Note that a section /stops counting/ when zero has been reached. The characteristic of a "pulse swallowing" counter is that it stops counting when a predetermined number of pulses has been received. This choice will reflect the trade-off between speed requirements and the constraint mentioned above. This makes it suitable for high speed counting work. Although the series carry scheme is slower. The following diagram shows a down-counting Binary Coded Decimal (BCD) counter in a simplified "pulse swallowing" setup. The curious reader would probably be wondering how the actual (and faster) incoming clock frequency is actually reflected in the slower counting circuit. slower counting circuit. There are a number of ways in which a prescaler can be used. but one sophisticated setup is the /"pulse swallowing"/ counter. it has little or no counting features since such features will only impede its operating speed. -----------------------------------------------------------------------/*Prescaling*/ /" The Concept "/ The idea of /prescaling/ is to provide a /"prescaling"/ stage between the/incoming clock frquency/ and the counting circuit. a /divide-by-n/ prescaler will generate a pulse when it has received /n/ input pulses. Consequently. This "clock" pulse is then fed to the counting circuit. /UC/ is fed back to the prescaler as the .gets bigger. there are prescalers that can accept a range of frequencies ranging from a few hundred Megahertx to a few Gigahertz. The point of the prescaler is to divide an incoming clock and. The outputs(/Q3-Q0/) reset to the preset values when /Pe/ is high. the /Tens/ and /Units/ sections of a BCD counter are shown. understand the function it performs in the overall counter. thereby provide a clock to a larger. Both sections are presettable via/P3-P0/. Despite its suitability to high speed counting work. This technique will be considered in subsequent sections. ECL benefits from very fast switching capabilities. /BCD Pulse Swallowing Counter/ In the above setup. A prescaler generates a /"clock"/ pulse after it has received a number of input pulses. For example. To overcome this. At present.

Upon prediction. the prescaler divides-by. How does this actually help in speeding things up? Let's say the detection of an event and the setting of the required outputs take 20ns. They appear at the outputs on the next clock pulse when the event actually occurs. These new value(s) are /stored/latched/ using flip-flops (usually D type). This is reflected in the slower counter by /simultaneously / driving the Tens and Units section. The propagation of the outputs takes another 10ns. let's consider an example. To demonstrate the principle of "pulse swallowing"./10/ or/11/ repectively before generating a "clock" pulse. If the above actions had to be performed in one clock cycle. If these two sets of ./Mode(M)/ input signal. a "pulse swallowing" counter "swallows up" fast incoming clock pulses. When /M/ is high or low. It "predicts" an event one(usually) clock cycle before it is to occur. certain output value(s) (resulting that from that event) are set. the minimum clock period would be 30 ns(without pipelining). Suppose we preset a value of 32 (0011 0010). The outputs will have values as shown below : * Tens Units Mode(M) Decimal Value ---------after 0 clock pulses----------0011 0010 0 32 ---------after 11 clock pulses---------0010 0001 0 21 ---------after 22 clock pulses---------0001 0000 1 10 ---------after 32 clock pulses---------0000 0000 1 00 ---------------------------------------* Effectively. -----------------------------------------------------------------------*/Pipelining/* /Pipelining/ is a /"predict and store" / technique. Consider the two situations where pipelining is used and not used. Therefore the net effect of such a combination (of prescaler and counter) is a counter operating at a much higher speed than what it was capable of alone.

xilinx. it looks complicated but the reader may have noticed that there are many similar blocks of logic circuitry. With this setup. the overall frequency/speed of the circuit is improved.preset via these inputs / On first sight. the minimum clock period is 20ns(with pipelining). an /inverted/ version of /Q0 / is propagated through AND gate /A/.002) Maximum Clock Frequency 8 bits : 71 MHz 16 bits : 55 Mhz This counter demonstrates the /parallel carry synchronous counter structure/ and the /pipelining technique/.com/toc. /when TERMINAL COUNT high/ /TERMINAL COUNT low/ As seen below. /*Consider block producing Q0*/ /Block Producing Q0 (least significant bit) / /TERMINAL COUNT high/ As seen below. Therefore the output of /B/ is /low/.actions were performed in two separate clock periods. Q0 toggles on every rising edge of the clock pulse. the /inverted/ version of /Q0 / is not propagated through .counter bits D. /D_0 / is not propagated through A because an /inverted /version of /TERMINAL COUNT/ is fed into /B/. Let's take a look at some of these blocks and see how they work.htm>/* # Synchronous Presettable Counter (Xilinx Application Notes XAPP 003. /Presettable Up Counter/ /Q. Let's consider an up-counting version of this counter. This is illustrated schematically as follows : " Pipelining speeds things up!! " -----------------------------------------------------------------------*/Fast Counters From /**/Xilinx <http://www. With pipelining.

The different outputs driving the AND gates are summarised schematically as follows : /AND Gate Tree Diagrams/ In this setup. /*Consider the Carry connections*/ /The Carry Connections/ Let's focus our attention on the generation of the /T/ outputs(see above). This minimises the worst case delay (compare with the series carry scheme). /when TERMINAL COUNT high/ /TERMINAL COUNT low/ The preset value is loaded on the next clock pulse as before. . /Q3/ toggles. /Q0/ will have the value of/D_0 / on the next clock pulse./A/. /D_0 / is propagated through /B / because an /inverted/ version of /TERMINAL COUNT/ is fed into /B/. Therefore. the /T/ input is replaced by /Q1/) Effectively. the output of the EX-OR gate /C/ will be propagated through /A/.It is noted that the preset value /D/ appears as the output /Q/ on the next clock pulse (after terminal count). The output of /C/ is /high/ when either(not both) /T_3 / or /Q3 / is /high/. Subsequent bits feed in parallel to the relevant AND gates. /when TERMINAL COUNT low/ /*Consider block producing Q3*/ /Block Producing Q3/ /TERMINAL COUNT high/ As seen below.(Note that in the /Q1/ stage. in all the bit stages. The additional gate delay introduced by /T_x / does not affect the critical paths from /Q0/ to /Q7/ because of the way the numbers change. This applies to all bit stages. Therefore. an output bit toggles when the preceding bits are high. /T_3 / is the /ANDED/ version of all preceding outputs(/Q0-Q2/ ). The output of the OR gate will have the value of /D_0 /. This counter uses an adapted version of the parallel carry scheme by employing an AND gate tree. /Q0/ is fed directly to the next bit stage and in parallel to all the /T(T2-T6) / AND gates. When /T_3 / is /high/. /Q3/ stays the same when /T_3 / is /low/.

The counter can be represented in a block diagram as follows : /Non-Loadable Binary Counter/ The counter is implemented on a Field Programmable Logic Device (FPGA). the required /TERMINAL COUNT/ value (/low/) is fed to the input of the flip-flop. /TERMINAL COUNT/ is low ("load preset value")./*Consider the Pipelining block*/ /Pipelining TERMINAL COUNT / When the counter output is 11111110. Therfore. The reader does not need to concern himself/herself with this. thereby slowing the counter down./CEP /. the least significant (/LS/) tri-bit(/Q0-Q2 /) provides the prescaling function. /CET/) are high. The counter employs the concept of /prescaling / but does not use a /dedicated prescaler/ (ECL device). Note : when any other values are detected. The /7/ clock cycles when the LS /CEO/ is /low/ gives the /CEO/-/CET/ /ripple chain/ (of subsequent tri-bits) time to settle. This would become clearer when we examine the actual implementation of this counter. the settling time would have to be taken into account when determining the minimum clock period of the counter. All tri-bits respond (increment) to a clock pulse if its /Count-Enable/ inputs (/CE/. /TB1/ ------------------------------------------------------------------------ .002) Max Clock Frequency 8 bits : 200 MHz 16 bits : 115 MHz The counter demonstrates /prescaling/ and /pipelining/. On the next clock pulse(when it is terminal count). This propagates the preset values (/D0-D7/) to the inputs of the flip-flops. This would significantly limit the minimum clock period. -----------------------------------------------------------------------# High-Speed Synchronous Prescaler Counter ( Xilinx Application Notes 001. when the value preceding terminal count is detected. This requires it to be implemented as tri-bit blocks(/TB1/ and /TB2 /) for optimal resource usage. Note that there is no change in the original clock rate. Instead. the NAND gate output is low. The /"prescaler"/ pulse effectively reduces the clock rate to the rest of the tri-bits by a factor of /8/. Thus /TERMINAL COUNT/ is /high / ("do not load preset value"). If this prescaling was not done. the NAND gate output is/high/. The /CEO/ of the /LS/ tri-bit is /high/ once in every /8/ clock cycles when all its outputs are high.

. the worst case delay is the propagation of this "information" from Q3 through the ripple chain and to the flip-flop input of Q23. As evident from the diagrams. the /Count-Enable/ inputs effectively "enable" or "disable" the complementing function. To appreciate the sigificance of this delay. The speed of the counter can be improved further by /pipelining/the LS /CEO/ signal : /Pipelining CEO / We see that when 110 is detected. /Generation of Q_a in TB1(A) and TB2(B)/ When the /Count-Enable/ inputs are high.. This does not affect the effective operating frequency of the counter because the "prescaler"(LS tri-bit) still operates at the faster clock rate. This value appears as /CEO/ on the next clock pulse(when 111 . /Qa/ and /Qc/ represent the LSB and MSB of a tri-bit respectively. /The Ripple Chain/ The delay of this ripple chain is the sum of all the gate delays presented by the chain of AND gates. Q3 will become 1./TB2/ Note : all clock inputs are assumed to be driven by a common clock..(all ones).110. This "information" about the change in Q3 has to be propagated to subsequent tri-bits before the next clock pulse. Suppose the current values from Q23-Q3 is 01111. /Generation of Q_b in TB1(A) and TB2(B)/ When both /Q_a / and the /Count-Enable/ inputs are high. let's consider an example. /Generation of CEO in TB1(A) and TB2(B)/ /CEO/s are /high/ only when /CE/s(or /CET/ s) and the outputs /Q/(/Q_a -Q_c /)are high. the complementing function is enabled. /Generation of Q_c / The generation of Qc is similar to the generation of Qb except that the value of Qb is also fed into the AND gate. Therefore. the EX-OR gate complements /Q_a /. This is necessary to ensure the correct changes(on the next clock pulse) to subsequent bits. The "prescaler" accommodates this delay by allowing time for the propagation of this "information".. /CEO/ is set and fed to the flip-flop input. On the next "prescaler" pulse. This delay is a major and common problem with most binary counters.

Since Q0 is high at this point. This additional prescaler is needed to accommodate a large counter(more bits). The effective "clock" rate provided by this prescaler is 1/2 of the actual clock rate. This counter eliminates the delay by replicating QO for bits after Q1. In the previous example. This value is fed to the Flip-flop input.occurs). Since QY01 is low. When the LS three bits are 101(Q2-Q0). On the next clock cycle. CEP2 is selected by the . the value of A is selected and appears at the output of multiplexer B. the output of AND gate A is high. This is done by the following chain/network of flip-flops : /Network To Replicate Q_0 / To best describe the function of such a network. the value appears as CEP2(high). This second prescaling stage allows the rest of the counting circuit to employ the /series carry scheme /. the LS bit Q0 acts as the "prescaler". The effective "clock" rate provided by this prescaler to the rest of the counter is /1/8/ of the actual clock rate. The use of such a carry scheme allows a larger counter to be constructed. The actual implemetation of LS tri-bit with pipelining is seen below : /Implemention of LS tri-bit with Pipeline / -----------------------------------------------------------------------# Ultra-Fast Synchronous Counter (Xilinx Application Notes XAPP 014. From the diagram.001) Maximum Clock Frequency 8 bits : 256MHz 16 bits : 108MHz /Ultra-Fast Counter/ In this counter. At this point. The effect of this is that bits after Q1 appear to be driven directly by Q0 and without the line transmission delay. let's take a look at the timing diagram depicting the output values : /The Timing Diagram/ It is seen that all QX0 outputs are in sync with Q0 after the initial delays. the LS three bits is 110. /The Second "Prescaler"/ Here Q1 and Q2 act as the second "prescaler". the distribution of the CEO signal (from the LS to the MS tri-bit) introduces a line transmission delay. CEP2 is pipelined. This improves the minimum clock period.

multiplexer.* *Title:* Logic Design Principles *Author(s):* Edward J. CEP2 is high again.* *Title:* *Author(s):* *Source:* *Type:* URL *Usefulness:* @ @ @ *Readability:* @ @ @@@ *Good* Counting and Counters R M M Oberman The Macmillan Press Ltd @@*Fair* -----------------------------------------------------------------------*2. This is summarised below : Q2 Q2 Q1 1 1 1 1 0 0 1 1 0 1 0 1 A 1 1 0 0 D-input(flip-flop) 0 1 1 0 CEP2 0 0 1 1 /References/ @@@@ *Excellent* @*Poor* *1. Thus.* *Title:* Electronic Counters *Author(s):* R M M Oberman *Source:* The Macmillan Press Ltd *Type:* URL *Usefulness:* @ @ *Readability:* @ @ -----------------------------------------------------------------------*3.* *Title:* Digital System Design *Author(s):* Barry Wilkinson with Rafic Makki *Source:* Prentice Hall International *Type:* URL . on the next clock cycle. McCluskey *Source:* Prentice Hall International *Type:* URL *Usefulness:* @ @ *Readability:* @ @ @ -----------------------------------------------------------------------*4.

* *Title:* Digital Logic Design *Author(s):* Brian Holdsworth *Source:* Butterworth-Heinemann Ltd *Type:* URL *Usefulness:* @ @ *1/2* *Readability:* @ @ @ -----------------------------------------------------------------------*9.* *Title:* Digital Design : Principles and Practices *Author(s):* John F.* *Title:* Practical Digital Design Using ICs *Author(s):* Joseph D. Greenfield *Source:* John Wiley & Sons *Type:* URL *Usefulness:* @ @ *Readability:* @ @ -----------------------------------------------------------------------*8. McCluskey .* *Title:* Digital Design *Author(s):* M.* *Title:* Digital Systems : Principles and Practices *Author(s):* Ronald J. Morris Mano *Source:* Prentice Hall International> *Type:* URL *Usefulness:* @ @ @ *1/2* *Readability:* @ @ @ @ -----------------------------------------------------------------------*10. Wakerly *Source:* Prentice Hall International *Type:* URL *Usefulness:* @ @ @ @ *Readability:* @ @ @ *1/2* -----------------------------------------------------------------------*6. Tocci *Source:* Prentice Hall International *Type:* URL *Usefulness:* @ @ @ *Readability:* @ @ @ @ -----------------------------------------------------------------------*7.*Usefulness:* @ @ @ *1/2* *Readability:* @ @ @ -----------------------------------------------------------------------*5.* *Title:* Logic Design Principles *Author(s):* Edward J.

* *Title:* Digital Electronics *Author(s):* Christopher E. *Type:* URL *Usefulness:* @ @ @ @ *Readability:* @ @ -----------------------------------------------------------------------*15.* *Title:* Digital Logic and State Machine Design *Author(s):* David J.*Source:* *Type:* URL *Usefulness:* Prentice Hall International @ @ *Readability:* @ @ @ -----------------------------------------------------------------------*11.* *Title:* Digital Circuits and Microprocessors *Author(s):* Herbert Taub *Source:* Prentice Hall International *Type:* URL *Usefulness:* @ @ *Readability:* @ @ @ -----------------------------------------------------------------------*14. *Source:* Xilinx Inc. Morris Mano *Source:* Prentice Hall International *Type:* URL .* *Title:* Digital Logic and Computer Design *Author(s):* M.* *Title:* The Programmable Logic Data Book *Author(s):* Xilinx Inc. Strangio *Source:* Prentice Hall International *Type:* URL *Usefulness:* @ @ @ *Readability:* @ @ @ -----------------------------------------------------------------------*12. Comer *Source:* Saunders College Publishing *Type:* URL *Usefulness:* @ @ *Readability:* @ @ @ -----------------------------------------------------------------------*13.

* *Title:* ISE Second Year Digital Electronics Notes *Author(s):* Mike Brookes *Source:* Mike Brookes *Type:* URL *Usefulness:* @ @ *Readability:* @ @ @ ----------------------------------------------------------------------------------------------------------------------------------------------- .*Usefulness:* @ @ *Readability:* @ @ @ -----------------------------------------------------------------------*16.

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