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Chapter 7 Complementary MOS (CMOS) Logic Design Microelectronic Circuit Design Richard C. Jaeger Travis N.

Chapter 7 Complementary MOS (CMOS) Logic Design

Microelectronic Circuit Design

Richard C. Jaeger Travis N. Blalock

Chapter Goals

Chapter Goals • Introduce CMOS logic concepts • Explore the voltage transfer characteristics CMOS inverters •

• Introduce CMOS logic concepts

• Explore the voltage transfer characteristics CMOS inverters

• Learn to design basic and complex logic gates

• Discuss static and dynamic power in CMOS logic

• Present expressions for dynamic performance of CMOS logic devices

• Present noise margins for CMOS logic

• Introduce dynamic logic and domino CMOS logic techniques

• Introduce design techniques for “cascade buffers”

• Explore layout of CMOS logic gates

• Discuss the concept of “latchup”

CMOS Inverter Technology

CMOS Inverter Technology • Complementary MOS, or CMOS, needs both PMOS and NMOS devices for their

• Complementary MOS, or CMOS, needs both PMOS and NMOS devices for their logic gates to be realized

• The concept of CMOS was introduced in 1963 by Wanlass and Sah, but it did not become common until the 1980’s as NMOS microprocessors were dissipating as much as 50 W and alternative design technique was needed

• CMOS still dominates digital IC design today

CMOS Inverter Technology

CMOS Inverter Technology • The CMOS inverter consists of a PMOS stacked on top on a

• The CMOS inverter consists of a PMOS stacked on top on a NMOS, but they need to be fabricated on the same wafer

• To accomplish this, the technique of “n-well” implantation is needed as shown in the figure which shows the cross- section of a CMOS inverter

is needed as shown in the figure which shows the cross- section of a CMOS inverter
is needed as shown in the figure which shows the cross- section of a CMOS inverter

Jaeger/Blalock

CMOS Inverter

CMOS Inverter (a) Circuit schematic for a CMOS inverter (b) Simplified operation model with a high
CMOS Inverter (a) Circuit schematic for a CMOS inverter (b) Simplified operation model with a high
(a) Circuit schematic for a CMOS inverter (b) Simplified operation model with a high input
(a)
Circuit schematic for a CMOS inverter
(b)
Simplified operation model with a high input applied
(c)
Simplified operation model with a low input applied

Jaeger/Blalock

CMOS Inverter Operation

CMOS Inverter Operation • When v I is pulled high (V D D ), the PMOS

When v I is pulled high (V DD ), the PMOS inverter is turned off, while the NMOS is turned on pulling the output down to V SS

When v I is pulled low (V SS ), the NMOS inverter is turned off, while the PMOS is turned on pulling the output up to V DD

CMOS Inverter Layout

CMOS Inverter Layout • Two methods of laying out a CMOS inverter are shown • The
CMOS Inverter Layout • Two methods of laying out a CMOS inverter are shown • The

• Two methods of laying out a CMOS inverter are shown

• The PMOS transistors lie within the n-well, whereas the NMOS transistors lie in the p- substrate

• Polysilicon is used to form common gate connections, and metal is used to tie the two drains together

Static Characteristics of the CMOS Inverter

Static Characteristics of the CMOS Inverter • The figure shows the two modes of static operation
Static Characteristics of the CMOS Inverter • The figure shows the two modes of static operation

• The figure shows the two modes of static operation with the circuit and simplified models

Notice that V H = 5V and V L = 0V, and that I D = 0A which means that there is no static power dissipation

= 0V, and that I D = 0A which means that there is no static power

Jaeger/Blalock

CMOS Voltage Transfer Characteristics

CMOS Voltage Transfer Characteristics • The VTC shown is for a CMOS inverte r that is
• The VTC shown is for a CMOS inverte r that is symmetrical (K P
The VTC shown is for a CMOS
inverte
r
that is symmetrical (K P = K N ) ‏
Region 1: v O = V H
v I < V TN
Region 2: |v DS | ≤ |v GS – V TP |
Region 4: v DS ≥ v GS – V TN
Region 5: v O = V L
v I > V DD – |V TP |

CMOS Voltage Transfer Characteristics

CMOS Voltage Transfer Characteristics • • • Simulation result shows the varying VTC of the inverter
• • •

Simulation result shows the varying VTC of the inverter as V DD is changed.

Minimum voltage supply:

2V T ·ln(2)

CMOS Voltage Transfer Characteristics

CMOS Voltage Transfer Characteristics • The simulation result shows the varying VTC of the inverter as
CMOS Voltage Transfer Characteristics • The simulation result shows the varying VTC of the inverter as

• The simulation result shows the varying VTC of the inverter as K N /K P = K R is changed

For K R > 1 the NMOS current drive is greater and it forces v I < V DD /2

For K R < 1 the PMOS current drive is greater and it forces v I > V DD /2

Noise Margins for the CMOS Inverter

Noise Margins for the CMOS Inverter • Noise margins are defined by the regions shown in
Noise Margins for the CMOS Inverter • Noise margins are defined by the regions shown in

• Noise margins are defined by the regions shown in the figure

Noise Margins for the CMOS Inverter

Noise Margins for the CMOS Inverter Jaeger/Blalock 10/15/03 McGraw-Hill
Noise Margins for the CMOS Inverter Jaeger/Blalock 10/15/03 McGraw-Hill

Propagation Delay Estimate

Propagation Delay Estimate • The two modes of capacitive charging that contribute to propagation delay Jaeger/Blalock
Propagation Delay Estimate • The two modes of capacitive charging that contribute to propagation delay Jaeger/Blalock
Propagation Delay Estimate • The two modes of capacitive charging that contribute to propagation delay Jaeger/Blalock

• The two modes of capacitive charging that contribute to propagation delay

Propagation Delay Estimate

Propagation Delay Estimate τ P L H = R O N p C ln 4 V
Propagation Delay Estimate τ P L H = R O N p C ln 4 V

τ P LH = R ONp C ln 4 V DD + V T P 1

V

H

2V T P

V T P

V H +

For “symmetrical” inverter (W/L) P = 2.5(W/L) N ,

τ PLH = τ PHL

Rise and Fall Times

Rise and Fall Times • The rise and fall times are given by the following expressions:

• The rise and fall times are given by the following expressions:

and Fall Times • The rise and fall times are given by the following expressions: Jaeger/Blalock

Reference Inverter Example

Reference Inverter Example • Design a reference inverter to achieve a delay of 250ps with a

• Design a reference inverter to achieve a delay of 250ps with a 0.1pF load given the following information:

to achieve a delay of 250ps with a 0.1pF load given the following information: Jaeger/Blalock 10/15/03

Reference Inverter Example

Reference Inverter Example • Assuming the inverter is symmetrical and using the values given in Table

• Assuming the inverter is symmetrical and using the values given in Table 7.1:

• Assuming the inverter is symmetrical and using the values given in Table 7.1: Jaeger/Blalock 10/15/03
• Assuming the inverter is symmetrical and using the values given in Table 7.1: Jaeger/Blalock 10/15/03
• Assuming the inverter is symmetrical and using the values given in Table 7.1: Jaeger/Blalock 10/15/03

Reference Inverter Example

Reference Inverter Example • Solving for R o n N : • Then solve for the

Solving for R onN :

Reference Inverter Example • Solving for R o n N : • Then solve for the
Reference Inverter Example • Solving for R o n N : • Then solve for the

• Then solve for the transistor ratios:

• Solving for R o n N : • Then solve for the transistor ratios: Jaeger/Blalock
• Solving for R o n N : • Then solve for the transistor ratios: Jaeger/Blalock
• Solving for R o n N : • Then solve for the transistor ratios: Jaeger/Blalock

Delay of Cascaded Inverters

Delay of Cascaded Inverters • Ideal step used to derive previous delay equations, but this is

• Ideal step used to derive previous delay equations, but this is not possible to implement

• Using the following circuit in SPICE, it is possible to deduct more accurate equations

the following circuit in SPICE, it is possible to deduct more accurate equations Jaeger/Blalock 10/15/03 McGraw-Hill

Delay of Cascaded Inverters

Delay of Cascaded Inverters • The output of the previous circuit looks is shown below. Delay

• The output of the previous circuit looks is shown below. Delay for the non-ideal step input ~ twice than the ideal case

is shown below. Delay for the non-ideal step input ~ twice than the ideal case Jaeger/Blalock
is shown below. Delay for the non-ideal step input ~ twice than the ideal case Jaeger/Blalock
is shown below. Delay for the non-ideal step input ~ twice than the ideal case Jaeger/Blalock

Static Power Dissipation

Static Power Dissipation • CMOS logic: no static power dissipation • DC current driving a capacitive

• CMOS logic: no static power dissipation

• DC current driving a capacitive load is zero

• This is not completely accurate since MOS transistors have leakage currents associated with the reverse-biased drain-to-substrate connections

Dynamic Power Dissipation

Dynamic Power Dissipation • Two components contribute to dynamic power dissipation: – – – Capacitive load

Two components contribute to dynamic power dissipation:

– – –

Capacitive load charging at a frequency f given by:

P D = CV DD f

Current flowing through both N- and PMOS that occurs during switching which can be seen in the figure

that occurs during switching which can be seen in the figure Peak current occurs when v

Peak current occurs when v i = v out =V DD /2 for symmetrical design

Power-Delay Product

Power-Delay Product The power-delay product is given as: • The figure shows a symmetrical inverter switching

The power-delay product is given as:

Power-Delay Product The power-delay product is given as: • The figure shows a symmetrical inverter switching
Power-Delay Product The power-delay product is given as: • The figure shows a symmetrical inverter switching
Power-Delay Product The power-delay product is given as: • The figure shows a symmetrical inverter switching

Power-Delay Product The power-delay product is given as: • The figure shows a symmetrical inverter switching

The figure shows a symmetrical inverter switching waveform

product is given as: • The figure shows a symmetrical inverter switching waveform Jaeger/Blalock 10/15/03 McGraw-Hill
product is given as: • The figure shows a symmetrical inverter switching waveform Jaeger/Blalock 10/15/03 McGraw-Hill

Jaeger/Blalock

CMOS NOR Gate

CMOS NOR Gate CMOS NOR gate implementation Reference Inverter Jaeger/Blalock 10/15/03 McGraw-Hill
CMOS NOR Gate CMOS NOR gate implementation Reference Inverter Jaeger/Blalock 10/15/03 McGraw-Hill

CMOS NOR gate implementation

Reference Inverter

CMOS NOR Gate Sizing

CMOS NOR Gate Sizing • Size transistors to keep delay times the same as the reference

• Size transistors to keep delay times the same as the reference inverter.

– the on-resistance on the PMOS branch of the NOR gate must be the same as the reference inverter

For a two-input NOR gate, the (W/L) p must be made twice as large

CMOS NOR Gate Body Effect

CMOS NOR Gate Body Effect • Since the bottom PMOS body contact is not connected to

• Since the bottom PMOS body contact is not connected to its source, its threshold voltage

changes as V SB changes during switching

Once v O = V H is reached, the bottom PMOS is not affected by body effect, thus the total on-resistance of the PMOS branch is the same

However, the rise time is slowed down due to |V TP | being a function of time

Two-Input NOR Gate Layout

Two-Input NOR Gate Layout Jaeger/Blalock 10/15/03 McGraw-Hill
Two-Input NOR Gate Layout Jaeger/Blalock 10/15/03 McGraw-Hill

Three-Input NOR Gate Layout

Three-Input NOR Gate Layout • It is possible to extend this same design technique to create

• It is possible to extend this same design technique to create multiple input NOR gates

is possible to extend this same design technique to create multiple input NOR gates Jaeger/Blalock 10/15/03
is possible to extend this same design technique to create multiple input NOR gates Jaeger/Blalock 10/15/03

Jaeger/Blalock

Shorthand Notation for NMOS and PMOS Transistors

Shorthand Notation for NMOS and PMOS Transistors Jaeger/Blalock 10/15/03 McGraw-Hill
Shorthand Notation for NMOS and PMOS Transistors Jaeger/Blalock 10/15/03 McGraw-Hill

CMOS NAND Gates

CMOS NAND Gates CMOS NAND gate implementation Reference Inverter Jaeger/Blalock 10/15/03 McGraw-Hill
CMOS NAND Gates CMOS NAND gate implementation Reference Inverter Jaeger/Blalock 10/15/03 McGraw-Hill

CMOS NAND gate implementation

Reference Inverter

CMOS NAND Gates Sizing

CMOS NAND Gates Sizing • The same rules apply for sizing the NAND gate as the

• The same rules apply for sizing the NAND gate as the did for the NOR gate, except for now the NMOS transistors are in series

The (W/L) N will be twice the size of the reference inverter’s NMOS

Multi-Input CMOS NAND Gates

Multi-Input CMOS NAND Gates Jaeger/Blalock 10/15/03 McGraw-Hill
Multi-Input CMOS NAND Gates Jaeger/Blalock 10/15/03 McGraw-Hill

Complex CMOS Logic Gate Design Example

Complex CMOS Logic Gate Design Example • Design a CMOS logic gate for (W/L) p ,

Design a CMOS logic gate for (W/L) p,ref =5/1 and for (W/L) n,ref =2/1 that exhibits the function: Y = A + BC +BD

• By inspection (knowing Y), the NMOS branch of the gate can drawn as the following with the corresponding graph, while considering the longest path for sizing purposes:

the corresponding graph, while considering the longest path for sizing purposes: Jaeger/Blalock 10/15/03 McGraw-Hill
the corresponding graph, while considering the longest path for sizing purposes: Jaeger/Blalock 10/15/03 McGraw-Hill

Jaeger/Blalock

Complex CMOS Logic Gate Design Example

Complex CMOS Logic Gate Design Example • By placing nodes in the interior of each arc,

• By placing nodes in the interior of each arc, plus two more outside the graph for V DD (3) and the complementary output (2’), the PMOS branch can be realized as shown on the left figure

• Connect all of the nodes in the manner shown in the right figure, and the NMOS arc that PMOS arc intersects have the same inputs

in the right figure, and the NMOS arc that PMOS arc intersects have the same inputs
in the right figure, and the NMOS arc that PMOS arc intersects have the same inputs

Jaeger/Blalock

Complex CMOS Logic Gate Design Example

Complex CMOS Logic Gate Design Example • From the PMOS graph, the PMOS branch can now
Complex CMOS Logic Gate Design Example • From the PMOS graph, the PMOS branch can now

• From the PMOS graph, the PMOS branch can now be drawn for the final CMOS logic gate while once again considering the longest PMOS path for sizing

Complex CMOS Gate with a Bridging Transistor Design Example

Complex CMOS Gate with a Bridging Transistor Design Example • Design a CMOS gate that implements

• Design a CMOS gate that implements the following logic function using the same reference inverter sizes as the previous example:

Y = AB +CE + ADE + CDB

• The NMOS branch can be realized in the following manner using bridging NMOS D to implement Y. The corresponding NMOS graph

is shown to the right.

bridging NMOS D to implement Y. The corresponding NMOS graph is shown to the right. Jaeger/Blalock
bridging NMOS D to implement Y. The corresponding NMOS graph is shown to the right. Jaeger/Blalock

Jaeger/Blalock

Complex CMOS Gate with a Bridging Transistor Design Example

Complex CMOS Gate with a Bridging Transistor Design Example • By using the same technique as

• By using the same technique as before, the PMOS graph can now be drawn

Example • By using the same technique as before, the PMOS graph can now be drawn

Complex CMOS Gate with a Bridging Transistor Design Example

Complex CMOS Gate with a Bridging Transistor Design Example By using the PMOS graph the PMOS
Complex CMOS Gate with a Bridging Transistor Design Example By using the PMOS graph the PMOS

By using the PMOS graph the PMOS branch can now be realized as the one shown on the left.

The longest path was used to select sizing.

P7.58

P7.58 Jaeger/Blalock 10/15/03 McGraw-Hill
P7.58 Jaeger/Blalock 10/15/03 McGraw-Hill

P7.59

P7.59 Jaeger/Blalock 10/15/03 McGraw-Hill
P7.59 Jaeger/Blalock 10/15/03 McGraw-Hill

P7.46

P7.46 Jaeger/Blalock 10/15/03 McGraw-Hill
P7.46 Jaeger/Blalock 10/15/03 McGraw-Hill

Jaeger/Blalock

P.7.63

P.7.63 Design a CMOS logic gate that implements the following function Y=(ABC+DE)’ Based on the CMOS

Design a CMOS logic gate that implements the following function Y=(ABC+DE)’ Based on the CMOS reference inverter. Select transistor sizes to obtain the same delay.

P.7.64

P.7.64 • Design CMOS L.G. to implement Y=[A(B+C(D+E))]’ Select sizes to obtain same delay as reference

• Design CMOS L.G. to implement

Y=[A(B+C(D+E))]’

Select sizes to obtain same delay as reference inverter.

Minimum Size Gate Design and Performance

Minimum Size Gate Design and Performance • With CMOS technology, there is a area/delay tradeoff that

• With CMOS technology, there is a area/delay tradeoff that needs to be considered

• If minimum feature sized are used for both devices, then the τ PLH will be decreased compared to the symmetrical reference inverter

Minimum Size Complex Gate and Layout

Minimum Size Complex Gate and Layout The following shows the layout of a complex minimum size

The following shows the layout of a complex minimum size logic gate

and Layout The following shows the layout of a complex minimum size logic gate • Jaeger/Blalock
and Layout The following shows the layout of a complex minimum size logic gate • Jaeger/Blalock

Practice Problems

Practice Problems • Chapter 7 probs. 8, 9, 11, 14, 15, 16, 17, 23, 28, 35,

• Chapter 7 probs. 8, 9, 11, 14, 15, 16, 17, 23, 28, 35, 57 to 69, 75, 77, 79, 81 to 84

Dynamic Domino CMOS Logic

Dynamic Domino CMOS Logic • technique to help decrease power in MOS logic circuits is dynamic

• technique to help decrease power in MOS logic circuits is dynamic logic

• uses pre-charge and evaluation phases that are controlled by a system clock to eliminate the dc current path in single channel logic circuits

• Early MOS logic required multiphase clocks to accomplish this, but CMOS logic can be operated dynamically with a single clock

Dynamic Domino CMOS Logic

Dynamic Domino CMOS Logic • The figure demonstrates the basic concept of domino CMOS logic operation

• The figure demonstrates the basic concept of domino CMOS logic operation

Logic • The figure demonstrates the basic concept of domino CMOS logic operation Jaeger/Blalock 10/15/03 McGraw-Hill

Simple Dynamic Domino Logic Circuit

Simple Dynamic Domino Logic Circuit Jaeger/Blalock 10/15/03 McGraw-Hill
Simple Dynamic Domino Logic Circuit Jaeger/Blalock 10/15/03 McGraw-Hill
Simple Dynamic Domino Logic Circuit Jaeger/Blalock 10/15/03 McGraw-Hill

Dynamic Domino CMOS Logic

Dynamic Domino CMOS Logic • Domino CMOS circuits only produce true logic outputs • To overcome

• Domino CMOS circuits only produce true logic outputs

• To overcome this problem use with registers that have both true and complemented output to complete the function

with registers that have both true and complemented output to complete the function Jaeger/Blalock 10/15/03 McGraw-Hill
with registers that have both true and complemented output to complete the function Jaeger/Blalock 10/15/03 McGraw-Hill

Jaeger/Blalock

Dynamic Domino CMOS Logic

Dynamic Domino CMOS Logic • P7.75 (a) draw a diagram of a dynamic domino CMOS logic

• P7.75 (a) draw a diagram of a dynamic domino CMOS logic OR gate (b) same for AND

• P7.82 Draw a dynamic domino CMOS logic circuit that implements Z=AB+CD

Cascade Buffers

Cascade Buffers - Sometimes large capacitances (C L ~50pF) must be driven - use even numbers

- Sometimes large capacitances (C L ~50pF) must be driven - use even numbers of inverters to drive load

(C L ~50pF) must be driven - use even numbers of inverters to drive load Jaeger/Blalock

Cascade Buffers

Cascade Buffers • The taper factor β determines the increase of the cascaded inverter’s size in

• The taper factor β determines the increase of the cascaded inverter’s size in manner shown of the previous image.

inverter’s size in manner shown of the previous image. where C o is the unit inverter’s

where C o is the unit inverter’s load capacitance

• The delay of the cascaded buffer is given by the following:

The delay of the cascaded buffer is given by the following: τ o is the unit

τ o is the unit inverter’s propagation delay

For optimum value of N , set to 0 and solve; Jaeger/Blalock 10/15/03 McGraw-Hill

For optimum value of N, set to 0 and solve;

Optimum Design of Cascaded Stages

Optimum Design of Cascaded Stages Optimum cascaded buffer But: you MUST use integer N - below

Optimum cascaded buffer

But: you MUST use integer N - below or above N OPT - (N I ) that gives lower τ

use integer N - below or above N O P T - (N I ) that
use integer N - below or above N O P T - (N I ) that

Example 7.4

Example 7.4 • Design a cascade buffer to drive a load cap of 50pF if C

• Design a cascade buffer to drive a load cap of 50pF if C 0 =50 fF. Find overall delay for a 3.3-V supply with V TN = 0.75V and V TP = -0.75V

The CMOS Transmission Gate

The CMOS Transmission Gate • CMOS transmission gate (T-gate): useful circuits for both analog and digital
The CMOS Transmission Gate • CMOS transmission gate (T-gate): useful circuits for both analog and digital

• CMOS transmission gate (T-gate): useful circuits for both analog and digital applications

• Acts as a switch that can operate up to V DD and down to V

SS

The CMOS Transmission Gate

The CMOS Transmission Gate • Needs to consider the equivalent on-resistance which is given by the

• Needs to consider the equivalent on-resistance which is given by the following expression:

consider the equivalent on-resistance which is given by the following expression: Jaeger/Blalock 10/15/03 McGraw-Hill

CMOS Latchup

CMOS Latchup • There is one major downfall to the CMOS logic gate – Latchup •

• There is one major downfall to the CMOS logic gate – Latchup

• There are many safeguards that are done during fabrication to suppress this, but it can still occur under certain transient or fault conditions

CMOS Latchup

CMOS Latchup • Latchup occurs due parasitic bipolar transistors that exist in the basic inverter as

• Latchup occurs due parasitic bipolar transistors that exist in the basic inverter as shown below

due parasitic bipolar transistors that exist in the basic inverter as shown below Jaeger/Blalock 10/15/03 McGraw-Hill

CMOS Latchup

CMOS Latchup • The configuration of these bipolar transistors create a positive feedback loop, and will
CMOS Latchup • The configuration of these bipolar transistors create a positive feedback loop, and will

• The configuration of these bipolar transistors create a positive feedback loop, and will cause the logic gate to latchup as shown to the left

• By using heavily doped material where R n and R p exist, there resistance will be lowered thereby reducing the chance of latchup occurring

End of Chapter 7 Jaeger/Blalock 10/15/03 McGraw-Hill

End of Chapter 7