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10MHz to 51.84MHz TCXO
The DS4026 is a temperature-compensated crystal oscillator (TCXO) that provides ±1ppm frequency stability over the -40°C to +85°C industrial temperature range. The DS4026 is also available in Stratum 3 versions (see the Ordering Information—Stratum 3 table). Each device is factory calibrated over temperature to achieve the ±1ppm frequency stability. Standard frequencies for the device include 10, 12.8, 19.44, 20, 38.88, 40, and 51.84MHz. Contact the factory for custom frequencies. The DS4026 provides excellent phase-noise characteristics. The output is a push-pull CMOS square wave with symmetrical rise and fall times. In addition, the DS4026 is designed to provide a maximum frequency deviation of less than ±4.6ppm over 20 years. The device also provides an I2C interface to allow pushing and pulling of the output frequency by a minimum of ±8ppm (±5ppm for 10MHz) with typical 1ppb resolution. The DS4026 implements a temperature-to-voltage conversion with a nonlinear relationship. The output from the temperature-to-voltage converter is used to drive the voltage-controlled crystal oscillator to compensate for frequency change. The device implements an on-chip temperature sensor lookup table, and a digital-to-analog converter (DAC) to adjust the frequency. An I2C interface used to communicate with the DS4026 performs temperature readings and frequency push-pull.
♦ ±1ppm Frequency Accuracy Over -40°C to +85°C ♦ Standard Frequencies: 10, 12.8, 19.44, 20, 38.88, 40, 51.84MHz ♦ Stratum 3 Frequencies: 10, 12.8, 19.2, 20MHz ♦ Maximum ±4.6ppm Deviation Over 20 Years ♦ Minimum ±8ppm (±5ppm for 10MHz) Digital Frequency Tuning Through I2C Interface ♦ Surface-Mount 16-Pin SO Package ♦ Pb Free/RoHS Compliant
TOP VIEW +
GNDA 1 VREF 2 VCC 3 VOSC 4 GNDOSC 5 N.C. 6 N.C. 7 N.C. 8 16 VCCD 15 FOUT 14 GNDD 13 SCL
12 SDA 11 GND 10 N.C. 9 N.C.
Reference Clock Generation Telecom/Datacom/SATCOM Wireless Test and Measurement
PART DS4026S+ACC DS4026S+ACN DS4026S+BCC DS4026S+BCN DS4026S+ECC DS4026S+ECN DS4026S+FCC DS4026S+FCN TEMP RANGE 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C OUTPUT (fC) (MHz, CMOS) 10.00 10.00 12.80 12.80 16.80 16.80 16.384 16.384 PIN-PACKAGE 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO TOP MARK* DS4026-ACC DS4026-ACN DS4026-BCC DS4026-BCN DS4026-ECC DS4026-ECN DS4026-FCC DS4026-FCN
Ordering Information continued at end of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package. *The top mark will include a “+” for a lead(Pb)-free/RoHS-compliant device. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
.135 TYP 3.5 4 mA 9 3 mA 5 +1 +1 VCC + 0. CL = 10pF...5 x VCCD (Note 5) 45 2. 3) PARAMETER VCC Active-Supply Current VOSC Oscillator Active-Supply Current SYMBOL ICC (Note 4) FOUT CMOS output on......3 VCC = 3.-0..4 0.. These are stress ratings only.10MHz to 51........ frequency < 25MHz FOUT CMOS output on. and FOUT Relative to Ground...3 x VCC 3 μA μA V V mA V V ns % UNITS mA I OSC VCCD Driver Active-Supply Current SCL Input Leakage SDA Leakage SCL......135 3....8V Voltage Range on SDA.....3V to +3..135 3.. 2. I OL = 2..465 UNITS V V V DC ELECTRICAL CHARACTERISTICS (VCC = 3.... Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.. SDA Low Input Voltage SDA Logic 0 Output FOUT High Output Voltage FOUT Low Output Voltage FOUT Rise/Fall Time FOUT Duty Cycle ILI ILO VIH VIL I OL VOH VOL tR/tF tD 2 _______________________________________________________________________________________ .....3V to (VCC + 0. frequency 25MHz -1 Output off -1 0..84MHz TCXO DS4026 ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC. VCCD.) (Notes 1.-0.135V to 3. VOL = 0.7 x VCC -0.4 2 55 CONDITIONS MIN TYP 1.465 3...3 3...Refer to the IPC/JEDEC J-STD-020 Specification.. CL = 10pF.0V... CL = 10pF.. frequency < 25MHz ICCD FOUT CMOS output on...3 3....-40°C to +85°C Storage Temperature Range ... frequency 25MHz FOUT CMOS output on.(0. unless otherwise noted....465V.....5 3 5 2 3 MAX 2....1 x VCCD) ....... I OH = -2mA VCCD = 3V..3V) Operating Temperature Range (noncondensing).. unless otherwise noted. TA = -40°C to +85°C...................... RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C.465 3........ and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied........-40°C to +85°C Soldering Temperature...... CL = 10pF. SCL.0mA (0.3 +0....... SDA High Input Voltage SCL..9 x VCCD) 0.. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.3 MAX 3.. and VOSC Relative to Ground...4V VCCD = 3V..........) PARAMETER Power-Supply Voltage Oscillator Power Supply Driver Power Supply SYMBOL VCC VOSC VCCD CONDITIONS MIN 3...
20 -119.84 -145.33 +3.28 +0.87 -151.67 -146.59 -151.84 -150.00 -153.18 -152.25 -152.10MHz to 51.28 -150.8 24. Load Change Free-Run Accuracy Holdover Stability (24 Hours) SYMBOL CONDITIONS MIN TYP MAX UNITS STRATUM 3 FREQUENCY STABILITY fTEMP/fC -40°C to +85°C (Note 6) -0. aging (20 years) (Notes 5.33 -147.16 -125.44 -120.84 10. CL = 10pF to ground.1 +4. supply.12 -120.88 -143.6 -0.135V to +3.28 -0.32 +0.465V.0 10Hz -88. +25°C.00 51.384 16. unless otherwise noted.3V ±5%. and initial tolerance. 3. Temperature Frequency Stability vs.01 -80. TA = -40°C to +85°C. /fC +25°C (Note 7) fAGING/fC fC = Nominal (Note 8) fLOAD/fC Load = 10pF ±5%.96 -150.72 -152.75 -141.) (Note 1) PARAMETER Frequency Stability vs.8 +0.44 -141.67 CARRIER FREQUENCY _______________________________________________________________________________________ 3 .00 38.75 -151.6 -83.33 100kHz -151.80 19.8 -0. load. unless otherwise noted.) (Note 1) PARAMETER Frequency Stability vs.135V to 3. Voltage Frequency Stability vs.32 ppm ppm ppm ppm ppm ppm ppm f INITIAL /fC TA = +25°C.1 -4.80 -74.41 -82.0 16. 9) /fC PHASE NOISE PHASE NOISE (dBc/Hz) (TYPICAL.71 -151.78 -151. ±3°C and VDD = 3.03 -145.44 -89.84 -151. Voltage Aging Frequency Pull Range First Year Years 2–20 Except 10MHz 10MHz SYMBOL f/fC CONDITIONS CL = 10pF to ground MIN fC – 1ppm -2 -1 -2 ±8 ±5 ±15 ±10 1 TYP fC MAX fC + 1ppm +2 +1 +2 UNITS ppm ppm/V ppm ppm ppb DS4026 f VOLTAGE CL = 10pF to ground. +25°C /fC fAGING/fC (Note 5) f/fC fRES/fC FTUNEH = 3Fh and FTUNEL = FFh.84MHz TCXO AC ELECTRICAL CHARACTERISTICS—TCXO (VCC = 3.76 -120.45 1kHz -147.71 -79.39 -134.33 -3.22 -147.52 -151.84 -146.06 -153.90 -150. 8) f24HOURS 24-hour elapsed time (Notes 5.98 100Hz -130.0 -0.53 -126.3V f VOLTAGE VCC = 3.44 20.45 -153.87 -150.93 -150.0 +0. Aging/20 Years Frequency Stability vs.6 +0.88 40.465V. FTUNEH = 40h and FTUNEL = 00h at +25°C Frequency Pull Resolution AC ELECTRICAL CHARACTERISTICS—STRATUM 3 (VCC = +3.83 -128.3V) OFFSET (MHz) 12. Temperature Initial Tolerance and Reflow Frequency Stability vs.94 -150.50 -152.37 -153.59 -151.08 10kHz -150.14 -150.09 -92.34 1MHz -151.21 -151.63 -83.52 -87.69 -151. +25°C (Note 5) Operating temperature. TA = -40°C to +85°C.17 -142.06 -115.
7 0.1CB 20 + 0.1CB 20 + 0.) (Note 2) PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition (Note 10) Low Period of SCL Clock High Period of SCL Clock Data Hold Time (Notes 11.9 0.7 1.10MHz to 51.6 20 + 0.0 0.1CB 4. unless otherwise noted.) (Note 1) PARAMETER Temperature Sensor Accuracy Temperature Sensor Conversion Time Temperature Sensor Resolution SYMBOL T tCONVT N2 CONDITIONS MIN -3 TYP MAX +3 11 12 UNITS °C ms Bits AC ELECTRICAL CHARACTERISTICS—I2C SERIAL INTERFACE (VCC = 3.7 1.465V.6 4. 12) Data Setup Time (Note 13) START Setup Time Rise Time of Both SDA and SCL Signals (Note 14) Fall Time of Both SDA and SCL Signals (Note 14) Setup Time for STOP Condition Pin Capacitance SDA.84MHz TCXO DS4026 TEMPERATURE SENSOR ELECTRICAL CHARACTERISTICS (VCC = 3.3 4.135V to 3.135V to 3.9 TYP MAX 100 400 UNITS kHz μs μs μs μs μs ns μs ns ns μs pF 4 _______________________________________________________________________________________ .7 0.6 0 0 250 100 4.465V. SCL (Note 5) SYMBOL f SCL tBUF tHD:STA tLOW tHIGH tHD:DAT t SU:DAT t SU:STA tR tF t SU:STO CI/O Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode CONDITIONS Standard mode MIN 0 100 4. TA = -40°C to +85°C. unless otherwise noted.1CB 20 + 0. TA = -40°C to +85°C.0 0.6 10 1000 300 300 300 0.3 4.
) (Note 2) PARAMETER Capacitive Load for Each Bus Line (Note 14) Pulse Width of Spikes That Must Be Suppressed by the Input Filter SYMBOL CB CONDITIONS MIN TYP MAX 400 UNITS pF DS4026 t SP Fast mode 30 ns Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Typical values are at +25°C. nominal supply voltages.fMIN)/2 as measured within a 24-hour period. Voltages referenced to ground. Limits at -40°C are guaranteed by design and not production tested. Specified with I2C bus inactive. the first clock pulse is generated. temperature is defined as (ΔfMAX . Note 13: A fast-mode device can be used in a standard-mode system. it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Guaranteed by design and not production tested. Maximum power-supply variations to meet the specification are 5%.ΔfMIN)/2. Note 14: CB—total capacitance of one bus line in pF. but the requirement that tSU:DAT ≥ 250ns must then be met. Crystal vendor specification.84MHz TCXO AC ELECTRICAL CHARACTERISTICS—I2C SERIAL INTERFACE (continued) (VCC = 3. unless otherwise noted. Frequency stability vs.135V to 3.465V. Note 12: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW) of the SCL signal. TA = -40°C to +85°C. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL.10MHz to 51. If such a device does not stretch the low period of the SCL signal. After this period. This is automatically the case if the device does not stretch the low period of the SCL signal. Holdover is defined as (fMAX . Warmup time = 1 hour. unless otherwise indicated. Data Transfer on I2C Serial Bus SDA tBUF tLOW tR tF tHD:STA tSP SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO _______________________________________________________________________________________ 5 .
4 0.0 -80.5 0 12.5 3.0 2.0 PHASE NOISE (dBc/Hz) -55.2 0.3V.4 1.) ACTIVE-SUPPLY CURRENT vs.1 3.8 51.0 4.3 0.3 VCCD (V) 3.8MHz -155.6 0.44MHz DS4026 toc06 20 15 10 5 OFFSET (ppm) 0 -5 -10 -15 -20 -25 -30 4000h 000h VC (V) 3FFFh 12.0 4.6 3.8 0.1 3.0 -105.5 3.2 1.10MHz to 51.0 CURRENT (mA) DS4026 toc03 5.000 1. POWER-SUPPLY CURRENT 1.2 3.1 0 3.1 3.0 3.84 DCOMP = 1 DEVIATION (ppm) DCOMP = 0 38.4 3.0 1.0 12.8 51.000. OSCILLATOR POWER SUPPLY DS4026 toc02 ACTIVE-SUPPLY CURRENT vs.4 3.1 1.84 12.0 -0.0 -180. FTUNE DS4026 toc04 FREQUENCY vs.0 0.5 1.0 3. DRIVER POWER SUPPLY 10.3 VCC (V) 3.84MHz 19.8 2.5 CURRENT (mA) 3.3 1.7 0.8 51.0 3.0 12.5 3.0 51.4 3.5 0.5 4.6 1.0 3. unless otherwise noted.0 0.000 100.0 51.0 -30.5 1.84 8.9 0.6 FREQUENCY vs.84MHz TCXO DS4026 Typical Operating Characteristics (VCC = +3.6 3. TA = +25°C.1 3.5 2.3 VOSC (V) 3.84 CURRENT (mA) 6. TEMPERATURE 20 18 15 13 10 8 5 3 0 -3 -5 -8 -10 -13 -15 -40 -20 0 DS4026 toc05 PHASE NOISE (TYP) -5.0 -130.2 3.2 DS4026 toc01 ACTIVE-SUPPLY CURRENT vs.000 TEMPERATURE (°C) OFFSET (Hz) 6 _______________________________________________________________________________________ .88MHz 20 40 60 80 10 100 1000 10.
1μF VOSC 3. Ground for Oscillator Circuit No Connection.3V 0. Typical Operating Circuit _______________________________________________________________________________________ 7 . SDA SCL Figure 1. Serial Clock Input. SDA is the data input/output for the I2C interface.C.C.C. and Controller Substrate Serial Data Input/Output.3V 0. GND SDA SCL GNDD FOUT VCCD Ground for DAC Voltage Reference Output. A 20 resistor must be placed in series between the power supply and VCCD.1μF 3. Power Supply for Oscillator Circuit. N.C. This pin must be decoupled with a 0.1μF capacitor to ground.C. This pin must be decoupled with a 0.1μF GNDOSC N. SCL is the clock input for the I2C Interface and is used to synchronize data movement on the serial interface. Must be connected to ground.3V ±5% DS4026 VCC 3. Power Supply for Digital Control and Temperature Sensor. FUNCTION DS4026 20Ω GNDA 100μF ±20% CERAMIC VREF VCCD FOUT GNDD 0.10MHz to 51. This open-drain pin requires an external pullup resistor.C. N.84MHz TCXO Pin Description PIN 1 2 3 4 5 6–10 11 12 13 14 15 16 NAME GNDA VREF VCC VOSC GNDOSC N. Ground for Oscillator Output Driver Frequency Output. N. This pin must be decoupled with a 100μF ceramic capacitor to ground. Temperature Sensor. CMOS Push-Pull Power Supply for Oscillator Output Driver. Ground for Digital Control. GND N.1μF capacitor to ground. This pin must be decoupled with a 100nF capacitor to ground.
and it allows digital tuning of the fundamental frequency. The variable capacitor is adjusted by the DAC to provide temperature compensation. control lookup table. a minimum pullability of ±8ppm (±5ppm for 10MHz) is achieved with a typical resolution of 1ppb (typ) per LSB. 8 _______________________________________________________________________________________ . and adjust the DAC input • DAC output to adjust the capacitive load • I2C interface to communicate with the chip The oscillator block consists of an amplifier and variable capacitor in a Pierce crystal oscillator with a crystal resonator of fundamental mode. Functional Diagram Detailed Description The DS4026 is a TCXO capable of operating at 3. The DS4026 contains the following blocks: • Oscillator block with variable capacitor for compensation • Output driver block • Temperature sensor • Controller to read the temperature. and its minimum pullability is ±8ppm with a typical resolution of 1ppb (typ) per LSB. The oscillator amplifier is a single transistor amplifier and its transconductance is temperature compensated. With the FTUNEH and FTUNEL registers. The device is calibrated in the factory to achieve an accuracy of ±1ppm over the industrial temperature range.3V ±5%.84MHz TCXO DS4026 VCC VCC TEMP SENSOR EEPROM ARRAY A/D GND VCC SCL SDA VCC GND VREF I2C INTERFACE CONTROLLER DAC DS4026 GNDA GND GND VCCD VOSC CMOS BUFFER FOUT GNDOSC GNDD Figure 2.10MHz to 51.
the controller looks up the two corresponding capacitance trim codes from the lookup table at a 0. For FTUNEH = 3Fh and FTUNEL = FFh.5°C increment. and bit 0 of FTUNEL is the LSB (see Table 1). The monotonic DAC provides an analog voltage based on temperature compensation to drive the variable capacitor. POR = 00h table).0625°C resolution. When set to logic 1. Each bit typically represents about 1ppb (typ). The frequency tuning value is represented in two’s complement data. the device pushes the base frequency by approximately +15ppm. The FTUNE registers are still functional when DCOMP is disabled. conversions continue but temperature updates are inhibited. The sensor is in continuous conversion mode. The trim codes are interpolated to 0. the temperature register still performs temperature conversions. This disabling prevents the variable capacitor in the oscillator block from changing. Access is obtained by implementing a START condition and providing a device identification code followed by data. The DS4026 operates as a slave device on the serial bus. POR = 00h ADDRESS 00h POR 01h POR BIT 7 DCOMP 0 Data 0 BIT 6 Sign 0 Data 0 BIT 5 Data 0 Data 0 BIT 4 Data 0 Data 0 BIT 3 Data 0 Data 0 BIT 2 Data 0 Data 0 BIT 1 Data 0 Data 0 BIT 0 Data 0 Data 0 Temperature Register (02h–03h) ADDRESS 02h POR 03h POR BIT 7 Sign 0 Data 0 BIT 6 Data 0 Data 0 BIT 5 Data 0 Data 0 BIT 4 Data 0 Data 0 BIT 3 Data 0 0 0 BIT 2 Data 0 0 0 BIT 1 Data 0 0 0 BIT 0 Data 0 0 0 _______________________________________________________________________________________ 9 .84MHz TCXO The output driver is a CMOS square-wave output with symmetrical rise and fall time. The temperature trim code from the last temperature conversion before DCOMP is enabled is used for temperature compensation. These frequency tuning register bits allow the tuning of the base frequency. the next temperature update cycle sums the programmed value with the factory compensated value. this bit’s temperature-compensation function is disabled. The controller coordinates the conversion of temperature into digital codes. Address Map Disable Compensation Update (DCOMP) DCOMP is bit 7 of the frequency tuning register (see the Frequency Tuning Register (00h–01h). The temperature sensor provides a 12-bit temperature reading with a resolution of 0. The result is added with the tuning value from the frequency tuning register and loaded into the DAC registers to adjust voltage output. When the temperature reading is different from the previous one or the frequency tuning register is changed. Subsequent registers can be accessed sequentially until a STOP condition is executed. DS4026 Frequency Tuning Register (00h–01h). This allows the user to digitally control the base frequency using the I2C protocol.10MHz to 51. When the tuning register low (01h) is programmed with a value. However. Bit 6 of FTUNEH is the sign. If DCOMP is set. bit 5 is the MSB.0625°C. The frequency tuning registers adjust the base frequency.
I2C Serial Data Bus The DS4026 supports a bidirectional I2C bus and data transmission protocol. Connections to the bus are made through the open-drain I/O lines SDA and SCL. SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 6 7 8 9 ACK START CONDITION REPEATED IF MORE BYTES ARE TRANSFERED 1 2 3–7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER Figure 3. if the two temperature registers are read in individual I2C transactions. and the results can be inaccurate. The bus must be controlled by a master device that generates the serial clock (SCL). Register Map ADDRESS 00 01 02 03 SIGN BIT 7 DCOMP BIT 6 SIGN BIT 5 BIT 4 BIT 3 FTUNEH FTUNEL TREGH TREGL BIT 2 BIT 1 BIT 0 FUNCTION Frequency Tuning High Frequency Tuning Low Temperature MSB Temperature LSB Read Mode In the temperature register (see the Temperature Register (02h–03h) table). the registers are set to a +25°C default temperature and the controller starts a temperature conversion. Upon power reset. The device that controls the message is called a master. To prevent this from occurring. it is possible for a temperature conversion to occur between reads.10MHz to 51. a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The following bus protocol has been defined (Figure 3): • Data transfer can be initiated only when the bus is not busy. controls the bus access. I2C reads do not affect the internal temperature registers. The temperature register stores new temperature readings. The DS4026 works in both modes. temperature is represented as a 12-bit code and is accessible at location 02h and 03h. The upper 8 bits are at location 02h and the lower 4 bits are in the upper nibble of the byte at location 03h. The DS4026 operates as a slave on the I2C bus. The devices that are controlled by the master are slaves. A device that sends data onto the bus is defined as a transmitter and a device receiving data is defined as a receiver.84MHz TCXO DS4026 Table 1. and generates the START and STOP conditions. multibyte read operation (Figure 5). Within the bus specifications. the registers should be read using a single. I2C Data Transfer Overview 10 ______________________________________________________________________________________ . The current temperature is loaded into the (user) temperature registers when a valid I2C slave address and write is received and when a word address is received. Consequently.
the slave must leave the data line high to enable the master to generate the STOP condition. Slave Transmitter Mode (Read Mode) <R/W> ______________________________________________________________________________________ <R/W> 11 . Data valid: The state of the data line represents valid data when. Acknowledge: Each receiving device. The first byte (the slave address) is transmitted by the master. The data on the line must be changed during the low period of the clock signal. the data line is stable for the duration of the high period of the clock signal. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. is obliged to generate an acknowledge (ACK) after the reception of each byte. At the end of the last received byte. The master device generates all the serial clock pulses and the START and STOP conditions. the data line must remain stable whenever the clock line is high. DS4026 <WORD <SLAVE ADDRESS (n)> <DATA (n)> <DATA (n + 1)> <DATA (n + X)> ADDRESS> S 1000001 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P S = START DATA TRANSFERRED A = ACKNOWLEDGE (X + 1 BYTES + ACKNOWLEDGE) P = STOP R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 82h <SLAVE <DATA (n)> <DATA (n + 1)> <DATA (n + 2)> <DATA (n + X)> ADDRESS> S 1000001 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P DATA TRANSFERRED S = START (X + 1 BYTES + ACKNOWLEDGE) A = ACKNOWLEDGE NOTE: LAST DATA BYTE IS FOLLOWED BY P = STOP A NOT ACKNOWLEDGE (A) SIGNAL A = NOT ACKNOWLEDGE R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 83h Figure 4. The master device must generate an extra clock pulse that is associated with this acknowledge bit. Data transfer from a slave transmitter to a master receiver. There is one clock pulse per bit of data. STOP data transfer: A change in the state of the data line from low to high. Each data transfer is initiated with a START condition and terminated with a STOP condition. a not acknowledge (NACK) is returned. Next follows a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. Next follows a number of data bytes transmitted by the slave to the master.10MHz to 51. Figures 4 and 5 detail how data transfer is accomplished on the I2C bus. Because a repeated START condition is also the beginning of the next serial transfer. the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. while the clock line is high. The first byte transmitted by the master is the slave address. The slave returns an acknowledge (ACK) bit after each received byte. Changes in the data line while the clock line is high are interpreted as control signals. Slave Receiver Mode (Write Mode) Figure 5. Accordingly. two types of data transfer are possible: Data transfer from a master transmitter to a slave receiver. defines a START condition. the bus is not released. and is determined by the master device. setup and hold times must be taken into account. after a START condition. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. when addressed. START data transfer: A change in the state of the data line from high to low.84MHz TCXO • During data transfer. Depending upon the state of the R/W bit. while the clock line is high. Of course. A transfer is ended with a STOP condition or with a repeated START condition. defines a STOP condition. The slave then returns an acknowledge bit. The number of data bytes transferred between the START and the STOP conditions is not limited. In this case.
The master can then transmit zero or more bytes of data.84MHz TCXO The DS4026 can operate in the following two modes: Slave receiver mode (write mode): Serial data and clock are received through SDA and SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. Serial data is transmitted on SDA by the DS4026 while the serial clock is input on SCL. DS4026 12 ______________________________________________________________________________________ . START and STOP conditions are recognized as the beginning and end of a serial transfer. which is 0 for a write. Address recognition is performed by hardware after reception of the slave address and direction bit. with the DS4026 acknowledging each byte received. followed by the direction bit (R/W). After the DS4026 acknowledges the slave address and write bit. The master generates a STOP condition to terminate the data write. This sets the register pointer on the DS4026. The slave address byte contains the 7-bit DS4026 address. After each byte is received. After receiving and decoding the slave address byte. the DS4026 outputs an acknowledge on SDA. If the register pointer is not written to before the initiation of a read mode. However. The slave address byte is the first byte received after the master generates a START condition. After receiving and decoding the slave address byte. The slave address byte is the first byte received after the master generates a START condition. the master transmits a word address to the DS4026. followed by the direction bit (R/W). which is 1 for a read. Address recognition is performed by hardware after reception of the slave address and direction bit. The DS4026 must receive a not acknowledge to end a read. The DS4026 then begins to transmit data starting with the register address pointed to by the register pointer. with the DS4026 acknowledging the transfer. the direction bit indicates that the transfer direction is reversed. The register pointer increments after each data byte is transferred. The slave address byte contains the 7-bit DS4026 address. which is 1000001. the first address that is read is the last one stored in the register pointer. which is 1000001. the DS4026 outputs an acknowledge on SDA. in this mode. an acknowledge bit is transmitted.10MHz to 51. Slave transmitter mode (read mode): The first byte is received and handled as in the slave receiver mode.
44 19. 712 SUBSTRATE CONNECTED TO GROUND PROCESS: CMOS PACKAGE TYPE 16 SO (300 mils) Package Information For the latest package outline information and land patterns.84 51.84MHz TCXO Ordering Information (continued) PART DS4026S+HCC DS4026S+HCN DS4026S+JCC DS4026S+JCN DS4026S+MCC DS4026S+MCN DS4026S+PCC DS4026S+PCN DS4026S+QCC DS4026S+QCN DS4026S+RCC DS4026S+RCN TEMP RANGE 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C OUTPUT (fC) (MHz.00 12. CMOS) 19. Chip Information TRANSISTOR COUNT: 77.84 24.20 20.00 PIN-PACKAGE 16 SO 16 SO 16 SO 16 SO TOP MARK* DS4026S3-ACN DS4026S3-BCN DS4026S3-GCN DS4026S3-JCN +Denotes a lead(Pb)-free/RoHS-compliant package. PACKAGE CODE W16+H1 DOCUMENT NO. *The top mark will include a “+” for a lead(Pb)-free/RoHS-compliant device. CMOS) 10.00 24.10MHz to 51.com/packages.00 20.00 40.maxim-ic. Ordering Information—Stratum 3 PART DS4026S3+ACN DS4026S3+BCN DS4026S3+GCN DS4026S3+JCN TEMP RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C OUTPUT (fC) (MHz.00 51.44 20.00 38. 21-0042 ______________________________________________________________________________________ 13 .80 19. go to www.88 38.00 PIN-PACKAGE 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO 16 SO TOP MARK* DS4026-HCC DS4026-HCN DS4026-JCC DS4026-JCN DS4026-MCC DS4026-MCN DS4026-PCC DS4026-PCN DS4026-QCC DS4026-QCN DS4026-RCC DS4026-RCN DS4026 +Denotes a lead(Pb)-free/RoHS-compliant package.88 40. *The top mark will include a “+” for a lead(Pb)-free/RoHS-compliant device.
1μF. Inc. added ±5ppm (min. 5. changed push-pull value from ±15ppm (typ) to ±8ppm (min).84MHz to 10MHz to 51. No circuit patent licenses are implied. Changed maximum frequency deviation from over 10 years to over 20 years. added ordering information for Stratum 3 parts. Changed device from 12. DESCRIPTION PAGES CHANGED — 1 9/07 1–12 2 4/08 1. added new ordering information and phase noise data.10MHz to 51. 120 San Gabriel Drive. CA 94086 408-737-7600 © 2008 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products. Sunnyvale. .8MHz to 51. 14 ____________________Maxim Integrated Products.84MHz TCXO DS4026 Revision History REVISION NUMBER 0 REVISION DATE 2/07 Initial release. Added Stratum 3 electrical characteristics table. 13 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. changed capacitor value designators from 10nF to 0. typ) digital frequency tuning for the 10MHz option.84MHz. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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