t
k
refdc k p i
rms
u t
i t K e t K e d
U
Where
_ refdc k
i is the current for the kphase (k=a, b and c),
( )
k
u t is the supply voltage of phase k and
rms
U is the RMS
value of the supply voltage. The ( ) e t signal corresponds to
the error between the reference value of the DCbus voltage
3
(
dcref
U ) and the value of this voltage at time t ( ( )
dc
u t ),
according to equation (2).
( ) ( )  ( ) 2 =
dcref dc
e t U u t
The constants K
p
and K
i
correspond to the proportional and
integral gain of the PI controller, respectively. In this paper,
the constant K
p
is calculated so that the DC voltage reaches
the reference in a semicycle of the supply voltage. In this way,
the current and voltage of each DCbus capacitor are related
by the equations (3) and (4), see Fig. 2.
( ) ( )
1
1 1
( )
3 =
dc
dc
du t
i t C
dt
( ) ( )
2
2 2
( )
4 =
dc
dc
du t
i t C
dt
Assuming that, ( )
1 dc
i t and ( )
2 dc
i t maintain a constant value
in each semicycle of the supply voltage ( / 2 AT ), the
amplitude of these currents should satisfy (5) and (6)
respectively, with the aim that the DCbus voltage reaches the
reference value in almost one semicycle.
( ) ( ) ( )
1
1
, ( / 2) 5
/ 2
dc b b b
C
I t e t for t t t T
T
= < < + A
A
( ) ( ) ( )
2
2
, ( / 2) 6
/ 2
dc b b b
C
I t e t for t t t T
T
= < < + A
A
Where
b
t is the beginning of each semicycle of the supply
voltage.
In this way, a sinusoidal equivalent signal which transfers to
the capacitors the same electric charge, in each semicycle,
leads to a K
p
value given in (7).
( ) 7
3
p
C
K
T
t
=
A
The above equation is considering a three phase signal and the
same capacity (C
1
=C
2=
C) for the capacitors.
On the other hand, the constant K
i
represents the number of
times that the proportional action is repeated. This constant is
set by the help of simulations, taking into account the system
to be controlled.
Then, the algorithm proposed in (1) aims to maintain the DC
bus voltage in a reference value. However, if the SAPF has to
supply zero sequence currents, this algorithm does not
consider the voltage unbalance in the DCbus. For this
situation, an independently voltage control for each capacitor
is proposed. Equation (8) shows the resulting algorithm for
calculating the reference current.
( )
( ) ( )
( )
( )
( ) ( )
( )
( )
( )
1 1
0
_
2 2
0
para >0
2
8
para 0
2
t
k
p i k
rms
refdc k
t
k
p i k
rms
u t
K e t K e d u t
U
i t
u t
K e t K e d u t
U
t t
t t
+
=
+ <
 

\ .
 
\ .
Where,
( ) ( )
1 1 1
 ( ) 9
dcref dc
e t U u t =
( ) ( )
2 2 2
 ( ) 10
dcref dc
e t U u t =
1 dcref
U y
2 dcref
U are the dcvoltage references in the capacitor
C
1
y C
2
, respectively. In the algorithm, the voltage in the
capacitor C
1
is controlled when the voltage supply has positive
values (positive semicycle) and the voltage in the capacitor C
2
is controlled when the voltage supply has negative values
(negative semicycle).
In (11), the RMS value of the supply voltage is calculated
considering that it is balanced and undistorted. If the voltage
have harmonic components or unbalance, it is necessary a
previous filtering or the use of an additional algorithm to
calculate the RMS.
( ) ( ) ( ) ( ) ( )
2 2 2
2
2 11
3
rms a b c
U u t u t u t = + +
IV. REFERENCE CALCULATION AND CURRENT CONTROLLER
As was mentioned in section II, the control system in the
SAPF is composed by three control loops, these are: the
current reference control, DCvoltage control and current
control. The second one was explained in the above section.
Following, it is presented a short description for the remaining
loops.
A. Current reference calculation
The current reference control is realized using the Fryze
Theory [8]. This theory is based on the natural reference
frame (abc) and it has as goal that the grid current after
compensation is in phase with the supply voltage. Moreover,
this current must deliver the active power that needs the load
[4], [6], [8]. This current is given by:
( ) ( ) ( )
_
2
12
p k k
rms
P
i t u t
U
=
where ( )
k
u t is the phasetoground voltage (for the phase k),
rms
U is the RMS value of the supply voltage and P is the active
power demanded by the load.
In this way, the nonactive current, which is the current to
compensate, it is given by (13).
( ) ( ) ( )
_ _
2
13
ref k L k k
rms
P
i t i u t
U
=
4
When the supply voltage does not have distortion and
unbalances, the compensation based on (13) can be used to
compensate: harmonic currents, power factor and unbalance
currents in the grid currents [4]. Finally, the total current
reference that must generate the SAPF is given by the sum of
the current reference for compensating the load, and the
current reference for controlling the DCvoltage. The
expression for the total current reference is given by (14)
( ) ( )
_ _ _
14
cref k ref k dcref k
i t i i = +
B. Current controller
The current control is based on the hysteresis controller.
The aim of the control is to obtain the switching signals from
the comparison between the current error and a fixed tolerance
band (normally this band is close to 0). If the mismatch
between the actual and reference current is positive, the
inverter voltage output must be positive and if the mismatch is
negative, the inverter voltage output must be negative [4], [9].
V. SIMULATION RESULTS
To evaluate the performance of the DCbus voltage
controller, for both the algorithm based on (1) and for the
modified algorithm based on (8), some simulations in ATP are
presented. These simulations were done for three different
disturbing loads in order to evaluate the algorithms
performance in the following compensation cases:
 Power factor correction and harmonics mitigation.
 Load balancing, considering zero sequence currents.
 Load balancing, considering a DC level in the neutral
current.
The system and the SAPF parameters used for the simulation
are presented in Table I.
TABLE I
SYSTEM PARAMETERS
PARAMETER VALUE
Line system voltage Ul 208 Vrms
System frequency fs 60 Hz
Hysteresis tolerance band h 0.001 A
Filter inductance Lf 20 mH
Filter resistance Rf 1
Capacitance C1 2200 F
Capacitance C2 2200 F
C1 reference voltage Udcref1 270 Vdc
C2 reference voltage Udcref2 270 Vdc
Simulation step 1s
Integral constant Ki 0.003
Proportional constant Kp 0.138
The initial condition for each capacitor voltage is considered
null in t=0 s and the compensation action of the filter starts at
t=0.2s.
A. Case 1: Power factor correction and harmonics mitigation
In this case, the algorithm performance was evaluated with
an inductive load connected in shunt with a nonlinear load.
Regarding to the inductive load, this has a pf=0.7 and it
demands 1KW. On the other hand, the nonlinear load is
comprised of a 3phase diode bridge rectifier with a resistive
load of 1kW. The total load is connected to the system through
a 15 mH inductor and a resistance of 0.1.
1) Simulation results using the algorithm based on (1)
Fig. 3 shows the total DCbus voltage (U
dc
), the voltage in
capacitor C
1
(U
dc1
) and the voltage in capacitor C
2
(U
dc2
). The
required time to achieve the 99% of the reference value is
0.097s for U
dc
, 0.098s for U
dc1
and 0.095s for U
dc2
, which
corresponds to almost six cycles of the supply voltage. Notice
that, using equation (1) appears a little unbalance in the mean
value of the voltages in the capacitors after compensation.
However, this unbalance does not affect the compensation
goals.
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
100
0
100
200
300
400
500
600
Time [s]
D
C
b
u
s
v
o
l
t
a
g
e
s
[
V
]
u
dc
u
dc1
u
dc2
Fig. 3. DC bus voltages using the algorithm based on (1). Case 1.
The currents supplied by the grid are shown in Fig. 4. Notice
that, before compensation, the currents supplied by the grid are
distorted and lagged with respect to the voltage in the PCC.
After t=0.2s the filter mitigates the current distortion and
corrects the power factor. These results show the outstanding
performance of the controllers. On the other hand, Fig. 5
shows a zoom of Fig 4. In this figure, it can be observed that
the grid current, for phase a, is a pure sinusoid and it is in
phase with the voltage in the PCC after t=0.2s. In addition, the
RMS value of the grid current is the lowest.
0.17 0.18 0.19 0.2 0.21 0.22 0.23
10
8
6
4
2
0
2
4
6
8
10
Time [s]
S
o
u
r
c
e
c
u
r
r
e
n
t
s
[
A
]
i
sa
i
sb
i
sc
Fig. 4. Source currents using the algorithm based on (1). Case 1.
0.2655 0.266 0.2665 0.267 0.2675 0.268 0.2685 0.269 0.2695 0.27 269
269.2
269.4
269.6
269.8
270
270.2
Time [s]
D
C
b u s v o l t a g e s [ V ]
5
0.17 0.18 0.19 0.2 0.21 0.22 0.23
20
15
10
5
0
5
10
15
20
Time [s]
S
o
u
r
c
e
c
u
r
r
e
n
t
[
A
]
a
n
d
v
o
l
t
a
g
e
i
n
t
h
e
P
C
C
[
V
]
i
sa
u
a
/10
Fig. 5. Source current for phase a and voltage in the PCC scaled by 10, using
the algorithm based on (1). Case 1.
2) Simulation results using the algorithm based on (8)
Fig. 6 shows the DCbus voltages U
dc
, U
dc1
and U
dc2
. In this
case, the required time to achieve the 99% of the reference
value is 0.137s for the three voltages, which corresponds to
almost eight cycles of the supply voltage. Notice that in this
case, after compensation the voltages in the capacitors have
the same mean value.
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
100
0
100
200
300
400
500
600
Time [s]
D
C
b
u
s
v
o
l
t
a
g
e
s
[
V
]
u
dc
u
dc1
u
dc2
Fig. 6. DC bus voltages using the algorithm based on (8). Case 1.
The grid currents are shown in Fig. 7. Notice that, these results
are the same that those obtained using the algorithm based on
(1), see Fig 4. After t=0.2s the filter mitigates the current
distortion and corrects the power factor.
0.17 0.18 0.19 0.2 0.21 0.22 0.23
10
8
6
4
2
0
2
4
6
8
10
Time [s]
S
o
u
r
c
e
c
u
r
r
e
n
t
s
[
A
]
i
sa
i
sb
i
sc
Fig. 7. Source currents using the algorithm based on (8). Case 1.
B. Case 2: Load balancing, considering zero sequence
currents
In this case, the algorithm performance was evaluated with
an unbalance resistive load connected in a wye (Y)
configuration with the system. The values of the resistance for
each phase are: R
a
=12, R
b
=R
c
=22. The total load is
connected to the system through a 15 mH inductor and a
resistance of 0.1.
1) Simulation results using the algorithm based on (1)
Fig. 8 shows the DCbus voltages U
dc
, U
dc1
and U
dc2
. Notice
that, there is an unbalance in the mean value of the voltages in
the capacitors, due to the injection of zero sequence currents.
These currents have to return by the midpoint of the
capacitors.
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
100
0
100
200
300
400
500
600
Time [s]
D
C
b
u
s
v
o
l
t
a
g
e
s
[
V
]
u
dc
u
dc1
u
dc2
Fig. 8. DC bus voltages using the algorithm based on (1). Case 2.
The grid currents are shown in Fig. 9. Notice that, before
compensation, the currents supplied by the grid are unbalance
and lagged with respect to the voltage in the PCC. After
t=0.2s, the filter mitigates the current unbalance and corrects
the power factor. In this way, the grid current is a pure
sinusoid of positive sequence and it is in phase with the
voltage in the PCC. These results show the outstanding
performance of the controllers.
0.17 0.18 0.19 0.2 0.21 0.22 0.23
15
10
5
0
5
10
15
Time [s]
S
o
u
r
c
e
c
u
r
r
e
n
t
s
[
A
]
i
sa
i
sb
i
sc
Fig. 9. Source currents using the algorithm based on (1). Case 2.
On the other hand, Fig. 10 shows the neutral current. After
t=0.2s, the zero sequence component of the grid current is null,
so the filter supplies this current to achieve the compensation
goals.
0.2655 0.266 0.2665 0.267 0.2675 0.268 0.2685 0.269 0.2695 0.27 268.6
268.7
268.8
268.9
269
269.1
269.2
269.3
269.4
Time [s]
D
C
b u s v o l t a g e s [ V ]
0.265 0.27 0.275 0.28 0.285 265
266
267
268
269
270
271
272
273
274
275
Time [s]
D
C
b u s v o l t a g e s [ V ]
6
0.15 0.2 0.25 0.3
2
1.5
1
0.5
0
0.5
1
1.5
2
Time [s]
C
u
r
r
e
n
t
b
y
t
h
e
n
e
u
t
r
a
l
o
f
t
h
e
g
r
i
d
[
A
]
iN
Fig. 10. Neutral current using the algorithm based on (1). Case 2.
2) Simulation results using the algorithm based on (8)
Fig. 11 shows the DCbus voltages U
dc
, U
dc1
y U
dc2
. In this
case, the voltages in the capacitors have the same mean value.
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
100
0
100
200
300
400
500
600
Time [s]
D
C
b
u
s
v
o
l
t
a
g
e
s
[
V
]
u
dc
u
dc1
u
dc2
Fig. 11. DC bus voltages using the algorithm based on (8). Case 2.
The grid currents are shown in Fig. 12. Notice that, after
t=0.2s the filter corrects the power factor and reduces the
current unbalance. However, the grid currents are not
completely balance after compensation. On the other hand,
Fig. 13 shows the neutral current. In this figure, it can be
observed that the zero sequence component of the grid current
is not null after t=0.2s. Accordingly, it is required a zero
sequence component in the grid current to guarantee that the
voltages in the capacitors have the same mean value.
Therefore, in this case the compensation is not perfect.
0.17 0.18 0.19 0.2 0.21 0.22 0.23
15
10
5
0
5
10
15
Time [s]
S
o
u
r
c
e
c
u
r
r
e
n
t
s
[
A
]
i
sa
i
sb
i
sc
Fig. 12. Source currents using the algorithm based on (8). Case 2.
0.15 0.2 0.25 0.3
2
1.5
1
0.5
0
0.5
1
1.5
2
Time [s]
C
u
r
r
e
n
t
b
y
t
h
e
n
e
u
t
r
a
l
o
f
t
h
e
g
r
i
d
[
A
]
iN
Fig. 13. Neutral currents using the algorithm based on (8). Case 2.
C. Case 3: Load balancing, considering a DC level in the
neutral current
In this case, the algorithm performance was evaluated with a
balance resistive load (R
a
= R
b
=R
c
=20) connected in a wye
(Y) configuration with the system and a monophase diode
rectifier connected to the phase a with a resistor of 21 in the
DCside. The total load is connected to the system through a
15 mH inductor and a resistance of 0.1.
1) Simulation results using the algorithm based on (1)
Fig. 14 shows the DCbus voltages U
dc
, U
dc1
y U
dc2
. Notice
that, the total DCbus voltage follows its reference value.
However, after t=0.2s there is an unbalance in the mean value
of the voltages in the capacitors and the filter loses the
controllability, when U
dc2
< 270 V, approximately. The
algorithm based on (1) controls the total DCbus voltage, but it
does not have an independent voltage control for each
capacitor.
0 0.1 0.2 0.3 0.4 0.5 0.6
100
0
100
200
300
400
500
600
Time [s]
D
C
b
u
s
v
o
l
t
a
g
e
s
[
V
]
u
dc
u
dc1
u
dc2
Fig. 14. DC bus voltages using the algorithm based on (1). Case 3.
Fig. 15 presents the grid currents. Notice that, the
compensation goals are not achieved and the grid current is
still unbalance due to the loss of the filter controllability. On
the other hand, Fig. 16 shows the neutral current. In this figure,
it can be observed that there is still a zero sequence component
in the grid current after compensation.
0.265 0.27 0.275 0.28 0.285 265
266
267
268
269
270
271
272
273
274
Time [s]
D
C
b u s v o l t a g e s [ V ]
7
0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
15
10
5
0
5
10
15
Time [s]
S
o
u
r
c
e
c
u
r
r
e
n
t
s
[
A
]
i
sa
i
sb
i
sc
Fig. 15. Source currents using the algorithm based on (1). Case 3.
0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
0.5
0
0.5
1
1.5
2
2.5
Time [s]
C
u
r
r
e
n
t
b
y
t
h
e
n
e
u
t
r
a
l
o
f
t
h
e
g
r
i
d
[
A
]
iN
Fig. 16. Neutral current using the algorithm based on (1). Case 3.
2) Simulation results using the algorithm based on (8)
Fig. 17 shows the DCbus voltages U
dc
, U
dc1
y U
dc2
. Notice
that, there is a little unbalance in the mean value of the
voltages in the capacitors. However, this unbalance does not
affect the compensation goals. In this case, the algorithm based
on (8) controls the total DCbus voltage, and it has an
independent voltage control for each capacitor.
0 0.1 0.2 0.3 0.4 0.5 0.6
100
0
100
200
300
400
500
600
Time [s]
D
C
b
u
s
v
o
l
t
a
g
e
s
[
V
]
u
dc
u
dc1
u
dc2
Fig. 17. DC bus voltages using the algorithm based on (8). Case 3.
The grid currents are shown in Fig. 18. Notice that, after
t=0.2s the filter corrects the power factor and reduces the
current unbalance. However, the grid currents are not
completely balance. . On the other hand, Fig. 19 shows the
neutral current. In this figure, it can be observed that there is
still zero sequence component in the grid current after t=0.2s.
Accordingly, it is required a zero sequence component in the
grid current to guarantee the filter controllability. Therefore, in
this case the compensation is not perfect.
0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
10
5
0
5
10
15
Time [s]
S
o
u
r
c
e
c
u
r
r
e
n
t
s
[
A
]
i
sa
i
sb
i
sc
Fig. 18. Source currents using the algorithm based on (8). Case 3.
0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
0.5
0
0.5
1
1.5
2
2.5
Time [s]
C
u
r
r
e
n
t
b
y
t
h
e
n
e
u
t
r
a
l
o
f
t
h
e
g
r
i
d
[
A
]
iN
Fig. 19. Neutral current using the algorithm based on (8). Case 3.
VI. CONCLUSIONS
In this paper, an algorithm to control the DC bus voltage of a
SAPF, based on the performance of the PI controller was
presented. The topology of fourwire threeleg VSI with split
capacitor is considered. The algorithm is based on the
calculation of a current in phase with the supply voltage at the
fundamental frequency, in a way that this current demands the
active power required to maintain the DCbus voltage in a
reference value.
The results presented above show that the controllers based in
one and two PI have an outstanding performance when the
SAPF does not inject currents with zero sequence components
and with DC level. On the other hand, when the filter has to
inject zero sequence currents without DC level, the algorithm
based on one PI has an outstanding performance. However, the
algorithm based on two PI does not mitigate completely the
current unbalance, but it guarantees that the voltages in the
capacitors have the same mean value. Finally, when there is a
DC level in the neutral current, the algorithm based on one PI
produces the loss of the filter controllability. On the other
hand, the algorithm based on two PI guarantees the filter
controllability, but it does not compensate completely the
unbalance in the grid currents.
VII. ACKNOWLEDGMENT
The authors gratefully acknowledge the financial assistance
given by the Universidad Industrial de Santander through the
Facultad de Ingenieras Fisicomecnicas and the project DIEF
5538 VIE.
8
VIII. REFERENCES
[1] A. Baggini, Handbook of Power Quality, John Wiley & Sons Ltd,
England, 2008.
[2] B. Singh, K. AlHaddad, and A. Chandra, "A review of active filters for
power quality improvement," Industrial Electronics, IEEE Transactions
on, vol. 46, pp. 960971, 1999.
[3] M. ElHabrouk, M.K. Darwish, and P. Mehta, "Active power filters: a
review," Electric Power Applications, IEE Proceedings , vol. 147, pp.
403413, 2000.
[4] J.F. Petit, "Control de filtros activos de potencia para la mitigacin de
armnicos y mejora del factor de potencia en sistemas desequilibrados,"
Ph.D. dissertation, Universidad Carlos III de Madrid, Oct 2007.
[5] P. Rodrguez, Aportaciones a los acondicionadores activos de corriente
en derivacin para redes trifsicas de cuatro hilos, Ph.D. dissertation,
Universidad Politcnica de Catalua, Barcelona, 2005.
[6] J.F. Petit, G. Robles, and H. Amaris, "Current Reference Control for
Shunt Active Power Filters Under Nonsinusoidal Voltage Conditions,"
Power Delivery, IEEE Transactions on, vol. 22, pp. 22542261, 2007.
[7] A. Ghosh and G. Ledwich, Power quality enhancement using custom
power devices, 1st ed.: Kluwer's power electronics and power systems
series, 2002
[8] M. Depenbrock, The fbdmethod, a generally applicable tool for
analyzing power relations, IEEE Trans. Power Syst.,vol. 8,no.2,pp.
381387, May 1993.
[9] S. Buso, L. Malesani, and P. Mattavelli, "Comparison of current control
techniques for active filter applications," Industrial Electronics, IEEE
Transactions on, vol. 45, pp. 722729, 1998.
IX. BIOGRAPHIES
Mara A. Mantilla Villalobos was born in
Bucaramanga (Santander), Colombia, 1985. She
received the B.Sc degree in electronical engineering
from the Universidad Industrial de Santander (UIS),
Bucaramanga, Colombia, in 2008 and she is
currently pursuing the M.Sc. degrees in electronics
engineering in the UIS. She works with the Grupo
de Investigacin en Sistemas de Energa Elctrica
(GISELUIS). Her research interests include: power
quality, power electronics, active power filters, custom power devices and
rational and efficient use of the energy.
Johann F. Petit Surez was born in Villanueva (La
Guajira), Colombia. He received the B.Sc. and
M.Sc. degrees in electrical engineering from the
Universidad Industrial de Santander (UIS),
Bucaramanga, Colombia, in 1997 and 2000,
respectively. He received his PhD in Electrical
Engineering from the Universidad Carlos III de
Madrid (UC3M), Spain, in 2007. Currently, he is a
Professor at the Universidad Industrial de Santander
(UISColombia) and his areas of interest include power quality, power
electronics and signal processing algorithm for electrical power systems.