Automatic Generation of JTAG Interface and Debug Mechanism for ASIPs Application Specific Instruction Set Processors (ASIPs) are increasingly used in complex System On Chip (SoC) designs. They combine a high computational performance with the flexibility of programmable solutions, as they are specialized according to particular application needs. Different realizations are compared in the architecture exploration phase in order to find an optimal solution. This requires a software tool-suite including assembler, linker, simulator and sometimes even a C-compiler. Architecture Description Languages (ADLs) are used to automate the development of the tool-suite and to quickly implement model changes. A high modelling efficiency can be achieved as ADLs describe the target architecture on a higher level of abstraction than Register Transfer Level (RTL). Details about the hardware implementation are neglected and the link to the physical parameters, such as clock speed, gate count or energy consumption, get lost. The LISA processor design platform enables the generation of the software tool-suite as well as the synthesis of the complete processor core in a Hardware Description Language (HDL). The languages currently supported are: VHDL, Verilog and RTL-SystemC. Thus, the designer is able to perform a gate-level synthesis and to take the physical parameters into account already in the exploration phase. Considering only the gate-level synthesis results of the generated architectures, the cores may already replace adequately the hand-written VHDL or Verilog models, as shown in previous work. However, the generated processor core is often not sufficient compared to real-world ASIPs as important functionality is missing. For example, real-world ASIPs support a debug interface, which is neglected by ADLs in order to shorten the architecture exploration phase. Thus, the designer has to implement a debug mechanism manually on RTL. This influences all registers, memories, pipeline registers and pipeline control. Modifying an architecture regarding those many elements introduces inconsistencies and contradicts the idea of an automated ADL to RTL design-flow. Also, it is obvious that the influence of a debug mechanism cannot be considered during the design-space exploration this way. In this paper we are proposing a JTAG interface and a debug mechanism generation which is embedded in our RTL-processor-synthesis from LISA. Thus, it is possible to estimate the required area or clock speed already during the design-space exploration phase and even to accept the generated RTL model for the final implementation. The synthesis process is based on a Unified Description Layer (UDL), which combines details about a RTL hardware implementation and architecture specification given in the LISA model. Thus, it is possible to automatically insertì¥Á15@ 11ð¿1111111111111ð11 2bjbjÏ2Ï22222222222222222222--22X22X22ð¤222222222222222ÿÿ¤22222222information about the architecture 2ÿÿ¤222222222ÿÿ¤22222222222222222ˆ22222¤ V222222¤ 222222¤ 222222¤ 222222¤ 22µ22222222222¸ 222222@222222@222222@222222@22 3 architecture exploration. The configurable elements are: Number and type of data-breakpoints, number of program breakpoints, read or write accesses to registers or memories, the debug-instruction operand coding and more. In our case study we derived an assembly-program-compatible architecture of the Motorola M68HC11 architecture. Among other changes, the instruction throughput of this architecture is improved by reorganizing the instruction-coding to 16-bit and 32-bit instructions and by increasing the memory interface bit-width. M68HC11 legacy code is still executable on this new architecture, as the assembler is also generated from the LISA description. We evaluated several configurations of the debug-mechanism to demonstrate the importance of a reasonable selection of features. The generated LISA6811 core counts 23k gates, a full debug support increases this amount by 10k gates. In our paper we discuss different implementations and provide design hints for an optimized ASIP realization.
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