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BY Rick NelsoN, editoR-iN-chief

The time is now for 3-D stacked die

s the semiconductor industry moves from more Moore to more than Moore, 3Dstackeddie implementations will become critical for implementing everdenser chip pack ages. Interest in the technology is strong, based on an over flow crowd attending a June 16 DAC (Design Automation Conference) panel, 3D stacked dienow or in the fu ture? The consensus seemed to be that the 3D revolution is imminent. Panelist LC Lu of TSMC (Taiwan Semiconductor Manufacturing Co) said that his company is developing the TSV (throughsiliconvia) technology that will interconnect the stacked chips in stacked die, with a focus on design, packaging, and testingnot just the fabrication process.
a 3D design to backend implementa tion without knowing for certain that its partitioned correctly. The demonstration grew out of what Riko Radojcic of Qualcomm called PathFinding technology, which Qual comm has been developing over a number of years. According to Radojcic, with traditional Moores law process mi grationfrom 90 to 65 nm, for example its relatively easy to project what will happen. The new ge ometry will yield de vices that are smaller, faster, and more prone to leakageinformation that can assist in building working and yielding parts. Such projections arent necessar ily valid or helpful with 3D parts. Something that allows you to explore knobs at both the architectural and the process ends is necessary, said Ra dojcic. Thats PathFinding to me. The collaboration with Atrenta, Auto ESL, and IMEC, he added, is an effort to build a commercial set of tools that assist the PathFinding function.

There are obstacles, however. Panel ist MyungSoo Jang of Samsung sug gested that accurate design and analysis tools that work together in a seamlessly integrated flow could speed the adop tion of 3D implementations. Lu agreed that new design methods could help address challenges related to gooddie sorting, process variations, and thermal and mechanical stress. Manufacturers are making progress on the designtool front. Atrenta, Auto ESL, Qualcomm, and IMEC at DAC demonstrated a working prototype frontend 3D chipdesign system. The flow the companies demonstrated ad dresses 3Daware highlevel synthesis, early partitioning, floorplanning, and multidomain analysis. The daunting challenges of 3D design demand a 3D aware highlevelsynthesis approach, said Atul Sharan, president and chief executive officer of AutoESL. Early partitioning, floorplanning, and analysis yield substantial benefits for design predictability on convention al advanced SOCs, said Ravi Varadara jan, Atrenta fellow. With the emer gence of 3D multitechnology design, this activity now becomes an absolute musthave. You simply cannot hand off

Pol Marchal, principal scientist for IMECs 3D SOCdesign initiative, who assisted with the June 14 demon stration, addressed PathFinding tech nology on June 8 at the IMEC Tech nology Forum at IMEC headquarters in Leuven, Belgium. IMECs overall 3D efforts, he said, involve investigations of TSV technology, wafer thinning and backside processing, the packaging of 3D die stacks, cost modeling, and 3D system exploration, with the last being germane to PathFinding technology. Marchal called PathFinding a system atic exploration of tradeoffs. Under standing the system requirements pro vides the engineer with inputs to guide design and technology decisions, he said, adding that a PathFinding flow al lows engineers to iterate on design and technology choices to optimize foot print, timing, thermal performance, and other functions. Marchal cited as an example a mobile consumer device, which would require three or four chip tiers with a package thickness of less than 0.6 mm and more than 1000 TSVs per tier operating at 400 MHz and providing a 12.8Gbyte/ sec data rate, all while consuming less than 2.5 pJ/bit. PathFinding analysis, he said, shows the feasibility of building such a device. Despite the emer gence of 3Ddesign tools, obstacles will remain to the wide spread adoption of 3D techniques. DAC panelist Joe Adam of JMA Consulting predict ed that incumbents with sig nificant investment in 2D tech nologies will be reluctant to change. Ultimately, however, resistance is fu tile. As IMECs Marchal told the June 16 DAC panel attendees, Practice today or dont play tomorrow.EDN
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JUly 15, 2010 | EDN 9