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Charge-Transferred Presensing and Efficiently Precharged Negative Word-Line Schemes for Low-Voltage DRAMS
Jae-Yoon Sim, Young-Gu Gang, Kyu-Nam Lim, Joong-Yong Choi, Sang-Keun Kwak, Ki-Chul Chun, Jei-Hwan Yoo, Dong-I1 Seo, Soo-In Cho Memory Product and Technology Division, Samsung Electronics, Korea


A 256Mb SDRAM is implemented with a 0.12pm technology to verify two circuit schemes suitable for mobile application. A charge transferred presensing is proposed t o achieve fast low-voltage sensing and robust operation. With a precharge disabler for productivity, new negative word-line scheme is also proposed t o bypass the majority of discharging current to VSS without switching control. K e y w o r d s : D R A M , low-voltage, s e n s i n g

Low power requirements in mobile system have driven the low voltage trend of DRAM product which seeks for challengeable circuit and process technologies to improve performance as well as stability. Though DRAM has successfully managed to move down to 1.8V era[l], further voltage scaling has been limited by critical problems such as sensing speed degradation, tightened power budget, and retention characteristics. Fig. 1 shows the bit-line(BL) flipping affected by VCCprecharged IO lines in the conventional VBL(=VCCA/Z) precharged BL scheme. VCC and VCCA represent internally generated voltage sources for periphery and array, respectively. This BL flipping error occurs when CSL is enabled too fast after the sensing start under the circumstances of process/design-induced skews, such as mismatch in threshold voltages of N3 and N4 and difference in resistance between BL-to-IO and BLB-to-IOB paths. Such performance degradation by the BL flipping hrcnmes more serioiis in low voltage operation due to the reduced data keeping capability of the latcb(N1, N2, P1, Pa). Chargetransferred presensing(CTPS) schemes[2][3] removed the BL flipping by precharging the sensing BLs(SBL, SBLB) with high level. Fig. 2 shows the circuit and timing diagrams of a typical CTPS scheme. Though CTPS schemes improved the low voltage sensing, they are difficult to be implemented due to the complex constraints in the additional bias levels(Vmid and VH) and ratios of capacitances(Ccm,L, CBL and C S B L )t o guarantee N5 and N6 to be operated in the saturation region[2]. The small rnrrent driving capability of t h e cell access t,ransist,nr i s st,ill another limit,nt,ion factor for low voltage operation. The threshold voltage of the cell access transistor i s not, sralahle along with operating voltage due to

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t,hn retention time requirements. Furthermore the gen. eration of higher VPP from low voltage requires multistage pumping with poor efficiency[l]. Addressing those issues, negative word-line(WL) schemes have been proposed[4][5][6].Negative bias generation by charge pumping, however, requires large current consumption, causing serious fliirt,uations during the fast-cycle operation. Tightened current allowance of mobile application at power-down or self-refresh mode is another critical probk m in the negative scheme. In terms of productivity, significant portion of DRAM product is exposed to WT.-to-RT. hridge defects during the fabrication process. Though the bridges are repairable with redundant WLs or BLs, the amount of current flowing through the bridges still remains after the repair. So charge pumping is required to compensate the leakage current flowing to the negative bias, resulting in additional current consumption L which is not in the ground-precharged W scheme. The inrrease of current in the power-down modes causes significant yield loss in productivity.






Fig, 4. Circuit(a) and timing(h) diagrams of the proposed negative WL scheme used in a typical array with local SWDs.

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Fig. 3 shows circuit(a) and timing(b) diagram of the



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sharing phase, enable switches(N7 and N8) for the p r o sensing turn on. Then SBL and SBLB are developed ! W L by the presensirig with N9 and N10. The presensing is followed by regenerating amplification with the positive i yBBi feedback configuration of N9 and NI0 and the pull-up ' ~ ~ - - - - - ~ ~ - - - - - - . ~ ~ - - - - - ~ ~ ~ ~ ~ - - - - ' sensing by P1 and P2. This regeneration guarantees ro- ~ i 5. ~ , proposed VBL.precharKe disabling circuit. hitst. operation without additional bias voltages; eliminnting the complex constraints in the conventional CTPS[2].

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Fig. 6. Simulated waveforms of a sensing and precharge cycle for the conventional(a)and the proposed(b) sensing schemes shown in Fig. 1 and Fig. 3, respectively.

very small, the WL-to-BL bridge pulls down BL and BLB to almost VBBP. That results in bit-failures along column direction which can he repaired by column redundancy. At the repair stage, by cutting the fuse F1 to disable CSL, EQE is also disabled t o VBBZ, which eliminates VBL-to-VBB2 current path through NE4, NEZ, and NS. Results

After the main pull-down sensing enabled by high-tolow- transition of SAN, RSTi goes to V P P level to restore the sensing result t o the storage cell. Negatively P r e c h a r g e d Word-Line Scheme Fig. 4 shows circuit(a) and timing(b) diagrams of the proposed negative WL scheme used in a typical array with local sub-word decoder(SWD). VBBZ represents the negative bias for the precharged WLs. At the start of the precharge phase, WL and heavily loaded PXD discharge to both VSS and VBBP simultaneously. The majority of the discharging current flows to VSS through WZ: pulldown NMOS of I1 and W1, due to their large W / L ratio and high gate bias. When PXD becomes lower than Vtn, W1 turns off. Then W3 and W4, with small W / L ratios, slowly discharge the rest of charge to VBBZ. Subsequently the discharging path of WLE is switched from VSS tu VBBP in response to the voltage of WLE itself. W3 and W4 should have high-Vtn to minimize leakage current caused by positive Vcs during the phase of WL activation. About 60-percent of current flowing to VBBZ is reduced by minimizing VBBZ transition of WL control signals and bypassing the discharging current of the heavily loaded nodes to VSS. To use the negative WL scheme fur mobile product, the leakage current caused by the WL-to-BL bridge defect should be removed. Fig. 5 shows a disabling scheme of VBL-precharge. If W / L ratio of NE4 is designed t o be

To verify the proposed schemes, a 256-Mb SDRAM was designed and fabricated with a 0.12prn technology. For normal operation, VCC, VCCA, VPP, and VBB2 were designed to be l.GV, 1.3V: 2.9V, and -0.4V, respectively. Fig. 6 shows simulated waveforms of a sensing and precharge cycle for the conventional(a) and the proposed(b) sensing schemes showxi in Fig. 1 and Fig. 3, respectively. For the precharge scheme: the proposed negative WL scheme shown in Fig. 4 was applied to both cases. The CTPS scheme gives about 17-percent larger voltage difference a t the end of the charge sharing phase, because the effective BL capacitance was reduced by the isolation of SBLs. .4s shown in Fig. 6, the proposed CTPS achieved fast development of SBL and SBLB from the start of the sensing. T h e slow high-to-low transition of WL when WL is less than 0.7V does not degrade the precharge performance, since the cell access transistor almost turns off when WL is less than l\. Fig. 7 shows simulated results of the differential sensing current flowing through CSL gates, i(I0)-i(IOB), in the conventional(Fig. 1) and the proposed(Fig. 3) sensing schemes. With the asymmetric BL-to-IO line model as designed, 70mV-mismatch in threshold voltage of CSL gates was introduced in this simulation tu verify the immunity against the BL flipping. While t h e conventional scheme suffers from the BL flipping when the sensingto-CSL time is up to 3ns, the proposed CTPS makes it



2003 Symposium on VLSl Circuits Digest of Technical Papers

possible for CSL to be timed from the start point of the sensing. With this simulation, improvements in the minimum allowable RAS-tc+CAS delay of 3ns is expected at VCCA=1.3V. Fig. 8 shows a photomicrograph of the test chip. To verify the effect of the proposed sensing scheme, A and C banks were allocated for CTPS, and B and D banks for the conventional scheme. Each bank has two cases of Cb/Cs ratios, 5.3 and 7. The chip size overhead was 3.2-percent for CTPS, and 0.9-percent for negative WL schemes, respectively. Fig. 9 shows measured shmoo plots of RAS-to-CAS delay vs. voltage(=VCC=VCCA). In the proposed sensing scheme, the minimum RAS-to-CAS delay was 12ns at VCC of 1.3V showing less sensitivity to voltage variation. The improvements were more dramatic in the case of larger Cb/Cs ratio, because the readout performance depends on the voltage difference between SBL and SBLB, not being affected by the capacitance of BL and BLB. Fig. 10 shows measured current vs. voltage (=VCC=VCCA), with active cycle time of 15011s. To break down the pumping current for VBBP generation, power for the negative charge pumping was driven by a separated pin. Comparing with simulated current for direct discharging case, the proposed WL scheme reduced about 60-percent of pumping current. Conclusions

Fig. 8. Photomicrograph of the test chip.


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A charge transferred presensiug and a negative wordline schemes were proposed to achieve high performance and stability for low voltage mobile application. The implemented schemes were verified using a 256Mb SDRAM with a 0.12Wm technology. The proposed CTPS improved R.AS-tc+CAS delay being free from the design constraints required in the conventional CTPS. Without loss in productivity, the negative WL scheme automatically switches the discharging path in response to the discharging nodes itself eliminating additional switching control.
[l] J . Y. Sim, et al., "Double boosting pump, hybrid current

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sense amplifier, and binary weighted temperature sensor adjustment schemes for 1.8V 1ZBMb mobile DRAMS,"Dig. Symp. VLSI Cir. , pp. 294-295, 2002. [Z] M. Tsukude, et al., "A 1.2V to 3.3V wide voltagerange/low-power DRAM with a charge-transfer presensing scheme," IEEE JSSC, pp. 1721-1727, Nov. 1997. [3] L. Heller, et al., "High sensitivity charge-transfer sense amplifier," IEEE JSSC, pp. 596-601, Oct. 1976. [4] H. Tanaka, et al., "A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme," IEEE JSSC, pp. 1084-1090, Aug. 1999. 11 H. Yamauchi, et al., "A circuit technology for self-refresh 5 16Mh DR.AM with less than 0.5 uA/MB data-rdention current,'' IEEE JSSC, pp. 1174-1182, Nov. 1995. 161 T. Yamagata, et al., "Low voltage circuit design techniques f r hat.tery-operated and/or giga-scale DRAM'S," I E E E o .ISSC, pp. 1183-1188, Nov. 1995.
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