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74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register

April 1988 Revised January 2002

74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register


General Description
The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P0P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal. When M is LOW, data is shifted out of the most significant bit position while information present on the Serial (SI) input shifts into the least significant bit position. A HIGH signal on the Chip Select (CS) input prevents both parallel and serial operations.

Features
s 16-bit parallel-to-serial conversion s 16-bit serial-in, serial-out s Chip select control s Slim 24 lead 300 mil package

Ordering Code:
Order Number 74F676SC 74F676PC 74F676SPC Package Number M24B N24A N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

2002 Fairchild Semiconductor Corporation

DS009588

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74F676

Unit Loading/Fan Out


Pin Names P0P15 CS CP M SI SO Description Parallel Data Inputs Chip Select Input (Active LOW) Clock Pulse Input (Active LOW) Mode Select Input Serial Data Input Serial Output U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/0.6 mA 20 A/0.6 mA 20 A/0.6 mA 20 A/0.6 mA 20 A/0.6 mA

1 mA/20 mA

Functional Description
The 16-bit shift register operates in one of three modes, as indicated in the Shift Register Operations Table. HOLD a HIGH signal on the Chip Select (CS) input prevents clocking, and data is stored in the sixteen registers. Shift/Serial Load data present on the SI pin shifts into the register on the falling edge of CP. Data enters the Q0 position and shifts toward Q15 on successive clocks, finally appearing on the SO pin. Parallel Load data present on P0P15 are entered into the register on the falling edge of CP. The SO output represents the Q15 register output. To prevent false clocking, CP must be LOW during a LOW-to-HIGH transition of CS.

Shift Register Operations Table


Control Input Operating Mode CS H L L M X L H CP

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = HIGH-to-LOW Transition

 

Hold Shift/Serial Load Parallel Load

Block Diagram

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74F676

Absolute Maximum Ratings(Note 1)


Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA)

65C to +150C 55C to +125C 55C to +150C 0.5V to +7.0V 0.5V to +7.0V 30 mA to +5.0 mA

Recommended Operating Conditions


Free Air Ambient Temperature Supply Voltage 0C to +70C

+4.5V to +5.5V

0.5V to VCC 0.5V to +5.5V

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICC Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current 60 4.75 3.75 0.6 150 72 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 5.0 7.0 50 Min 2.0 0.8 1.2 Typ Max Units V V V V V A A A V A mA mA mA Min Min Min Max Max Max 0.0 0.0 Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = 18 mA IOH = 1 mA IOH = 1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A, All Other Pins Grounded VIOD = 150 mV, All Other Pins Grounded VIN = 0.5V VOUT = 0V

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74F676

AC Electrical Characteristics
TA = +25C Symbol Parameter Min fMAX tPLH tPHL Maximum Clock Frequency Propagation Delay CP to SO 100 4.5 5.0 VCC = +5.0V CL = 50 pF Typ 110 9.0 9.0 11.0 12.5 Max TA = 55C to 125C VCC = +5.0V CL = 50 pF Min 45 4.5 5.0 17.0 14.5 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 90 4.5 5.0 12.0 13.5 Max MHz ns Units

AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(L) tH(H) Setup Time, HIGH or LOW SI to CP Hold Time, HIGH or LOW SI to CP Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW M to CP Hold Time, HIGH or LOW M to CP Setup Time, LOW CS to CP Hold Time, HIGH CS to CP tW(H) tW(L) CP Pulse Width HIGH or LOW 4.0 4.0 4.0 4.0 3.0 3.0 4.0 4.0 8.0 8.0 2.0 2.0 10.0 10.0 4.0 6.0 Max TA = 55C to 125C VCC = +5.0V Min 4.0 4.0 4.0 4.0 3.0 3.0 4.0 4.0 8.0 8.0 2.0 2.0 12.0 10.0 5.0 9.0 Max TA, VCC = ____ VCC = +5.0V Min 4.0 4.0 4.0 4.0 3.0 3.0 4.0 4.0 8.0 8.0 2.0 2.0 10.0 ns 10.0 4.0 6.0 ns ns ns Max Units

ns

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74F676

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide Package Number N24A

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74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N24C

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