nTX

User’s Guide and Tutorial

NOVAS Software, Inc.
NOVAS Software, Inc. 2025 Gateway Place, Suite 400, San Jose, CA 95110 Phone: 1-888-NOVAS-38 (1-888-668-2738) Fax: 408-467-7889 www.novas.com

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Printing
Printed on June 30, 2006.

Version
This manual supports Verdi and nTX 2006.04 and higher versions.

Copyright
All rights reserved. No part of this manual may be reproduced in any form or by any means without written permission of: NOVAS Software, Inc. 2025 Gateway Place, Suite 400, San Jose, CA 95110 www.novas.com Copyright (c) 1996-2006 NOVAS Software, Inc.

Trademarks
Debussy is a registered trademark and Verdi is a trademark of Novas Software, Inc. Verdi, nTrace, nSchema, nState, nWave, Temporal Flow View, nBench, nCompare, nLint, nECO, nESL, nTX, nAnalyzer, Active Annotation, and Knowledge-Based Debugging are trademarks of Novas Software, Inc. The product names used in this manual are the trademarks or registered trademarks of their respective owners.

Restricted Rights
The information contained in this document is subject to change without notice.

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Contents

Contents
About This Book 7
Purpose......................................................................................................... 7 Audience ...................................................................................................... 7 Book Organization ....................................................................................... 8 Conventions Used in This Book .................................................................. 9 Related Publications................................................................................... 10 How to Reach Novas Software, Inc........................................................... 11

Introduction

13

Overview - Why nTX?............................................................................... 13 Technology ................................................................................................ 14 Transaction Analysis ............................................................................ 14 Transaction Generation/Extraction....................................................... 14

Debug with Transactions

15

Overview.................................................................................................... 15 What is a Transaction?.......................................................................... 15 Generating Transaction Data ................................................................ 15 Use Model.................................................................................................. 16 Detailed Transaction View ................................................................... 16 Selecting Transactions .......................................................................... 17 Transaction Properties .......................................................................... 18 Transaction Attributes .......................................................................... 19 Analyzing Transactions ........................................................................ 19 Generating Transaction Data ................................................................ 20

Transaction Extraction

23

Use SystemVerilog Assertions (SVA)....................................................... 23 Use Model............................................................................................. 23 SVA Code............................................................................................. 24 Use nTE ..................................................................................................... 29 Pre-requisites ........................................................................................ 29 Installing nTE from the Internet ........................................................... 30 Set Up the Environment........................................................................ 31 Use Model............................................................................................. 31

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nTX User’s Guide and Tutorial

Bus Configuration File (BCF) Format.................................................. 32 nTE Results........................................................................................... 35

Transaction Tutorials

37

Before You Begin ...................................................................................... 37 View Transactions in nWave ..................................................................... 38 Import FSDB File ................................................................................. 38 Add Transaction Waveforms................................................................ 38 View Transactions in Transaction Analyzer Window ............................... 41 Import FSDB File ................................................................................. 41 Add/Remove Transaction Streams ....................................................... 41 Merge Transaction Streams .................................................................. 43 Manipulate the Stream View ................................................................ 45 Generate Statistics ................................................................................ 50 Analyze Transactions Using TCL.............................................................. 54 Execute the TCL File............................................................................ 54 Manipulate Transactions and View Statistics with TCL ...................... 55 Example TCL Script ............................................................................. 58 Generate an FSDB File with Transaction Information .............................. 64 PLI Background.................................................................................... 64 Procedures for Writing a PLI Routine .................................................. 65 Steps for Writing FSDB........................................................................ 69 Steps to Dump Transactions to FSDB .................................................. 70 C Files for FSDB Writer API ............................................................... 72 Use Provided C Files for PCI Transaction Dumping ........................... 73

Appendix A: AMBA AHB Transactor

75

Overview.................................................................................................... 75 BCF Format ............................................................................................... 75 Name..................................................................................................... 75 Mapping Root ....................................................................................... 75 Signal Map............................................................................................ 76 Parameters............................................................................................. 76 Transactor Configurations .................................................................... 78 Transaction Hierarchy................................................................................ 78 Protocol Tree ........................................................................................ 79 Transaction Description........................................................................ 80 Additional Information .............................................................................. 86 Data Types ............................................................................................ 86 Transactor Constants ............................................................................ 88

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................................................................. 115 Protocol Tree ............................. 105 Protocol Tree ........................................................................................................................................................ 116 www......................... 106 Additional Information ............................................................................................ 111 Signal Map....................................... 89 BCF Format ........................................................................................................................................................... 101 Signal Map...................... 92 Protocol Tree .................. 113 Transactor Configurations .............. 101 Name..................................................................................... 111 Name............................................................................................................................... 91 Transaction Hierarchy.................................................................. 109 Appendix D: AMBA AXI Transactor 111 Overview................. 100 Appendix C: AMBA APB Transactor 101 Overview..... 89 Mapping Root ....................................................... 94 Additional Information ......................................................cadfamily....................................................... 111 Mapping Root ................................................. 102 Parameters.....we will delete ....................................................................................................................................................................................................................... 112 Parameters.................................................................................... 102 Transactor Configurations ........if tort to your rights....................................................................................................................................................................... 101 Mapping Root ....Appendix B: AMBA AHB Lite Transactor 89 Overview...............................................................................................com 3 The document is for study only............................................... 89 Signal Map................................................................................ 98 Data Types ..................................................................................................................................................................................................................... 93 Transaction Description.........................................com EMail:cadserv21@hotmail......................................... 101 BCF Format .............................................................................................................. 103 Transaction Hierarchy.............................................................................................................................................................................. 90 Parameters........................................................... 89 Name.................................................................................................... 109 Transactor Constants ................................................................................................... 90 Transactor Configurations ....................................................................................... 105 Transaction Description..... 98 Transactor Constants ................................................................ 109 Data Types ............................................................................ 111 BCF Format ..... 114 Transaction Hierarchy.................................................................................................please inform us.........

...................... 138 Data Types .if tort to your rights....................................................................... 139 Name......................................... 132 Transactor Configurations ......................... 141 Transactor Configurations .................................................................................................................... 155 Data Types ...................................................................................................................................................................... 156 Appendix G: PCI-Express (PCIe) Transactor 157 Overview.......................................................................... 133 Transaction Hierarchy........................................................................................................ 133 Protocol Tree ......................................................... 146 Protocol Tree .................... 140 Parameters.............................................................................................. 131 Name.............................................................................................................................................................. 131 Signal Map.................................................................... 148 Additional Information ...... 139 Limitations............................................................................................... 131 BCF Format ..................................................................... 134 Transaction Description...................................................................................... 157 Name............................................................................... 145 Transaction Hierarchy..................................................................................................................................................................................................................................................................................nTX User’s Guide and Tutorial Transaction Description.......................................................................................................................................................................................................... 140 Signal Map............................ 157 Mapping Root . 135 Additional Information ....................................................com EMail:cadserv21@hotmail................... 147 Transaction Description....................... 157 BCF Format ....................................................................................................................... 138 Appendix F: OCP-IP Transactor 139 Overview............................ 131 Mapping Root ............... 132 Parameters..............................................we will delete .....................................................................................................................................................................................................................com 4 The document is for study only.................................................................................................... 129 Appendix E: MPEG2_TS Transactor 131 Overview........................................................................cadfamily.......................................... 117 Additional Information ........please inform us............. 127 Transactor Constants . 155 Transactor Constants ...... 127 Data Types ................................................................... 139 Mapping Root ............................................. 157 www... 139 BCF Format ...........................................................................................................................................................................

..... 187 Name....................................................... 158 Parameters.................................................................................... 175 BCF Format ......................................... 188 Parameters......................................................... 180 Transaction Description.. 178 Protocol Tree ............................................................................................................................... 198 Data Types ..................................................... 160 Transaction Hierarchy................................................................................................................................................................................................................................................................................................................if tort to your rights..................... 185 Appendix I: USB Transactor 187 Overview........ 159 Transactor Configurations ............. 161 Transaction Description..................................................................... 175 Name.................................................................................................................................. 176 Transactor Configurations ............................................................................. 188 Transactor Configurations .......................................................................... 175 Mapping Root ..... 169 Appendix H: UART Transactor 175 Overview.................................................................. 190 Protocol Tree ... 179 Protocol Tree .............. 187 Mapping Root ...................... 178 Transaction Hierarchy....................................... 169 Data Types ..........................................................................................................cadfamily.......................................................... 176 Parameters.......................................................................................we will delete ................................................................................................................................... 161 Protocol Tree ............................................................................... 185 Data Types ......................................................... 192 Additional Information .................TX......................................................com EMail:cadserv21@hotmail............................................................................................. 198 Index 201 www....... 190 Transaction Hierarchy........................................................... 187 BCF Format ...............Signal Map......... 187 Signal Map......................................................................................... 181 Additional Information ................................................................................ 176 Signal Map........................................................................................................................................................................................com 5 The document is for study only.......... 162 Additional Information ............................................. 191 Transaction Description..............please inform us.................................................................................................................................................................................................................................................................RX.................................................

com 6 The document is for study only.cadfamily.please inform us.we will delete .nTX User’s Guide and Tutorial www.com EMail:cadserv21@hotmail.if tort to your rights.

and digital logic design.com EMail:cadserv21@hotmail.if tort to your rights.About This Book About This Book Purpose This book is designed to allow you to quickly become proficient in the nTX module. boardlevel. You should already be familiar with Verdi before beginning this book. The manual should be read from beginning to end. please review the Verdi User’s Guide and Tutorial document first. and developing hardware and/or software designs using C. Modeling at this abstract level requires more capable. The application domain of these modeling approaches and languages can be for System-on-Chip (SoC). This book focuses on the most commonly used commands without going into detail on everything.we will delete . please refer to the appropriate chapter of the Novas Command Reference Manual. automated debugging tools. both scalable and efficient.cadfamily. This document assumes that you have a basic knowledge of the platform on which your version of Verdi runs: UNIX or Linux and that you are knowledgeable in Verilog or VHDL. simulation software. although you may skip any sections with which you are already familiar.please inform us. an add-on to Novas’s Verdi debugging system.com 7 The document is for study only. Audience The audience for this manual includes engineers who are familiar with modeling techniques and languages used in high level design such as the use of transactions. or platform designs implemented with Application Specific Integrated Circuits (ASICs). www. SystemC. C++. For detailed descriptions of individual commands. If you do not feel comfortable with basic Verdi operations. and numerous other programmable or custom design blocks and components. Field Programmable Gate Arrays (FPGAs).

Appendix A-I provides detailed information for extracting the AHB.cadfamily. AHB-lite.com 8 The document is for study only. • www. Introduction provides an overview of nTX and introduces its broadly applicable use methodology and unique environment. transactions in Verdi with nTX. Transaction Tutorials provides examples regarding the recording and creation of. Debug with Transactions provides details regarding the recording and creation of.if tort to your rights. Transaction Extraction provides details on different methods for extracting transactions. OCP-IP. AXI.we will delete . APB. as well as debug with. Index is a detailed index to this book.com EMail:cadserv21@hotmail. UART and USB protocols respectively with nTE.nTX User’s Guide and Tutorial Book Organization This nTX User’s Guide and Tutorial is organized as follows: • • • • • • About This Book provides an introduction to this book and explains how to use it. transactions in Verdi with nTX. capabilities. MPEG2-TS. and utilities.please inform us. PCI. as well as debug with.

com EMail:cadserv21@hotmail. Shift-click-left means press and hold the <Shift> key then click the left mouse button on the indicated item. Double-click means click twice consecutively with the left mouse button. highlight titles.cadfamily.com 9 The document is for study only. and other nTX terms. Drag-left means press and hold the left mouse button.we will delete . warnings. file path. Click-middle means click the middle mouse button on the indicated item.About This Book Conventions Used in This Book The following conventions are used in this book: • • • • • • • • • • • • Italics font is used for emphasizes. design names. book titles. Courier type is used for program listings. Click-left or Click means click the left mouse button on the indicated item. www. section names. Bold is used to emphasize text. It is also used for test messages that nTX displays on the screen. menu items.if tort to your rights. or unique commands. Note describes important information. then move the pointer to the destination and release the button. Click-right means click the right mouse button on the indicated item. and file names within paragraphs.please inform us. Menu->Command identifies the path used to select a menu command. Drag means press and hold the middle mouse button on the indicated item then move and drop the item to the other window.

nCompare User’s Manual . Verdi and Debussy Quick Reference Guide . please refer to the appropriate language standards board (www.ieee.com.nTX User’s Guide and Tutorial Related Publications • • • • Novas Installation and System Administration Guide . see the Verdi Release Notes shipped with the product and the installation files in the distribution directories.we will delete . www. www.com EMail:cadserv21@hotmail. nESL User’s Guide and Tutorial . etc. www.gives a brief summary of the different modules and related mouse commands and bind keys. Verdi User’s Guide and Tutorial .com. Vera.com) websites.) and verification (e. Library Developer’s Guide .cadfamily. For language related documents. Verdi and Debussy Command Reference Manual .if tort to your rights.cadence.accellera. nAnalyzer User’s Guide and Tutorial . Verdi Release Notes .synopsys.detailed information on using nCompare.) language reference materials are not included in this manual.detailed information on using nLint.verisity. Language Documentation Hardware description (Verilog. nLint User’s Guide and Tutorial .for current information about the latest software version. verifying and using symbol libraries.com 10 The document is for study only. VHDL. Linking Novas Files with Simulators to Enable FSDB Dumping .detailed information on using nESL.detailed information on using nAnalyzer.org) or vendor (www.detailed information on using Verdi.explains how to install Novas products including Verdi.gives detailed information on the Verdi and Debussy command set including nTX. • • • • • • • • • www.please inform us.gives detailed information on linking Novas object files with supported simulators for FSDB dumping.org. nECO User’s Guide and Tutorial . SystemVerilog. etc.provides information on creating.detailed information on using nECO.

S. Phone: 1-888-NOVAS-38 (1-888-668-2738) or 408-467-7888 FAX: 408-467-7889 E-Mail: sales@novas.please inform us.A.About This Book How to Reach Novas Software. Taiwan R. No.com 11 The document is for study only.com Asia Headquarters: 5F.novas.if tort to your rights.com EMail:cadserv21@hotmail. 25. Phone: 886-3-567-9656 FAX: 886-3-567-0066 www. URL: http://www.cadfamily.we will delete . Industry East Road IV Science-Based Industrial Park Hsinchu. support@novas.O.com for license request and sales information. Inc.com for technical support. CA 95110 U. Suite 400 San Jose. Corporate Headquarters: 2025 Gateway Place.C.

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com EMail:cadserv21@hotmail. nTX.com 13 The document is for study only.cadfamily. system performance evaluation such as throughput and latency. The nTX technology addresses multiple key requirements: • • Comprehensive transaction analysis environment that provides easy understanding of complex device communication. engineers still need a way to visualize. resource usage. mainly with in-house simulation environments. They are an extremely powerful datalevel abstraction that help users think about high-level design and functionarchitecture trade-offs. adding advanced system and platform debugging technologies with unified support for the diverse methodologies involved in such designs. Transaction-level abstractions ease the understanding of on-chip communication and bus complexity.Introduction Introduction Overview . understand and debug the information. builds on top of the comprehensive Verdi debug system. correlation across bus bridges. however.Why nTX? Transactions have been used for years to model system-level behavior. particularly with complex protocols. synchronization and the like. Leverage powerful automated RTL debug system and significant debug experience from a wealth of application areas.please inform us. www. Automation tools must enable analysis functions including bus loading and utilization.if tort to your rights.we will delete .

com 14 The document is for study only. Spreadsheet view that supports data management and presentation functions such as sorting/filtering of transactions and statistical analysis.nTX User’s Guide and Tutorial Technology nTX provides support in the following areas.please inform us.) Transaction IP-provider partners such as Denali and Spiratech. SystemC SCV methods.com EMail:cadserv21@hotmail. End user coding using the FSDB writer API. • • • www. Transaction Generation/Extraction The transaction data can be obtained from one or more of the following diverse sources: • Native FSDB dumper function calls embedded in the system model.we will delete . and also from the HVLs (such as ‘e’. Extraction from SystemVerilog Assertions.if tort to your rights. Transaction Analysis The current support for transaction level verification and debug in nTX is as follows: • • Transaction waveform visualization in nWave.cadfamily. available soon.

Create relationships between existing transaction. 4. even if the sets of attributes that constitute two transactions are the same. Create a stream. 2. you must follow the steps below: 1. System design is in a very early stage of the whole design process. as in SCV. transaction IP partners. if the entire system is to be verified.com EMail:cadserv21@hotmail. www. Create a transaction. Transaction streams can be dumped into FSDB format using dumping libraries provided by Novas and its partners or using the Open Transaction Interface (OTI) extension of the Novas FSDB Writer API. That is.com 15 The document is for study only. 3. For testbench verification. Transactions are organized into streams.if tort to your rights. Streams hold transactions. Create attributes. When an error is found in the transaction level.cadfamily. Transaction data can also be extracted from your code using SystemVerilog Assertions. What is a Transaction? Transactions are higher level abstractions of signal-level detailed activity. Generating Transaction Data The transaction data can be obtained from Novas provided native FSDB dumpers. there is no such concept as "transaction type".please inform us. Each transaction consists of a set of attributes and is independent of one another. a powerful viewing mechanism for transactions is mandatory to system designers. therefore. or the FSDB writer API and Open Transaction Interface (OTI). transaction level checking is efficient and easy to focus comparisons of system behavior against system specification.we will delete . the signal level is then investigated.Debug with Transactions Debug with Transactions Overview Transactions are an important piece of abstraction in system design and debug. When you create a transaction.

nTX User’s Guide and Tutorial

Use Model
The transaction FSDB file is loaded into nWave the same way as a general FSDB file. A stream name will be shown in the signal pane; begin time, end time, and attributes are shown in the value pane; and the transaction will be shown in the waveform pane as rectangles enclosing all the attributes. This section includes the following topics: • • • • • • Detailed Transaction View Selecting Transactions Transaction Properties Transaction Attributes Analyzing Transactions Generating Transaction Data

Detailed Transaction View
The following figure summarizes the different aspects of transaction viewing in nWave.

Figure: Detailed Transaction View

Although there is a begin time and end time in a transaction, when you click on a transaction, the cursor will be located at the begin time. When you select a stream, you can click the Search Backward/Search Forward icons (blue left/ right arrows) on the nWave toolbar to step through the transactions. A dashed line

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Debug with Transactions

under the transaction box indicates there are more attributes than are currently displayed. You can increase (decrease) the height of the stream in the signal pane to show more (less) attributes. Alternatively, you can move the cursor on top of the transaction attributes in the value pane (middle column) to activate a tip showing all attributes as displayed in the following figure.

Figure: Transaction Tip

Selecting Transactions
Individual transactions can be selected by clicking on the label in the waveform pane; the background color of the selected transaction will change to light blue. Pressing the Search Backward/Search Forward toolbar icons will not change the selected transaction but will change waveform cursor time. The selection is important for viewing the covered or obscured transactions when there is a time overlap for multiple transactions. The top triangle is used to select the underlying transaction and bring it to the front.

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nTX User’s Guide and Tutorial

If there are transactions related to the selected one, the related transaction will be highlighted with a pink background color, similar to the following example.

Figure: Transaction Relationships

Transaction Properties
Transactions contain a lot of data. You can view the attributes and relationships of a selected transaction in a tabular format. To open the Transaction Property form, select a transaction, click-right to open the context menu, and chose the Properties… command. The Attributes tab summarizes the transaction attributes, as shown in the following example:

Figure: Transaction Property Dialog Window - Attributes

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Debug with Transactions

You can view the selected transaction relationships by selection the Relationship tab in the Transaction Property form.

Transaction Attributes
You can use string matching to search attributes. In nWave, choose Waveform -> Set Search Attributes… to open the Search Attribute Value form. Alternatively, you can click-left on the Search By: icon on the toolbar and select the Transaction Attribute Values option.

Figure: Search Attribute Value Form

You can specify the attribute name and value. Once you’ve entered the search criteria and clicked OK, you can use the Search Forward/Search Backward icons on the nWave toolbar to step through the transactions of the selected streams.

Analyzing Transactions
In addition to the waveform viewing capability for transactions, you can open the Transaction Analyzer window by invoking Tools -> Transaction Analyzer -> Open Transaction Analyzer Window from nWave. Once the window is open, you can load one or more streams individually or merge multiple streams together.

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we will delete . or View -> Filter to filter and display transactions whose attributes match user-specified conditions. SystemC SCV. you can choose View -> Show All to restore all the transaction data. you can use View -> Find to locate a string or pattern.com 20 The document is for study only.nTX User’s Guide and Tutorial The window will be similar to the following: Figure: Transaction Analyzer Window For the current selected stream (or merged streams). These commands allow you to more quickly navigate the streams and focus on the transactions of interest. Generating Transaction Data The transaction data can be obtained from the following sources.com EMail:cadserv21@hotmail. After filtering a stream. SystemC/SCV -. • • • www. Specman/e SystemVerilog test bench in conjunction with simulator support (VCS.cadfamily. and HVL simulators. ModelSim) • Vera Click here to access the SystemC Linking chapter in the Linking Novas Files with Simulators to Enable FSDB Waveform Dumping manual for details on linking native FSDB dumpers.supported OSCI and NCSC simulators.please inform us.if tort to your rights. Provided FSDB Dumpers Dump transaction data from languages directly with native FSDB dumpers.

com EMail:cadserv21@hotmail.please inform us.cadfamily. SVA Extraction You can add SystemVerilog Assertions (SVA) constructs to your design code to represent transactions. www. Click here for an example.com 21 The document is for study only. you can use the Open Transaction Interface (OTI) extension of the FSDB writer API to dump transaction data. The transactions can then be extracted from a signal level FSDB.we will delete . FSDB Writer API and the Open Transaction Interface (OTI) If you are unable to generate transaction data in FSDB format from any of the previously mentioned methods. AHB) directly for details on dumping FSDB format from their available intellectual property (IP). Click here for more details.Debug with Transactions Transaction IP Partners Please contact Denali (PCI-Express) or Spiratech (AMBA AXI.if tort to your rights.

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This opens the Transaction Evaluator form where all SVA assert signals are listed.com EMail:cadserv21@hotmail. 2.if tort to your rights.com 23 The document is for study only.we will delete .please inform us. Use SystemVerilog Assertions (SVA) SVA can be added to your design and then extracted to display as transactions. 3. you can extract the transactions by invoking Tools -> Transaction -> Transaction Evaluator.cadfamily. Add SVA code to your design either inlined or as a separate file.Transaction Extraction Transaction Extraction There are two primary methods of extracting transaction information from a signal level FSDB: • • Use SystemVerilog Assertions (SVA) Use nTE The SVA method can be used with proprietary protocols and the nTE method supports a variety of industry standard protocols. Load the design and FSDB file into Verdi. www. Once the design and FSDB file are loaded into Verdi. Use Model Before you can to extract transactions from SVA. Generate an FSDB file containing design data with your preferred simulator. you must do the following: 1.

com EMail:cadserv21@hotmail.if tort to your rights.please inform us. Transaction signals have an _nTX suffix appended to the assertion name. www. After you click Run. NOTE: You will need to add the transaction waveforms using nWave’s Get Signals command. you can select the assertions to be extracted and you can specify the results file name. you can display the assertions using a Table or Tree view.com 24 The document is for study only.nTX User’s Guide and Tutorial Figure: Transaction Evaluator Form In the Transaction Evaluator form. Recommended Coding Style The following coding styles are recommended for optimum transaction extraction results: • Only “assert” directive is supported.cadfamily. You can also drag any of the assertions to the nTrace source code pane to see the related code. This FSDB file will automatically be loaded into Verdi and you can start using all transaction viewing and analysis commands for debug in addition to the standard Verdi capability. SVA Code When it comes to adding SVA code to your design that will ultimately be used to extract transactions. the transactions will be extracted from the assertion code and saved to the specified file. the following sections contain a summary of recommended and unsupported coding styles.we will delete .

int localvar.we will delete .. Example 1: sequence single_read. endsequence should be modified as: sequence s1. int ws. int localvar1. . Using constructs below the sequence layer is recommended for modeling the transaction. will be recorded as attributes of transactions. logic [31-1:0] data. endsequence sequence s2.cadfamily. data = hrdata). int localvar. Refer to unsupported coding style for details.. and “ws” variables of sequence “single_read” will be recognized as the attributes of assertion statement “SINGLE_READ”. Example 2: sequence s1. ws = ws + 1) [*0:$] ##1 (hready.. .. including those declared in the sub-sequence of a specific assertion. .com EMail:cadserv21@hotmail. addr = haddr) ##1 ((!hready && hsel).please inform us.if tort to your rights.com 25 The document is for study only. www.Transaction Extraction • • • Most SVA constructs are supported. endsequence sequence s2. SVA local variables.ws = 0) ## 0 (hready) ##1 (!hready && hsel) [*0:$] ##1 ((hready && hsel && `SR_CTRL). do not declare local variables with the same name across different sequences/properties.. therefore. logic [31:0] addr. @(posedge hclk) (`true.. The local variables “addr”. endsequence SINGLE_READ: assert property(single_read). “data”.

.. If you specify the following for an assertion statement: sequence s1.. (..com 26 The document is for study only.... label_nTX = “my_s2”. For example.. Then the sub-sequence/property’s “label_nTX” variable (if one exists) would be used as its transaction label....nTX User’s Guide and Tutorial int localvar2. .if tort to your rights... endsequence a_s1 : assert property((@posedge clk) s1 ##1 s2). (... endsequence Then the transaction label name would be “my_single_read”.. the label would be either “my_s1” or “my_s2”. endsequence sequence s2.) . Three types of assertion successes will not be recognized as a transaction: • The vacuous SUCCESS of the implication will not be recognized as a transaction.. label_nTX = “my_single_read”. if you specify the following for a sequence/ property: sequence single_read.) .. and assigning a label name to it. www.. Only the “assert” directive is supported. string label_nTX..cadfamily.....com EMail:cadserv21@hotmail.. SVA “cover” and “assume” directives are not supported..) ..we will delete .. label_nTX = “my_s1”. (. endsequence • You can specify the transaction label name of a specific sequence by declaring a string type local variable named “label_nTX”.. In this case.please inform us. string label_nTX. string label_nTX. Unsupported Coding Style The following coding styles are not supported for transaction extraction: • • • • Multiple clocking is not supported Immediate assertion coding style is not supported.

please inform us.g.uFL_AMBA_SRAM. Code Example The following SVA code example: bind test assert_checker bind_transaction_evaluator( . Addr = ADDR) ##1 (RDInvalid == 1'b0) ##1 (1.DO). input [31:0] DI. (1) ## 0 (WE==1'b0 && RST==1'b0 && RDInvalid==1'b0.mem.uFL_AMBA_SRAM. “seq1[*0].ADDR (test. output [31:0] DO. input WE.ram_2kx32.uFL_AMBA_SRAM.mem.RST (test.ADDR). input CLK. Addr = ADDR.DO (test.uFL_AMBA_SRAM. .CLK). .mem.ram_2kx32. .mem.DI (test. logic [10:0] Addr.ram_2kx32.com 27 The document is for study only. Empty matches.uFL_AMBA_SRAM.uSMI.” will not be recognized as a transaction.cadfamily. Data = DI) ##1 (!(EN == 1'b1 && WE == 1'b1)). sequence core_memory_write. . Data = DO). endsequence sequence core_memory_read.DI). .CLK (test. input [10:0] ADDR. e. logic [31:0] Data.ram_2kx32.uFL_AMBA_SRAM. (1) ## 0 (EN == 1'b1 && WE == 1'b1.mem.ram_2kx32.ram_2kx32. .uFL_AMBA_SRAM.Transaction Extraction • • The abort SUCCESS of 'disable iff' will not be recognized as a transaction. input RST.mem.WE (test.com EMail:cadserv21@hotmail. input RDInvalid ).EN (test.we will delete .uFL_AMBA_SRAM.if tort to your rights. logic [31:0] Data. endsequence www.EN).RST).ram_2kx32. module assert_checker ( input EN.mem. .RDInvalid (test. logic [10:0] Addr.iXOEN_d) ).WE).

com 28 The document is for study only. endmodule will be extracted and displayed as transaction waveforms similar to the following: Figure: Extracted Transaction Waveform www.please inform us.if tort to your rights. CORE_MEM_READ : assert property(@(posedge CLK) core_memory_read).com EMail:cadserv21@hotmail.nTX User’s Guide and Tutorial CORE_MEM_WRITE : assert property(@(posedge CLK) core_memory_write).cadfamily.we will delete .

Transaction Extraction

Use nTE
nTE uses various transactors from SpiraTech to extract transactions from signal level simulation results. A source FSDB file containing signal activity, together with a bus configuration file (BCF), is loaded into the transactor using nTE. An FSDB file is produced containing a transaction hierarchy, together with the original signals. This may be viewed using nWave and the Transaction Analyzer window.

Pre-requisites
Pre-requisites include: • • The concept of models at different levels of abstraction, e.g. transactionlevel modeling. Familiarity with one of the supported bus protocols (see the relevant protocol specification), as listed below: • AMBA AHB • AMBA AHB-Lite • AMBA APB • AMBA AXI • MPEG2 Transport Stream • OCP-IP • PCI Express • UART • USB Refer to the appendices for more information on configuring nTE and interpreting the transaction hierarchy for each of the protocols. Installation of the nTE package.

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nTX User’s Guide and Tutorial

Installing nTE from the Internet
Complete the following steps to install nTE from the internet: 1. Create a directory for the software.
> mkdir <NTE_INST_DIR>

2. Change to the installation directory.
> cd <NTE_INST_DIR>

3. Connect to web http://www.novas.com. 4. Select Support-> Downloads and follow the instructions. In addition to the standard Verdi installation files, the following compressed file is available:
Novas-2006??-nte.tar.gz # nTE Package

where 2006 corresponds to the year, e.g. 2006 and ?? corresponds to the month, e.g. 04. When there is a patch release between quarterly releases, a p# will be appended to the version, e.g. 200604p1. 5. Decompress and extract the software:
> gzip -cd Novas-2006??-nte.tar.gz | tar xvf -

The following directories are created:
nte_examples adaptor_lib i686-linux-gcc-2.96 sparc-sol-gcc-2.95 Examples Transactor library files Linux binaries Solaris 2 binaries

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Transaction Extraction

Set Up the Environment
1. Specify the following environment variables:
> setenv CY_HOME "<path_to_nte_installation>" > setenv CY_PLATFORM "<platform>"

where platform is: • i686-linux for Linux (RedHat7, RedHat 9 and compatible) • sparc-sol for Solaris (Solaris 7, 8, and 9) 2. Add the nTE installation to the search path in your login script: For C (csh) shell: set path = ($CY_HOME/$CY_PLATFORM/bin $path) For Bourne (sh) and Korn (ksh) shells: PATH=$CY_HOME/$CY_PLATFORM/bin:$PATH 3. Add the Novas installation to the search path (which includes fsdbmerge) in your login script: For the C (csh) shell: set path = (<NOVAS_INST_DIR>/bin $path) For Bourne (sh) and Korn (ksh) shells: PATH=<NOVAS_INST_DIR>/bin:$PATH 4. Add the following to your LD_LIBRARY_PATH: > setenv LD_LIBRARY_PATH "$CY_HOME/$CY_PLATFORM/lib"

Use Model
To run nte, a command of the following format should be issued:
nte –input wires.fsdb –output transactions.fsdb \ –config config.bcf

Where: wires.fsdb is the output of the wire level simulation. transactions.fsdb is the desired output name (any existing file of the same name will be overwritten). • config.bcf contains a configuration to suit the transactor being used. Once the output FSDB has been generated by nte from the input FSDB and BCF configuration, the results can be viewed in nWave, which will display the original wire data and the recognized transactions. Refer to the Transaction chapter for more details. • •

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nTX User’s Guide and Tutorial

Bus Configuration File (BCF) Format
nTE makes use of the BCF (Bus Configuration File) Format for configuration. The BCF format supports C style single line (//), and multiple line (/* ... */) comments. The BCF features currently supported by nTE are defined in the following sections.

Bus Definition Block
The BCF file should contain one or more ‘bus definition blocks’, as follows.
<nte_transactor_library_name> <user_name> { }

‘nte_transactor_library_name’ selects which transactor to use, e.g. nte_UART_v2p1_ns. ‘user_name’ is a name for this bus definition block, which can consist of upper and lower case letters, numbers, and underscores (_). This name must be unique for each bus definition block within a single BCF file. Within the bus definition block nTE supports a number of statements and subblocks. For example:
nte_UART_v2p1_ns UARTtest { SIGMAP { // signal mappings... } PARAMETER { // bus parameters... } }

Multiple bus definition blocks can be used to extract transactions for multiple interfaces within the input FSDB file and combine the results into a single output FSDB file.
NOTE: nTE 1.3 or later is required to support multiple bus definition blocks.

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www. There can be any number of signal mappings within the signal mapping block.please inform us.com 33 The document is for study only. See the appendix for the protocol you are interested in for a full listing of the signals in each of the nTE transactors. Not every signal within the nTE transactor library has to be mapped. then clk_* parameters do not need to be set within the PARAMETER block. unmapped signals will simply be left with a default value.if tort to your rights.cadfamily. as follows: MAPPING_ROOT = "<root_user_signal_path>".com EMail:cadserv21@hotmail. SIGMAP { /UART/TX = "/tx". } ‘nte_transactor_signal_name’ is the name of a signal defined within the nTE transactor library that has been selected for this bus definition block. . <nte_transactor_signal_name> = "<user_signal_name>". Clock Mapping A clock can either be user-defined by setting the clk_* parameters within the PARAMETER block of the BCF file. . However. For example: nte_UART_v2p1_ns UARTtest { MAPPING_ROOT = "/tbuart/tb". For this reason a warning is written to the log file for each unmapped signal. or a clock can be mapped so that the extraction process 'learns' the characteristics of the clock on a continuous basis. ‘root_user_signal_path’ is prefixed to each of the ‘user_signal_names’ in the signal mapping block. as follows: SIGMAP { <nte_transactor_signal_name> = "<user_signal_name>".Transaction Extraction Signal Mapping Block The signal mapping block is defined within the bus definition block.we will delete . If you choose to map the clock. Mapping Root Statement The mapping root statement is defined within the bus definition block. . this can result in nTE not being able to fully interpret the protocol. ‘user_signal_name’ is the name of a signal within the FSDB file that will be used as input to nTE.

0. } = = <value>.com 34 The document is for study only. ‘nte_transactor_parameter_name’ is the name of a parameter defined within the nTE transactor library that has been selected for this bus definition block. The separator should not be included in both places. as this will result in a complete signal name like /tbuart/tb//tx which is incorrect. the root mapping does not have a separator (/) at the end of it. <value>. . For example: PARAMETER { UART_word_length = 8. } } NOTE: In this example. See the appendix for the protocol you are interested in for a full listing of what these are. as follows: PARAMETER { <nte_transactor_parameter_name> <nte_transactor_parameter_name> .nTX User’s Guide and Tutorial /UART/RX } } = "/rx".we will delete . ‘value’ is the value to be assigned to that parameter.please inform us.com EMail:cadserv21@hotmail. Any parameters that are not assigned a value will take on a default value. } There can be any number of parameter assignments within the bus parameter block.cadfamily. /UART/RX = "/tbuart/tb/rx". Bus Parameter Block The bus parameter block is defined within the bus definition block. is equivalent to nte_UART_v2p1_ns UARTtest { SIGMAP { /UART/TX = "/tbuart/tb/tx". UART_stop_bit_length = 1.if tort to your rights. . www. so it is included at the start of each of the user's signal names.

The following message indicates a wire is in adaptor but has not been connected to FSDB wire. the following messages should be displayed once nTE is invoked: nTE complete for instance (INSTANCE_NAME) of protocol (PROTOCAL_NAME) nTE moving output file nTE complete If any settings are incorrect. Failed to relate /RAM_bus/rd_data with /RAM_bus_example/st/ iRAM_I/iRAM_I/rd_data The following messages indicate the configured bus width in the adaptor does not match the bus width in the input FSDB file: NTE_ERROR: Error: Aggregate value is the wrong length '"0000000000000000"' to an 8 bit field NTE_ERROR: Invalid aggregate passed to wire RAM_bus. www.we will delete . the following warning or error messages may be displayed: nTE adaptor failed This would be followed by any of the next messages.Transaction Extraction nTE Results If all the settings are correct.if tort to your rights. Failed to connect to /RAM_bus/addr The following message indicates a wire is in BCF file but not in the adaptor.rd_data The following message indicates a parameter has been set outside the legal range: NTE_HALT: Fatal: Configured Addr bus width greater than maximum allowed.com EMail:cadserv21@hotmail.please inform us. This does not cause nTE to fail as you may not want to connect a signal.com 35 The document is for study only.cadfamily.

if tort to your rights.com EMail:cadserv21@hotmail.we will delete .nTX User’s Guide and Tutorial www.cadfamily.please inform us.com 36 The document is for study only.

please inform us. Make a copy of these demo files in your working directory: % cp -r <NOVAS_INST_DIR>/demo <working_dir> www. 2.com EMail:cadserv21@hotmail. Add the Verdi application (binary) to the search path: % set path=(<NOVAS_INST_DIR>/bin $path) NOTE: The percent ('%') character on the left-hand side of the command represents the system prompt.we will delete . Create a working directory: % mkdir <working_dir> 4. 3. you (or your system manager) must have installed Verdi (which automatically installs nTX) as described in the accompanying Novas Installation and System Administration Guide. Specify the search path to the license file: % setenv NOVAS_LICENSE_FILE <license_file> NOTE: Your license file must include an nTX feature line for this tutorial.Transaction Tutorials Transaction Tutorials The following topics are included: • • • • • Before You Begin View Transactions in nWave View Transactions in Transaction Analyzer Window Analyze Transactions Using TCL Generate an FSDB File with Transaction Information Before You Begin Before you begin the tutorials.if tort to your rights. You must also complete the following actions in order to set up the Novas environment and the files required for this tutorial: 1.cadfamily.com 37 The document is for study only. All of the tutorial data resides in the <NOVAS_INST_DIR>/demo directory.

) are available with FSDB files containing transactions. All nWave manipulation functions (zoom. for a complete introduction to nWave.cadfamily. Execute Verdi to import the FSDB file: > verdi -ssf ahb32.fsdb & The nTrace and nWave windows open and the FSDB file is loaded.com 38 The document is for study only. In nWave.bus.nTX User’s Guide and Tutorial View Transactions in nWave This tutorial will familiarize you with transaction viewing and search operations. Import FSDB File 1. Click on MyAHB_1 to show the streams under this hierarchy. NOTE: This tutorial only has an FSDB file that contains transactions and there isn’t a related design.please inform us. The transaction FSDB is loaded displaying BusTop as the top hierarchy and MyAHB_1(_AHB_) as the first hierarchical level which is for different protocols. etc. choose Signal -> Get Signals… to open the Get Signals form. 2. Add Transaction Waveforms 1. cursor.com EMail:cadserv21@hotmail. Refer to the Tutorials chapter.we will delete . Change the directory to <working_dir>/demo/nTX. % cd <working_dir>/demo/nTX 2. marker. re-size. nWave section in the Verdi User’s Guide and Tutorial document.if tort to your rights. www.

the cursor moves to the begin time of each transaction. Click Search Forward icon (blue right arrow) in toolbar to step through the transactions. then click OK. Click on the Search By: in the nWave toolbar and choose the last option. Move the mouse cursor over the attributes in the value pane to show the details in a tip. 4. you can adjust the height by dragging the small grey line in the lower left corner of the stream name in the signal pane.cadfamily. www. In nWave.com EMail:cadserv21@hotmail. 6.Displaying Streams 3. enter “BurstType” for Attribute and “incr 4” for Value. Transaction Attribute Values. Since there are more attributes than the default signal height can display. 7.com 39 The document is for study only. Select AhbTransfer and AhbTransaction. Note. In the Search Attribute Value form.we will delete . Click on the AhbTransaction stream in the signal pane to select it.Transaction Tutorials The results will be similar to the following example: Figure: Get Signals . 9. re-size the signal and value panes to more readily display the text and zoom in on the waveform pane to see the transaction details. 8.if tort to your rights. 5.please inform us. 10.

com 40 The document is for study only.please inform us. which is burst read of “incr 4” type. The child transactions are highlighted in pink.nTX User’s Guide and Tutorial The form should look similar to the following: Figure: Search Attributes 11.we will delete . There will be 4 AhbTransfer burst read command transactions and 3 busy ones as the children of the selected transaction. click-right to open the right mouse button context menu and choose Properties to open the Transaction Property form which shows all the attributes and relationships for the selected transaction. 13. Click on the transaction in the waveform pane at time 4810000ps. With the same transaction selected.if tort to your rights. Figure: Search Results with Related Transactions 14. 12. www. Click OK.com EMail:cadserv21@hotmail. Click the Search Forward/Search Backward icons on the toolbar to locate a matching transaction at 4810000ps. The cursor in the waveform will automatically move to the nearest transaction with BurstType = incr 4.cadfamily.

The FSDB file currently loaded in nWave will be the default in the Transaction Analyzer window. In the Transaction Analyzer window. Execute Verdi to import the FSDB file: > verdi -ssf ahb32. Add/Remove Transaction Streams After loading a FSDB file with transaction data. In nWave.bus. NOTE: This tutorial only has an FSDB file that contains transactions and there isn’t a related design. 1. choose Stream -> Get Stream to open the Select Stream form.we will delete .Transaction Tutorials View Transactions in Transaction Analyzer Window This tutorial will familiarize you with transaction viewing and search operations in a spreadsheet-like view. Change the directory to <working_dir>/demo/nTX.cadfamily. choose Tools -> Transaction Analyzer -> Open Transaction Analyzer Window to open the Transaction Analyzer window.if tort to your rights. % cd <working_dir>/demo/nTX 2. 2.fsdb & The nTrace and nWave windows open and the FSDB file is loaded.com 41 The document is for study only.please inform us. Import FSDB File 1. you can view and manipulate the results in the Transaction Analyzer window.com EMail:cadserv21@hotmail. www.

Double-click on AhbTransfer to automatically add the stream to the Transaction Analyzer window.cadfamily.if tort to your rights.com EMail:cadserv21@hotmail.we will delete . www.nTX User’s Guide and Tutorial The form should look similar to the following: Figure: Select Stream Form All of the transaction streams available in the FSDB file will be listed in a tree-like format.please inform us.com 42 The document is for study only. 3. The stream name changes to gray and is appended with a red dot. Left-click to select AhbTransaction and click OK to add the stream and close the form. 4.

1. in the Transaction Analyzer window.if tort to your rights. Each stream has a tab of its own. 5. 6. In the Transaction Analyzer window.cadfamily.com EMail:cadserv21@hotmail. AhbTransfer and AhbTransaction. The currently selected stream name is blue.we will delete . it does not effect the FSDB file.please inform us. Note the stream has been removed from the Transaction Analyzer window. www. Choose Stream -> Close Stream. NOTE: The Merge Stream command only merges the transaction streams for viewing purposes. When streams are merged you can search and filter all the transaction attributes simultaneously.Transaction Tutorials The Transaction Analyzer window should look similar to the following: Figure: Transaction Analyzer Window with Streams Loaded There are two streams. You can change the width of the columns by selecting the vertical line in the column header and dragging-left. You can select the stream name to see the details of the stream.com 43 The document is for study only. Left-click to select the AhbTransaction. Merge Transaction Streams You can also merge two or more streams in the Transaction Analyzer window. choose Stream -> Merge Stream to open the Merge Stream form.

After the stream is added.if tort to your rights.we will delete . 6. Left-click to select the Error stream in the Merged Stream column. Click the button to move all streams to the Merged Stream column.com 44 The document is for study only.cadfamily. its name becomes gray with a red dot in the Stream Name column and can not be selected again. 3. Click the Default button to automatically generated the merged stream name which will consist of each stream name linked with an underscore. The stream name is changed to black and is selectable again.please inform us. Left-click to select the AhbTransaction stream in the Merged Stream column. Click the UP button to move AhbTransaction above AhbTransfer. 4. Click OK. Click the button to move the selection back to the Stream Name column. 5. 8. www.nTX User’s Guide and Tutorial The form will be similar to the following: Figure: Merge Stream Form All of the transaction streams available in the FSDB file will be listed in a tree-like format in the Stream Name column.com EMail:cadserv21@hotmail. 2. 7.

Transaction Tutorials The form will be similar to the following: Figure: Merged Stream in the Transaction Analyzer Window If the different streams have transactions at the same time.cadfamily. Click-left anywhere on the row for Index 13 to set the cursor time. Choose View -> Sync Cursor Time to synchronize the cursor globally. Scroll until you can see Index 25. select the AhbTransfer stream. You can change which columns (attributes) are displayed and in what order. Manipulate the Stream View There are several ways to manipulate the streams in the Transaction Analyzer window. Click-left anywhere on the row for Index 18 to set the cursor time. The selected row is highlighted in yellow. You can also filter the transactions based on one or two attribute conditions.com 45 The document is for study only. www. 1. Set the Cursor/Marker In this example.please inform us. you’ll set the cursor/marker position in the Transaction Analyzer window and learn how to synchronize it with the other Verdi windows.com EMail:cadserv21@hotmail. both will be displayed. 2. 5. 4. If you had a design loaded and active annotation enabled. Click-middle anywhere on the row for Index 25 to set the marker time.we will delete . the cursor time would change in nTrace and nSchema as well. The selected row is highlighted in red. Note the cursor time changes in nWave as well even without waveforms being displayed. 6. 3. In the Transaction Analyzer window.if tort to your rights.

5. 4. 7.we will delete .please inform us.nTX User’s Guide and Tutorial Change the Column (Attribute) Display In this example.com 46 The document is for study only. 3. Repeat the previous steps for Response.cadfamily.if tort to your rights. Only one attribute can be selected at a time. Choose View -> Column Configuration to open the Config Bus Table form. Click the button to move it to the Hide Column section. In the Transaction Analyzer window. 1. The form will be similar to the following: Figure: Config Bus Table Form By default. select Index. Click the DOWN button multiple times until Index is at the bottom of the list. www. you’ll select some columns (attributes) to remove from the display and re-order the remaining columns. all the columns (attributes) will be listed in the Show Column section. In the Show Column section. select BurstType. 6. 2. select the AhbTransfer stream. Select Label in the Show Column section. and EndTime individually. Slave.com EMail:cadserv21@hotmail. In the Show Column section. 8.

Choose View -> Show All and all columns (attributes) are added back to the view in the original order. In the Pattern text field. enter aa9.cadfamily. 3. you will search for a text string.com EMail:cadserv21@hotmail. In the Transaction Analyzer window. 10.if tort to your rights. Search the Transactions In this example.please inform us. 1.we will delete . The Transaction Analyzer window should be updated as follows: Figure: Modified Attribute Display for AhbTransfer Stream Note four columns have been removed from the display and the remaining columns have been re-ordered. 2.com 47 The document is for study only. Click OK. 12. The Find String form should be similar to the following: www. Click the UP button multiple times until BurstType is located below Command. The Index column is now the right-most column and BurstType is next to Command. 11.Transaction Tutorials 9. Left-click on the Command column to sort by the command attribute types. Choose View -> Find to open the Find String form. select the AhbTransfer stream.

There are multiple. you will filter the transactions based on certain attributes. In the Find String form. Toggle the Column field and select Command. 3. 1. click Close on the Find String form. 2. select the AhbTransfer stream.com 48 The document is for study only. 5. The form will be similar to the following: Figure: Filter Form .com EMail:cadserv21@hotmail. Filter the Transactions In this example. 4. When you are done searching for different patterns. Continue to click the Next/Previous buttons to locate more occurrences of ‘aa9’. The first occurrence of ‘aa9’ will be highlighted in blue in the Data column of the Transaction Analyzer window.Command = single write www. 6.we will delete . Choose View -> Filter to open the Filter form.cadfamily. In the first Criteria row. click Next.if tort to your rights.nTX User’s Guide and Tutorial Figure: Find String Form 4. In the Transaction Analyzer window.please inform us. toggle the criteria to = and enter single write in the related text field.

cadfamily. 6.com EMail:cadserv21@hotmail.please inform us. In the first Criteria row. toggle the criteria to >= and enter 2 byte in the related text field. toggle the Column field and select SizePerBeat. You can sort the current results by clicking another column header or you can further reduce the display by specifying another filter or you can restore the stream and start over. 7.Transaction Tutorials 5.if tort to your rights.SizePerBeat >= 2byte www. In the Filter form (which should still be open unless you closed it). The Transaction Analyzer window will be updated to display transactions whose command attribute is of type single write. Let’s specify another filter. The form will be similar to the following: Figure: Filter Form . similar to the following: Figure: Filter Results for Command single write At this point you have several options.com 49 The document is for study only. Click Apply.we will delete .

com 50 The document is for study only.cadfamily. Click Apply. Choose Tools -> Statistic Window to open the Perform Statistical Calculation form.we will delete .nTX User’s Guide and Tutorial 8. similar to the following: Figure: Filter Results for Command single write with SizePerBeat >= 2 bytes At this point you have several options. You can sort the current results by clicking another column header or you can further reduce the display by specifying another filter or you can restore the stream and start over. you can generate a variety of statistics for the stream. In the Transaction Analyzer window.com EMail:cadserv21@hotmail. The Transaction Analyzer window will be updated to display transactions whose command attribute is of type single write and whose SizePerBeat attribute value is greater than or equal to 2 bytes. 1.if tort to your rights. select the AhbTransaction_AhbTransfer merged stream. Choose View -> Show All and transaction rows are added back to the view in the original order. Let’s restore the stream and start over. NOTE: Although this example will use the entire merged stream. 9. you can filter the stream first and then generate statistics based on the reduced display. 2. Generate Statistics In addition to viewing and manipulating the transactions in a spreadsheet-like view. www.please inform us.

Toggle the Category Column field and select BurstType.com EMail:cadserv21@hotmail.com 51 The document is for study only. www.cadfamily.we will delete . In this example you want to view the frequency of BurstType for the entire simulation range. 3.Transaction Tutorials The form will be similar to the following: Figure: Perform Statistical Calculation Form You have several options for setting up the form.please inform us. Click the Full Range button to automatically enter the from and to times.if tort to your rights. Click OK. 5. 4.

com 52 The document is for study only.com EMail:cadserv21@hotmail.nTX User’s Guide and Tutorial A Statistics Window similar to the following will open. you can easily see the frequency of the burst types. or duplicate the window.please inform us. www. 6. Figure: Bar Chart for BurstType For the stream combination.we will delete .cadfamily.if tort to your rights. In the Statistics Window. At this point. You can also change the view to a pie chart or table. choose View -> Pie Chart. you can capture the results in PNG format.

we will delete . Choose File -> Close to close the Statistics Window. 8. Choose File -> Exit in nTrace to close the Verdi session.Transaction Tutorials The window will be updated similar to the following.please inform us.cadfamily. www.com 53 The document is for study only. Figure: Bar Chart for BurstType 7.com EMail:cadserv21@hotmail. You can generate more statistics for different attribute types.if tort to your rights.

. 1. % cd <working_dir>/demo/nTX 2.cadfamily. The FSDB used contains transactions of the AMBA AHB interface.tcl & The nTrace window opens with a new menu item.com EMail:cadserv21@hotmail. query. To launch the TA Example window as shown below.we will delete .please inform us. Figure: TA Example Window This menu item was added as a result of the following code in the TCL file: # Append a Verdi menu item eMenuAppendItem -win $_nTrace1 -menuName Tools -itemName "Launch TA Example. Execute the TCL File The TCL script ta_ex. Both files can be found in the <working_dir>/demo/nTX directory. and statistic TCL commands in a TK program that can be launched from Verdi." -tclCmd createMainWin -shortKey Y AddEventCallback [tk appname] cursorTimeChangedCB taCursorTimeChange 0 AddEventCallback [tk appname] markerTimeChangedCB taMarkerTimeChange 0 AddEventCallback [tk appname] tableRowSelectedCB stsTableRowSelected 0 www..if tort to your rights. Change the directory to <working_dir>/demo/nTX.nTX User’s Guide and Tutorial Analyze Transactions Using TCL This tutorial demonstrates the usage of transaction manipulation.com 54 The document is for study only. choose Tools -> Launch TA Example in nTrace. 3. Execute Verdi to play the TCL file and load the FSDB file: > verdi -play ta_ex.tcl operates on a transactional FSDB.

The Transaction Analyzer window opens with the ahb32.bus.cadfamily.com EMail:cadserv21@hotmail. Choose CommandTest -> Load a Stream. the values will automatically be updated in the ahbStat window. In the Transaction Analyzer window.we will delete . In the TA Example window. In the TA Example window. choose CommandTest -> Load File. 4.if tort to your rights. The AhbTransaction stream is added to the Transaction Analyzer window. 1. similar to the following example: Figure: ahbStat Window Note if you change the cursor or marker position in the Transaction Analyzer window. choose Statistics -> AHB Statistics.com 55 The document is for study only. 2. click-left on 7 in the Index column to set the cursor and click-middle on 23 to set the marker.fsdb file loaded. This opens the ahbStat window. Manipulate Transactions and View Statistics with TCL The transaction manipulation commands can be executed from the CommandTest menu of the TA Example window. www.please inform us. An information window is displayed when these commands are executed.Transaction Tutorials AddEventCallback [tk appname] tableRowUnselectedCB stsTableRowUnselected 0 The Command 1-3 buttons are reserved for user-defined commands. Load File and Load a Stream should be executed before executing other commands. 3.

In the ahbStat window. 7.we will delete . click the Command Frequency (Bar Graph) or Burst Type Frequency (Pie Chart) buttons to display the frequency of AHB commands or burst type for the transactions within the current cursor/ marker time.com 56 The document is for study only.com EMail:cadserv21@hotmail.please inform us. www. read bytes and write bytes. click the Update button to update the number of transactions. In the ahbStat window.if tort to your rights.cadfamily. Change the cursor or marker positions in the Transaction Analyzer window to select the first and last transaction and then click Update in the ahbStat window. The results will be similar to the following: Figure: AHB Transaction Statistics 6.nTX User’s Guide and Tutorial 5.

if tort to your rights.we will delete .com 57 The document is for study only. Note the statistic results are calculated based on the transactions within the cursor and marker time. click the orange bar for SingleWrite.com EMail:cadserv21@hotmail.cadfamily. In the Statistics Window for the Command Frequency.Transaction Tutorials The results will be similar to the following: Figure: Bar Graph and Pie Chart The TCL script includes sample code for highlighting the related transactions for certain statistic items. in the Command Frequency bar graph window. similar to the following: Figure: Highlighted Transactions www. For example.please inform us. 8. you can click on bars to see their related transactions in the Transaction Analyzer window. The corresponding transactions will be highlighted in the Transaction Analyzer window.

file -tearoff 0 $w...we will delete .menuBar add cascade -menu $w.nTX User’s Guide and Tutorial Example TCL Script #!/bin/sh # the next line restarts using wish \ exec wish "$0" "$@" # Global variables set cursorTime 0 set markerTime 0 set cursorIdx 0 set markerIdx 0 set numTrans 0 set numRByte 0 set numWByte 0 # Statistics table set cmdTbl 0 # Related transaction list (command frequency) set trListSR {} set trListSW {} set trListBR {} set trListBW {} proc createMainWin {} { global cursorTime set w .menuBar..menuBar add cascade -menu $w.please inform us..cmdTest add command -label "Load a Stream" -command "taAddStream -stream MyAHB_1/AhbTransaction" -underline 0 $w.menuBar.template catch {destroy $w} toplevel $w wm title $w "TA Example" # TA example menu bar menu $w.menuBar add cascade -menu $w.menuBar.staTest -label "Statistics" -underline 0 # File menu menu $w.bus.cmdTest -tearoff 0 $w.cmdTest add command -label "Config Columns" -command "taConfigureColumn {Idx BeginTime EndTime Command StartAddress Master Slave}" -underline 0 www.cmdTest -label "CommmandTest" -underline 0 $w.menuBar # Command Test menu menu $w.if tort to your rights.menuBar.file add command -label "nWave.cadfamily.menuBar -tearoff 0 $w.file -label "File" underline 0 $w.file add command -label "Quit" -command "debExit" underline 0 $w configure -menu $w.fsdb" -underline 0 $w.menuBar.menuBar.menuBar.menuBar.file add command -label "TransactionAnalyzer.menuBar." -command "createWV" -underline 0 $w.menuBar.cmdTest add command -label "Load File" -command "loadFile ahb32.com 58 The document is for study only.com EMail:cadserv21@hotmail.menuBar." command "createTA" -underline 0 $w.

cursorName -side left pack $w.debFrame.cmdTest add command -label "Sort by address" -command "taSort -orderBy StartAddress" -underline 0 $w.cadfamily.cursorTime.cmdTest add command -label "Set Radix of \"StartAddress\" to Decimal" -command "taSetRadix -column StartAddress -format Dec" -underline 0 $w.debFrame.debFrame.cmdTest add command -label "Jump To Marker" -command "taJumpToMarker" -underline 0 $w.cursorTime.menuBar.cmd3 -text "Command 3" -command {onCommand Command3} pack pack pack pack pack } $w.menuBar.cursorTime label $w.cursorVal button $w.cmd3 -fill $w.staTest -tearoff 0 $w.debFrame.staTest add command -label "AHB Statistics" -command "showAhbStat" -underline 0 # Frame for Verdi commands frame $w.debFrame.menuBar.cmdTest add command -label "Set Marker to 14110000" command "taSetMarker -time 14110000" -underline 0 $w.cmd2 -text "Command 2" -command {onCommand Command2} button $w.menuBar.cmd1 -fill $w.Transaction Tutorials $w.menuBar.debFrame.cmd2 -fill $w.com 59 The document is for study only.cursorVal -width 20 -relief sunken -anchor w -textvar cursorTime pack $w.cursorTime.debFrame.cursorTime.cursorTime $w.menuBar.debFrame.com EMail:cadserv21@hotmail.menuBar.menuBar.debFrame -borderwidth 10 frame $w.menuBar.menuBar.cmdTest add command -label "Set Cursor to 760000" command "taSetCursor -time 760000" -underline 0 $w.cmdTest add command -label "Close File" -command "taCloseFile" -underline 0 # Statistics menu menu $w.please inform us.debFrame.cmdTest add command -label "Delete Stream" -command "taDeleteStream -stream MyAHB_1/AhbTransaction" -underline 0 $w.menuBar.cmdTest add command -label "Find Text (incr)" command "taFind incr" -underline 0 $w.debFrame -fill both -fill x x -pady x -pady x -pady -pady 2 2 2 2 # Create transaction analyzer window proc createTA {} { set ta_win [taCreateWindow] } www.menuBar.cmdTest add command -label "Filter to Single Read" command "taFilter {Command = single read}" -underline 0 $w.cmdTest add command -label "Show All Transactions" command "taShowAll -stream MyAHB_1/AhbTransaction" -underline 0 $w.we will delete .cursorName -text "Cursor Time: " label $w.menuBar.debFrame.debFrame.cmdTest add command -label "Jump To Cursor" -command "taJumpToCursor" -underline 0 $w.debFrame.menuBar.cmdTest add command -label "Set 100th Transaction as Active" -command "taSetActiveTransaction -trans 100" -underline 0 $w.if tort to your rights.cmd1 -text "Command 1" -command {onCommand Command1} button $w.

nTX User’s Guide and Tutorial # Create waveform window proc createWV {} { set wv_win [wvCreateWindow] } proc onCommand btn { tk_dialog .buttons.ahbStat] { toplevel .if tort to your rights.buttons -side bottom -fill x button .buttons pack ." info 0 OK } # Cursor Time change callback proc cursorTimeChangedCB args { global cursorTime set cursorTime [lindex $args [expr [lsearch $args "-time"]+ 1]] } # Marker Time change callback proc markerTimeChangedCB args { global markerTime set markerTime [lindex $args [expr [lsearch $args "-time"]+ 1]] } # Table row selected callback proc tableRowSelectedCB args { global cmdTbl global trListSR trListSW trListBR trListBW set tbl [lindex $args [expr [lsearch $args "-table"] + 1]] if {$tbl == $cmdTbl} { switch [lindex $args [expr [lsearch $args "-rowIdx"] + 1]] { 0 {taHighlightTransactions -transList $trListSR -color cyan} 1 {taHighlightTransactions -transList $trListSW -color cyan} 2 {taHighlightTransactions -transList $trListBR -color cyan} 3 {taHighlightTransactions -transList $trListBW -color cyan} } } } # Marker Time change callback proc tableRowUnselectedCB args { taClearAllHighlightTransactions } # Load a file proc loadFile args { if {[taGetCurrentWindow] == "0"} { taCreateWindow } taOpenFile -file $args } # AHB statistic dialog proc showAhbStat {} { global cursorTime markerTime if ![winfo exists .ahbStat.ahbStat.cadfamily.we will delete .ahbStat -border 5 frame .com EMail:cadserv21@hotmail.com 60 The document is for study only.update -text "Update" \ -default active -command "updateAHBStat" www.ahbStat.dialog1 "Info" "Button $btn pressed.please inform us.

name config -text "Marker time:" .name config -text "Number of write bytes:" .cadfamily.value .info.info.buttons.please inform us. } www.ahbStat.name config -text "Number of read bytes:" .value .cmdChart -text "Command Frequency (Bar Graph)" -command "showCmdChart" pack .info.name label .ahbStat.ahbStat" pack .value -side right } .$i.ahbStat.ahbStat.info.info.cmdChart -side bottom -fill x -pady 2 } } # Display bar chart of AHB command distribution proc showCmdChart {} { global cursorTime markerTime cmdTbl global trListSR trListSW trListBR trListBW set set set set set set set set trListSR trListSW trListBR trListBW cntSR cntSW cntBR cntBW {} {} {} {} 0 0 0 0 if {[checkAhbStream] == 0} { return 0.f5.f4.if tort to your rights.ahbStat.buttons.info.com EMail:cadserv21@hotmail.btChart -text "Burst Type Frequency (Pie Chart)" -command "showBurstChart" pack .info -expand yes -fill both -padx 1 -pady 2 foreach i {f1 f2 f3 f4 f5} { frame .ahbStat.value config config config config config -anchor -anchor -anchor -anchor -anchor w w w w w -textvar -textvar -textvar -textvar -textvar cursorTime markerTime numTrans numRByte numWByte # Charts button .ahbStat.btChart -side bottom -fill x button .we will delete .info.$i -bd 2 pack .info.ahbStat.value -relief sunken -width 40 pack .$i.ahbStat.close -text Close \ -default active -command "destroy .ahbStat.info.value .ahbStat.info.info.ahbStat.f1.ahbStat.ahbStat.f1.ahbStat.ahbStat.ahbStat.f2.info.ahbStat.ahbStat.$i.info.$i -side top -fill x -pady 2 label .info.ahbStat.name config -text "Number of transactions:" .info.info.f4.update -side left -expand 1 -pady 2 button .info.ahbStat.Transaction Tutorials pack .info pack .name -side left pack .buttons.ahbStat.ahbStat.ahbStat.f2.name config -text "Cursor time:" .close -side left -expand 1 -pady 2 frame .value .f5.info.f3. } set transList [taGetTransactionList -time $cursorTime $markerTime] if {$transList == {0}} { return 0.info.com 61 The document is for study only.$i.ahbStat.f3.info.

please inform us.} "single write" {incr cntSW.com 62 The document is for study only.cadfamily. } set transList [taGetTransactionList -time $cursorTime $markerTime] if {$transList == {0}} { return 0.com EMail:cadserv21@hotmail. lappend trListBW $idx.nTX User’s Guide and Tutorial foreach idx $transList { set cmd [lindex [taGetAttributeValue -trans $idx -attr "Command"] 1] switch $cmd { "single read" {incr cntSR.we will delete . lappend trListSW $idx.} } } set cmdTbl [taCreateTable -name "Command Frequency" -cols {Command Count}] taAddRow -table $cmdTbl -valueList "SingleRead $cntSR" taAddRow -table $cmdTbl -valueList "SingleWrite $cntSW" taAddRow -table $cmdTbl -valueList "BurstRead $cntBR" taAddRow -table $cmdTbl -valueList "BurstWrite $cntBW" taCreateView -view BarGraph -table $cmdTbl } # Display pie chart of AHB burst type distribution proc showBurstChart {} { global cursorTime markerTime set cntSingle 0 set cntIncr 0 set cntWrap4 0 set cntIncr4 0 set cntWrap8 0 set cntIncr8 0 set cntWrap16 0 set cntIncr16 0 if {[checkAhbStream] == 0} { return 0. } foreach idx $transList { set bt [lindex [taGetAttributeValue -trans $idx -attr "BurstType"] 1] switch $bt { "single" {incr cntSingle} "incr" {incr cntIncr} "wrap 4" {incr cntWrap4} "incr 4" {incr cntIncr4} "wrap 8" {incr cntWrap8} "incr 8" {incr cntIncr8} "wrap 16" {incr cntWrap16} "incr 16" {incr cntIncr4} } } set btTbl [taCreateTable -name "Burst Type Fequency" -cols {Command Count}] taAddRow -table $btTbl -valueList "SINGLE $cntSingle" taAddRow -table $btTbl -valueList "INCR $cntIncr" taAddRow -table $btTbl -valueList "WRAP4 $cntWrap4" taAddRow -table $btTbl -valueList "INCR4 $cntIncr4" taAddRow -table $btTbl -valueList "WRAP8 $cntWrap8" www.} "burst write" {incr cntBW. lappend trListSR $idx.if tort to your rights. lappend trListBR $idx.} "burst read" {incr cntBR.

} elseif {[string match *write $cmd]} { set numWByte [expr $numWByte + $byteCnt].if tort to your rights..Transaction Tutorials taAddRow -table $btTbl -valueList "INCR8 $cntIncr8" taAddRow -table $btTbl -valueList "WRAP16 $cntWrap16" taAddRow -table $btTbl -valueList "INCR16 $cntIncr16" taCreateView -view PieChart -table $btTbl } # Update AHB statistics proc updateAHBStat {} { global cursorTime markerTime numTrans numRByte numWByte if {[checkAhbStream] == 0} { return 0.. } } } # Check if AHB transaction is loaded. } set transList [taGetTransactionList -time $cursorTime $markerTime] if {$transList == {0}} { return 0." -tclCmd createMainWin -shortKey Y AddEventCallback [tk appname] cursorTimeChangedCB taCursorTimeChange 0 AddEventCallback [tk appname] markerTimeChangedCB taMarkerTimeChange 0 AddEventCallback [tk appname] tableRowSelectedCB stsTableRowSelected 0 AddEventCallback [tk appname] tableRowUnselectedCB stsTableRowUnselected 0 www.please inform us. } # Update numTrans set numTrans [llength $transList] # Update numRByte and numWByte set numRByte 0 set numWByte 0 foreach idx $transList { set cmd [lindex [taGetAttributeValue -trans $idx -attr "Command"] 1] set beatCnt [lindex [taGetAttributeValue -trans $idx -attr "BeatCount"] 1] set sizePerBeat [lindex [taGetAttributeValue -trans $idx attr "SizePerBeat"] 1] set byteCnt [expr [lindex $sizePerBeat 0] * [lindex $beatCnt 1]] if {[string match *read $cmd]} { set numRByte [expr $numRByte + $byteCnt]. proc checkAhbStream {} { if {[taSelectStream -stream MyAHB_1/AhbTransaction] == 0} { tk_dialog .com EMail:cadserv21@hotmail.cadfamily.we will delete . } return 1.dialog1 "Warning" "AHB stream not loaded!" info 0 OK return 0. } # Append a Verdi menu item eMenuAppendItem -win $_nTrace1 -menuName Tools -itemName "Launch TA Example.com 63 The document is for study only.

www.cadfamily.c to associate the C function with the simulator system task. If you are already familiar with this type of information.org. 1. If you are already familiar with this procedure. you can skip to the next section. you can skip to the last section for the example.com 64 The document is for study only. PLI Background The following summarizes the typical process for adding new PLI functions to your simulator environment.opencores. 2. Write C functions that have PLI routines (see following section for details).we will delete .com EMail:cadserv21@hotmail.please inform us.if tort to your rights.nTX User’s Guide and Tutorial Generate an FSDB File with Transaction Information A "simple" simulation-time transaction recognizer for the PCI bus protocol has been created using an open source code design called “PCI Bridge IP Core” from www. Use the veriuser. The following new tasks are provided to dump transactions along with normal HDL signals to a single FSDB file during simulation: $fsdb_tr_file $fsdb_tr_stream $fsdb_tr_attribute $fsdb_tr_begin $fsdb_tr_data $fsdb_tr_abort $fsdb_tr_end $fsdb_tr_close This section includes the following topics: • PLI Background • Procedures for Writing a PLI Routine • Steps for Writing FSDB • Steps to Dump Transactions to FSDB • C Files for FSDB Writer API • Use Provided C Files for PCI Transaction Dumping The first several sections provide background detail for creating PLI routines and using the FSDB writer API.

so in UNIX). int my_calltf().h> 2. extern int plimisc_tr_scope(). as explained in the next step. if the functions are in separate files. 4.c and C functions dynamically to generate shared lib (*. Specify the function prototype and variable declaration.com EMail:cadserv21@hotmail. 1. such as. extern int plicompile_tr_stream().if tort to your rights. Procedures for Writing a PLI Routine The following summarizes the typical process for writing a new PLI routine (corresponds to #1 above). when the simulator encounters the user defined system tasks (those starting with $). extern int plimisc_tr_file(). the execution control is passed to the PLI routine (C/C++ function).please inform us. (This is called linking. extern int plitask_tr_scope(). During execution of the Verilog code by the simulator. run the simulator like any normal Verilog simulation. pass the C/C++ function details to the simulator during the compile process of Verilog code. extern int plitask_tr_file().c containing the main PLI/C program must have the following lines: #include <veriuser. Compile veriuser. If you are already familiar with this procedure.DLL in Windows and *. it will be as shown below. www. extern int plitask_tr_stream(). Include the header files. NCSIM also allows dynamic linking.cadfamily. This part of the program contains all the local variables and the functions that it invokes as part of the system call. In the present case. my_checktf(). Some simulators. you can skip to the next section. However. extern int plicompile_tr_file(). You should refer to the simulator user guide to understand how this is done.we will delete .com 65 The document is for study only.) 5. The file veriuser. 6. they should be declared as external functions. extern int plicompile_tr_scope().h> #include <vxl_veriuser.Transaction Tutorials 3. Once linked. Based on the simulator.

/* sizetf routine */ plitask_tr_file.nTX User’s Guide and Tutorial extern int plimisc_tr_stream(). extern int plimisc_tr_close(). These are the variables through which the simulator communicates with the C code. /* misctf routine */ www. extern int plitask_tr_data().if tort to your rights.cadfamily. extern int plitask_tr_attribute(). extern int plitask_tr_abort(). extern int plicompile_tr_abort().com EMail:cadserv21@hotmail. extern int plicompile_tr_attribute(). /* type of PLI routine */ 0. static s_tfcell deb_veriusertfs[] = #else s_tfcell veriusertfs[] = #endif { { usertask. extern int plitask_tr_end().com 66 The document is for study only. /* checktf routine */ 0. Create the essential data structure. extern int plicompile_tr_data(). The simulator looks at this table and figures out which properties the system call corresponding to this PLI routine would be associated with. extern int plitask_tr_close(). 3. There are a number of data structures that must be defined in a PLI program. extern int plimisc_tr_data(). /* calltf routine */ plimisc_tr_file. extern int plimisc_tr_end(). extern int plimisc_tr_abort(). extern int plimisc_tr_begin(). extern int plimisc_tr_attribute().please inform us. extern int plitask_tr_begin(). Veriusertfs[]: the main interaction between the C code that one writes and the Verilog simulator is done through a table. extern int plicompile_tr_begin(). /* user_data value */ plicompile_tr_file. extern int plicompile_tr_end(). extern int plicompile_tr_close().we will delete .

{ usertask. "$fsdb_tr_attribute". 1 }. plimisc_tr_scope.if tort to your rights. 0. plitask_tr_stream.please inform us. 0. plitask_tr_attribute.we will delete .Transaction Tutorials "$fsdb_tr_file". 0. plicompile_tr_scope. plicompile_tr_stream. plitask_tr_scope. 1 }. { usertask. "$fsdb_tr_stream". 0. 0. { usertask. plimisc_tr_stream. { usertask. plitask_tr_begin. { usertask.com EMail:cadserv21@hotmail. 0. 0. "$fsdb_tr_scope". 1 }.com 67 The document is for study only. plicompile_tr_begin. 0. plimisc_tr_attribute.cadfamily. /* system task/function name www. plicompile_tr_data. */ 1/* forward reference = true */ }. plimisc_tr_begin. 0. 0. "$fsdb_tr_begin". plicompile_tr_attribute. 1 }.

nTX User’s Guide and Tutorial plitask_tr_data, plimisc_tr_data, "$fsdb_tr_data", 1 }, { usertask, 0, plicompile_tr_abort, 0, plitask_tr_abort, plimisc_tr_abort, "$fsdb_tr_abort", 1 }, { usertask, 0, plicompile_tr_end, 0, plitask_tr_end, plimisc_tr_end, "$fsdb_tr_end", 1 }, { usertask, 0, plicompile_tr_close, 0, plitask_tr_close, plimisc_tr_close, "$fsdb_tr_close", 1 }, {0} /*** final entry must be 0 ***/ };

4. Include the appropriate tf routines. a. checktf routine • Optional. • Simulator checks the routine once right before simulation. b. calltf routine • Perform the task or function. c. sizetf • Returns the size.

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Transaction Tutorials

• Has to be a userfunction or userRealfunction routine. • Default returns 32-bit values. d. misctf • Routine called depending upon reasons e.g. reason_endofcompile, reason_paramvc, etc.

Steps for Writing FSDB
The following summarizes the typical process for writing an FSDB file. If you are already familiar with this procedure, you can skip to the next section. 1. Open an FSDB. An FSDB is opened by the ffw_Open API, which asks the application to give the file name and file type. The file type tells the source of the information, and is defined as fsdbFileType in fsdbShr.h header file. Once the file is opened successfully, the application can get a pointer to the FSDB writer object, which is a must parameter for most FSDB Writer APIs. 2. Set scale unit and other information. If the simulation does have a scale unit, then the application must set it. If it does not, then the default value is 1ns. Other information such as simulation date and simulator version are optional and for reference only. 3. Choose the tree creation scheme. The tree creation scheme is chosen by calling the ffw_CreateTreeByIdcodeScheme or ffw_CreateTreeByHandleScheme APIs. The default is idcode scheme if nothing is called. 4. Initialize data type creation (if necessary). If there is user defined data type, then the application must call the data type creation API to notify the FSDB writer, so that it can initialize the necessary data structures to store the data type definition. This can be done by calling the ffw_GetDataTypeCreationReady API. For most cases, there aren’t user defined data types; therefore, by default, the FSDB writer assumes there are no user defined data types. 5. Create the design hierarchy. The design hierarchy is composed by calling tree creation APIs. The ffw_BeginTree API creates a top scope, which has no name. The ffw_CreateScope API creates a scope, which is a child of “the current scope,” and then moves “the current scope” down to the newly created one. The ffw_CreateUpscope moves “the current scope” up to its parent scope.

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nTX User’s Guide and Tutorial

The ffw_CreateVarByIdcode or ffw_CreateVarByHandle APIs create a variable, which belongs to “the current scope.” The ffw_EndTree API completes the design hierarchy. Note that an FSDB file may contain none, one, or multiple design hierarchies. 6. Create the value changes. Conceptually, a value change is composed of a pair: a time and a value. The time is created by calling ffw_CreateXCoorByHnL, while the value is created by calling the ffw_CreateVarValueByIdcode or ffw_CreateVarValueByHandle APIs. 7. Close the FSDB. An FSDB is closed by calling the ffw_Close API, which flushes the necessary in-core data and temporary files to the FSDB file. Then it performs some clean up tasks and completes the FSDB file.

Steps to Dump Transactions to FSDB
The following summarizes the typical process for dumping transactions to an FSDB file. If you are already familiar with this procedure, you can skip to the next section. 1. Create transaction file name in the FSDB file using $fsdb_tr_file. Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_file} {"FILE_ID"} (in Verilog code) $fsdb_tr_file("FILE_ID"); Example:
ncsim> call {$fsdb_tr_file} {"pci_tr.fsdb"}

2. Create a transaction stream name in the FSDB file using $fsdb_tr_stream. Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_stream} {"STREAM_ID"} (in Verilog code) $fsdb_tr_stream("STREAM_ID"); Examples:
ncsim> ncsim> ncsim> ncsim> call call call call {$fsdb_tr_stream} {$fsdb_tr_stream} {$fsdb_tr_stream} {$fsdb_tr_stream} {"CON_RD"} {"CON_WR"} {"IO_RD"} {"IO_WR"}

3. Create a transaction attribute name in the FSDB file using $fsdb_tr_attribute.

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Transaction Tutorials

Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_attribute} {"ATTRIBUTE_ID"} (in Verilog code) $fsdb_tr_attribute("ATTRIBUTE_ID"); Examples:
ncsim> call {$fsdb_tr_attribute} {"addr"} ncsim> call {$fsdb_tr_attribute} {"data"}

4. Create a transaction hierarchical scope name in the FSDB file using $fsdb_tr_scope. Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_scope} {"Top.level1.leve2.level3...."} (in Verilog) code $fsdb_tr_scope("Top.level1.level2.level3....."); Example:
ncsim> call {$fsdb_tr_scope} {"SYSTEM.monitor32"}

5. Begin a transaction in the FSDB file (for this PCI transaction address phase) using $fsdb_tr_begin. Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_begin} {"TRANS_ID",address_attribute} (in Verilog code) $fsdb_tr_begin("TRANS_ID", address_attribute); Example:
$fsdb_tr_begin("IO_READ",ad_prev[PCI_BUS_DATA_RANGE:0]);

6. Begin a data transaction in the FSDB file (for this PCI transaction data phase) using $fsdb_tr_data. Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_data} {data_attribute} (in Verilog code) $fsdb_tr_data(data_attribute); Example:
$fsdb_tr_data("PCI_DATA",pci_ext_ad[PCI_BUS_DATA_RANGE:0]);

7. Abort any previous transaction in the FSDB file (for this PCI transaction abort phase) using $fsdb_tr_abort. Syntax: (in ncsim.rc) ncsim> call {$fsdb_tr_abort}

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rc) ncsim> call {$fsdb_tr_end} (in Verilog code) $fsdb_tr_end. 8.c fsdb_tr_end.cadfamily. These are provided in the <NOVAS_INST_DIR>/share/PLI/nTX_ex directory.c Abort transaction. Close a transaction in the FSDB file using $fsdb_tr_close.we will delete .com 72 The document is for study only. C Files for FSDB Writer API The following table summarizes the C files that were created for the corresponding FSDB writer API.com EMail:cadserv21@hotmail. C File Name Function fsdb_tr_abort.c Begin address transaction and create value change. Close the FSDB file. Example: $fsdb_tr_end. End transaction. End any transaction in the FSDB file (for this PCI transaction end phase) using $fsdb_tr_end. fsdb_tr_begin.nTX User’s Guide and Tutorial (in Verilog code) $fsdb_tr_abort. Create transaction file name www. Syntax: (in ncsim. 9. Example: $fsdb_tr_abort. fsdb_tr_attribute. Syntax: (in ncsim.c fsdb_tr_close.if tort to your rights.rc) ncsim> call {$fsdb_tr_close} (in Verilog code) $fsdb_tr_close. Begin data transaction and create value change.c Create transaction attribute name. Example: $fsdb_tr_close.please inform us.c fsdb_tr_file.c fsdb_tr_data.

Generate the libpli. % mkdir <working_dir> 2. 3.opencores. please modify the make file appropriately.so and pli. The new system tasks have been inserted into a new version of the module pci_bus_monitor (<install>/bench/verilog/pci_bus_monitor.v. Create a working directory.org/pdownloads. Run ncvlog.cgi/list/pci?no_loop=yes You should select All. www. Use Provided C Files for PCI Transaction Dumping The following steps summarize how to use the provided C files to dump the open source “PCI Bridge IP Core” transactions to the FSDB file. Create transaction stream name in FSDB. % cd <working_dir>/pci/nTX_ex/link % make 2. ncelab and ncsim on the PCI design with FSDB dumping.orig % cp <NOVAS_INST_DIR>/share/PLI/nTX_ex/bench/verilog/ pci_bus_monitor.we will delete . If you use a different simulator. 4. Download the design and related documentation from the following link: http://www.v pci_bus_monitor.a for PLI linking. pci should be the main directory with several sub-directories. 5. The C files that are provided by Novas can be found in the <NOVAS_INST_DIR>/share/PLI/nTX_ex/link directory. % cd <working_dir>/pci/bench/verilog % mv pci_bus_monitor.Transaction Tutorials fsdb_tr_scope.v .cadfamily.com 73 The document is for study only. Copy these files locally.v file).com EMail:cadserv21@hotmail. The file included in the download package need to be replaced with this new version.c fsdb_tr_stream. The following steps are based on the NCSIM simulator.please inform us. Now everything should be set up to run the example and generate an FSDB file with transaction information. 1.if tort to your rights.c Get transaction hierarchical scope name from user to create the FSDB signal tree. Unzip and untar the downloaded file and install in your working directory. % cd <working_dir>/pci % cp <NOVAS_INST_DIR>/share/PLI/nTX_ex/link . 1.

we will delete .nTX User’s Guide and Tutorial % cd <working_dir>/pci/sim/rtl_sim/run % make Once the FSDB file is created.cadfamily.if tort to your rights.please inform us.com EMail:cadserv21@hotmail. view and manipulate the transactions. you can use the steps in the previous tutorial to load.com 74 The document is for study only. www.

nte_AMBA_AHB_v2p8_2x16_32_ns MyAHB_1 { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.com EMail:cadserv21@hotmail. IDLE and BUSY transfer types. www.Appendix A: AMBA AHB Transactor Appendix A: AMBA AHB Transactor Overview The AMBA-AHB Transactor supports the following features: • • • • Data bus width from 8-bits to 1024-bits.please inform us.we will delete . BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description. Name The bus declaration (nte_AMBA_AHB_v2p8_2x16_32_ns) must be one of the supported transactors.if tort to your rights.cadfamily. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements. Split transactions.com 75 The document is for study only. Sequential and non-sequential single transfers. MAPPING_ROOT = "/AHB_2x2_system/test_AHB".

/ahb_core/HLOCK[1] ="/V_AHB_core/HLOCK[1]". /ahb_core/HGRANT[1] ="/V_AHB_core/HGRANT[1]". /ahb_core/HRESP ="/V_AHB_core/HRESP".com EMail:cadserv21@hotmail. however. control and // write data MUX) // all of these are inputs to each slave /ahb_core/HTRANS ="/V_AHB_core/HTRANS". /ahb_core/HBURST ="/V_AHB_core/HBURST". /ahb_core/HMASTER ="/V_AHB_core/HMASTER".nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side. // signals from slave MUX (read data and response) // all of these are inputs to each master /ahb_core/HREADY ="/V_AHB_core/HREADY". /ahb_core/HSPLIT_1[0] ="/V_AHB_or_gate_S[1]/HSPLIT[0]". /ahb_core/HSPLIT_1[1] ="/V_AHB_or_gate_S[1]/HSPLIT[1]". /ahb_core/HSPLIT_0[1] ="/V_AHB_or_gate_S[0]/HSPLIT[1]". /ahb_core/HADDR ="/V_AHB_core/HADDR". // signals from each slave /ahb_core/HSPLIT_0[0] ="/V_AHB_or_gate_S[0]/HSPLIT[0]".please inform us. If this is done they will be assigned a default value (normally 0). // signals from each master /ahb_core/HBUSREQ[0] ="/V_AHB_core/HBUSREQ[0]". SIGMAP { // signals from master MUX (address. /ahb_core/HWRITE ="/V_AHB_core/HWRITE". The SIGMAP code example is for an unmapped clock.cadfamily. /ahb_core/HLOCK[0] ="/V_AHB_core/HLOCK[0]". /ahb_core/HPROT ="/V_AHB_core/HPROT".if tort to your rights. } Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file: www. NOTE: Clock can be mapped to /ahb_core/HCLK. For example you can leave the HSPLIT signal unconnected for slaves that do not support the split feature. /ahb_core/HBUSREQ[1] ="/V_AHB_core/HBUSREQ[1]". /ahb_core/HSIZE ="/V_AHB_core/HSIZE". /ahb_core/HWDATA ="/V_AHB_core/HWDATA". it is possible to leave signals unconnected by removing them from the sigmap section.we will delete . /ahb_core/HRDATA ="/V_AHB_core/HRDATA".com 76 The document is for study only. The transactor signals are pre-defined as shown in the file below and must not be changed. // signals from arbiter /ahb_core/HGRANT[0] ="/V_AHB_core/HGRANT[0]". /ahb_core/HMASTLOCK ="/V_AHB_core/HMASTLOCK".

• allow_no_bus_transfers: Recognize AHB_no_bus_transfer transactions when set to the default state of true. An example is shown below: • • • Figure: Clock Setup // parameters PARAMETER { clk_init_value = 0. //ns warn_after_n_ready_low_cycles = 100. } NOTE: PARAMETER code example is for an unmapped clock. allow_no_bus_transfers = true. clk_phase_shift: The time of the first transition from the initial value. • hold_time: The hold time for all AHB signals. //ns clk_1st_time = 5 ns.Appendix A: AMBA AHB Transactor clk_init_value: The initial value of the clock (0 or 1). where ‘n’ is equal to the number set for the parameter.we will delete . clk_1st_time: The relative time of the first clock change after the initial phase shift change. //ns hold_time = 1 ns.if tort to your rights. //ns setup_time = 2 ns.please inform us. //initial value of clock clk_phase_shift = 0 ns. The clock set up is important for the correct operation of the transactor. • setup_time: The setup time for all AHB signals.com EMail:cadserv21@hotmail. //ns clk_2nd_time = 5 ns.com 77 The document is for study only. If the clock is mapped then clk_* parameters do not need to be set. www. • warn_after_n_ready_low_cycles: A warning will be issued when the ready signal from selected slave has remained low for ‘n’ clock cycles after it was selected. • clk_2nd_time: The relative time of second clock change after the previous change.cadfamily.

if tort to your rights. ‘64’. In this section the function. Transaction Hierarchy The transactor consists of a number of transactions that enable communication at different levels of abstraction. e. where ‘ver’. These are in turn made up of one or more of the appropriate cycles. the width of the read and write data busses (‘16’. These transactions are then made up of one or more of the appropriate phases.g. This does not have to match the time scale of the input FSDB file. ‘32’. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor. ‘8x16’. ‘fs’).please inform us. ‘16x16’) ‘dw’ – data width. An additional transaction. e. www. AHB_request and AHB_grant. ‘dw’ and ‘tu’ have the following meanings and valid values: • • • • ‘ver’ – version (‘v2p8’) ‘ms’ – master/slave configuration. indicates the maximum number of masters and split-capable slaves (‘2x16’. types and attributes of these transactions are described in detail. The naming convention used is nte_AMBA_AHB_‘ver’_‘ms’_‘dw’_‘tu’. ‘ms’. AHB_no_bus_transfer contains AHB_request_grant_phase. The protocol tree shows how the transactions are inter-related. represents the output of the SPLIT signals from AHB slaves.g.com EMail:cadserv21@hotmail. however.cadfamily.com 78 The document is for study only. ‘ns’.nTX User’s Guide and Tutorial Transactor Configurations A number of transactor configurations are available. The AHB Transactor recognizes transactions from the AHB active signals. orthogonal to the core transaction hierarchy. any signal changes below this time resolution will not be seen by nTE. ‘128’.we will delete . ‘256’) ‘tu’ – time unit (‘ps’. ‘4x16’. At the highest level are transactions representing complete transfers.

com 79 The document is for study only.if tort to your rights.cadfamily.we will delete .please inform us.Appendix A: AMBA AHB Transactor Protocol Tree www.com EMail:cadserv21@hotmail.

Attributes: T_request Request master >=> arbiter. word Data MUX_S >=> master AHB_idle_busy_transfer AHB_idle_bust_transfer is a multi-directional transaction used when a bus master is granted access to the bus but does not immediately perform a data transfer. word Address MUX_M >=> slave & decoder & arbiter. word Data MUX_S >=> master AHB_transfer_attempt AHB_transfer_attempt is a multi-directional transaction used for a complete data. T_WriteNread WriteNread MUX_M >=> slave. busy. split.com EMail:cadserv21@hotmail. T_PROT ProtectionCtrl MUX_M >=> slave. T_lock Lock master >=> arbiter. T_burst_type BurstType MUX_M >=> slave & arbiter. and is specified in the form ‘bit attribute_name[C_constant]’ (see Transactor Constants). T_transfer_size TransferSize MUX_M >=> slave. word Address MUX_M >=> slave & decoder & arbiter T_burst_type BurstType MUX_M >=> slave & arbiter. T_PROT ProtectionCtrl MUX_M >=> slave. Attributes: T_request Request master >=> arbiter. It will connect a split transfer with its respective completion.nTX User’s Guide and Tutorial Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer. T_transfer_size TransferSize MUX_M >=> slave.we will delete . or idle transfer. or is to continue with a transfer later.com 80 The document is for study only. www. to the unit (or units) to the right of the symbol.cadfamily.please inform us. T_slave_response Response MUX_S >=> master & arbiter. T_slave_response Response MUX_S >=> master & arbiter. T_WriteNread WriteNread MUX_M >=> slave.if tort to your rights. from the unit to the left of the symbol. T_lock Lock master >=> arbiter. configuration in use. NOTE: The size of a number of the attributes is dependant on the transactor AHB_single_transfer AHB_single_transfer is a multi-directional transaction used for single bus transfers.

Attributes: T_WriteNread WriteNread MUX_M >=> slave.com EMail:cadserv21@hotmail. T_burst_type BurstType MUX_M >=> slave & arbiter. Attributes: T_WriteNread WriteNread MUX_M word Address MUX_M T_transfer_type TransferType T_burst_type BurstType MUX_M T_transfer_size TransferSize T_PROT ProtectionCtrl MUX_M T_slave_response Response word Data MUX_S >=> slave. T_PROT ProtectionCtrl MUX_M >=> slave. MUX_M >=> slave & arbiter.we will delete .Appendix A: AMBA AHB Transactor Attributes: T_request Request master >=> arbiter.com 81 The document is for study only. word Address MUX_M >=> slave & decoder & arbiter. Attributes: T_request Request T_lock Lock master >=> arbiter.if tort to your rights.cadfamily. T_transfer_type TransferType MUX_M >=> slave & arbiter. master >=> arbiter AHB_transfer_data AHB_transfer_data item is a multi-directional transaction used to perform a data transfer. T_burst_type BurstType MUX_M >=> slave & arbiter. T_PROT ProtectionCtrl MUX_M >=> slave www. T_lock Lock master >=> arbiter. MUX_S >=> master & arbiter.please inform us. >=> master AHB_control_phase AHB_control_phase is a multi-directional transaction used to perform the control phase of a data transfer. word Data MUX_S >=> master AHB_no_bus_transfer AHB_no_bus_transfer is a multi-directional transaction used as a result of a master not being granted access to the bus by the arbiter. T_WriteNread WriteNread MUX_M >=> slave. MUX_M >=> slave. >=> slave. word Address MUX_M >=> slave & decoder & arbiter. >=> slave & decoder & arbiter. T_transfer_size TransferSize MUX_M >=> slave. T_transfer_type TransferTypeMUX_M >=> slave & arbiter. >=> slave & arbiter. T_slave_response Response MUX_S >=> master & arbiter. T_transfer_size TransferSizeMUX_M >=> slave.

synchronized to the rising edge of the system clock of duration one clock period. of access to the bus. Attributes: T_slave_response Response word Data MUX_S >=> master & arbiter. MUX_S >=> master AHB_data_write_phase AHB_data_write_phase is a multi-directional transaction used to perform the write phase of a data transfer. MUX_M >=> slave AHB_response_cycle AHB_response_cycle is a multi-directional transaction used to perform the response to the data transfer.please inform us.com EMail:cadserv21@hotmail.if tort to your rights. master >=> arbiter. Attributes: bit ready MUX_S >=> master & arbiter & slave T_slave_response Response MUX_S >=> master & arbiter AHB_request_grant_phase AHB_request_grant_phase is a bi-directional transaction used to perform request and granting.nTX User’s Guide and Tutorial AHB_data_read_phase AHB_data_read_phase is a multi-directional transaction used to perform the read phase of a data transfer.we will delete .cadfamily. Attributes: bit split_info_core[C_max_num_masters] www. or not granting.com 82 The document is for study only. Attributes: T_request Request T_lock Lock T_grant Grant master >=> arbiter. Attributes: T_slave_response Response word Data MUX_S >=> master & arbiter. arbiter >=> master AHB_split_info_core AHB_split_info_core is a uni-directional transaction used to unlock a master from a split transaction.

if tort to your rights. Attributes: bit Address[C_addresswidth] AHB_slave_control AHB_slave_control is a uni-directional transaction used to instruct the slave to control its response. synchronized to the rising edge of the system clock of duration one clock period. synchronized to the rising edge of the system clock of duration one clock period.com 83 The document is for study only. Attributes: bit active_master[4] AHB_write_data AHB_write_data is a uni-directional transaction used to pass data from a master to a slave. T_transfer_size TransferSize. synchronized to the rising edge of the system clock of duration one clock period. Attributes: bit Data[C_datawidth] AHB_read_data AHB_read_data is a uni-directional transaction used to pass data from a slave to a master.cadfamily.Appendix A: AMBA AHB Transactor AHB_active_master AHB_active_master is a uni-directional transaction used to indicate the ID of the master currently active on the bus. Attributes: bit Data[C_datawidth] AHB_address AHB_address is a uni-directional transaction used to pass the address from a master to a slave. synchronized to the rising edge of the system clock of duration one clock period.we will delete . bit ProtectionCtrl[4] www. Attributes: bit WriteNread.please inform us. synchronized to the rising edge of the system clock of duration one clock period.com EMail:cadserv21@hotmail.

bit Lock AHB_grant AHB_grant is a uni-directional transaction used to grant access to the bus.nTX User’s Guide and Tutorial AHB_trans_control AHB_trans_control is a uni-directional transaction used to control the transfer on the bus.com 84 The document is for study only. T_burst_type BurstType AHB_request AHB_request is a uni-directional transaction used to request access to the bus. Attributes: bit grant AHB_master_Locked AHB_master_Locked is a uni-directional transaction used to lock a master access to the bus. synchronized to the rising edge of the system clock of duration one clock period. Attributes: bit master_Locked AHB_slave_ready AHB_slave_ready is a uni-directional transaction used to indicate that a transfer has completed on the bus. synchronized to the rising edge of the system clock of duration one clock period. synchronized to the rising edge of the system clock of duration one clock period.please inform us. synchronized to the rising edge of the system clock of duration one clock period. Attributes: T_transfer_type TransferType. synchronized to the rising edge of the system clock of duration one clock period. Attributes: bit ready www.cadfamily.com EMail:cadserv21@hotmail. Attributes: bit Request.if tort to your rights.we will delete .

size number_of_masters array of bits. size data_width MUX_M >=> slave bit array. and synchronized to the rising edge of the system clock of duration one clock period. size 4 bit array bit array.com 85 The document is for study only.please inform us. Wires Name HTRANS HADDR HWRITE HSIZE HBURST HPROT HWDATA HREADY HRESP HRDATA HBUSREQ HLOCK HGRANT HMASTER Type bit array. size data_width MUX_S >=> master Master >=> arbiter Master >=> arbiter Arbiter >=> master arbiter >=> MUX_M & slave arbiter >=> master & slave HMASTLOCK bit www. size number_of_masters bit array. It is orthogonal to the core transaction hierarchy and is not included in the protocol tree. size 2 array of bits. Attributes: T_slave_response Response stp_split_info stp_split_info is a uni-directional transaction.if tort to your rights. synchronized to the rising edge of the system clock of duration one clock period. representing the output of the SPLIT signals from AHB slaves.com EMail:cadserv21@hotmail. size number_of_masters array of bits.we will delete .cadfamily.Appendix A: AMBA AHB Transactor AHB_slave_response AHB_slave_response is a uni-directional transaction used to provide additional information on the status of the transfer. size 2 bit array. It has no attributes. size 3 bit array. size address_width bit bit array. size 4 Direction MUX_M >=> slave & arbiter MUX_M >=> slave & decoder & arbiter MUX_M >=> slave MUX_M >=> slave MUX_M >=> slave & arbiter MUX_M >=> slave MUX_S >=> master & arbiter & slave MUX_S >=> master & arbiter bit array. size 3 bit array.

NONSEQ = 2.if tort to your rights. BUSY = 1. RETRY = 2. the AHB transactor makes use of the following types: type enum T_slave_response:2 { OKAY = 0. type enum T_transfer_type:2 { IDLE = 0. WRAP4 = 2. INCR8 = 5. INCR = 1.com EMail:cadserv21@hotmail. WRAP16 = 6. INCR4 = 3. size or_gate_S >=> arbiter max_number_of_masters bit bit clock_source >=> arbiter & master & slave reset_source >=> arbiter & master & slave Additional Information Data Types In addition to the standard transactor types. type enum T_burst_type:3 { SINGLE = 0.nTX User’s Guide and Tutorial Name HSPLIT_core HCLK HRESETn Type Direction bit array. INCR16 = 7 www. and ‘bit’. SPLIT = 3 }.com 86 The document is for study only.we will delete . such as ‘int’.cadfamily. WRAP8 = 4. ERROR = 1. SEQ = 3 }.please inform us.

com 87 The document is for study only.com EMail:cadserv21@hotmail.we will delete . T_bufferable bufferable. type enum T_data_nOpcode:1 { OPCODE= 0. bits_1024 = 7 }. PRIVILEGED = 1 }. DATA = 1 }.cadfamily. bits_128 = 4. type enum T_privileged:1 { USER = 0. WRITE = 1 }. bits_64 = 3.please inform us. BUFFERABLE = 1 }. type struct T_PROT { T_data_nOpcode data_opcode. bits_32 = 2. www. bits_512 = 6. bits_16 = 1. type enum T_cacheable:1 { NOT_CACHEABLE = 0. bits_256 = 5. type enum T_WriteNread:1 { READ = 0. type enum T_transfer_size:3 { bits_8 = 0. CACHEABLE = 1 }. type enum T_bufferable:1 { NOT_BUFFERABLE= 0. T_privileged privileged.Appendix A: AMBA AHB Transactor }.if tort to your rights.

nTX User’s Guide and Tutorial T_cacheable cacheable. Transactor Constants • • • C_max_num_masters – the number of masters in use (valid values are 2. type enum T_grant:1 { NO_GRANT = 0.com 88 The document is for study only. type enum T_request:1 { NO_REQUEST= 0. GRANT = 1 }. type enum T_lock:1 { NO_LOCK = 0.com EMail:cadserv21@hotmail.if tort to your rights. 32. }. LOCK = 1 }.please inform us. 64.cadfamily. 128 and 256) C_addresswidth – the width of the address bus (valid value is 32) www. REQUEST = 1 }. 8 and 16) C_datawidth – the width of the data bus (valid values are 16. 4.we will delete .

Sequential and non-sequential single transfers.please inform us.Appendix B: AMBA AHB Lite Transactor Appendix B: AMBA AHB Lite Transactor Overview The AMBA-AHB Transactor supports the following features: • • • Data bus width from 8-bits to 1024-bits. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements.com 89 The document is for study only. BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description. MAPPING_ROOT = "/AHB_lite_system/test_AHB".com EMail:cadserv21@hotmail.if tort to your rights.we will delete . www.cadfamily. nte_AMBA_AHB_lite_v2p8_32_ns MyAHB_1 { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed. Name The bus declaration (nte_AMBA_AHB_lite_v2p8_32_ns) must be one of the supported transactors. IDLE and BUSY transfer types.

cadfamily.please inform us. /ahb_core/HWRITE ="/V_AHB_core/HWRITE".we will delete . control and // write data MUX) // all of these are inputs to each slave /ahb_core/HTRANS ="/V_AHB_core/HTRANS". /ahb_core/HPROT ="/V_AHB_core/HPROT". /ahb_core/HMASTLOCK ="/V_AHB_core/HMASTLOCK". warn_after_n_ready_low_cycles: A warning will be issued when the ready signal from selected slave has remained low for ‘n’ clock cycles www.nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side. clk_phase_shift: The time of the first transition from the initial value. setup_time: The setup time for all AHB signals. /ahb_core/HADDR ="/V_AHB_core/HADDR". however. /ahb_core/HWDATA ="/V_AHB_core/HWDATA". clk_2nd_time: The relative time of the second clock change after the previous change. clk_1st_time: The relative time of the first clock change after the initial phase shift change. If this is done they will be assigned a default value (normally 0). // signals from slave MUX (read data and response) // all of these are inputs to each master /ahb_core/HREADY ="/V_AHB_core/HREADY". it is possible to leave signals unconnected by removing them from the sigmap section. The SIGMAP code example is for an unmapped clock. /ahb_core/HSIZE ="/V_AHB_core/HSIZE". The transactor signals are pre-defined as shown in the file below and must not be changed.com 90 The document is for study only. SIGMAP { // signals from master MUX (address.if tort to your rights. /ahb_core/HBURST ="/V_AHB_core/HBURST".com EMail:cadserv21@hotmail. /ahb_core/HRDATA ="/V_AHB_core/HRDATA". hold_time: The hold time for all AHB signals. NOTE: Clock can be mapped to /ahb_core/HCLK. /ahb_core/HRESP ="/V_AHB_core/HRESP". } Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file: • • • • • • • clk_init_value: The initial value of the clock (0 or 1).

An example is shown below: Figure: Clock Setup // parameters PARAMETER { clk_init_value = 0. //ns warn_after_n_ready_low_cycles = 100. //ns hold_time = 1 ns. The naming convention used is nte_AMBA_AHB_lite_‘ver’_‘dw’_‘tu’. ‘fs’). Transactor Configurations A number of transactor configurations are available.com EMail:cadserv21@hotmail. ‘128’. ‘ns’. If the clock is mapped then clk_* parameters do not need to be set. //ns clk_2nd_time = 5 ns. ‘64’. ‘32’. //initial value of clock clk_phase_shift = 0 ns. The clock set up is important for the correct operation of the transactor.cadfamily. where ‘ver’. www.we will delete . //ns setup_time = 2 ns.com 91 The document is for study only. This does not have to match the time scale of the input FSDB file. however. ‘256’) ‘tu’ – time unit (‘ps’. //ns clk_1st_time = 5 ns. ‘dw’ and ‘tu’ have the following meanings and valid values: • • • ‘ver’ – version (‘v2p8’) ‘dw’ – width of data bus (‘16’.please inform us. where ‘n’ is equal to the number set for the parameter. any signal changes below this time resolution will not be seen by nTE.if tort to your rights. } NOTE: PARAMETER code example is for an unmapped clock.Appendix B: AMBA AHB Lite Transactor after it was selected.

we will delete . AHB_control_phase is made up of AHB_address. These are in turn made up of one or more of the appropriate cycles. www.g.com EMail:cadserv21@hotmail. These transactions are then made up of one or more of the appropriate phases. e. AHB_slave_control and AHB_trans_control transactions. AHB_single_transfer contains AHB_transfer_data. types and attributes of these transactions are described in detail. or AHB_data_read_phase. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor. The protocol tree shows how the transactions are inter-related.if tort to your rights.g. The highest level includes transactions representing complete transfers.cadfamily.please inform us. In this section the function.com 92 The document is for study only. e.nTX User’s Guide and Tutorial Transaction Hierarchy The AHB-Lite transactor consists of a number of transactions that enable communication at different levels of abstraction. which is made up of AHB_control_phase and AHB_data_write_phase.

if tort to your rights.com 93 The document is for study only.Appendix B: AMBA AHB Lite Transactor Protocol Tree www.please inform us.cadfamily.com EMail:cadserv21@hotmail.we will delete .

T_burst_type BurstType master >=> slave. word Data MUX_S >=> master AHB_transfer_data AHB_transfer_data item is a multi-directional transaction used to perform a data transfer. Attributes: T_WriteNread WriteNread master >=> slave. word Data MUX_S >=> master AHB_idle_busy_transfer AHB_idle_busy_transfer is a multi-directional transaction used when the master does not perform a read or write transfer.please inform us. NOTE: The size of a number of the attributes is dependant on the transactor AHB_single_transfer AHB_single_transfer is a multi-directional transaction used for single bus transfers. Attributes: T_WriteNread WriteNread master >=> slave.if tort to your rights.com 94 The document is for study only.we will delete . configuration in use. T_PROT ProtectionCtrl master >=> slave. T_PROT ProtectionCtrl master >=> slave. Attributes: T_WriteNread WriteNread word Address T_transfer_type TransferType master >=> slave.nTX User’s Guide and Tutorial Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer. T_slave_response Response MUX_S >=> master.com EMail:cadserv21@hotmail. www.cadfamily. and is specified in the form ‘bit attribute_name[C_constant]’ (see Transactor Constants). master >=> slave. T_transfer_size TransferSize master >=> slave. from the unit to the left of the symbol. to the unit (or units) to the right of the symbol. T_slave_response Response MUX_S >=> master. word Address master >=> slave & decoder T_burst_type BurstType master >=> slave T_transfer_size TransferSize master >=> slave. master >=> slave & decoder. word Address master >=> slave & decoder.

Appendix B: AMBA AHB Lite Transactor T_burst_type BurstType T_transfer_size TransferSize T_PROT ProtectionCtrl T_slave_response Response word Data master >=> slave &, master >=> slave, master >=> slave, MUX_S >=> master, MUX_S >=> master

AHB_control_phase
AHB_control_phase is a multi-directional transaction used to perform the control phase of a data transfer. Attributes:
T_WriteNread WriteNread word Address T_transfer_type TransferType T_burst_type BurstType T_transfer_size TransferSize T_PROT ProtectionCtrl master master master master master master >=> >=> >=> >=> >=> >=> slave, slave & decoder, slave, slave, slave, slave

AHB_data_read_phase
AHB_data_read_phase is a multi-directional transaction used to perform the read phase of a data transfer. Attributes:
T_slave_response Response word Data MUX_S >=> master, MUX_S >=> master

AHB_data_write_phase
AHB_data_write_phase is a multi-directional transaction used to perform the write phase of a data transfer. Attributes:
T_slave_response Response word Data MUX_S >=> master, master >=> slave

AHB_response_cycle
AHB_response_cycle is a multi-directional transaction used to perform the response to the data transfer. Attributes:
bit ready T_slave_response Response MUX_S >=> master & slave MUX_S >=> master

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nTX User’s Guide and Tutorial

AHB_write_data
AHB_write_data is a uni-directional transaction used to pass data from the master to a slave, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
bit Data[C_datawidth]

AHB_read_data
AHB_read_data is a uni-directional transaction used to pass data from a slave to the master, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
bit Data[C_datawidth]

AHB_address
AHB_address is a uni-directional transaction used to pass the address from the master to a slave, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
bit Address[C_addresswidth]

AHB_slave_control
AHB_slave_control is a uni-directional transaction used to pass control information from the master to a slave, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
bit WriteNread, T_transfer_size TransferSize, bit ProtectionCtrl[4]

AHB_trans_control
AHB_trans_control is a uni-directional transaction used to pass additional control information from the master to a slave, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
T_transfer_type TransferType, T_burst_type BurstType

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Appendix B: AMBA AHB Lite Transactor

AHB_master_Locked
AHB_master_Locked is a uni-directional transaction used to indicate the master wishes locked access to the slave, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
bit master_Locked

AHB_slave_ready
AHB_slave_ready is a uni-directional transaction used to indicate that a transfer has completed on the bus, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
bit ready

AHB_slave_response
AHB_slave_response is a uni-directional transaction used to indicate the transfer completion response of the slave, synchronized to the rising edge of the system clock of duration one clock period. Attributes:
T_slave_response Response

Wires
Name HTRANS HADDR HWRITE HSIZE HBURST HPROT HWDATA HREADY HRESP HRDATA Type bit array, size 2 bit array, size address_width bit bit array, size 3 bit array, size 3 bit array, size 4 bit array, size data_width bit array bit array, size 2 bit array, size data_width Direction master >=> slave master >=> slave & decoder master >=> slave master >=> slave master >=> slave master >=> slave master >=> slave MUX_S >=> master & slave MUX_S >=> master MUX_S >=> master master >=> slave

HMASTLOCK bit

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nTX User’s Guide and Tutorial

Name HCLK HRESETn

Type bit bit

Direction clock_source >=> master & slave reset_source >=> master & slave

Additional Information
Data Types
In addition to the standard transactor types, such as ‘int’, and ‘bit’, the AHB-Lite transactor makes use of the following types: type enum T_slave_response:2
{ OKAY = 0, ERROR = 1, RETRY = 2, SPLIT = 3 }; type enum T_transfer_type:2 { IDLE = 0, BUSY = 1, NONSEQ = 2, SEQ = 3 }; type enum T_burst_type:3 { SINGLE = 0, INCR = 1, WRAP4 = 2, INCR4 = 3, WRAP8 = 4, INCR8 = 5, WRAP16 = 6, INCR16 = 7 };

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type enum T_cacheable:1 { NOT_CACHEABLE = 0. T_bufferable bufferable. bits_256 = 5. bits_16 = 1. bits_512 = 6. www.com 99 The document is for study only. bits_128 = 4.if tort to your rights.please inform us. BUFFERABLE = 1 }. bits_1024 = 7 }. CACHEABLE = 1 }. T_privileged privileged.com EMail:cadserv21@hotmail. PRIVILEGED = 1 }. type enum T_bufferable:1 { NOT_BUFFERABLE= 0. bits_32 = 2. bits_64 = 3.cadfamily. type enum T_data_nOpcode:1 { OPCODE= 0.Appendix B: AMBA AHB Lite Transactor type enum T_transfer_size:3 { bits_8 = 0. type enum T_privileged:1 { USER = 0. }. T_cacheable cacheable. type enum T_WriteNread:1 { READ = 0. WRITE = 1 }.we will delete . DATA = 1 }. type struct T_PROT { T_data_nOpcode data_opcode.

64.if tort to your rights. 32.we will delete . Transactor Constants • • C_datawidth – the width of the data bus (valid values are 16.cadfamily.nTX User’s Guide and Tutorial type enum T_request:1 { NO_REQUEST= 0. type enum T_grant:1 { NO_GRANT = 0. 128 and 256) C_addresswidth – the width of the address bus (valid value is 32) www. LOCK = 1 }. GRANT = 1 }.please inform us. REQUEST = 1 }.com 100 The document is for study only.com EMail:cadserv21@hotmail. type enum T_lock:1 { NO_LOCK = 0.

This is prefixed to the signal names specified on the right hand side of the SIGMAP statements.com EMail:cadserv21@hotmail.com 101 The document is for study only. www.Appendix C: AMBA APB Transactor Appendix C: AMBA APB Transactor Overview The AMBA-AXI Transactor supports the following features: • • AMBA 2.if tort to your rights. MAPPING_ROOT = "/APB_test/st_APB/APB_bus".please inform us.we will delete . nte_AMBA_APB_v1p0_32x16_ns my_APB { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.cadfamily. BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description.0 APB Support for single slave systems with no select bus. Name The bus declaration (nte_AMBA_APB_v1p0_32x16_ns) must be one of the supported transactors.

com 102 The document is for study only.nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side. If there are less slaves in the system. "/PSEL_9". The SIGMAP code example is for an unmapped clock. "/PSEL_1". The available parameters are: • • • clk_init_value: The initial value of the clock (0 or 1). "/PSEL_12". "/PSEL_10". "/PSEL_15". "/PSEL_4".com EMail:cadserv21@hotmail. "/PSEL_3". "/PENABLE". "/PSEL_5". "/PSEL_13". "/PSEL_6". "/PSEL_14". clk_phase_shift: The time of the first transition from the initial value.if tort to your rights. This example is for a transactor with 16 APB slaves connected. "/PSEL_7". Configuration of the transactor is made via the PARAMETER section of the bcf file. www. "/PRDATA". SIGMAP { /APB_bus/PADDR /APB_bus/PSEL[0] /APB_bus/PSEL[1] /APB_bus/PSEL[2] /APB_bus/PSEL[3] /APB_bus/PSEL[4] /APB_bus/PSEL[5] /APB_bus/PSEL[6] /APB_bus/PSEL[7] /APB_bus/PSEL[8] /APB_bus/PSEL[9] /APB_bus/PSEL[10] /APB_bus/PSEL[11] /APB_bus/PSEL[12] /APB_bus/PSEL[13] /APB_bus/PSEL[14] /APB_bus/PSEL[15] /APB_bus/PENABLE /APB_bus/PWRITE /APB_bus/PRDATA /APB_bus/PWDATA } = = = = = = = = = = = = = = = = = = = = = "/PADDR". "/PSEL_8". clk_1st_time: The relative time of the first clock change after the initial phase shift change. The transactor signals are pre-defined as shown in the file below and must not be changed.we will delete . "/PSEL_0". "/PWDATA". then some of these can be left unconnected (remove the mapping from the SIGMAP block). NOTE: Clock can be mapped to /APB_bus/PCLK. Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file. "/PSEL_11". "/PSEL_2".cadfamily.please inform us. "/PWRITE".

Defaults to ‘true’. 1 ns. If the clock is mapped then clk_* parameters do not need to be set. 50 ns.please inform us. The naming convention used is nte_AMBA_APB_‘ver’_‘dw’x‘max_slaves’_‘tu’ where ‘ver’. Transactor Configurations A number of transactor configurations are available.cadfamily.we will delete .com EMail:cadserv21@hotmail. true.16. The clock set up is important to the correct operation of the transactor. 1 ns. 50 ns. An example is shown below: Figure: Clock Setup // parameters PARAMETER { clk_init_value clk_phase_shift clk_1st_time clk_2nd_time setup_time hold_time use_select allow_idle } = = = = = = = = 0b0. 32) www. 50 ns. ‘dw’. • allow_idle: Recognize idle transactions (‘true’ or ‘false’). setup_time: The setup time for all APB signals. hold_time: The hold time for all APB signals. Note that if this is set to false. Setting this to false will also disable recognition of idle transactions.com 103 The document is for study only. Defaults to ‘true’. Set this to ‘false’ if the system has a single slave.if tort to your rights. then PSEL should not be mapped in the SIGMAP block. NOTE: PARAMETER code example is for an unmapped clock. true. and no PSEL bus. ‘max_slaves’ and ‘tu’ have the following meanings and valid values: • • ‘ver’ – version (‘v1p0’) ‘dw’ – width of data bus (8.Appendix C: AMBA APB Transactor • • • • clk_2nd_time: The relative time of the second clock change after the previous change. use_select: Use the slave select bus (‘true’ or ‘false’). Setting to ‘false’ will result in smaller output FSDB.

com 104 The document is for study only.if tort to your rights. ‘ns’.com EMail:cadserv21@hotmail. any signal changes below this time resolution will not be seen by nTE. sets width of PSEL (16. ‘max_slaves’ – maximum number of connected slaves.nTX User’s Guide and Tutorial • • ‘tu’ – time unit (‘ps’. however. ‘fs’).cadfamily. 64) www.we will delete . This does not have to match the time scale of the input FSDB file.please inform us.

com 105 The document is for study only.Appendix C: AMBA APB Transactor Transaction Hierarchy The APB transactor consists of a number of transactions that enable communication at different levels of abstraction.com EMail:cadserv21@hotmail.if tort to your rights.please inform us. In this section the function. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor. types and attributes of these transactions are described in detail.we will delete .cadfamily. Protocol Tree www.

RnW and wdata if it is valid.com EMail:cadserv21@hotmail.if tort to your rights. Attributes indicate the currently selected slave. master >=> slave. PENABLE = 0). from the unit to the left of the symbol. Attributes: word bit bit slave_id addr[C_APB_addresswidth] data[C_APB_wdatawidth] master >=> slave. wdata[C_APB_wdatawidth] //only used/written to //when RnW == write enable A single cycle transaction representing the ENABLE state of the APB bus (PSELx = 1. slave >=> master write write is an APB write from a master (typically an APB bridge) to a slave. to the unit (or units) to the right of the symbol. addr[C_APB_addresswidth]. PENABLE = 0). data[C_APB_wdatawidth] idle A single cycle transaction representing the IDLE state of the APB bus (PSELx = 0. addr[C_APB_addresswidth]. RnW. read read is an APB read from a master (typically an APB bridge) to a slave. Attributes indicate the currently selected slave. Attributes: None setup A single cycle transaction representing the SETUP state of the APB bus (PSELx = 1.we will delete . www.nTX User’s Guide and Tutorial Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer. PENABLE = 1). along with values of address.cadfamily.please inform us. Attributes: word bit bit slave_id.com 106 The document is for study only. Attributes: word T_WriteNread bit bit slave_id.

slave_id enable_cycle enable_cycle is a single cycle transaction that holds the value of the enable signal.Appendix C: AMBA APB Transactor along with values of address. Attributes: bool word selected.we will delete . Attributes: www.com 107 The document is for study only. Attributes: T_WriteNread bit RnW.if tort to your rights. Attributes: bit wdata[C_APB_wdatawidth] rdata_cycle rdata_cycle is a single cycle transaction that holds the value of the read data bus.cadfamily. RnW and data (either read or write data depending on the current value of RnW).com EMail:cadserv21@hotmail. Attributes: bit en control_cycle control_cycle is a single cycle transaction that holds the values of the RnW and address signals. bit addr[C_APB_addresswidth] master >=> slave. // data holds either read or write data depending on RnW bit data[] master >=> slave || slave >=> master selected_slave selected slave is a single cycle transaction used to indicate whether or not a slave is selected. T_WriteNread RnW master >=> slave. addr[C_APB_addresswidth] wdata_cycle wdata_cycle is a single cycle transaction that holds the value of the write data bus.please inform us. Attributes: word slave_id master >=> slave. the id of that slave. and if so.

cadfamily.com EMail:cadserv21@hotmail.com 108 The document is for study only. see the section on Signal Descriptions in the AMBA AXI Protocol Specification.please inform us. Name PCLK PADDR PSEL PENABLE PWRITE PRDATA PWDATA Type bit bit [C_APB_addresswidth] [C_num_slaves] bit bit bit bit [C_APB_rdatawidth] bit [C_APB_wdatawidth] Direction clock_source >=> master & slave master to slave master to slave master to slave master to slave slave to master master to slave www.nTX User’s Guide and Tutorial bit rdata[C_APB_rdatawidth] Wires For a description of each of these wires (signals).if tort to your rights.we will delete .

such as ‘int’.com 109 The document is for study only. and ‘bit’. the APB transactor makes use of the following types: type enum T_WriteNread:1 { READ = 0.please inform us.we will delete .Appendix C: AMBA APB Transactor Additional Information Data Types In addition to the standard transactor types.if tort to your rights. WRITE = 1 }.com EMail:cadserv21@hotmail.cadfamily. Transactor Constants • • • • C_APB_rdatawidth – the width of the read data bus C_APB_wdatawidth – the width of the write data bus C_APB_addresswidth – the width of the address bus C_num_slaves – the width of the slave select bus (determines the maximum number of slaves) www.

please inform us.nTX User’s Guide and Tutorial www.com 110 The document is for study only.cadfamily.we will delete .if tort to your rights.com EMail:cadserv21@hotmail.

com EMail:cadserv21@hotmail.if tort to your rights.cadfamily. transaction ID) Recognition of complete bursts as a single transaction Out-of-order transaction completion Full support for narrow transfers and unaligned transfers (encoding/ decoding of data onto the data bus) BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description. nte_AMBA_AXI_v1p6_32_32_32_4_ns my_AXI { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.please inform us.we will delete . write data.com 111 The document is for study only. www. read data. MAPPING_ROOT = "/verilog_conc_model/AXI_structure/iAXI".Appendix D: AMBA AXI Transactor Appendix D: AMBA AXI Transactor Overview The AMBA-AXI Transactor supports the following features: • • • • Configurable bus widths (address. Name The bus declaration (nte_AMBA_AXI_v1p6_32_32_32_4_ns) must be one of the supported transactors. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements.

The transactor signals are pre-defined as shown in the file below and must not be changed. www. The SIGMAP code example is for an unmapped clock. "/RREADY". NOTE: Clock can be mapped to /AXI/ACLK. /AXI/ARSIZE = "/ARSIZE". "/RID". /AXI/AWADDR = "/AWADDR". /AXI/AWSIZE = "/AWSIZE". // Read channel /AXI/RVALID /AXI/RLAST /AXI/RDATA /AXI/RRESP /AXI/RID /AXI/RREADY // Write channel = = = = = = "/RVALID". If this is done they will be assigned a default value (normally 0). /AXI/AWREADY = "/AWREADY". SIGMAP { // From reset source /AXI/ARESETn = "/ARESETn". "/RLAST".com EMail:cadserv21@hotmail.if tort to your rights. however. it is possible to leave signals unconnected by removing them from the sigmap section. "/RDATA". /AXI/AWCACHE = "/AWCACHE". /AXI/ARID = "/ARID". /AXI/ARADDR = "/ARADDR".please inform us.com 112 The document is for study only. // Read address channel /AXI/ARVALID = "/ARVALID". /AXI/AWLOCK = "/AWLOCK". /AXI/ARCACHE = "/ARCACHE". /AXI/AWLEN = "/AWLEN". /AXI/AWID = "/AWID". // Write address channel /AXI/AWVALID = "/AWVALID". /AXI/AWBURST = "/AWBURST".we will delete . /AXI/ARLOCK = "/ARLOCK". /AXI/ARBURST = "/ARBURST". /AXI/ARREADY = "/ARREADY". /AXI/ARLEN = "/ARLEN". "/RRESP".nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side.cadfamily. /AXI/AWPROT = "/AWPROT". /AXI/ARPROT = "/ARPROT".

/AXI/BRESP = "/BRESP". • clk_2nd_time: The relative time of second clock change after the previous change. • hold_time: The hold time for all AXI signals. "/WLAST".we will delete . The available parameters are: clk_init_value: The initial value of the clock (0 or 1). • byte_level_transactions: Boolean value (true/false) to determine whether the top level AXI transactions are AXI_read/write (true) or AXI_buswidth_read/write (false). Configuration of the transactor is made via the PARAMETER section of the bcf file. clk_1st_time: The relative time of the first clock change after the initial phase shift change. • setup_time: The setup time for all AXI signals. // Write response channel /AXI/BVALID = "/BVALID". /AXI/BREADY = "/BREADY". "/WREADY". } Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file. /AXI/BID = "/BID". • rdata_width: Tthe width of the read data bus (in bits).if tort to your rights. clk_phase_shift: The time of the first transition from the initial value. "/WID".com EMail:cadserv21@hotmail. An example is shown below: • • • www. "/WSTRB". must be less than or equal to the maximum width for the transactor. "/WDATA". The clock set up is important to the correct operation of the transactor. • wdata_width: The width of the write data bus (in bits).please inform us.com 113 The document is for study only. must be less than or equal to the maximum width for the transactor.cadfamily.Appendix D: AMBA AXI Transactor /AXI/WVALID /AXI/WLAST /AXI/WDATA /AXI/WSTRB /AXI/WID /AXI/WREADY = = = = = = "/WVALID".

please inform us. This does not have to match the time scale of the input FSDB file. 128.we will delete . 5 ns.com EMail:cadserv21@hotmail. The naming convention used is nte_AMBA_AXI_‘ver’_‘rw’_‘ww’_‘aw’_‘iw’_‘tu’ where ‘ver’. any signal changes below this time resolution will not be seen by nTE.if tort to your rights. ‘rw’. ‘ww’. // // = 32. ‘iw’ and ‘tu’ have the following meanings and valid values: • • • • • ‘ver’ – version (‘v2p8’) ‘rw’/’ww’ – read/write width (16.cadfamily. 1 ns. If the clock is mapped then clk_* parameters do not need to be set. 32. ‘ns’. 256 –equal values) ‘aw’ – address width (‘32’) ‘iw’ – ID width (‘4’) ‘tu’ – time unit (‘ps’. www.com 114 The document is for study only. // // // = 32. // // top level transaction selection (byte level or buswidth variants) width of read data in bits width of write data in bits NOTE: PARAMETER code example is for an unmapped clock. ‘fs’). true. 0 ns. however. ‘aw’. 64. Transactor Configurations A number of transactor configurations are available. 2 ns.nTX User’s Guide and Tutorial Figure: Clock Setup // parameters PARAMETER { clk_init_value clk_phase_shift clk_1st_time clk_2nd_time setup_time hold_time byte_level_transactions rdata_width wdata_width } = = = = = = = 0. 5 ns.

we will delete .cadfamily.please inform us. In this section the function.Appendix D: AMBA AXI Transactor Transaction Hierarchy The transactor consists of a number of transactions that enable communication at different levels of abstraction. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor.com 115 The document is for study only.com EMail:cadserv21@hotmail. types and attributes of these transactions are described in detail.if tort to your rights. www.

nTX User’s Guide and Tutorial Protocol Tree www.if tort to your rights.com EMail:cadserv21@hotmail.cadfamily.we will delete .please inform us.com 116 The document is for study only.

com EMail:cadserv21@hotmail. These can overlap due to pipe-lining and the use of the ID signal.cadfamily. slave. with read data (and length) expressed in words of size equal to the bus width. A read_control transaction passes address and control information from the master to the slave. slave. configuration in use. Attributes: bit addr[AXI_MAX_ADDRESS_WIDTH] T_AXI_SIZE size T_AXI_BURST burst T_AXI_LOCK lock T_AXI_CACHE cache T_AXI_PROT prot bit id[AXI_MAX_ID_WIDTH] int data_length bit data_bytes[AXI_MAX_RDATA_LENGTH][8] T_AXI_RESPONSE resp[AXI_MAX_BURST_LENGTH] master master master master master master master master slave slave >=> >=> >=> >=> >=> >=> >=> >=> >=> >=> slave. slave.com 117 The document is for study only. from the unit to the left of the symbol. slave. with read data (and length) expressed in bytes. Attributes: www. This is followed by a read_data_burst transaction returning the requested data and response status from slave to master.please inform us.we will delete . slave. There can be multiple outstanding (concurrent) reads. slave. A read_control transaction passes address and control information from the master to the slave. This is followed by a read_data_burst transaction returning the requested data and response status from slave to master. Note that AXI_buswidth_read is mutually exclusive to AXI_read. slave. There can be multiple outstanding (concurrent) reads. These can overlap due to pipe-lining and the use of the ID signal.Appendix D: AMBA AXI Transactor Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer.if tort to your rights. master data_length is the number of bytes in the transaction. NOTE: The size of a number of the attributes is dependant on the transactor AXI_read AXI_read is a bidirectional read transaction between the master and slave. AXI_buswidth_read AXI_buswidth_read is a bidirectional read transaction between the master and slave. master. to the unit (or units) to the right of the symbol. Note that AXI_read is mutually exclusive to AXI_buswidth_read. and is specified in the form ‘bit attribute_name[C_constant]’ (see Transactor Constants).

with write data (and length) expressed in bytes. slave. The AXI_write transaction is finished by a write_response transaction passing status information from the slave to the master. slave. with the two transactions being linked together by a common id. A write_data_burst transaction passes data and strobe www. be in parallel with or follow the write_control. These can overlap due to pipe-lining and the use of the ID signal. AXI_write AXI_write is a bidirectional write transaction between the master and slave.if tort to your rights. int ntransfers master >=> slave. The write_data_burst may precede.com EMail:cadserv21@hotmail. slave. A write_control transaction passes address and control information from the master to the slave. T_AXI_RESPONSE resp[AXI_MAX_BURST_LENGTH] slave >=> master ntransfers is the number of words of size equal to the bus width in the transaction. There can be multiple outstanding (concurrent) writes.we will delete .nTX User’s Guide and Tutorial bit addr[AXI_MAX_ADDRESS_WIDTH] master >=> slave.com 118 The document is for study only. AXI_buswidth_write AXI_buswidth_write is a bidirectional write transaction between the master and slave. T_AXI_LOCK lock master >=> slave. A write_control transaction passes address and control information from the master to the slave. T_AXI_SIZE size master >=> slave. bit data_words[AXI_MAX_BURST_LENGTH][AXI_MAX_RDATA_WIDTH] slave >=> master. T_AXI_BURST burst master >=> slave. bit id[AXI_MAX_ID_WIDTH] master >=> slave. T_AXI_CACHE cache master >=> slave. with write data (and length) expressed in words of size equal to the bus width.please inform us. slave. master data_length is the number of bytes in the transaction. slave. slave. slave. Attributes: bit addr[AXI_MAX_ADDRESS_WIDTH] T_AXI_SIZE size T_AXI_BURST burst T_AXI_LOCK lock T_AXI_CACHE cache T_AXI_PROT prot bit id[AXI_MAX_ID_WIDTH] int data_length bit data_bytes[AXI_MAX_WDATA_LENGTH][8] T_AXI_RESPONSE resp master master master master master master master master master slave >=> >=> >=> >=> >=> >=> >=> >=> >=> >=> slave. T_AXI_PROT prot master >=> slave. slave. Note that AXI_write is mutually exclusive to AXI_buswidth_write. A write_data_burst transaction passes data and strobe information from master to slave.cadfamily.

with the two transactions being linked together by a common id. cache. There can be multiple outstanding (concurrent) writes. It consists of a single read_addr_channel_phase. Note that AXI_buswidth_write is mutually exclusive to AXI_write. id[AXI_MAX_ID_WIDTH] ntransfers is the number of words (of size equal to the bus width) to be transferred. T_AXI_BURST burst master >=> slave.if tort to your rights. The AXI_write transaction is finished by a write_response transaction passing status information from the slave to the master. bit id[AXI_MAX_ID_WIDTH] master >=> slave. bit write_strobes[AXI_MAX_BURST_LENGTH][AXI_MAX_WSTRB_WIDTH] master >=> slave. size. read_control read_control is a unidirectional transaction passing address and control information from master to slave as part of a read transaction.cadfamily. www. T_AXI_PROT prot master >=> slave. bit data_words[AXI_MAX_BURST_LENGTH][AXI_MAX_WDATA_WIDTH] master >=> slave. ntransfers.we will delete . T_AXI_SIZE size master >=> slave. be in parallel with or follow the write_control. burst. A read_control transaction may take multiple clock cycles to complete. These can overlap due to pipelining and the use of the ID signal. prot.com 119 The document is for study only. Attributes: bit int T_AXI_SIZE T_AXI_BURST T_AXI_LOCK T_AXI_CACHE T_AXI_PROT bit addr[AXI_MAX_ADDRESS_WIDTH]. The write_data_burst may precede.Appendix D: AMBA AXI Transactor information from master to slave. lock.com EMail:cadserv21@hotmail.please inform us. T_AXI_LOCK lock master >=> slave. but only one may be active at any time. Attributes: bit addr[AXI_MAX_ADDRESS_WIDTH] master >=> slave. T_AXI_RESPONSE resp slave >=> master ntransfers is the number of words of size equal to the bus width in the transaction. int ntransfers master >=> slave. T_AXI_CACHE cache master >=> slave.

There can be multiple outstanding (concurrent) write data bursts. write_data_burst write_data_burst is a unidirectional transaction passing data and strobe information from master to slave as part of a write transaction. ntransfers. but only one may be active at any time. Attributes: int ntransfers. lock. id[AXI_MAX_ID_WIDTH] ntransfers is the number of words (of size equal to the bus width) to be transferred. There can be multiple outstanding (concurrent) read data bursts. It consists of a single write_addr_channel_phase. write_control write_control is a unidirectional transaction passing address and control information from master to slave as part of a write transaction. Attributes: bit int T_AXI_SIZE T_AXI_BURST T_AXI_LOCK T_AXI_CACHE T_AXI_PROT bit addr[AXI_MAX_ADDRESS_WIDTH]. size. cache. These can overlap due to pipelining and the use of the ID signal. prot.cadfamily. bit id[AXI_MAX_ID_WIDTH] ntransfers is the number of words (of size equal to the bus width) being transferred. A write_control transaction may take multiple clock cycles to complete.com EMail:cadserv21@hotmail.please inform us.com 120 The document is for study only. It consists of one or more read_channel_phase transactions.nTX User’s Guide and Tutorial read_data_burst read_data_burst is a unidirectional transaction passing data and status information from slave to master as part of a read transaction. www. It consists of one or more write_channel_phase transactions. Attributes: int ntransfers. T_AXI_RESPONSE resp[AXI_MAX_BURST_LENGTH].we will delete .if tort to your rights. bit data_words[AXI_MAX_BURST_LENGTH][AXI_MAX_RDATA_WIDTH]. burst. These can overlap due to pipelining and the use of the ID signal.

cache. Attributes: T_AXI_RESPONSE bit resp. It consists of one or more read_channel_cycle transactions. A write_response transaction may take multiple clock cycles to complete. size. Attributes: bit bit T_AXI_SIZE T_AXI_BURST T_AXI_LOCK T_AXI_CACHE T_AXI_PROT bit addr[AXI_MAX_ADDRESS_WIDTH]. A read_addr_channel_phase transaction may take multiple clock cycles to complete.Appendix D: AMBA AXI Transactor bit data_words[AXI_MAX_BURST_LENGTH][AXI_MAX_WDATA_WIDTH].com 121 The document is for study only. It consists of one or more read_addr_channel_cycle transactions. A read_channel_phase transaction may take multiple clock cycles to complete. write_response write_response is a unidirectional transaction passing status information from slave to master as part of a write transaction.please inform us.com EMail:cadserv21@hotmail.if tort to your rights. prot.cadfamily. burst.we will delete . id[AXI_MAX_ID_WIDTH] The number of transfers is defined as length+1 read_channel_phase read_channel_phase is a unidirectional transaction passing a single word of data and status information from slave to master as part of a read transaction. It consists of a single write_resp_channel_phase. but only one may be active at any time. lock. id[AXI_MAX_ID_WIDTH] read_addr_channel_phase read_addr_channel_phase is a unidirectional transaction passing address and control information from master to slave as part of a read transaction. bit id[AXI_MAX_ID_WIDTH] ntransfers is the number of words (of size equal to the bus width) being transferred. www. bit strb[AXI_MAX_BURST_LENGTH][AXI_MAX_WSTRB_WIDTH]. determined by the RREADY signal. but only one may be active at any time. but only one may be active at any time. length[4]. determined by the ARREADY signal.

A write_channel_phase transaction may take multiple clock cycles to complete. data[AXI_MAX_RDATA_WIDTH]. write_channel_phase write_channel_phase is a unidirectional transaction passing a single word of data and strobe information from master to slave as part of a write transaction. but only one may be active at any time. cache. size. length[4]. id[AXI_MAX_ID_WIDTH] write_addr_channel_phase write_addr_channel_phase is a unidirectional transaction passing address and control information from master to slave as part of a write transaction. id[AXI_MAX_ID_WIDTH] The number of transfers is defined as length+1. but only one may be active at any time. id[AXI_MAX_ID_WIDTH] write_resp_channel_phase write_resp_channel_phase is a unidirectional transaction passing a status information from slave to master as part of a write transaction.if tort to your rights.cadfamily. data[AXI_MAX_WDATA_WIDTH]. prot. strb[AXI_MAX_WSTRB_WIDTH]. determined by the WREADY signal. burst. It consists of one or more write_addr_channel_cycle transactions.please inform us. A write_resp_channel_phase www.nTX User’s Guide and Tutorial Attributes: T_AXI_LAST bit T_AXI_RESPONSE bit last.com 122 The document is for study only. Attributes: T_AXI_LAST bit bit bit last. It consists of one or more write_resp_channel_cycle transactions. lock. It consists of one or more write_channel_cycle transactions. A write_addr_channel_phase transaction may take multiple clock cycles to complete. Attributes: bit bit T_AXI_SIZE T_AXI_BURST T_AXI_LOCK T_AXI_CACHE T_AXI_PROT bit addr[AXI_MAX_ADDRESS_WIDTH].we will delete .com EMail:cadserv21@hotmail. determined by the AWREADY signal. resp.

One or more read_channel_cycles make up a read_channel_phase. size. Each write_addr_channel_cycle groups the set of write address channel signals and synchronizes them to a clock. prot.com EMail:cadserv21@hotmail.Appendix D: AMBA AXI Transactor transaction may take multiple clock cycles to complete. cache. id[AXI_MAX_ID_WIDTH] read_channel_cycle read_channel_cycle is a unidirectional transaction lasting a single clock cycle on the bus. burst. Attributes: T_AXI_VALID T_AXI_LAST bit T_AXI_RESPONSE bit valid. Attributes: T_AXI_VALID bit bit T_AXI_SIZE T_AXI_BURST T_AXI_LOCK T_AXI_CACHE T_AXI_PROT bit valid. the number of which is determined by ARREADY. with only one active at a time. resp. Each read_channel_cycle groups the set of read channel signals (for data/response) and synchronizes them to a clock.please inform us. determined by the BREADY signal. but only one may be active at any time. id[AXI_MAX_ID_WIDTH] read_addr_channel_cycle read_addr_channel_cycle is a unidirectional transaction lasting a single clock cycle on the bus.if tort to your rights. One or more read_addr_channel_cycles make up a read_addr_channel_phase.com 123 The document is for study only. addr[AXI_MAX_ADDRESS_WIDTH]. the number of which is determined by RREADY. with only one active at a time. data[AXI_MAX_RDATA_WIDTH]. Each read_addr_channel_cycle groups the set of read address channel signals and synchronizes them to a clock. lock. id[AXI_MAX_ID_WIDTH] write_addr_channel_cycle write_addr_channel_cycle is a unidirectional transaction lasting a single clock cycle on the bus.cadfamily. length[4]. Attributes: T_AXI_RESPONSE bit resp. www. last. with only one active at a time.we will delete .

length[4].com 124 The document is for study only. Attributes: T_AXI_VALID T_AXI_RESPONSE bit valid. with only one active at a time. with only one active at a time.nTX User’s Guide and Tutorial One or more write_addr_channel_cycles make up a write_addr_channel_phase. id[AXI_MAX_ID_WIDTH] read_addr_channel_ready This item lasts a single clock cycle on the bus. id[AXI_MAX_ID_WIDTH] write_channel_cycle write_channel_cycle is a unidirectional transaction lasting a single clock cycle on the bus.we will delete .com EMail:cadserv21@hotmail.cadfamily. resp. One or more write_resp_channel_cycles make up a write_resp_channel_phase. This item synchronizes the ARREADY signal to the clock. cache. and only one can be active at a time. the number of which is determined by AWREADY. the number of which is determined by BREADY. id[AXI_MAX_ID_WIDTH] write_resp_channel_cycle write_resp_channel_cycle is a unidirectional transaction lasting a single clock cycle on the bus. prot. addr[AXI_MAX_ADDRESS_WIDTH]. Attributes: T_AXI_VALID bit bit T_AXI_SIZE T_AXI_BURST T_AXI_LOCK T_AXI_CACHE T_AXI_PROT bit valid. the number of which is determined by WREADY. burst. Attributes: T_AXI_VALID T_AXI_LAST bit bit bit valid. last. One or more write_channel_cycles make up a write_channel_phase. strb[AXI_MAX_WSTRB_WIDTH]. Each write_resp_channel_cycle groups the set of write response channel signals and synchronizes them to a clock. lock. Each write_channel_cycle groups the set of write channel signals (for data/strobe) and synchronizes them to a clock. data[AXI_MAX_WDATA_WIDTH].if tort to your rights.please inform us. Attributes: www. size.

Attributes: T_AXI_READY ready write_addr_channel_ready This item lasts a single clock cycle on the bus. Name ACLK ARESETn ARVALID ARADDR Type bit bit bit Direction clock_source to master.com 125 The document is for study only. Attributes: T_AXI_READY ready write_resp_channel_ready This item lasts a single clock cycle on the bus. and only one can be active at a time.please inform us.if tort to your rights. This item synchronizes the BREADY signal to the clock.we will delete . see the section on Signal Descriptions in the AMBA AXI Protocol Specification. and only one can be active at a time. and only one can be active at a time.cadfamily. and only one can be active at a time.com EMail:cadserv21@hotmail. size AXI_ADDRESS_WIDTH master to slave www. This item synchronizes the RREADY signal to the clock. Attributes: T_AXI_READY ready write_channel_ready This item lasts a single clock cycle on the bus. This item synchronizes the AWREADY signal to the clock.Appendix D: AMBA AXI Transactor T_AXI_READY ready read_channel_ready This item lasts a single clock cycle on the bus. slave and reset_source reset_source to master and slave master to slave bit array. This item synchronizes the WREADY signal to the clock. Attributes: T_AXI_READY ready Wires For a description of each of these wires (signals).

com EMail:cadserv21@hotmail.cadfamily. size AXI_WDATA_WIDTH bit array. size 2 bit array. size 3 bit array.nTX User’s Guide and Tutorial Name ARLEN ARSIZE ARBURST ARLOCK ARCACHE ARPROT ARID ARREADY AWVALID AWADDR AWLEN AWSIZE AWBURST AWLOCK AWPROT AWID RVALID RLAST RDATA RRESP RID RREADY WVALID WLAST WDATA WSTRB WID WREADY BVALID BRESP Type bit array. size 4 AWREADY bit www. size 2 bit array. size AXI_ADDRESS_WIDTH master to slave AWCACHE bit array. size AXI_ID_WIDTH bit bit bit array.we will delete . size 4 bit array.if tort to your rights.please inform us. size 2 bit array. size AXI_ID_WIDTH bit bit bit array. size AXI_WSTRB_WIDTH bit array.com 126 The document is for study only. size 2 bit array. size 3 bit array. size 3 bit array. size 2 Direction master to slave master to slave master to slave master to slave master to slave master to slave master to slave slave to master master to slave master to slave master to slave master to slave master to slave master to slave master to slave master to slave slave to master slave to master slave to master slave to master slave to master slave to master master to slave master to slave master to slave master to slave master to slave master to slave slave to master slave to master slave to master bit array. size AXI_ID_WIDTH bit bit bit array. size 4 bit array. size 2 bit array. size 3 bit array. size 4 bit array. size AXI_RDATA_WIDTH bit array. size AXI_ID_WIDTH bit bit bit bit array.

VALID = 1 }. // Last phase in burst transfer type enum T_AXI_LAST:1 { MORE_TO_COME = 0. such as ‘int’.we will delete .com 127 The document is for study only. BYTES_2 = 1. BYTES_4 = 2. write_addr_channel_cycle_invalid.please inform us. These are identical to the read_addr_channel_cycle. www. with the exception that they represent cycles where the valid signal is low. write_channel_cycle_invalid and write_resp_channel_cycle_invalid are also available.com EMail:cadserv21@hotmail. write_addr_channel_cycle.Appendix D: AMBA AXI Transactor Name BID BREADY Type bit array.cadfamily. LAST = 1 }. // Word size encoding type enum T_AXI_SIZE:3 { BYTES_1 = 0. read_channel_cycle. read_channel_cycle_invalid. write_channel_cycle and write_resp_channel_cycle.if tort to your rights. the AXI transactor makes use of the following types: // Validity of a channels signals type enum T_AXI_VALID:1 { INVALID = 0. size AXI_ID_WIDTH bit Direction slave to master master to slave Additional Communication Items Additional items read_addr_channel_cycle_invalid. and ‘bit’. Additional Information Data Types In addition to the standard transactor types.

BYTES_16 = 4.cadfamily. RESERVED_0100 = 4. RESERVED = 3 }. WRAP = 2.com EMail:cadserv21@hotmail. NORM_NONSEC_DATA = PRIV_NONSEC_DATA = NORM_SEC_INST = 4. RESERVED_1100 = 12. // Burst type . www.please inform us. CACHE_WTHROUGH_ALLOC_R_ONLY = 6. BYTES_128 = 7 }. 3. BUF_ONLY = 1. PRIV_SEC_DATA = 1. CACHE_WBACK_ALLOC_RW = 15 }. RESERVED_1000 = 8.if tort to your rights. CACHE_WBACK_ALLOC_W_ONLY = 11. RESERVED_0101 = 5. CACHE_BUF_NOALLOC = 3. CACHE_WTHROUGH_ALLOC_RW = 14. INCR = 1. RESERVED_1001 = 9.we will delete . CACHE_WBACK_ALLOC_R_ONLY = 7. CACHE_NOALLOC = 2. BYTES_32 = 5.determines address calculation type enum T_AXI_BURST:2 { FIXED = 0. BYTES_64 = 6. // Protection type type enum T_AXI_PROT:3 { NORM_SEC_DATA = 0. 6. CACHE_WTHROUGH_ALLOC_W_ONLY = 10. 7 // Cache type type enum T_AXI_CACHE:4 { NONCACHE_NONBUF = 0. 2. PRIV_SEC_INST = 5. RESERVED_1101 = 13. NORM_NONSEC_INST = PRIV_NONSEC_INST = }.com 128 The document is for study only.nTX User’s Guide and Tutorial BYTES_8 = 3.

if tort to your rights.we will delete .com EMail:cadserv21@hotmail. Transactor Constants • • • • • • • • AXI_MAX_ADDRESS_WIDTH – the maximum width of the address bus (read and write) AXI_MAX_ID_WIDTH – the maximum width of the id bus (read and write) AXI_MAX_RDATA_WIDTH – the maximum width of the read data bus AXI_MAX_WDATA_WIDTH – the maximum width of the write data bus AXI_MAX_WSTRB_WIDTH – the maximum width of the write strobe bus AXI_MAX_RDATA_LENGTH – the maximum number of bytes in an AXI_read transfer AXI_MAX_WDATA_LENGTH – the maximum number of bytes in an AXI_write transfer AXI_MAX_BURST_LENGTH – the maximum number of words in a burst www. DECERR = 3 }. EXCLUSIVE = 1.please inform us. READY = 1 }. // Ready signal values type enum T_AXI_READY:1 { WAIT = 0.Appendix D: AMBA AXI Transactor // Response type type enum T_AXI_RESPONSE:2 { OKAY = 0. SLVERR = 2.cadfamily. // Lock type for atomic accesses type enum T_AXI_LOCK:2 { NORMAL = 0. EXOKAY = 1. RESERVED = 3 }.com 129 The document is for study only. LOCKED = 2.

please inform us.com EMail:cadserv21@hotmail.nTX User’s Guide and Tutorial www.cadfamily.com 130 The document is for study only.we will delete .if tort to your rights.

please inform us. BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description.if tort to your rights.com 131 The document is for study only.cadfamily. nte_MPEG2_TS_v1p0_ns MyMPEG2_TS_1 { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.com EMail:cadserv21@hotmail. MAPPING_ROOT = "/MPEG_TS_top_level/MPEG_structure/the_transport_stream". Name The bus declaration (nte_MPEG_TS_v1p0_ns) must be one of the supported transactors. Byte-wide data bus. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements.we will delete . www.Appendix E: MPEG2_TS Transactor Appendix E: MPEG2_TS Transactor Overview The MPEG_TS Transactor supports the following features: • • • • ISO/IEC 13818-1:2000 Audio/Video qualifier. Optional Adaptation Field.

The transactor signals are pre-defined as shown in the file below and must not be changed. An example is shown below: • • • • Figure: Clock Setup www. sync_byte: Defaults to 0x47. clk_phase_shift: The time of the first transition from the initial value. = "/MPEG2_TS_audio_video". clk_1st_time: The relative time of the first clock change after the initial phase shift change. • setup_time: The setup time for all MPEG2 TS signals. NOTE: Clock can be mapped to /MPEG2_TS/MPEG2_TS_clock. If this is done they will be assigned a default value (normally 0). • clk_2nd_time: The relative time of second clock change after the previous change. Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file.please inform us.nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side.we will delete .com EMail:cadserv21@hotmail. "/MPEG2_TS_valid".com 132 The document is for study only. The available parameters are: clk_init_value: The initial value of the clock (0 or 1). however.cadfamily. • hold_time: The hold time for all MPEG2 TS signals.if tort to your rights. Configuration of the transactor is made via the PARAMETER section of the bcf file. it is possible to leave signals unconnected by removing them from the sigmap section. The SIGMAP code example is for an unmapped clock. "/MPEG2_TS_data". The clock set up is important to the correct operation of the transactor. SIGMAP { /MPEG2_TS/MPEG2_TS_sync = /MPEG2_TS/MPEG2_TS_audio_video /MPEG2_TS/MPEG2_TS_valid = /MPEG2_TS/MPEG2_TS_data = } "/MPEG2_TS_sync".

adaptation_header_phase.cadfamily. This transaction is then made up of phases. where ‘ver’ and ‘tu’ have the following meanings and valid values: • • ‘ver’ – version (‘v1p0’) ‘tu’ – time unit (‘ps’. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor. ‘ns’. This does not have to match the time scale of the input FSDB file.com 133 The document is for study only. 1 ns. Transactor Configurations A number of transactor configurations are available.com EMail:cadserv21@hotmail.if tort to your rights. In this section the function. ‘fs’). e.please inform us. 50 ns. sync_phase. 1 ns. optional_fields_phase and payload_phase. The protocol tree shows how the transactions are inter-related. 50 ns. The MPEG2_TS Transactor recognizes transactions from the transport stream active signals. www. 50 ns. At the highest level is a transaction (stream_packet_phase) representing a complete MPEG2 packet. however. types and attributes of these transactions are described in detail.g.Appendix E: MPEG2_TS Transactor // parameters PARAMETER { clk_init_value sync_byte clk_phase_shift clk_1st_time clk_2nd_time setup_time hold_time } = = = = = = = 0b0. 0x47. any signal changes below this time resolution will not be seen by nTE. If the clock is mapped then clk_* parameters do not need to be set. header_phase.we will delete . The naming convention used is nte_MPEG2_TS_‘ver’_‘tu’. Transaction Hierarchy The transactor consists of a number of transactions that enable communication at different levels of abstraction. NOTE: PARAMETER code example is for an unmapped clock.

com EMail:cadserv21@hotmail.com 134 The document is for study only.if tort to your rights.cadfamily.please inform us.we will delete .nTX User’s Guide and Tutorial Protocol Tree www.

Attributes: T_MPEG_TS_transport_packet_header transport_packet_header. stream_packet_phase stream_packet_phase is a uni-directional transaction used for complete transport packet transfers. ts_start_indicator. T_MPEG_TS_transport_adaptation_header transport_adaptation_header. ts_identifier[13]. www. byte transport_optional_fields[].Appendix E: MPEG2_TS Transactor Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer. Attributes: bit bit ts_adaptation_header_length[8]. header_phase header_phase is a uni-directional transaction used to transfer the 4-byte header. ts_continuity[4] adaptation_header_phase adaptation_header_phase is a uni-directional transaction used to transfer the adaptation field.we will delete .if tort to your rights. ts_adaptation_field. Attributes: none. ts_payload_flag.cadfamily.please inform us.com EMail:cadserv21@hotmail. ts_adaptation_header_flags[8].com 135 The document is for study only. from the unit to the left of the symbol. to the unit (or units) to the right of the symbol. ts_scrambling[2]. byte transport_packet_payload[] sync_phase sync_phase is a uni-directional transaction used to indicate the start of a packet and to transfer the sync byte 0x47. Attributes: bit bit bit bit bit bit bit bit ts_error_indicator. ts_priority.

please inform us. Attributes: byte data[] payload_phase payload_phase is a uni-directional transaction used to transfer the packet payload.cadfamily. Attributes: bit bit sync.if tort to your rights. Attributes: bit av MUX_S >=> master stream_valid_byte stream_valid_byte is a uni-directional transaction used to transfer a valid byte. Attributes: bit bit bit sync.nTX User’s Guide and Tutorial optional_fields_phase optional_fields_phase is a uni-directional transaction used a to transfer optional fields. Attributes: byte data[] stream_av_phase stream_av_phase is a uni-directional transaction used to transfer the phase. valid. data[8] stream_packet_stripe stream_packet_stripe is a uni-directional transaction used to transfer a packet.com 136 The document is for study only.com EMail:cadserv21@hotmail. data[8] stream_packet_av_stripe stream_packet_av_stripe is a uni-directional transaction used to indicate an audio or video packet. Attributes: bit av www.we will delete .

cadfamily. size 8 Direction source >=> destination source >=> destination source >=> destination source >=> destination source >=> destination www.we will delete . Name MPEG_TS_clock MPEG_TS_sync MPEG_TS_audio_video MPEG_TS_valid MPEG_TS_data[8] Type bit bit bit bit bit array.Appendix E: MPEG2_TS Transactor Wires For a description of each of these wires (signals).please inform us.com 137 The document is for study only. see the section on Signal Descriptions in the MPEG2_TS Protocol Specification.com EMail:cadserv21@hotmail.if tort to your rights.

nTX User’s Guide and Tutorial Additional Information Data Types In addition to the standard transactor types. and ‘bit’. www. //Priority indicator //Identifies the content //of the packet //Transport //scrambling type bit bit bit transport_scrambling_flags[2]. continuity_counter[4].com EMail:cadserv21@hotmail.if tort to your rights. packet_identifier[13].please inform us.com 138 The document is for study only. }. bit adaptation_field_flag. the MPEG2 TS transactor makes use of the following types: type struct T_MPEG_TS_transport_packet_header { bit transport_error_indicator.cadfamily. //PUSI start of PES //in the packet transport_priority. //EI indicates error //from previous stages bit payload_unit_start_indicator. //Presence of adaptation //field in packet //Presence of payload //data in the packet //Between truncated PES //portions bit payload_flag. bit }. type struct T_MPEG_TS_transport_adaptation_header { bit adaptation_field_length[8].we will delete . such as ‘int’. bit adaptation_flags[8].

Appendix F: OCP-IP Transactor Appendix F: OCP-IP Transactor Overview The OCP-IP Transactor supports the following features: • • • • OCP-IP Release 2. data. BurstPrecise = 0 not supported. Incomplete support for sideband/test signals BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description.0 specification is covered by the OCP transactor.com EMail:cadserv21@hotmail. etc. However the following limitations exist with the current version: • • • OCP ordering model currently unsupported for transactions on same thread. nte_OCP_IP_v1p0_32_32_16_8_ns myOCP { www.com 139 The document is for study only.we will delete .please inform us.cadfamily.0 (see Limitations below) Configurable bus widths (address. thread ID. Name The bus declaration (nte_OCP_IP_v1p0_32_32_16_8_ns) must be one of the supported transactors.) Recognition of complete bursts as a single transaction Out-of-order transaction completion Limitations Over 90% of the OCP-IP 2.if tort to your rights.

"/MDataLast". The SIGMAP code example is for an unmapped clock.if tort to your rights. it is possible to leave signals unconnected by removing them from the sigmap section. "/SCmdAccept". // simple OCP extensions /OCP/MAddrSpace = /OCP/MByteEn = /OCP/MDataByteEn = /OCP/MDataInfo = /OCP/MReqInfo = /OCP/SDataInfo = /OCP/SRespInfo = // OCP burst extensions /OCP/MAtomicLength /OCP/MBurstLength /OCP/MBurstPrecise /OCP/MBurstSeq /OCP/MBurstSingleReq /OCP/MDataLast /OCP/MReqLast "/MAddrSpace". "/MDataValid". "/SDataInfo". "/MBurstSingleReq". "/SRespInfo". "/MDataInfo". SIGMAP { // basic OCP signals /OCP/MAddr /OCP/MCmd /OCP/MData /OCP/MDataValid /OCP/MRespAccept /OCP/SCmdAccept /OCP/SData /OCP/SDataAccept /OCP/SResp = = = = = = = = = "/MAddr". "/MByteEn". "/SResp". "/MDataByteEn". "/SDataAccept". "/MRespAccept".please inform us. "/MBurstPrecise". "/SData". If this is done they will be assigned a default value (normally 0). "/MData". NOTE: Clock can be mapped to /OCP/Clk. however. = = = = = = = "/MAtomicLength". "/MBurstLength". "/MReqLast".com EMail:cadserv21@hotmail.com 140 The document is for study only.we will delete . www. "/MBurstSeq".cadfamily. "/MCmd". Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side.nTX User’s Guide and Tutorial Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed. "/MReqInfo". This is prefixed to the signal names specified on the right hand side of the SIGMAP statements. The transactor signals are pre-defined as shown in the file below and must not be changed. MAPPING_ROOT = "/default_config_recognition/str/iOCP".

/OCP/SInterrupt = "/SInterrupt". = = = = = = = = = = "/Scanctrl". /OCP/SReset_n = "/SReset_n". These can be seen in the example below using values as allowed by the OCP specification. "/ControlWr". This is where the OCP configuration and the default values of the OCP wires must be set.com EMail:cadserv21@hotmail. "/SThreadID". /OCP/SFlag = "/SFlag". Configuration of the transactor is made via the PARAMETER section of the bcf file. /OCP/SError = "/SError". "/TCK". /OCP/MFlag = "/MFlag".we will delete . The available parameters are: www. /OCP/MReset_n = "/MReset_n". "/Scanin".cadfamily. "/Status". "/StatusBusy".please inform us. "/MThreadID". Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file.if tort to your rights. "/StatusRd". "/ControlBusy". // OCP thread extensions /OCP/MConnID = /OCP/MDataThreadID = /OCP/MThreadBusy = /OCP/MThreadID = /OCP/SDataThreadBusy = /OCP/SThreadBusy = /OCP/SThreadID = "/MConnID". "/TDO". "/SThreadBusy". // sideband OCP signals /OCP/MError = "/MError". "/TestClk". "/TDI". "/ClkByp".Appendix F: OCP-IP Transactor /OCP/SRespLast = "/SRespLast". "/Scanout". "/MThreadBusy".com 141 The document is for study only. "/TMS". /OCP/Control /OCP/ControlBusy /OCP/ControlWr /OCP/Status /OCP/StatusBusy /OCP/StatusRd // test OCP signals /OCP/Scanctrl /OCP/Scanin /OCP/Scanout /OCP/ClkByp /OCP/TestClk /OCP/TCK /OCP/TDI /OCP/TDO /OCP/TMS /OCP/TRST_N } = = = = = = "/Control". "/MDataThreadID". "/SDataThreadBusy". "/TRST_N".

0. 0. LITTLE. = 0. = 0. www.cadfamily. = 1. • setup_time: The setup time for all OCP signals • hold_time: The hold time for all OCP signals The clock set up is important to the correct operation of the transactor. • clk_2nd_time: The relative time of second clock change after the previous change. An example is shown below: • • • Figure: Clock Setup // parameters PARAMETER { //Protocol broadcast_enable burst_aligned burstseq_dflt1_enable burstseq_dflt2_enable burstseq_incr_enable burstseq_strm_enable burstseq_unkn_enable burstseq_wrap_enable burstseq_xor_enable endian force_aligned mthreadbusy_exact rdlwrc_enable read_enable readex_enable sdatathreadbusy_exact sthreadbusy_exact write_enable writenonpost_enable //Phase datahandshake reqdata_together writeresp_enable //Signal (Dataflow) addr addr_wdth addrspace = = = = = = = = = = = = = = = = = = = 0.com EMail:cadserv21@hotmail. 0. clk_phase_shift: The time of the first transition from the initial value. = 0. 1. 0. clk_1st_time: The relative time of the first clock change after the initial phase shift change.com 142 The document is for study only. = 0. 0. 0.nTX User’s Guide and Tutorial clk_init_value: The initial value of the clock (0 or 1). 1.please inform us.we will delete . 1. 0. 0.if tort to your rights. 0. 0. 0. 0. 0. 0. = 32.

Appendix F: OCP-IP Transactor addrspace_wdth atomiclength atomiclength_wdth burstlength burstlength_wdth burstprecise burstseq burstsinglereq byteen cmdaccept connid connid_wdth dataaccept datalast data_wdth mdata mdatabyteen mdatainfo mdatainfo_wdth mdatainfobyte_wdth mthreadbusy reqinfo reqinfo_wdth reqlast resp respaccept respinfo respinfo_wdth resplast sdata sdatainfo sdatainfo_wdth sdatainfobyte_wdth sdatathreadbusy sthreadbusy threads //Signal (Sideband) control controlbusy control_wdth controlwr interrupt merror mflag mflag_wdth mreset serror sflag sflag_wdth sreset status statusbusy statusrd status_wdth //Signal (Test) clkctrl_enable jtag_enable jtagtrst_enable = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 2. 1. 0. 0. 0. 0. 0. 0.please inform us. 0. 0. = 0. = 0. 0. 2. 0. 0. 2.we will delete . 0. 1. 1. 1. 0. 0. 2. 0. 0. 0.if tort to your rights. 2. 0. 0. 0. 0. 0. 0. 2.com 143 The document is for study only.com EMail:cadserv21@hotmail. 0. 8. 2. 0. 1. 1. 0. 8. 2. 4. 0. 1.cadfamily. www. 0. 0. 0. 0. 2. 32. 0. 0. = 0.

0xF. 0. 0. 0. 0. = 2. 0. 0. = = = = = = = = = = 0. 0. 0. 0. // simple OCP extensions default_MaddrSpace = default_MbyteEn = default_MdataByteEn = default_MdataInfo = default_MreqInfo = default_SdataInfo = default_SrespInfo = // OCP burst extensions default_MatomicLength default_MburstLength default_MburstPrecise default_MburstSeq default_MburstSingleReq default_MdataLast default_MreqLast default_SrespLast = = = = = = = = // OCP thread extensions default_MconnID = default_MdataThreadID = default_MthreadBusy = default_MthreadID = default_SdataThreadBusy = default_SthreadBusy = default_SthreadID = // sideband OCP signals default_Merror default_Mflag default_MReset_n default_Serror default_Sflag default_Sinterrupt default_SReset_n default_Control default_ControlBusy default_ControlWr default_Status default_StatusBusy default_StatusRd = = = = = = = = = = = = = www. 1. 0. 0. 0. 0. 1. 0. 0.com EMail:cadserv21@hotmail. 1. 0. 0. = 0. 0xF.we will delete . 0. 0.please inform us. 0. 0. 1.if tort to your rights. 1. 1. 0. 0. 0. 0. 0. 0. 0. 0. 0. 1. 0. 0.cadfamily. 0.com 144 The document is for study only.nTX User’s Guide and Tutorial scanctrl_wdth scanport scanport_wdth // basic OCP signals default_Clk default_MAddr default_MCmd default_Mdata default_MdataValid default_MrespAccept default_ScmdAccept default_Sdata default_SdataAccept default_Sresp = 2. 1. 0.

0. 0 ns. 256) ‘threads’ – number of threads (16) ‘blw’ – burst length width (8) ‘tu’ – time unit (‘ps’. 0. 1 ns. ‘fs’). } NOTE: PARAMETER code example is for an unmapped clock. 0. any signal changes below this time resolution will not be seen by nTE. 0.Appendix F: OCP-IP Transactor // test OCP signals default_Scanctrl default_Scanin default_Scanout default_ClkByp default_TestClk default_TCK default_TDI default_TDO default_TMS default_TRST_N // clock frequency clk_init_value clk_phase_shift clk_1st_time clk_2nd_time setup_time hold_time = = = = = = = = = = = = = = = = 0. 0. 1. 5 ns. 1 ns.com EMail:cadserv21@hotmail.please inform us. 0. The naming convention used is nte_OCP_IP_‘ver’_‘aw’_‘dw’_‘threads’_‘blw’_‘tu’ where ‘ver’. When the required configuration is not available. an transactor with bus widths greater than those required should be used. These and other run-time parameters must be configured using the PARAMETER section of the bcf file. If the clock is mapped then clk_* parameters do not need to be set. 0. ‘dw’.we will delete . ‘blw’ and ‘tu’ have the following meanings and valid values: ‘ver’ – version (‘v1p0’) ‘aw’ – address width (32) ‘dw’ – data width (16.if tort to your rights. 64. 32. Transactor Configurations A number of transactor configurations are available. ‘ns’. 5 ns. 0.cadfamily. however.com 145 The document is for study only. ‘aw’. 128. This does not have to match the time scale of the input FSDB file. 0. ‘threads’. • • • • • • www.

we will delete .com EMail:cadserv21@hotmail. types and attributes of these transactions are described in detail. In this section the function.please inform us. www.cadfamily.if tort to your rights.com 146 The document is for study only. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor.nTX User’s Guide and Tutorial Transaction Hierarchy The transactor consists of a number of transactions that enable communication at different levels of abstraction.

com EMail:cadserv21@hotmail.please inform us.Appendix F: OCP-IP Transactor Protocol Tree www.we will delete .cadfamily.com 147 The document is for study only.if tort to your rights.

NOTE: The size of a number of the attributes is dependant on the transactor Readburst Readburst is a bidirectional read transaction between the master and slave. There can be multiple outstanding (concurrent) reads. These can overlap due to pipe-lining and the use of the ThreadID signal.nTX User’s Guide and Tutorial Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer.com 148 The document is for study only.we will delete . and is specified in the form ‘bit attribute_name[C_constant]’ (see Transactor Constants). from the unit to the left of the symbol. One or more Sresponse_phase transactions return the requested data and response status from slave to master. configuration in use. Attributes: MCmd_encoding Rcmd master >=> slave bit Addr[(1<<OCP_burstlength_wdth)-1][OCP_addr_wdth] master >=> slave bit AddrSpace[OCP_addrspace_wdth] master >=> slave bit ReqInfo[OCP_reqinfo_wdth] master >=> slave bit BurstLength[OCP_burstlength_wdth] master >=> slave bit BurstPrecise master >=> slave MBurstSeq_encoding BurstSeq master >=> slave bit BurstSingleReq master >=> slave bit AtomicLength[OCP_atomiclength_wdth] master >=> slave bit ConnID[OCP_connid_wdth] master >=> slave bit ThreadID[OCP_log2_threads] master >=> slave bit ByteEnable[(1<<OCP_burstlength_wdth)-1][OCP_data_wdth/8] master >=> slave bit Data[(1<<OCP_burstlength_wdth)-1][OCP_data_wdth] slave >=> master bit DataInfo[(1<<OCP_burstlength_wdth)-1][OCP_sdatainfo_wdth] slave >=> master SResp_encoding Resp[(1<<OCP_burstlength_wdth)-1] slave >=> master bit RespInfo[OCP_respinfo_wdth] slave >=> master Writeburst Writeburst is a (possibly) bidrectional write transaction between the master and slave.com EMail:cadserv21@hotmail.cadfamily. to the unit (or units) to the right of the symbol. If datahandshake is enabled then a Writeburst is made up of one or more www. One or more Mrequest_phase transactions pass address and control information from the master to the slave. with write data (and length) expressed in words of size equal to the bus width.if tort to your rights.please inform us.

Attributes: MCmd_encoding bit bit bit bit bit MBurstSeq_encoding bit Cmd.com EMail:cadserv21@hotmail. one or more Sresponse_phase transactions. It consists of one or more Mrequest transactions. Attributes: MCmd_encoding Wcmd master >=> slave bit Addr[(1<<OCP_burstlength_wdth)-1][OCP_addr_wdth] master >=> slave bit AddrSpace[OCP_addrspace_wdth] master >=> slave bit ReqInfo[OCP_reqinfo_wdth] master >=> slave bit BurstLength[OCP_burstlength_wdth] master >=> slave bit BurstPrecise master >=> slave MBurstSeq_encoding BurstSeq master >=> slave bit BurstSingleReq master >=> slave bit AtomicLength[OCP_atomiclength_wdth] master >=> slave bit ConnID[OCP_connid_wdth] master >=> slave bit ThreadID[OCP_log2_threads] master >=> slave bit ByteEnable[(1<<OCP_burstlength_wdth)-1][OCP_data_wdth/8] master >=> slave bit Data[(1<<OCP_burstlength_wdth)-1][OCP_data_wdth] master >=> slave bit DataInfo[(1<<OCP_burstlength_wdth)-1][OCP_sdatainfo_wdth] master >=> slave SResp_encoding Resp[(1<<OCP_burstlength_wdth)-1] slave >=> master bit RespInfo[OCP_respinfo_wdth] slave >=> master Mrequest_phase Mrequest_phase is a unidirectional transaction passing address and control information from master to slave as part of a Readburst or Writeburst transaction. BurstPrecise. These can overlap due to pipe-lining and the use of the ThreadID signal. BurstSingleReq.we will delete . but only one may be active at any time. www.Appendix F: OCP-IP Transactor Mrequest_phase transactions. Addr[OCP_addr_wdth].com 149 The document is for study only. AddrSpace[OCP_addrspace_wdth].please inform us. There can be multiple outstanding (concurrent) writes. one or more MwriteData_phase transactions and. ReqInfo[OCP_reqinfo_wdth].if tort to your rights. BurstLength[OCP_burstlength_wdth]. BurstSeq. A Mrequest_phase transaction may take multiple clock cycles to complete.cadfamily. if writeresp_enable is set. one or more Sresponse_phase transactions. if writeresp_enable is set. If datahandshake is not enabled then a Writeburst is made up of one or more MrequestData_phase transactions and.

Addr[OCP_addr_wdth].please inform us. DataLast www. ByteEnable[OCP_data_wdth/8]. A MwriteData_phase transaction may take multiple clock cycles to complete. ThreadID[OCP_log2_threads]. ThreadID[OCP_log2_threads]. BurstSeq. DataInfo[OCP_sdatainfo_wdth] MwriteData_phase MwriteData_phase is a unidirectional transaction passing data from master to slave as part of a Writeburst transaction. It consists of one or more MrequestData transactions. Attributes: bit bit bit bit bit ThreadID[OCP_log2_threads].com 150 The document is for study only. AddrSpace[OCP_addrspace_wdth]. ConnID[OCP_connid_wdth]. Data[OCP_data_wdth]. BurstLength[OCP_burstlength_wdth].cadfamily. BurstSingleReq.nTX User’s Guide and Tutorial bit bit bit bit bit AtomicLength[OCP_atomiclength_wdth].com EMail:cadserv21@hotmail. Data[OCP_data_wdth]. A MrequestData_phase transaction may take multiple clock cycles to complete. AtomicLength[OCP_atomiclength_wdth]. but only one may be active at any time. ByteEnable[OCP_data_wdth/8]. ConnID[OCP_connid_wdth]. DataByteEn[OCP_data_wdth/8]. DataInfo[OCP_mdatainfo_wdth]. BurstPrecise. ReqLast MrequestData_phase MrequestData_phase is a unidirectional transaction passing control and data information from master to slave as part of a Writeburst transaction. It consists of one or more MwriteData transactions.if tort to your rights. ReqInfo[OCP_reqinfo_wdth].we will delete . ReqLast. Attributes: MCmd_encoding bit bit bit bit bit MBurstSeq_encoding bit bit bit bit bit bit bit bit Cmd. but only one may be active at any time.

ReqLast MrequestData MrequestData is a unidirectional transaction passing address and control and write data information from master to slave as part of a MrequestData_phase transaction.Appendix F: OCP-IP Transactor Sresponse_phase Sresponse_phase is a unidirectional transaction passing read data and read/write status information from slave to master as part of a Readburst or Writeburst transaction. Data[OCP_data_wdth]. A Sresponse_phase transaction may take multiple clock cycles to complete. ReqInfo[OCP_reqinfo_wdth]. DataInfo[OCP_sdatainfo_wdth].if tort to your rights. Resp. ThreadID[OCP_log2_threads]. BurstLength[OCP_burstlength_wdth].please inform us. www. BurstSingleReq. Attributes: MCmd_encoding bit bit Cmd. BurstPrecise. ByteEnable[OCP_data_wdth/8]. BurstSeq.com EMail:cadserv21@hotmail. It consists of one or more Sresponse transactions. RespLast Mrequest Mrequest is a unidirectional transaction passing address and control information from master to slave as part of a Mrequest_phase transaction. It takes a single clock cycle to complete and only one may be active at any time.we will delete . Addr[OCP_addr_wdth]. RespInfo[OCP_respinfo_wdth]. It takes a single clock cycle to complete and only one may be active at any time.com 151 The document is for study only. AtomicLength[OCP_atomiclength_wdth]. Addr[OCP_addr_wdth]. but only one may be active at any time. ConnID[OCP_connid_wdth].cadfamily. Attributes: bit bit bit SResp_encoding bit bit ThreadID[OCP_log2_threads]. AddrSpace[OCP_addrspace_wdth]. Attributes: MCmd_encoding bit bit bit bit bit MBurstSeq_encoding bit bit bit bit bit bit Cmd. AddrSpace[OCP_addrspace_wdth].

AtomicLength[OCP_atomiclength_wdth]. BurstPrecise.com EMail:cadserv21@hotmail. see the section on Signal Descriptions in the OCP-IP Protocol Specification. DataLast Sresponse Sresponse is a unidirectional transaction passing address and control and write data information from master to slave as part of a Sresponse_phase transaction. DataInfo[OCP_mdatainfo_wdth]. Data[OCP_data_wdth].com 152 The document is for study only. ConnID[OCP_connid_wdth]. It takes a single clock cycle to complete and only one may be active at any time. It takes a single clock cycle to complete and only one may be active at any time. BurstSingleReq. ByteEnable[OCP_data_wdth/8]. Data[OCP_data_wdth].nTX User’s Guide and Tutorial bit bit bit MBurstSeq_encoding bit bit bit bit bit bit bit bit ReqInfo[OCP_reqinfo_wdth]. BurstSeq.if tort to your rights. Name Clk Type bit Direction clock_source to master and slave www.please inform us. Attributes: bit bit bit bit bit ThreadID[OCP_log2_threads]. Attributes: bit bit bit SResp_encoding bit bit ThreadID[OCP_log2_threads]. ReqLast. RespLast Wires For a description of each of these wires (signals).we will delete .cadfamily. ThreadID[OCP_log2_threads]. DataInfo[OCP_sdatainfo_wdth]. DataInfo[OCP_sdatainfo_wdth] MwriteData MwriteData is a unidirectional transaction passing write data information from master to slave as part of a MwriteData_phase transaction. Data[OCP_data_wdth]. BurstLength[OCP_burstlength_wdth]. RespInfo[OCP_respinfo_wdth]. Resp. DataByteEn[OCP_data_wdth/8].

size OCP_datainfo_wdth bit array. size OCP_log2_threads bit array. size OCP_data_wdth/8 bit array. size OCP_addr_wdth bit bit bit bit array. size OCP_sdatainfo_wdth bit array. size 2 bit bit array. size OCP_reqinfo_wdth bit array.Appendix F: OCP-IP Transactor Name MAddr MCmd MData MDataValid MRespAccept SCmdAccept SData SDataAccept SResp MAddrSpace MByteEn MDataByteEn MDataInfo MReqInfo SDataInfo SRespInfo MAtomicLength MBurstLength MBurstPrecise MBurstSeq MBurstSingleReq MDataLast MReqLast SRespLast MConnID MDataThreadID MThreadBusy MThreadID SDataThreadBusy SThreadBusy SThreadID MError Type bit array. size OCP_burstlength_wdth master to slave master to slave master to slave master to slave master to slave master to slave slave to master master to slave master to slave master to slave master to slave slave to master slave to master slave to master master to slave www.cadfamily.com EMail:cadserv21@hotmail.if tort to your rights. size OCP_log2_threads bit array. size OCP_respinfo_wdth bit array. size 3 bit bit bit bit bit array.please inform us.we will delete . size OCP_addr_wdth bit array. size OCP_data_wdth/8 bit array. size OCP_threads bit array. size OCP_threads bit array. size 2 bit array.com 153 The document is for study only. size 3 bit array. size OCP_atomiclength_wdth bit bit array. size OCP_log2_threads bit Direction master to slave master to slave master to slave master to slave master to slave slave to master slave to master slave to master slave to master master to slave master to slave master to slave master to slave master to slave slave to master slave to master master to slave bit array. size OCP_addrspace_wdth bit array. size OCP_threads bit array. size OCP_connid_wdth bit array.

size OCP_sflag_wdth bit bit bit array.com 154 The document is for study only. size OCP_control_wdth bit bit bit array. size OCP_scanport_wdth bit array. size OCP_scanport_wdth bit array. size OCP_scanport_wdth bit bit bit bit bit bit bit Direction master to slave master to slave slave to master slave to master slave to master slave to master system to core core to system system to core core to system core to system system to core system to core system to core core to system system to core system to core system to core system to core core to system system to core system to core www.com EMail:cadserv21@hotmail.please inform us.nTX User’s Guide and Tutorial Name MFlag MReset_n SError SFlag SInterrupt SReset_n Control ControlBusy ControlWr Status StatusBusy StatusRd Scanctrl Scanin Scanout ClkByp TestClk TCK TDI TDO TMS TRST_N Type bit array.if tort to your rights.we will delete .cadfamily. size OCP_status_wdth bit bit bit array. size OCP_mflag_wdth bit bit bit array.

// core is big-endian www. // Unknown RSVD = 0b111 // Reserved }. // WriteNonPost WRC = 0b110. // Exclusive OR STRM = 0b101.we will delete . // ReadEx RDL = 0b100.com EMail:cadserv21@hotmail. // Write RD = 0b010. and ‘bit’. // Response encoding type enum SResp_encoding:2 { NULL = 0b00.please inform us. // Wrapping DFLT2 = 0b011. // No response DVA = 0b01. such as ‘int’. // Custom (packed) WRAP = 0b010.Appendix F: OCP-IP Transactor Additional Information Data Types In addition to the standard transactor types. // Data valid / accept FAIL = 0b10.com 155 The document is for study only. // core is little-endian BIG.if tort to your rights. // ReadLinked WRNP = 0b101. // Burst sequence encoding type enum MBurstSeq_encoding:3 { INCR = 0b000. // Custom (not packed) XOR = 0b100. // Idle WR = 0b001. // Incrementing DFLT1 = 0b001. // Streaming UNKN = 0b110. the AXI transactor makes use of the following types: // Command encoding type enum MCmd_encoding:3 { IDLE = 0b000. type enum endian_mode // no specific coding for this in the spec { LITTLE.cadfamily. // WriteConditional BCST = 0b111 // Broadcast }. // Request failed ERR = 0b11 // Response error }. // Read RDEX = 0b011.

Transactor Constants • • • • • • • • • • • • • • • • • • • • OCP_addr_wdth – the width of the MAddr bus OCP_data_wdth – the width of the MData and SData buses OCP_addrspace_wdth – the width of the MAddrSpace bus OCP_mdatainfo_wdth – the width of the MDataInfo bus OCP_mdatainfobyte_wdth – the size of the mdatainfo byte OCP_reqinfo_wdth – the width of MReqInfo OCP_sdatainfo_wdth – the width of SDataInfo OCP_sdatainfobyte_wdth – the size of the sdatainfo byte OCP_respinfo_wdth – the width of SRespInfo OCP_atomiclength_wdth – the width of MAtomicLength OCP_burstlength_wdth – the width of MBurstLength OCP_connid_wdth – the width of MConnID OCP_mflag_wdth – the width of MFlag OCP_sflag_wdth – the width of SFlag OCP_control_wdth – the width of Control OCP_status_wdth – the width of Status OCP_scanctrl_wdth – the width of Scanctrl OCP_scanport_wdth – the width of Scanin and Scanout OCP_threads – the number of threads (width of the *ThreadBusy buses) OCP_log2_threads – the width of MThreadID.cadfamily. memories. cores that deal only in OCP words) NEUTRAL }.if tort to your rights.please inform us.we will delete . CPUs) core has no inherent endianness (e.g.com 156 The document is for study only. SThreadID and SDataThreadID www. // // // // // core can be either big or little endian.g.nTX User’s Guide and Tutorial BOTH. depending on its static or dynamic configuration (e.com EMail:cadserv21@hotmail.

MAPPING_ROOT = "/tlp_dllp_idle_test2/PCI_express_structure/ PCI_Express_adaptor_I". nte_PCIe_v2p0_8_ns my_PCIe { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.we will delete . DLLP packet recognition.please inform us. Name The bus declaration (nte_PCIe_v2p0_8_ns) must be one of the supported transactors. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements. Configurable number of lanes. www.com EMail:cadserv21@hotmail.0a TLP packet recognition with matching completion. BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description.if tort to your rights. 'pad-or-idle' recognition.cadfamily. NTLP packet recognition.Appendix G: PCI-Express (PCIe) Transactor Appendix G: PCI-Express (PCIe) Transactor Overview The PCIe Transactor supports the following features: • • • • • • PCIe specification 1.com 157 The document is for study only.

NOTE: Clock can be mapped to /PCI_EXPRESS/PCLK0 and /PCI_EXPRESS/ PCLK1.com 158 The document is for study only. The parameter 'Differential_Wires' is used to indicate which set of signals transactions should be extracted from. /PCI_EXPRESS/D[0][4] = "/D[0][4]". /PCI_EXPRESS/D[1][4] = "/D[1][4]".cadfamily. /PCI_EXPRESS/D[0][3] = "/D[0][3]". /PCI_EXPRESS/D[1][1] = "/D[1][1]". // NB using 'SingleD' so Differential_Wires /PCI_EXPRESS/SingleD[0][1] = "/SingleD[0][1]". or single ended signals.if tort to your rights. /PCI_EXPRESS/D[1][6] = "/D[1][6]". /PCI_EXPRESS/D[0][7] = "/D[0][7]". The SIGMAP code examples are for an unmapped clocks. } Example using single ended signals: SIGMAP { /PCI_EXPRESS/SingleD[0][0] = "/SingleD[0][0]". /PCI_EXPRESS/D[1][3] = "/D[1][3]". /PCI_EXPRESS/D[1][5] = "/D[1][5]". however. PCI Express has two sets of signals. /PCI_EXPRESS/D[0][6] = "/D[0][6]". Example using differential pairs: SIGMAP { /PCI_EXPRESS/D[0][0] = "/D[0][0]". of which only one should be used.we will delete .com EMail:cadserv21@hotmail.please inform us. /PCI_EXPRESS/D[1][7] = "/D[1][7]". // must be set 'false' /PCI_EXPRESS/SingleD[0][2] = "/SingleD[0][2]". The following examples are for an 8 lane transactor. it is possible to leave signals unconnected by removing them from the sigmap section.nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side. /PCI_EXPRESS/D[1][2] = "/D[1][2]". depending on whether you are mapping to differential pairs. // NB using 'D' so Differential_Wires /PCI_EXPRESS/D[0][1] = "/D[0][1]". // must be set 'true' /PCI_EXPRESS/D[0][2] = "/D[0][2]". /PCI_EXPRESS/D[1][0] = "/D[1][0]". www. The transactor signals are pre-defined as shown in the file below and must not be changed. If this is done they will be assigned a default value (normally 0). and must be set correctly. /PCI_EXPRESS/D[0][5] = "/D[0][5]". signals must be removed or added for transactors with a fewer or greater number of lanes.

"/SingleD[0][6]". "/SingleD[1][3]". clk_phase_shift_1: The time of the first transition from the initial value for end 1. "/SingleD[0][5]". or single ended signals for each lane (true or false). clk_2nd_time_0: The relative time of second clock change after the previous change for end 0. "/SingleD[1][5]".please inform us.cadfamily.com 159 The document is for study only. "/SingleD[1][1]". otherwise. the 'SingleD' signals should be mapped. "/SingleD[0][4]".we will delete . "/SingleD[1][0]". It may be • www. clk_1st_time_1: The relative time of the first clock change after the initial phase shift change for end 1. clk_2nd_time_1: The relative time of second clock change after the previous change for end 1. If this is set to true. clk_init_value_0: The initial value of the clock for end 0 (0 or 1). Configuration of the transactor is made via the PARAMETER section of the bcf file. Use_request_complete: Use the TLP_request_complete transaction to link TLP requests with their completions (true or false).if tort to your rights. Differential_Wires: Use differential pairs. "/SingleD[1][6]".Appendix G: PCI-Express (PCIe) Transactor /PCI_EXPRESS/SingleD[0][3] /PCI_EXPRESS/SingleD[0][4] /PCI_EXPRESS/SingleD[0][5] /PCI_EXPRESS/SingleD[0][6] /PCI_EXPRESS/SingleD[0][7] /PCI_EXPRESS/SingleD[1][0] /PCI_EXPRESS/SingleD[1][1] /PCI_EXPRESS/SingleD[1][2] /PCI_EXPRESS/SingleD[1][3] /PCI_EXPRESS/SingleD[1][4] /PCI_EXPRESS/SingleD[1][5] /PCI_EXPRESS/SingleD[1][6] /PCI_EXPRESS/SingleD[1][7] } = = = = = = = = = = = = = "/SingleD[0][3]".com EMail:cadserv21@hotmail. "/SingleD[1][7]". "/SingleD[1][2]". clk_1st_time_0: The relative time of the first clock change after the initial phase shift change for end 0. clk_init_value_1: The initial value of the clock for end 1 (0 or 1). "/SingleD[0][7]". then each of the 'D' signals should be mapped. Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file. clk_phase_shift_0: The time of the first transition from the initial value for end 0. The available parameters are: • • • • • • • • • • PCI_Exp_Lanes: The number of lanes. "/SingleD[1][4]". Must be less than or equal to the maximum allowed by the specific transactor specified.

com EMail:cadserv21@hotmail.12. Transactor Configurations A number of transactor configurations are available.32) ‘tu’ – time unit (‘ps’. ‘ns’. www. The naming convention used is nte_PCIe_‘ver’_‘lanes’_‘tu’ where ‘ver’.2. //Use the 'D' (differential //pair) signals (true). An example is shown below: Figure: Clock Setup // parameters PARAMETER { PCI_Exp_Lanes = clk_init_value_0 = clk_init_value_1 = clk_phase_shift_0 = clk_phase_shift_1 = clk_1st_time_0 = clk_1st_time_1 = clk_2nd_time_0 = clk_2nd_time_1 = Differential_Wires } 8.8. the PCI_Exp_Lanes parameter cannot be set greater than this value (1. This does not have to match the time scale of the input FSDB file. ‘fs’). or //'SingleD' (single bit) //signals (false). The clock set up is important to the correct operation of the transactor. //initial value of clock[0] 0 ns. //First time period of clock[1] 1 ns.we will delete .4. or if the nTE is consuming too much memory during the extraction. //number of lanes 0 ns. //Second time period of clock[0] 1 ns.nTX User’s Guide and Tutorial useful to turn this off if only one direction is active. //phase shift of clock[1] 1 ns. If the clock is mapped then clk_* parameters do not need to be set.if tort to your rights.com 160 The document is for study only. //First time period of clock[0] 1 ns. //phase shift of clock[0] 1 ns. any signal changes below this time resolution will not be seen by nTE. Use_request_complete = true.16.please inform us. //Enable (true) or disable //(false) TLP_request_complete //transactions NOTE: PARAMETER code example is for an unmapped clock. ‘lanes’ and ‘tu’ have the following meanings and valid values: • • • ‘ver’ – version (‘v2p0’) ‘lanes’ – the maximum number of lanes. //initial value of clock[1] 1 ns. however. //Second time period of clock[1] = true.cadfamily.

we will delete .com 161 The document is for study only.com EMail:cadserv21@hotmail. types and attributes of these transactions are described in detail. Protocol Tree www.Appendix G: PCI-Express (PCIe) Transactor Transaction Hierarchy The transactor consists of a number of transactions that enable communication at different levels of abstraction.cadfamily.please inform us. In this section the function. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor.if tort to your rights.

com EMail:cadserv21@hotmail.please inform us.if tort to your rights. www. It is defined as an array of size 2.nTX User’s Guide and Tutorial Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer.com 162 The document is for study only.cadfamily. from the unit to the left of the symbol. one for each direction of the link. TLP_request_complete TLP_request_complete is a bi-directional transaction between PCIe endpoints.we will delete . to the unit (or units) to the right of the symbol. Attributes: e_TLP_Basic_Types request_type End_Unit[A] >=> End_Unit[B].

It is defined as an array of size 2.if tort to your rights. Note that the payload is an unsized array of bytes and will be set as appropriate to the transaction. Attributes: bit Sequence_Number[12] bool LCRC_Error e_TLP_detailed_Types Fmt_Type bit TC[3] bit Attr[2] bit TD bit EP bit Length[10] byte rest_of_header[12] byte data[] byte digest[4] NTLP_Packet NTLP_Packet is a uni-directional transaction used for the transfer of a Null TLP between End Units.com 163 The document is for study only. It is defined as an array of size 2. It is defined as an array of size 2. Attributes: e_AckNak bit bool AckNak_type Sequence_Number[12] CRC_16_Error DLLP_FC_Packet DLLP_FC_Packet is a uni-directional transaction used for the transfer of a DLL flow-control packet between End Units. one for each direction of the link.we will delete .com EMail:cadserv21@hotmail. one for each direction of the link.please inform us. It is defined as an array of size 2. Attributes: byte payload[] DLLP_AckNak_Packet DLLP_AckNak_Packet is a uni-directional transaction used for the transfer of a DLL ack/nack packet between End Units. one for each direction of the link.cadfamily.Appendix G: PCI-Express (PCIe) Transactor e_TLP_Basic_Types complete_type End_Unit[B] >=> End_Unit[A] TLP_Packet TLP_Packet is a unidirectional transaction used for the transfer of a TLP between End Units. Attributes: www. one for each direction of the link.

5 & D10.we will delete . one for each direction of the link. Attributes: Bit bool Vendor_Data[3][8] CRC_16_Error DLLP_Packet DLLP_Packet is a unidirectional transaction used for the transfer of a DLL packet between End Units. one for each direction of the link.if tort to your rights. one for each direction of the link.com EMail:cadserv21@hotmail.2 between End Units. one for each direction of the link. Attributes: e_Pm bool Pm_type CRC_16_Error DLLP_Vendor_Specific_Packet DLLP_Vendor_Specific_Packet is a uni-directional transaction used for the transfer of a DLL vendor specific packet between End Units. D21.please inform us. It is defined as an array of size 2. It is defined as an array of size 2.5. Attributes: bool delayed www.com 164 The document is for study only.cadfamily. Attributes: e_DLLP_Classes byte bool DLLP_class DLLP_payload[4] CRC_16_Error Compliance_OS Compliance_OS is a uni-directional transaction used to transfer the compliance pattern based on the sequence of 8b/10b Symbols K28. It is defined as an array of size 2. K28. It is defined as an array of size 2.nTX User’s Guide and Tutorial e_DLLP_Types e_DLLP_Msg_Subtype bit bit bit bool DLLP_Msg_Type DLLP_Msg_Subtype VC_ID[3] HdrFC[8] DataFC[12] CRC_16_Error DLLP_PM_Packet DLLP_PM_Packet is a uni-directional transaction used for the transfer of a DLL power management packet between End Units.5.

disable_link. one for each direction of the link. one for each direction of the link. The attribute ‘n’ refers to the number of SKP symbols in the ordered set (1. Attributes: bool bit bool bit bit bit bit bit bit bit bit link_number_valid. lane_number_valid. Attributes: none Skp_OS Skp_OS is a uni-directional transaction used to compensate for different bit rates for two communicating Ports between End Units. one for each direction of the link. Attributes: none Ts1_OS Ts1_OS is a uni-directional transaction used to indicate a Ts1 training sequence for initializing bit alignment. It is defined as an array of size 2. hot_reset. n_fts[8]. link_number[8]. data_rate_identifier[8].please inform us.5).if tort to your rights.. Symbol alignment and to exchange Physical Layer parameters between End Units.com EMail:cadserv21@hotmail.cadfamily. Attributes: word n FTS_OS FTS_OS is a uni-directional transaction used to indicate a Fast Training Sequence when moving from a L0s power-saving state to L0 normal state between End Units.we will delete . disable_scrambling. ts1_identifier[8] www. lane_number[8]. It is defined as an array of size 2. one for each direction of the link.Appendix G: PCI-Express (PCIe) Transactor Electrical_Idle_OS Electrical_Idle_OS is a uni-directional transaction used to indicate the state of the output drivers in which both lines of a link are driven to the DC common mode voltage. loopback.com 165 The document is for study only. It is defined as an array of size 2. It is defined as an array of size 2.

Symbol alignment and to exchange Physical Layer parameters between End Units. hot_reset. It is defined as an array of size 2. link_number[8]. Attributes: none PLLP_Packet PLLP_Packet is a uni-directional transaction used to transfer a PLL packet between End Units. ts2_identifier[8] pad_or_idle pad_or_idle is a uni-directional transaction used to transfer PAD or IDLE between End Units. one for each direction of the link. loopback. disable_link.com 166 The document is for study only. It is defined as a two-dimensional array of size 2. one for each direction of the link. n_fts[8]. or special Symbol) is being transmitted or received between End Units. one for each direction of the link. lane_number_valid. It is defined as an array of size 2. DLLPs. Attributes: none www. Attributes: e_PLLP_Types byte PLLP_Type payload[] Logical_Idle_Slice Logical_Idle_Slice is a uni-directional transaction to indicate when no information (TLPs. by the number_of_lanes. lane_number[8].if tort to your rights. Attributes: bool bit bool bit bit bit bit bit bit bit bit link_number_valid.please inform us. one for each direction of the link. data_rate_identifier[8].nTX User’s Guide and Tutorial Ts2_OS Ts2_OS is a uni-directional transaction used to indicate a Ts2 training sequence for initializing bit alignment.we will delete .cadfamily. It is defined as an array of size 2.com EMail:cadserv21@hotmail. disable_scrambling.

It is defined as a two-dimensional array of size 2 (one for each direction of the link) by the number_of_lanes. Attributes: e_Special_Symbols Special_Symbol Data_Byte Data_Byte is a uni-directional transaction used to transfer data bytes between End Units. It is defined as a two-dimensional array of size 2 (one for each direction of the link) by the number_of_lanes of duration 10*data_rate. one for each direction of the link.if tort to your rights.we will delete . by the number_of_lanes.cadfamily.com 167 The document is for study only. one for each direction of the link.Appendix G: PCI-Express (PCIe) Transactor Special_Symbols Special_Symbols is a uni-directional transaction used to transfer a Special Symbol between End Units.com EMail:cadserv21@hotmail. Attributes: Z_HGFEDCBA e_Validity z_byte Symbol_Validity Symbol Symbol is a uni-directional transaction used for the transfer of Symbols between End Units.please inform us. It is defined as a two-dimensional array of size 2 (one for each direction of the link) by the number_of_lanes. It is defined as a two-dimensional array of size 2. Attributes: bit abcdeifghj[10] www. Attributes: bit data_byte[8] Z_Byte Z_Byte is a uni-directional transaction used for the transfer of Special Symbols and Data Bytes. Attributes: bit bit Z HGFEDCBA[8] Pre_Encoded_Symbol Pre_Encoded_Symbol is a uni-directional transaction used for the transfer of preencoded symbols between End Units. by the number_of_lanes. It is defined as a two-dimensional array of size 2.

It is defined as a two-dimensional array of size 2 (one for each direction of the link) by the number_of_lanes.The data wires SingleD are non-differential. of duration equal to the data rate. Name RST D Type bit [2][number_of_lanes] bit [2] Direction Support >=> End_Unit [0] and End_Unit [1] End_Unit[0] >=> End_Unit[1] and End_Unit[1] >=> End_Unit[0] End_Unit[0] >=> End_Unit[1] and End_Unit[1] >=> End_Unit[0] SingleD [2][number_of_lanes] hdl_bit www.please inform us. of duration equal to the data_rate. Attributes: bit Differential_Data[2] Symbol_Single_Bit Symbol_Single_Bit is a uni-directional transaction used for the transfer of nondifferential Symbol bits between End Units. Attributes: hdl_bit Data Wires For a complete description of the link wires refer to section 4 of the PCIeTM Base Specification.we will delete . It is defined as a two-dimensional array of size 2 (one for each direction of the link) by the number of lanes. The data wires (D) are differential (implemented by the bit array bit[2]) and there are two End Units each having a number_of_lanes (implemented by [2][number_of_lanes]).com 168 The document is for study only.nTX User’s Guide and Tutorial Symbol_Bit Symbol_Bit is a uni-directional transaction used for the transfer of Symbols bits between End Units.if tort to your rights.com EMail:cadserv21@hotmail.cadfamily.

//Reserved CfgRd0 = 0b00_0_0100. Cpl = 11. CfgRd0 = 5. = 0b00_0_1101.we will delete . type enum e_TLP_detailed_Types:7 { MRd_32bit = 0b00_0_0000. such as ‘int’.Appendix G: PCI-Express (PCIe) Transactor Additional Information Data Types In addition to the standard transactor types. www. CfgRd1 = 7. IOWr = 4. CplLk = 13.com EMail:cadserv21@hotmail. 0b00_0_1010. IORd = 3.com 169 The document is for study only. //IO Read Request Reserved1 = 0b00_0_0011. 0b00_0_1000. Msg = 9.please inform us. //Reserved //Reserved //Reserved //Reserved //Completion without data //Completion for Locked //Memory Read without Data //Reserved //Reserved //Reserved = 0b00_0_1100. //Configuration Read Type 1 Reserved2 Reserved3 Reserved4 Reserved5 Cpl CplLk Reserved6 Reserved7 Reserved8 = = = = = = 0b00_0_0110. //Configuration Read Type 0 CfgRd1 = 0b00_0_0101.cadfamily. = 0b00_0_1110. MWr = 2. 0b00_0_1001. 0b00_0_1011. CplD = 12. CfgWr0 = 6. CfgWr1 = 8. //Memory Read Request-Locked //32-bit IORd = 0b00_0_0010. CplDLk = 14. Reserved = 15 }. MsgD = 10. the PCIe transactor makes use of the following types: type enum e_TLP_Basic_Types:4 { MRd = 0.if tort to your rights. //Memory Read Request 32-bit MRdLk_32bit = 0b00_0_0001. MRdLk = 1. and ‘bit’. 0b00_0_0111.

cadfamily. //Reserved = 0b01_0_0111. //Reserved = 0b01_0_1111. //Reserved = 0b01_0_1010. //Reserved = 0b01_0_1101.if tort to your rights. //Reserved = 0b00_1_0111. //Reserved = 0b00_1_1100. //Reserved = 0b00_1_1000. MsgReserved1 = 0b01_1_0110. //Reserved = 0b00_1_0011. //Reserved = 0b01_0_0011. //Reserved = 0b01_0_0110. //Reserved = 0b01_1_0000. //Reserved = 0b00_1_0110. //Reserved = 0b00_1_0100. //Reserved = 0b00_1_1111. //Message routed to route //complex //Message routed by address //Message routed by ID //Message broadcast from //root complex //Message local . //Reserved = 0b01_0_1100. //Reserved = 0b01_0_1011. //Reserved = 0b01_0_1000. //Reserved = 0b00_1_1010. MsgBroadComp = 0b01_1_0011. //Memory Read Request-Locked //64-bit = 0b01_0_0010. //Reserved = 0b00_1_0001.we will delete . //Reserved = 0b01_0_0101. //Reserved = 0b00_1_0010. MsgReserved2 = 0b01_1_0111.com 170 The document is for study only. //Reserved = 0b01_0_0000.com EMail:cadserv21@hotmail. //Reserved = 0b01_0_1110. //Reserved = 0b01_0_0100. MsgRoutID = 0b01_1_0010.please inform us.nTX User’s Guide and Tutorial Reserved9 Reserved10 Reserved11 Reserved12 Reserved13 Reserved14 Reserved15 Reserved16 Reserved17 Reserved18 Reserved19 Reserved20 Reserved21 Reserved22 Reserved23 Reserved24 Reserved25 MRd_64bit MRdLk_64bit Reserved26 Reserved27 Reserved28 Reserved29 Reserved30 Reserved31 Reserved32 Reserved33 Reserved34 Reserved35 Reserved36 Reserved37 Reserved38 Reserved39 MsgRoutComp = 0b00_0_1111. MsgLocal MsgGather = 0b01_1_0100. = 0b01_1_0101. //Reserved = 0b00_1_1101. //Reserved = 0b00_1_0101. //Reserved = 0b00_1_1011. //Memory Read Request 64-bit = 0b01_0_0001. //Reserved = 0b00_1_1001. //Reserved = 0b00_1_1110. //Reserved = 0b00_1_0000. www.terminate //at receiver //Message gathered and //routed to route complex //Message Reserved //Terminate at Receiver //Message Reserved //Terminate at Receiver MsgRoutAdd = 0b01_1_0001. //Reserved = 0b01_0_1001.

0b01_1_1101. 0b10_1_1000. = 0b10_0_0101. 0b10_1_1001. = 0b10_0_0100. 0b10_1_0110. 0b10_1_0100. 0b01_1_1010. 0b10_0_1110. 0b10_0_1001. 0b10_1_0101.we will delete . 0b10_1_0111. = 0b10_0_0010. //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Memory write request 32-bit //Reserved //IO write request //Reserved //Configuration write type 0 //Configuration write type 1 //Reserved //Reserved //Reserved //Reserved //Completion with data //Completion for locked //memory read //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved = 0b10_0_0000. 0b10_1_1011. 0b10_0_1000. = = = = 0b10_0_0110. = 0b10_0_0001.please inform us. 0b01_1_1111. 0b10_1_0001. 0b10_1_0010. 0b10_0_1101. Reserved54 Reserved55 Reserved56 Reserved57 Reserved58 Reserved59 Reserved60 Reserved61 Reserved62 Reserved63 Reserved64 Reserved65 Reserved66 Reserved67 Reserved68 Reserved69 Reserved70 Reserved71 Reserved72 = = = = = = = = = = = = = = = = = = = 0b10_0_1100.if tort to your rights.com 171 The document is for study only. 0b10_1_0011. 0b10_1_0000. = 0b10_0_1011. www.cadfamily. 0b01_1_1110.com EMail:cadserv21@hotmail. = 0b10_0_1010. = 0b10_0_0011.Appendix G: PCI-Express (PCIe) Transactor Reserved40 Reserved41 Reserved42 Reserved43 Reserved44 Reserved45 Reserved46 Reserved47 MWr_32bit Reserved48 IOWr Reserved49 CfgWr0 CfgWr1 Reserved50 Reserved51 Reserved52 Reserved53 CplD CplDLk = = = = = = = = 0b01_1_1000. 0b10_0_0111. 0b10_1_1101. 0b10_1_1010. 0b01_1_1011. 0b01_1_1001. 0b10_0_1111. 0b10_1_1110. 0b10_1_1100. 0b01_1_1100.

0b11_1_1001.nTX User’s Guide and Tutorial Reserved73 MWr_64bit Reserved74 Reserved75 Reserved76 Reserved77 Reserved78 Reserved79 Reserved80 Reserved81 Reserved82 Reserved83 Reserved84 Reserved85 Reserved86 Reserved87 Reserved88 MsgDRoutComp = 0b10_1_1111. = = = = = = = = = = = = = = = 0b11_0_0001. //Message broadcast from //root complex with data MsgDLocal = 0b11_1_0100. //Message gathered and //routed to route complex with data MsgDReserved1 = 0b11_1_0110. www. 0b11_0_1011. 0b11_1_1010. 0b11_0_0101. 0b11_0_1000.if tort to your rights. 0b11_0_0010. //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved = 0b11_1_0000. 0b11_1_1101. 0b11_0_1100.we will delete . 0b11_0_1001.cadfamily. //Message routed by ID with //data MsgDBroadComp = 0b11_1_0011. 0b11_1_1110.com 172 The document is for study only. 0b11_1_1100. //Message Reserved //Terminate at Receiver MsgDReserved2 = 0b11_1_0111. 0b11_0_1010. 0b11_1_1111. 0b11_0_0100.com EMail:cadserv21@hotmail. 0b11_1_1011. //Message local . 0b11_0_0111. 0b11_0_1101. //Reserved //Memory write request 64-bit //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Reserved //Message routed to route //complex with data MsgDRoutAdd = 0b11_1_0001. = 0b11_0_0000. 0b11_0_1111. //Message routed by address //with data MsgDRoutID = 0b11_1_0010. 0b11_0_0110. 0b11_0_1110.terminate //at receiver with data MsgDGather = 0b11_1_0101. //Message Reserved //Terminate at Receiver Reserved89 Reserved90 Reserved91 Reserved92 Reserved93 Reserved94 Reserved95 Reserved96 }. type enum e_AckNak : 1 = = = = = = = = 0b11_1_1000.please inform us. 0b11_0_0011.

InitFC1. Vendor_Specific.we will delete . NP. bit HGFEDCBA[8]. Vendor_Specific_Class. Nak}. type enum e_DLLP_Msg_Subtype : 2 {P. Pm_Act_State_Req. UpdateFC }. }. Fc_Class. Pm. Cpl }.com 173 The document is for study only. type enum e_Special_Symbols www. type enum e_DLLP_Classes : 3 {AckNak_Class. Pm_Req_Ack }. DLLP}. type struct Z_HGFEDCBA {bit Z. Unknown_Class }.Appendix G: PCI-Express (PCIe) Transactor {Ack. type enum e_Pm : 2 {Pm_Enter_L1. Pm_Enter_L23. // Posted // NonPosted // Completed type enum e_DLLP_Types : 3 {AckNak. type enum e_PLLP_Types : 2 {NULLIFIED_TLP.cadfamily. InitFC2.com EMail:cadserv21@hotmail. TLP. Pm_Class.please inform us.if tort to your rights.

04.please inform us. = = = = = = = = = = = = 00.we will delete . www. // // // // // // // // // // // // Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Disparity Disparity Disparity Disparity Disparity Disparity Disparity Disparity Disparity Disparity Disparity Disparity SKP FTS SDP IDL RES1 COM RES2 RES3 PAD STP END EDB Character Character Character Character Character Character Character Character Character Character Character Character type enum e_Validity {InValid.com EMail:cadserv21@hotmail. Valid}. 06. 05.cadfamily.if tort to your rights. 10. 11. 03. 02. 01.nTX User’s Guide and Tutorial {PD_SKP PD_FTS PD_SDP PD_IDL PD_RES1 PD_COM PD_RES2 PD_RES3 PD_PAD PD_STP PD_END PD_EDB }.com 174 The document is for study only. 09. 07. 08.

serial communication link.cadfamily. It enables the recognition of transactions from a wire level FSDB file.if tort to your rights. Even or Odd.we will delete . full duplex.com EMail:cadserv21@hotmail. • BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description. 2. nte_UART_v2p1_ns UARTtest { www. Independent receiver and transmitter operating frequency to enable dual speed channel applications. Features supported include: • • • Selectable serial data rates. Programmable character format: • Word Length of 5. • Stop Bit Length: 1.Appendix H: UART Transactor Appendix H: UART Transactor Overview The UART transactor fits between two industry standard UART devices to perform a point-to-point.please inform us. 6. Software Flow Control via XON/XOFF character generation/recognition. Name The bus declaration (nte_UART_v2p1_ns) must be one of the supported transactors.com 175 The document is for study only. 1½. The UART Transactor supports the majority of features present in 16C550 compatible devices. 7 or 8 bit words • Parity Selection: No Parity.

"/DSRn". however. Rx_bit_clk_1st_time: The relative time period of the first Rx_bit_clk change. NOTE: UART transactor does not have a clock that can be mapped. The transactor signals are pre-defined as shown in the file below and must not be changed. MAPPING_ROOT = "/UART_loopback/UART_structure/UART_I". "/RIn".nTX User’s Guide and Tutorial Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed. it is possible to leave signals unconnected by removing them from the sigmap section.com EMail:cadserv21@hotmail.if tort to your rights. Tx_sample_clk_2nd_time: The relative time period of the second Tx_sample_clk change after the previous change. Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side. If this is done they will be assigned a default value (normally 0). "/DTRn". "/CTSn".com 176 The document is for study only.cadfamily. "/RX". Tx_bit_clk_2nd_time: The relative time period of the second Tx_bit_clk change after the previous change. The available parameters are: • • • • • Tx_bit_clk_1st_time: The relative time period of the first Tx_bit_clk change.please inform us. "/RTSn". SIGMAP { /UART/TX /UART/RX /UART/DTRn /UART/RTSn /UART/CTSn /UART/RIn /UART/DCDn /UART/DSRn } = = = = = = = = "/TX". "/DCDn". Tx_sample_clk_1st_time: The relative time period of the first Tx_sample_clk change. Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file. www.we will delete . This is prefixed to the signal names specified on the right hand side of the SIGMAP statements. Configuration of the transactor is made via the PARAMETER section of the bcf file.

if tort to your rights. • UART_xon1: Value used as XON1. • UART_xoff2: Value used as XOFF2. Rx_bit_clk_1st_time = 800 ns. Tx_bit_clk_2nd_time = 800 ns. • UART_word_length: The number of bits per word. • UART_number_xon_xoff_chars: Number of XON/XOFF characters.cadfamily.com 177 The document is for study only. Tx_sample_clk_2nd_time = 50 ns.please inform us. UART_word_length = 8. • Rx_sample_clk_1st_time: The relative time period of the first Rx_sample_clk change. • Rx_sample_clk_2nd_time: The relative time period of the second Rx_sample_clk change after the previous change. Tx_sample_clk_1st_time = 50 ns. Rx_sample_clk_2nd_time = 50 ns.we will delete .Appendix H: UART Transactor Rx_bit_clk_2nd_time: The relative time period of the second Rx_bit_clk change after the previous change. • UART_xoff1: Value used as XOFF1. • UART_software_flow_control: Specify whether XON/XOFF characters are enabled. Rx_sample_clk_1st_time = 50 ns. Rx_bit_clk_2nd_time = 800 ns. • UART_parity_mode: Parity on or off. • UART_stop_bit_length: Number of stop bits. An example is shown below: • Figure: Clock Setup // parameters PARAMETER { Tx_bit_clk_1st_time = 800 ns.com EMail:cadserv21@hotmail. The clock set up is important for the correct operation of the transactor. • UART_parity_type: Even or odd parity. www. • UART_xon2: Value used as XON2.

This does not have to match the time scale of the input FSDB file. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor.we will delete . //sfc_dis | sfc_ena UART_number_xon_xoff_chars = 1. UART_xoff2 = 0b01010011. ‘fs’). however. UART_xon1 = 0b11100010. types and attributes of these transactions are described in detail. //parity_ena | parity_dis UART_parity_type = evn. Transaction Hierarchy The transactor consists of a number of transactions that enable communication at different levels of abstraction.nTX User’s Guide and Tutorial UART_parity_mode = parity_ena. any signal changes below this time resolution will not be seen by nTE.com 178 The document is for study only. UART_xon2 = 0b00011101. UART_xoff1 = 0b11111011. The naming convention used is nte_UART_'ver'_’tu’ where ‘ver’ and ‘tu’ have the following meanings and valid values: • • ‘ver’ – version (‘v2p1’) ‘tu’ – time unit (‘ps’. ‘ns’. } Transactor Configurations A number of transactor configurations are available. www.com EMail:cadserv21@hotmail.please inform us.cadfamily.0.if tort to your rights. UART_software_flow_control = sfc_dis. In this section the function. //evn | odd UART_stop_bit_length = 1.

Appendix H: UART Transactor Protocol Tree .com EMail:cadserv21@hotmail.com 179 The document is for study only.cadfamily.TX www.if tort to your rights.we will delete .please inform us.

cadfamily.if tort to your rights.com EMail:cadserv21@hotmail.RX www.com 180 The document is for study only.please inform us.we will delete .nTX User’s Guide and Tutorial Protocol Tree .

www.please inform us. Tx_XOFF_char Tx_XOFF_char is a uni-directional transaction from UART_unit_A to UART_unit_B indicating an XOFF character sequence.if tort to your rights.cadfamily. Tx_char Tx_char is a uni-directional transaction from UART_unit_A to UART_unit_B indicating a data character with correct parity. This transaction is only enabled when the Software Flow Control feature of the UART Transactor is enabled.com 181 The document is for study only.Appendix H: UART Transactor Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer. Attributes: mbit data[8] Rx_BRK_char Rx_BRK_char is a uni-directional transaction from UART_unit_B to UART_unit_A indicating the Break condition. to the unit (or units) to the right of the symbol. This transaction is only enabled when the Software Flow Control feature of the UART Transactor is enabled.we will delete .com EMail:cadserv21@hotmail. from the unit to the left of the symbol. Attributes: bit data[8] Tx_char_parity_error Tx_char_parity_error is a uni-directional transaction from UART_unit_A to UART_unit_B indicating a data character with incorrect parity. Tx_XON_char Tx_XON_char is a uni-directional transaction from UART_unit_A to UART_unit_B indicating an XON character sequence. Tx_BRK_char Tx_BRK_char is a uni-directional transaction from UART_unit_A to UART_unit_B indicating the Break condition.

This transaction is only enabled when the Software Flow Control feature of the UART Transactor is enabled. This transaction is only enabled when the Software Flow Control feature of the UART Transactor is enabled. 7.com 182 The document is for study only.nTX User’s Guide and Tutorial Rx_XOFF_char Rx_XOFF_char is a uni-directional transaction from UART_unit_B to UART_unit_A indicating an XOFF character sequence. Attributes: bit data[8] Rx_char_parity_error Rx_char_parity_error is a uni-directional transaction from UART_unit_B to UART_unit_A indicating a data character with incorrect parity.we will delete . Attributes: bit data[8] Tx_parity Tx_parity is a uni-directional transaction from UART_unit_A to UART_unit_B indicating a data character parity bit.cadfamily. Tx_word Tx_word is a uni-directional transaction from UART_unit_A to UART_unit_B indicating a 5.com EMail:cadserv21@hotmail. www. 6. Rx_char Rx_char is a uni-directional transaction from UART_unit_B to UART_unit_A indicating a data character with correct parity.please inform us. This transaction is only enabled when the Parity Mode feature has been enabled. Rx_XON_char Rx_XON_char is a uni-directional transaction from UART_unit_B to UART_unit_A indicating an XON character sequence.if tort to your rights. Attributes: bit data[8] Tx_start Tx_start is a uni-directional transaction from UART_unit_A to UART_unit_B indicating an active low Start bit. or 8-bit data character word.

Attributes: bit data Tx_start_sample Tx_start_sample is a uni-directional transaction from UART_unit_A to UART_unit_B of duration Tx_sample_clk_period indicating a Start Bit synchronized to the rising edge of Tx_sample_clk. The UART Transactor may be configured to recognize 1. This transaction is only enabled when the Parity Mode feature has been enabled. or 8-bit data character word. 1½. or 2 Stop Bits. 1½.cadfamily.Appendix H: UART Transactor Attributes: bit p Tx_stop Tx_stop is a uni-directional transaction from UART_unit_A to UART_unit_B indicating a character’s Stop Bit sequence.com 183 The document is for study only. 6. Rx_word Rx_word is a uni-directional transaction from UART_unit_B to UART_unit_A indicating a 5.please inform us.we will delete . Attributes: bit data Rx_start Tx_start is a uni-directional transaction from UART_unit_B to UART_unit_A indicating an active low Start bit. 7. Attributes: bit p Rx_stop Rx_stop is a uni-directional transaction from UART_unit_B to UART_unit_A indicating a character’s Stop Bit sequence. The UART Transactor may be configured to recognize 1. Attributes: bit data[8] Rx_parity Rx_parity is a uni-directional transaction from UART_unit_B to UART_unit_A indicating a data character parity bit. or 2 Stop Bits.if tort to your rights.com EMail:cadserv21@hotmail. www.

cadfamily.com EMail:cadserv21@hotmail. Attributes: bit data Tx_stop_halfbit Tx_stop_bit is a uni-directional transaction from UART_unit_A to UART_unit_B of duration Tx_half_bit_clk_period indicating a single Half Stop Bit synchronized to the rising edge of Tx_half_bit_clk.we will delete . www.if tort to your rights. Rx_bit Rx_bit is a uni-directional transaction from UART_unit_B to UART_unit_A of duration Rx_bit_clk_period indicating a single Data Bit synchronized to the rising edge of Rx_bit_clk.please inform us. Attributes: bit data Rx_stop_bit Rx_stop_bit is a uni-directional transaction from UART_unit_B to UART_unit_A of duration Rx_bit_clk_period indicating a single Stop Bit synchronized to the rising edge of Rx_bit_clk.nTX User’s Guide and Tutorial Tx_bit Tx_bit is a uni-directional transaction from UART_unit_A to UART_unit_B of duration Tx_bit_clk_period indicating a single Data Bit synchronized to the rising edge of Tx_bit_clk.com 184 The document is for study only. Attributes: bit data Rx_start_sample Rx_start_sample is a uni-directional transaction from UART_unit_B to UART_unit_A of duration Rx_sample_clk_period indicating a Start Bit synchronized to the rising edge of Rx_sample_clk. Attributes: bit data Tx_stop_bit Tx_stop_bit is a uni-directional transaction from UART_unit_A to UART_unit_B of duration Tx_bit_clk_period indicating a single Stop Bit synchronized to the rising edge of Tx_bit_clk.

see the section on Signal Descriptions in the AMBA AXI Protocol Specification. and ‘bit’.com EMail:cadserv21@hotmail.Appendix H: UART Transactor Attributes: bit data Rx_stop_halfbit Rx_stop_bit is a uni-directional transaction from UART_unit_B to UART_unit_A of duration Rx_half_bit_clk_period indicating a single Half Stop Bit synchronized to the rising edge of Rx_half_bit_clk. such as ‘int’.com 185 The document is for study only. Attributes: bit data Wires For a description of each of these wires (signals).please inform us.cadfamily. the UART transactor makes use of the following types: type enum e_ParitySelection { www. Name TX RX DTRn RTSn CTSn RIn DCDn DSRn RCLK Type bit bit bit bit bit bit bit bit bit Direction UART_unit_A >=> UART_unit_B UART_unit_B >=> UART_unit_A UART_unit_A >=> UART_unit_B UART_unit_A >=> UART_unit_B UART_unit_B >=> UART_unit_A UART_unit_B >=> UART_unit_A UART_unit_B >=> UART_unit_A UART_unit_B >=> UART_unit_A Support to UART_unit_A Additional Information Data Types In addition to the standard transactor types.we will delete .if tort to your rights.

nTX User’s Guide and Tutorial no_parity. type enum e_parity_mode { parity_dis. xoff2_character. two }. type enum e_sfc { sfc_dis. type enum e_StopBitLength { one. EVEN_parity.com EMail:cadserv21@hotmail. xon2_character }. parity_ena }.please inform us. sfc_ena }. type enum e_parity_type { evn.cadfamily. xon1_character. xoff1_character. odd }. force_parity_1. ODD_parity.com 186 The document is for study only. www.if tort to your rights. type enum special_characters { data_character. one_half.we will delete . force_parity_0 }.

com 187 The document is for study only. nte_USB2_v1p0_fs) must be one of the included transactor libraries.5Mb/s). Control. nte_USB2_v1p0_fs myUSB { Mapping Root The MAPPING_ROOT specifies an optional path under which all of the signals in the users design may be accessed.we will delete .g. Start Split. High-speed (480Mb/s). Start-of-Frame packets. Isochronous. Power-on Reset to determine speed (parameterized and selectable). Name The bus declaration (e. Interrupt. Bulk. This is prefixed to the signal names specified on the right hand side of the SIGMAP statements. MAPPING_ROOT = "/USB2_top_level/USB2_structure/the_usb_bus". Complete Split and Ping transactions. The following limitations apply to the current version of the USB 2.cadfamily.com EMail:cadserv21@hotmail.0 Transactor: • Suspend and Resume is not supported. Full-speed (12Mb/s) & Low-speed (1.0 (see Limitations below). BCF Format Refer to the Bus Configuration File (BCF) Format section of the nTE chapter for a general description.if tort to your rights.0 Transactor supports the following features: • • • • • USB Revision 2.please inform us. www.Appendix I: USB Transactor Appendix I: USB Transactor Overview The USB 2.

If set to ‘true’ then the transactor will detect the speed from the signals according to the USB 2.if tort to your rights.nTX User’s Guide and Tutorial Signal Map The SIGMAP statements map transactor signals on the left hand side to user signals on the right hand side. Parameters The values in the PARAMETER section configure the transactor to match the input FSDB file. clk_2nd_time: The relative time of second clock change after the previous change. enable_speed_detection: If set to ‘false’ the speed is set manually via the usb_speed_selector parameter.0 specification. clk_phase_shift: The time of the first transition from the initial value. NOTE: Clock can be mapped to /USB2/UCLK. SIGMAP { // USB signals /USB2/DP /USB2/DM } = "/DP". The available parameters are: • • • • • • • • clk_init_value: The initial value of the clock (0 or 1). hold_time: The hold time for all USB signals. clk_1st_time: The relative time of the first clock change after the initial phase shift change. • • • www. The transactor signals are pre-defined as shown in the file below and must not be changed. setup_time: The setup time for all USB signals. Configuration of the transactor is made via the PARAMETER section of the BCF file.com 188 The document is for study only. Can be set to ‘low’. = "/DM". This parameter is ignored if enable_speed_detection is set to ‘true’. The SIGMAP code example is for an unmapped clock.com EMail:cadserv21@hotmail. In this case the remaining parameters (below) must be set. tDRST: Length of complete reset speed detection.please inform us. ‘full’ or ‘high’.we will delete . tUCH: Minimum duration of a Chirp K from a high-speed capable device within the reset protocol.cadfamily. usb_speed_selector: Manually selects the speed of the USB bus. packet2packet_delay: The maximum delay permitted between a token packet and subsequent data packet (including zero-length data packets).

we will delete . If this is too short then reset SE0’s may be incorrectly detected during extraction. Figure: High Speed Detection Parameters Note that tWTREV + tWTRSTHS is the minimum time required for a valid SE0 to be recognized. resulting in the transactor resetting the speed mid-simulation. www. The clock set up is important for the correct operation of the transactor.Appendix I: USB Transactor tWTREV: Duration a high-speed capable device operating in high-speed must wait after start of SE0 before reverting to full-speed.cadfamily. • tWTDCH: Time after end of device Chirp K by which hub must start driving first Chirp K in the hub’s chirp sequence. The diagram below demonstrates the parameters that need to be set if speed is detection is required (enable_speed_detection = true).please inform us.if tort to your rights.com 189 The document is for study only. • tDCHSE0: Time before end of reset by which a hub must end its downstream chirp sequence. • tWTRSTHS: Time a device must wait after reverting to full-speed before sampling the bus state for SE0 and beginning the high-speed detection handshake.com EMail:cadserv21@hotmail. An example is shown below: • Figure: Clock Setup The USB interface speed can be detected by the transactor or set manually via the usb_speed_selector parameter.

‘fs’) Transaction Hierarchy The USB 2. 500 us. If the clock is mapped then clk_* parameters do not need to be set. 1 ms. Referring to the protocol tree can help to visualize transactions that are ‘recognized’ by the transactor. 100 us. high. 3 ms.nTX User’s Guide and Tutorial // parameters PARAMETER { clk_init_value clk_phase_shift clk_1st_time clk_2nd_time setup_time hold_time packet2packet_delay usb_speed_selector enable_speed_detection tDRST tUCH tWTREV tWTRSTHS tWTDCH tDCHSE0 } = = = = = = = = = = = = = = = 0b0. 0 fs. 500 ns. NOTE: PARAMETER code example is for an unmapped clock. 100 us. 10 ms.0 transactor consists of a number of transactions that enable communication at different levels of abstraction. 1041600 fs. In this section the function.we will delete . 100 fs. 100 fs. 1041600 fs.cadfamily.please inform us. The naming convention used is nte_USB2_‘ver’_‘tu’ where ‘ver’ and ‘tu’ have the following meanings and valid values: • • ‘ver’ – version (‘v1p0’) ‘tu’ – time unit (‘ps’.com 190 The document is for study only. false.com EMail:cadserv21@hotmail. www. types and attributes of these transactions are described in detail. Transactor Configurations A number of transactor configurations are available.if tort to your rights.

cadfamily.we will delete .com EMail:cadserv21@hotmail.please inform us.if tort to your rights.Appendix I: USB Transactor Protocol Tree www.com 191 The document is for study only.

please inform us. It includes the control token packet and any subsequent data packet used during control transfers. Setup_stage Setup_stage is a unidirectional write transaction between the host/hub and device.cadfamily. It includes the token packet and any subsequent data packet during write transfers.if tort to your rights. to the unit (or units) to the right of the symbol. from the unit to the left of the symbol.we will delete . It includes the token packet and any subsequent data packet during read transfers. Attributes: int int int data_packet_length address endpoint www. Attributes: int int T_USB2_bmRequestType_transfer_direction T_USB2_bmRequestType_type T_USB_bmRequestType_recipient bit bit bit int T_USB2_packet_identifier_field address endpoint transfer_direction transfer_type transfer_recipient bRequest[8] wValue[16] wIndex[16] wLength data_type_pid IN_data_stage IN_data_stage is a bi-directional read transaction between the host/hub and device. Attributes: int int int T_USB2_packet_identifier_field bit data_packet_length address endpoint data_type_pid data_in[][8] OUT_data_stage OUT_data_stage is a unidirectional transaction between the host/hub and device.com EMail:cadserv21@hotmail.com 192 The document is for study only.nTX User’s Guide and Tutorial Transaction Description NOTE: The ‘>=>’ notation is used to convey the direction of information transfer.

cadfamily.please inform us.Appendix I: USB Transactor T_USB2_packet_identifier_field bit data_type_pid data_out[][8] OUT_ssplit_stage OUT_ssplit_stage is a unidirectional write transaction between the host and hub. It includes the Start-Split token and FS/LS token during split-read transfers. Attributes: int int bit T_USB2_endpoint_type int int hub_address port_number speed_start endpoint_type address endpoint IN_ssplit_stage IN_ssplit_stage is a unidirectional read transaction between the host and hub.com EMail:cadserv21@hotmail. Attributes: int int bit bit T_USB2_endpoint_type int int hub_address port_number speed_start end endpoint_type address endpoint www. It includes the Complete-Split token and FS/LS token during split-write transfers.com 193 The document is for study only.we will delete . Attributes: int int bit bit T_USB2_endpoint_type int int int T_USB2_packet_identifier_field bit hub_address port_number speed_start end endpoint_type address endpoint data_packet_length data_type_pid data_out[][8] OUT_csplit_stage OUT_csplit_stage is a unidirectional write transaction between the host and hub. It includes the Start_Split token.if tort to your rights. FS/LS token and any subsequent data packet during split-write transfers.

endpoint and CRC5 values. endpoint and CRC5 values. Attributes: int address www.if tort to your rights.com EMail:cadserv21@hotmail. It contains the packet identifier. address.nTX User’s Guide and Tutorial IN_csplit_stage IN_csplit_stage is a bi-directional read transaction between the host and hub. It includes the Complete-Split token. Attributes: T_USB2_packet_identifier_field bit bit bool packet_id address[7] endpoint[4] crc5_error split_token_packet split_token_packet is a unidirectional transaction between a host and hub. speed.we will delete . It contains the packet hub address. Attributes: bit bit bit bit bit T_USB2_endpoint_type bool address[7] start_complete port[7] speed_start end end_type crc5_error ping_special_token ping_special_token is a unidirectional transaction between a host/hub and device. It contains the address and endpoint values. port number. Attributes: int int bit T_USB2_endpoint_type int int int T_USB2_packet_identifier_field bit hub_address port_number speed_start endpoint_type address endpoint data_packet_length data_type_pid data_in[][8] token_packet token_packet is a unidirectional transaction between a host/hub and device.please inform us.com 194 The document is for study only.cadfamily. FS/LS token and any subsequent data packet during split-read transfers.

Attributes: int T_USB2_packet_identifier_field bit bool payload_length packet_id data[][8] crc16_error handshake_packet handshake_packet is a unidirectional transaction between a host/hub and device. Attributes: bit bit bit bit start_complete port[7] speed_start end www. split_phase split_phase is a unidirectional transaction between a host and hub.we will delete . data bytes and CRC16. speed indication and endpoint type for split transfers. Attributes: none.please inform us.cadfamily.com 195 The document is for study only. packet identifier.com EMail:cadserv21@hotmail.if tort to your rights. Attributes: int bool frame_number crc5_error data_packet data_packet is a unidirectional transaction between a host/hub and device. It contains the payload length. It contains the handshake response from host or device.Appendix I: USB Transactor int endpoint start_of_frame_packet start_of_frame_packet is a unidirectional transaction between a host/hub and device. port address. It contains the start/complete identifier. It is generated every 125?s signifying the start of a micro-frame and contains the frame number. It signifies the start of a packet. Attributes: T_USB2_packet_identifier_field packet_id sync_phase sync_phase is a unidirectional transaction between a host/hub and device.

nTX User’s Guide and Tutorial bit end_type[2] identifier_phase identifier_phase is a unidirectional transaction between a host/hub and device. Attributes: bit address[7] endpoint_phase endpoint_phase is a unidirectional transaction between a host/hub and device. It controls when bit-stuffing is required.we will delete . Attributes: bit frame_number[11] data_phase data_phase is a unidirectional transaction between a host/hub and device. Attributes: www. It contains the packet identifier. Attributes: T_USB2_packet_identifier_field packet_id bit_stuff_phase bit_stuff_phase is a unidirectional transaction between a host/hub and device. Attributes: bit endpoint[4] frame_number_phase frame_number_phase is a unidirectional transaction between a host/hub and device. It contains the frame number.cadfamily. Attributes: bit bool data_bit data_valid address_phase address_phase is a unidirectional transaction between a host/hub and device.com EMail:cadserv21@hotmail. It contains the endpoint of the device.com 196 The document is for study only.if tort to your rights.please inform us. It contains the address of the device. It contains the data byte stream.

Appendix I: USB Transactor int payload_length bit data[][8] NOTE: The CRC16 value and 8-bit EOP are absorbed into the data byte stream as the last 3-bytes in the stream. Attributes: None. usb2_stripe usb2_stripe is a bi-directional transaction between a host/hub and device.cadfamily. Name DP DM Type bit bit Direction source to destination or destination to source source to destination or destination to source www.please inform us. end_of_packet_phase end_of_packet_phase is a unidirectional transaction between a host/hub and device.com EMail:cadserv21@hotmail. Attributes: None. Attributes: bit bit plus minus Wires For a description of each of these wires (signals). It signifies EOP for packets other than Start-of-Frame or Data.com 197 The document is for study only. crc5_phase crc5_phase is a unidirectional transaction between a host/hub and device.if tort to your rights. It contains the CRC5 value. It signifies the EOP for a Start-of-Frame packet. Attributes: bit crc5_data[5] end_of_sof_phase end_of_sof_phase is a unidirectional transaction between a host/hub and device. see the section on Signal Descriptions in the AMBA AXI Protocol Specification. It contains the un-coded bit values.we will delete .

t_vendor = 0b10. pid_out = 0b0001. the USB 2.com EMail:cadserv21@hotmail.cadfamily. endp_bulk = 0b10. and ‘bit’. t_class = 0b01. pid_nak = 0b1010. type enum T_USB2_endpoint_type:2 { endp_control = 0b00.0 transactor makes use of the following types: type enum T_USB2_packet_identifier_field:4 { pid_reserved = 0b0000. endp_interrupt = 0b11 }. pid_data2 = 0b0111. pid_mdata = 0b1111 }. pid_split = 0b1000. pid_data1 = 0b1011.nTX User’s Guide and Tutorial Additional Information Data Types In addition to the standard transactor types. endp_isochronous = 0b01. pid_stall = 0b1110. pid_ping = 0b0100. t_reserved = 0b11 www.we will delete . pid_pre_or_err = 0b1100.please inform us.if tort to your rights. type enum T_USB2_bmRequestType_type:2 { t_standard = 0b00. pid_in = 0b1001. pid_data0 = 0b0011.com 198 The document is for study only. pid_ack = 0b0010. pid_sof = 0b0101. type enum T_USB2_bmRequestType_transfer_direction:1 { host2device = 0b0. pid_setup = 0b1101. pid_nyet = 0b0110. device2host = 0b1 }. such as ‘int’.

recip_endpoint = 0b0_0010. high = 0b10. type enum T_USB2_speed:2 { low = 0b00.cadfamily. full = 0b01.Appendix I: USB Transactor }.we will delete . recip_interface = 0b0_0001. recip_other = 0b0_0011.com EMail:cadserv21@hotmail. type enum T_USB_bmRequestType_recipient:5 { recip_device = 0b0_0000.com 199 The document is for study only. www. }.please inform us.if tort to your rights. recip_reserved = 0b0_0100 }.

we will delete .com EMail:cadserv21@hotmail.if tort to your rights.please inform us.com 200 The document is for study only.cadfamily.nTX User’s Guide and Tutorial www.

cadfamily. 38.we will delete . 39 O Open Transaction Interface 15. 38. 71. 69 www. 72 attribute 70. 16. 44. 19. 69. 66 D dynamic link 65 F filter 45 FSDB 15.please inform us. 17. 21. 71 PLI 64. 46. 39.if tort to your rights. 70 streams 15. 69. 19. 21 overlap 17 P PCI 64. 40 Set Search Attributes 19 Show All 20. 47. 40 S Search Backward 16. 19. 50 stream 17. 19. 39. 21. 39. 17.Index Index A API 15. 72. 45. 40. 21 OTI 15. 18. 64.com EMail:cadserv21@hotmail.com 201 The document is for study only. 73 R related transaction 18 relationships 18. 40 Search Forward 16. 70. 19 Sync Cursor Time 45 system tasks 73 G Get Signals 38 Get Stream 41 H HDL 64 header file 65. 43. 65. 17. 72 attributes 15. 47 M marker 45 Merge Stream 43 C C code 66 C files 73 C functions 64 C program 65 child transactions 40 Column Configuration 46 cursor 45 cursor time 17 N nWave 16.

cadfamily. 66 W waveform 17 www. 70. 43.please inform us. 72. 41. 40. 71. 64.if tort to your rights.we will delete . 49. 39 transaction relationships 19 transaction streams 42.com EMail:cadserv21@hotmail. 45. 44 transactions 49. 50 Transaction Attribute Values 19. 41. 48. 18.com 202 The document is for study only. 38. 50 V Verdi 37 Verilog 65. 47. 16. 17. 73 Transaction Analyzer 19.nTX User’s Guide and Tutorial T transaction 15.

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