Lecture Notes Electrical Engineering

Volume 53
Alexander Barkalov and Larysa Titarenko
Logic Synthesis for
FSM-Based Control Units
ABC
Prof. Alexander Barkalov
Institute of Informatics and Electronics
University of Zielona Gora
Podgorna Street 50
65-246 Zielona Gora
Poland
E-mail: a.barkalov@iie.uz.zgora.pl
Dr. Larysa Titarenko
Institute of Informatics and Electronics
University of Zielona Gora
Podgorna Street 50
65-246 Zielona Gora
Poland
E-mail: abar54@mail.ru
ISBN 978-3-642-04308-6 e-ISBN 978-3-642-04309-3
DOI 10.1007/978-3-642-04309-3
Library of Congress Control Number: 2009934355
c 2009 Springer-Verlag Berlin Heidelberg
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Acknowledgements
Several people helped us with preparation of this manuscript. Our PhD stu-
dents Mr Jacek Bieganowski and Mr S lawomir Chmielewski worked with us
on initial planning of this work, distribution of tasks during the project, and
final assembly of this book.
We also thank Professor Marian Adamski for his support and special at-
tention to this work. His guidelines in making this book useful for students
and practitioners were very helpful in the organization of this book.
Contents
1 Hardwired Interpretation of Control Algorithms . . . . . . . . . 1
1.1 Principle of Microprogram Control . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Control Algorithm Interpretation with Finite State
Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Control Algorithm Interpretation with Microprogram
Control Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Organization of Compositional Microprogram Control
Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2 Matrix Realization of Control Units . . . . . . . . . . . . . . . . . . . . . 29
2.1 Primitive Matrix Realization of FSM. . . . . . . . . . . . . . . . . . . . . 29
2.2 Optimization of Mealy FSM Matrix Realization . . . . . . . . . . . 35
2.3 Optimization of Moore FSM Logic Circuit . . . . . . . . . . . . . . . . 42
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3 Evolution of Programmable Logic. . . . . . . . . . . . . . . . . . . . . . . . 53
3.1 Simple Field-Programmable Logic Devices . . . . . . . . . . . . . . . . 53
3.2 Programmable Logic Devices Based on Macrocells . . . . . . . . . 60
3.3 Programmable Devices Based on LUT Elements . . . . . . . . . . . 64
3.4 Design of Control Units with FPLD . . . . . . . . . . . . . . . . . . . . . 67
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4 Optimization for Logic Circuit of Mealy FSM. . . . . . . . . . . . 77
4.1 Synthesis of FSM with Replacement of Logical
Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2 Synthesis of FSM with Encoding of Collections of
Microoperations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.3 Synthesis of FSM with Encoding of Rows of Structure
Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
VIII Contents
4.4 Synthesis of FSM Multilevel Logic Circuits . . . . . . . . . . . . . . . 95
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5 Optimization for Logic Circuit of Moore FSM . . . . . . . . . . . 103
5.1 Optimization for Two-Level FSM Model . . . . . . . . . . . . . . . . . . 103
5.2 FSM Synthesis for CPLD with Embedded Memory
Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.3 Synthesis of Moore FSM with Logical Condition
Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6 FSM Synthesis with Transformation of GSA. . . . . . . . . . . . . 129
6.1 Optimization of Logical Condition Replacement Block . . . . . 129
6.2 Optimization for Block for Decoding of Microoperations . . . . 138
6.3 Synthesis of Multilevel FSM Models . . . . . . . . . . . . . . . . . . . . . 145
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7 FSM Synthesis with Object Code Transformation . . . . . . . 155
7.1 Principle of Object Code Transformation . . . . . . . . . . . . . . . . . 155
7.2 Logic Synthesis for Mealy FSM with Object Code
Transformation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
7.3 Logic Synthesis for Moore FSM with Object Code
Transformation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
7.4 Multilevel Models of FSM with Object Code
Transformation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
8 FSM Synthesis with Elementary Chains . . . . . . . . . . . . . . . . . 193
8.1 Basic Models of FSM with Elementary Chains . . . . . . . . . . . . 193
8.2 Optimization of Block of Input Memory Functions . . . . . . . . . 201
8.3 Optimization of Block of Microoperations . . . . . . . . . . . . . . . . 208
8.4 Synthesis for Multilevel Models of FSM with Elementary
Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Symbols
X = {x
1
, . . . , x
L
} set of logical conditions
Y = {y
1
, . . . y
N
} set of microoperations
Y
q
⊆ Y collection of microoperations (microinstruction)
Γ graph–scheme of algorithm
b
0
start vertex of GSA
b
E
end vertex of GSA
B
1
set of GSA operator vertices
B
2
set of GSA conditional vertices
E = {b
t
, b
q
} set of GSA arcs
a
m
∈ A internal state of FSM
K(a
m
) code of internal state a
m
∈ A
A = {a
1
, . . . , a
M
} set of FSM internal states
T = {T
1
, . . . , T
R
} set of FSM state variables
A
m
∈ A conjunction of state variables corresponding to the
state code K(a
m
)
Φ = {ϕ
1
, . . . , ϕ
R
} set of FSM input memory variables (excitation
functions)
H the number of structure table rows (lines)
Π
A
= {B
1
, . . . , B
I
} set of the classes of pseudoequivalent states
K(B
i
) code of class of pseudoequivalent states B
i
∈ Π
A
α
g
= b
g
1
, . . . , b
g
F
g
operational linear chain
M
i
matrix (AND- or OR-plane)
S(M
i
) area of matrix M
i
F = {F
1
, . . . , F
H
} set of FSM terms
X(a
m
) set of logical conditions determining transitions from
the state a
m
∈ A
p
g
∈ P additional variable used to replace logical conditions,
where |P| = G, G = max(|X(a
1
)|, . . . , |X(a
M
)|)
X(p
g
) set of logical conditions written in the column p
g
z
r
∈ Z additional variable used to encode the
microinstructions
K(Y
t
) binary code of collection Y
t
τ set of variables used to code classes B
i
∈ Π
a
, where
|τ| = R
0
and R
0
= log
2
I
X Symbols
BM FSM block generating variables for logical condition
replacement
BP FSM block generating variables written in the rows
of (transformed) structure table
BY FSM block generating microoperations and imple-
mented with embedded memory blocks
BD FSM block generating microoperations and imple-
mented with decoders
BF FSM block generating variables corresponding to rows
of (transformed) structure table
MX
g
multiplexer from block BM generating function
p
g
∈ P
K(y
n
) code of microoperation y
n
∈ Y
k
from the class k of
compatible microoperations
R
k
the number of bits in the code K(y
n
)
z
r
∈ Z
k
additional variables used for encoding of microopera-
tions y
n
∈ Y
k
DC
k
decoder from block BD generating microoperations
from the class k of compatible microoperations
K(F
h
) binary code of row h of FSM structure table
R
F
the number of bits in code K(F
g
)
H(f) the number of terms for SOP of some function f
q the number of terms for PAL-based macrocell
n(f, q) the number of macrocells having q terms, necessary
to implement the logic circuit for function f
NL
i
the number of FSM models having i levels
V (Γ) graph-scheme of algorithm Γ after verticalization
I set of identifiers for FSM with object codes
transformation
K(I
k
) binary code of identifier I
k
∈ I having R
V
= log
2
K
bits
V = {v
1
, . . . , v
R
V
} set of variables used for encoding of identifiers I
k
∈ I
CE = {α
1
, . . . , α
G
E
} set of elementary operational linear chains
R
E
the number of microinstruction address bits, where
R
E
= log
2
M
E

M
E
the number of operator vertices in transformed GSA
O
g
output of EOLC α
g
∈ C
E
A(O
g
) address of EOLC output O
g
I
j
input of EOLC α
j
∈ C
E
A(I
j
) address of EOLC input I
j
G
E
the number of EOLC in GSA Γ
M
g
the number of components in EOLC α
j
∈ C
E
Q
E
the maximal number of components in EOLC of
GSA Γ
Symbols XI
R
EO
the number of variables for encoding of EOLC, where
R
EO
= log
2
G
E

R
CO
the number of variables for encoding of EOLC, where
R
EO
= log
2
Q
E

K(α
g
) code of EOLC α
g
∈ C
E
K(b
t
) code of component b
t
∈ B
1
of EOLC α
g
∈ C
E
Abbreviations
ASIC application-specific integrated circuit
BAT block of address transformer
BTC block of code transformer
BM block for logical condition replacement
BP block forming input memory functions of FSM
BTC block for code transformation
BY block forming microoperations of FSM
CA control automaton
CAD computer-aided design
CAMI counter of microinstruction address
CC sequential circuit
CCS state code transformer
CFA circuit of address formation (sequencer)
CLB configurable logic block
CM control memory
CMCU compositional microprogram control unit
CMO circuit (block) of microoperation generation
CPLD complex programmable logic devices
EAB embedded array block
EPROM erasable programmable read-only memory
EEPROM electrically erasable programmable read-only memory
EOLC elementary operational linear chain
FPLD field-programmable logic devices
FSM finite state machine
FPGA field-programmable gate arrays
GFT generalized formula of transition
GSA graph- scheme of algorithm
HDL hardware description language
LAB logic array block
LE logic element
LUT look-up table
XIV Abbreviations
MCU microprogram control unit
MX multiplexer
OA operational automaton
OLC operational linear chain
PAL programmable array logic
PLD programmable logic device
PLA programmable logic array
PLS programmable logic sequencer
PROM programmable read-only memory
RAM random-access memory
RAMI register of microinstruction address
RG register
ROM read-only memory
SBF system of Boolean functions
SOP sums of products
SPLD simple programmable logic devices
ST structure table
TMS microoperation code transformer
TSM state code transformer
VGSA vertical graph- scheme of algorithm
VLSI very large scale integration circuit
Introduction
Tremendous achievements in the area of semiconductor electronics turn mi-
croelectronics into nanoelectronics. Actually, we observe a real technical
boom connected with achievements in nanoelectronics. It results in develop-
ment of very complex integrated circuits, particularly the field programmable
logic devices (FPLD). Up-to-day FPLD chips are so huge, that it is enough
only one chip to implement a really complex digital system including a data-
path and a control unit. Because of the extreme complexity of modern mi-
crochips, it is very important to develop effective design methods oriented
on particular properties of logic elements. The development of digital sys-
tems with use of FPLD microchips is not possible without use of different
hardware description languages (HDL), such as VHDL and Verilog. Different
computer-aided design tools (CAD) are wide used to develop digital system
hardware. As majority of researches point out, the design process is now very
similar to the process of program development. It allows a researcher to pay
more attention to some specific problems, where there are no standard for-
mal methods of their solution. But application of all these achievements does
not guarantee per se development of some competitive electronic product, es-
pecially in the acceptable time-to-market. This problem solution is possible
only if a researcher possesses fundamental knowledge of a design process and
knows exactly the mode of operation of industrial CAD tools in use. As it
is known, any digital system can be represented as a composition of a date-
path and a control unit. Logic schemes of data-path have regular structures;
it allows use of standard library elements of CAD tools (such as counters,
multibit adders, multipliers, multiplexers, decoders and so on) for their de-
sign. A control unit coordinates interplay of other system blocks producing
a sequence of control signals that causes some operations in a data-path. As
a rule, control units have irregular structures, which makes process of their
design very sophisticated. In case of complex logic controllers, the problem
of system design is reduced practically to the design of control units. Many
important features of a digital system, such as performance, power consump-
tion and so on, depend to a large extent on characteristics of its control
XVI Introduction
unit. Therefore, to design competitive digital systems with FPLD chips, a
designer should have fundamental knowledge in the area of logic synthesis
and optimization of logic circuits of control units. As our experience shows,
design methods used by standard industrial packages are, in case of com-
plex control units design, far from optimal. It means that a designer may
be forced to develop his own design methods, next to program them and at
last to combine them with standard packages to get a result with desired
characteristics. To help such a designer, this book is devoted to solution of
the problems of logic synthesis and reduction of hardware amount in con-
trol units, when a control unit is represented using the model of finite state
machine (FSM). The book contains some original design and optimization
methods based on the structural decomposition of FSM model. Such an ap-
proach results in multilevel models of FSM, where regularity of the device
increases in comparison with known single- and double-level models. Regu-
lar parts of these models can be implemented using such library elements as
memory blocks, decoders and multiplexers. In the same time, an irregular
part of the control units described by means of Boolean functions is reduced.
It permits to decrease the total number of logic elements (PAL, GAL, PLA, or
LUT macrocells) in comparison with logic circuits based on known models of
FSM. This approach is especially fruitful when a control unit is implemented
using up-to-day FPLD chips which include not only combinational macro-
cells, but also the embedded memory blocks. In our book, control algorithms
are represented by graph-schemes of algorithms (GSA). This choice is based
on obvious fact that this specification provides simple explanation of methods
proposed by authors. The methods of synthesis and design presented in the
book are not oriented to any particular FPLD chips, but to construction of
tables describing the behaviour of FSM blocks. These tables are used to find
the systems of Boolean functions, which can be used to implement logic cir-
cuits of particular FSM blocks. In order to implement corresponding circuits,
this information should be transformed using data formats of particular in-
dustrial CAD systems. This step is beyond the scope of our book, in which
the following information is presented:
Chapter 1 introduces such basic topics as principle of microprogramcontrol
and specification of control units by graph-scheme of algorithms. Such con-
ceptions as microoperations (FSM output signals), logical conditions (FSM
input signals), FSM states, interstate transitions, and FSM structure table
are introduced. Next, some methods of control algorithms interpretation are
discussed, such as finite state machines and microprogram control units. The
FSM models of Mealy and Moore are introduced; the methods of transition
from GSA to Mealy and Moore FSM graphs are shown. All FSM discussed
in the book are specified either by GSA or by structure table of FSM. Last
part of the chapter is devoted to organization principles of compositional mi-
croprogram control units, which can be viewed as a composition of Mealy
finite-state machine addressing microinstructions and microprogram control
unit with natural microinstruction addressing. These control units are Moore
Introduction XVII
FSMs using counter to represent their state codes; they can be used for in-
terpretation of linear GSA.
Chapter 2 discusses some problems, connected with logic synthesis and
optimization of FSM implemented with custom matrix integrated circuits.
The primitive matrix implementation of FSM circuit is analyzed first. It is
reduced to direct interpretation of FSM structure table and is characterized
by considerable redundancy. Next, the methods of logical condition replace-
ment and encoding of collections of microoperations are considered. These
methods allow decrease for circuit redundancy due increase of the number
of FSM model levels. Next, it is shown that the model of Moore FSM offers
an additional possibility for its circuit optimization due to existence of the
classes of pseudoequivalent states. Each such class corresponds to one state
of the equivalent Mealy FSM. Optimization methods are introduced based on
different approaches for state encoding, as well as on transformation of state
codes into class codes. The last part of the chapter is devoted to optimization
of the block generating microoperations.
Chapter 3 discussed contemporary field-programmable logic devices and
their evolution, starting from the simplest programmable logic devices such
as PROM, PLA, PAL and GAL, and finishing with very sophisticated chips
such as CPLD and FPGA. This analysis shows particular features of different
logic elements and permits to optimize the FSM logic circuits, in which some
particular elements are used. The analysis is accompanied by some examples
for systems of Boolean functions implementation using PROM, PLA and PAL
chips. The principle of functional decomposition oriented on FPGA chips is
analysed in the last part of the chapter.
Chapter 4 is devoted to the hardware amount reduction in the logic circuit
of Mealy FSM. The methods of logical condition replacement are analyzed, as
well as different methods of encoding of collections of microoperations (max-
imal encoding and encoding of the classes of compatible microoperations).
Next, the methods of structure table rows encoding are discussed. Each of
these methods produces double-level circuit of Mealy FSM. The main part
of the chapter is devoted to joint application of these methods, the main
advantage of whose is possibility of standard library cells use for implemen-
tation of logic circuits for some blocks of an FSM model. For example, the
logical condition replacement allows application of multiplexers, whereas the
encoding of collections of microoperations permits to use embedded mem-
ory blocks. Standard decoders can be used in case of encoding of the classes
of compatible microoperations. It increases FSM logic circuit regularity and
leads to simplification of its design process.
Chapter 5 is devoted to original synthesis and optimization methods ori-
ented on Moore FSM logic circuit implemented with CPLD. These methods
are based on results of joint investigations conducted by the authors and
their PhD students Cololo S. (Ukraine) and Chmielewski S. (Poland). These
methods deal with both homogenous and heterogeneous CPLD chips. In the
first case, only PAL- or PLA- based macrocells are used for logic circuit
XVIII Introduction
implementation. In the second case, the logic circuit is implemented using
both PAL-based macrocells and embedded memory blocks. The hardware
amount reduction is based on use of several sources (up to three) to rep-
resent the codes of classes of pseudoequivalent states. The methods assume
joint minimization of Boolean expressions for input memory functions and
microoperations of Moore FSM. The last part of the chapter is devoted to
joint application of proposed methods and logical condition replacement.
Chapter 6 is devoted to design methods based on transformation of an in-
terpreted graph-scheme of algorithm. The methods of decrease for the number
of logical conditions per FSM state are discussed. In extreme case, all FSM
transitions depend on single logical condition; it allows use of embedded mem-
ory blocks for implementation of FSM input memory functions. In this case
all FSM blocks are implemented using standard library cells (not just macro-
cells of a particular FPLD chip). The second part of the chapter is devoted
to hardware optimization for block of microoperations, based on verticaliza-
tion of an interpreted GSA. It permits to decrease the number of decoders
(up to 1) and bit capacity of microinstruction word, but this optimization
is connected with increase for the number of cycles required for a control
algorithm interpretation. At last, the models based on joint application of
these methods are discussed.
Chapter 7 is devoted to original optimization methods oriented on de-
crease of the number of outputs for FSM block generating input memory
functions. These methods are based on the object code transformation. The
FSM objects are either states or collections of microoperations. Sometimes,
some additional identifiers are needed for one-to-one representation of dif-
ferent objects. Such optimization methods are discussed for both Mealy and
Moore finite state machines. At last, the multilevel models of FSM with
object code transformation, logical condition replacement and encoding of
collections of microoperations are discussed. This chapter is written together
with employee of ”Nokia-Siemens Network” Alexander Barkalov (Ukraine).
Chapter 8 is devoted to original methods oriented on optimization of Moore
FSM interpreting graph-schemes of algorithms with long sequences of oper-
ator vertices having only one input. These sequences are named elementary
operational linear chains (EOLC). These FSM models include the counter
keeping, either microinstruction addresses or code of EOLC component. In
the beginning the Moore FSM models with code sharing are analysed, where
the register keeps EOLC codes. The methods of EOLC encoding and transfor-
mation are discussed; these methods permit to decrease the number of macro-
cells in the block generating input memory functions. The second part of the
chapter is devoted to reduction of the number of embedded memory blocks
in the FSM block generating microoperations. These methods are based on
transformation of microinstruction address represented as concatenation of
EOLC code and code of its component into either linear microinstruction
address or code of collection of microoperations. The last part of the chapter
discusses synthesis methods for multilevel FSM models with EOLC.
Introduction XIX
We hope that our book will be interesting and useful for students and
postgraduates in the area of Computer Science, as well as for designers of
modern digital devices. We think that proposed FSM models enlarge the class
of models applied for implementation of control units with modern CPLD and
FPGA chips.
Chapter 1
Hardwired Interpretation of Control Algorithms
Abstract. The chapter introduces such basic topics, as principles of microprogram
control and specification of the control unit behavior using the graph-scheme of al-
gorithm. Next, some methods of control algorithminterpretation, such as finite-state
machines (FSM) and microprogramcontrol units (MCU), are discussed. Last part of
the chapter is devoted to the organization principles of compositional microprogram
control units, which can be viewed as compositions of finite-state machine and mi-
croprogram control unit. These control units provide efficient interpretation of the
so-called linear GSA, in which long sequences of operator vertices can be found.
These sequences are called operational linear chains (OLC). Microinstructions cor-
responding to the components of OLC are addressed using the principle of natural
microinstruction addressing. It permits to use the counter to keep microinstruction
addresses and to simplify the combinational part of control unit, as compared with
the classical Moore FSM. The Mealy FSM is used in CMCU to address microin-
structions. It permits to calculate the transition address during one cycle of control
unit’s operation. Due to this feature, performance of the CMCU (proportional to
the number of cycles needed to execute the control algorithm) is better than perfor-
mance of the equivalent MCU with natural microinstruction addressing.
1.1 Principle of Microprogram Control
The principle of microprogramcontrol was proposed by M. Wilkes in 1951 [68, 69]
and was developed by V. Glushkov [1]. According to this principle, any complex
operation executed by a digital system is represented as a sequence of elemen-
tary operations of information processing. These elementary operations are named
microoperations. An ensemble of microoperations executed during one cycle of a
digital system operation is named microinstruction. Special logical conditions (sta-
tus signals or flags) are used to control the order of execution of microoperations.
Their values are calculated as some Boolean functions depending on the values
of operands. An algorithm of execution of some operation is represented in terms
of microinstructions and logical conditions is named microprogram [22]. A digital
A. Barkalov and L. Titarenko: Logic Synthesis for FSM-Based Control Units, LNEE 53, pp. 1–28.
springerlink.com c Springer-Verlag Berlin Heidelberg 2009
2 1 Hardwired Interpretation of Control Algorithms
system with microprogram control is represented by an operational unit. The oper-
ational unit is the composition of operational automaton (OA), which is a data-path
of the system, and control automaton (CA), which coordinates the interplay of all
system blocks (Fig. 1.1) [1, 8, 9].
Fig. 1.1 Structural diagram
of operational unit
Data path
Control
automation
Data F
X Y
Results
In the operational unit, CA analyses the code of operation together with values
of logical conditions from the set X = ¦x
1
, . . . , x
L
¦. Microinstructions Y
q
⊆ Y are
executed on the base of this analysis, where Y = ¦y
1
, . . . , y
N
¦ is a set of microoper-
ations, which initialize operand processing and obtaining of intermediate and final
results of operations, executed by the data-path. An algorithm of operational unit’s
operation is represented using one of the formal methods [8]. In this book we use
the language of graph- schemes of algorithm (GSA) which is very popular in design
practice [8, 9].
Graph-scheme of algorithmΓ is the directed connected graph, characterized by
a finite set of vertices, namely (Fig. 1.2): start (initial) vertex, end (final) vertex,
operator and conditional vertices.
Fig. 1.2 Types of vertices
of GSA
a) b) c) d)
Start
End
Y
q
x
l
1 0
The start vertex, denoted here by the symbol b
0
, corresponds to the beginning of
control algorithm to be interpreted and has no input. The end vertex, denoted here
by the symbol b
E
, corresponds to the end of control algorithm and has no output.
The operator vertex b
t
∈ B
1
, where B
1
is a finite set of operator vertices of GSA
Γ, contains a collection of microoperations Y
q
⊆Y which are executed in parallel.
The conditional vertex b
t
∈ B
2
, where B
2
is a set of conditional vertices of GSA
Γ, contains single element x
l
∈ X. It has two outputs, first corresponding to value
"1" and second to value "0" of the logical condition to be checked. Thus, GSA Γ is
characterized by a finite set of vertices B = B
1
∪B
2
∪¦b
0
, b
E
¦. The vertices b
t
∈ B
are connected by arcs from a finite set E = ¦'b
t
, b
q
`¦, where b
t
, b
q
∈ B.
1.1 Principle of Microprogram Control 3
For example, the GSA Γ
1
(Fig. 1.3) is characterized by the following sets:
• the set of vertices B = ¦b
0
, b
1
, . . . b
6
, b
E
¦;
• the set of arcs E = ¦'b
0
, b
1
`, 'b
1
, b
2
`, . . . , 'b
6
, b
E
`¦;
• the set of microoperations Y = ¦y
1
, . . . , y
4
¦;
• the set of logical conditions X = ¦x
1
, x
2
¦.
Fig. 1.3 Graph-scheme of
algorithmΓ
1
y
1
y
2
b
1
x
1
1 0
b
2
y
3
b
3 x
2
1 0
b
4
y
2
y
3
b
5
y
1
y
4
b
6
End b
E
Start b
0
A control algorithm can be implemented either as a program (program interpre-
tation) or as a network of logic elements connected in a particular way (hardwired
interpretation). In this book we discuss the methods of hardwired interpretation for
control algorithms represented by GSAs. These methods could be based either on
a model of a finite state machine (automaton with hardwired logic) or on the prin-
ciple of keeping the microprogram in a special control memory (automaton with
programmed logic) [1].
Methods of data-path design are not discussed in this book. They could be found,
for example, in [1, 6, 8, 35, 47]. Let us discuss the classical methods of control units
design.
4 1 Hardwired Interpretation of Control Algorithms
1.2 Control Algorithm Interpretation with Finite State
Machines
The finite state machine, called in [9] as microprogramautomaton, represents a con-
trol algorithm by a classical model, which is the composition of sequential circuit
CC and register RG (Fig. 1.4).
Fig. 1.4 Structural diagram
of finite state machine
CC
RG
Start
Clock
䃅 Y
X T
Presence of the register RG can be explained in the following way. The FSM
produces as its output information a time-distributed microinstruction sequence
Y(0),Y(1), . . . ,Y(t), where t is the automaton time determined by synchronization
pulse Clock. The initial instant t = 0 is determined by a single-shot pulse ”Start”.
To produce such a sequence, some information about prehistory of the system op-
eration is needed. This sequence is determined by input signals X(0), . . . , X(t −1)
for previous time intervals. Thus, output signal Y(t) at time t is determined by the
following expression:
Y(t) = f (X(0), . . . , X(t −1), X(t)). (1.1)
Expressions of this kind are very complex and could not be easy realized in hard-
ware, especially if they contain cycles with unpredictable number of iterations. The
internal states of FSM are used to represent the prehistory of its operation. The
states a
m
∈ A, where A = ¦a
1
, . . . , a
M
¦ is a set of internal states, are encoded by
binary codes K(a
m
) having
R = log
2
M| (1.2)
bits, where A| is the least integer, greater than or equal to A. This function is
known as a ceil function or ceiling [48]. Elements of the set of state variables
T = ¦T
1
, . . . , T
R
¦ are used to encode the states of FSM. The code of current state
is kept in register RG, which includes R flip-flops, and common timing signal Clock
is used for their synchronization. The code of initial state a
1
∈ A is loaded into reg-
ister using pulse ”Start”, the content of RG can be changed by pulse Clock on the
base of input memory (excitation) functions, which form the set Φ = ¦φ
1
, . . . , φ
R
¦.
As a rule, the register RG is implemented using D flip-flops [26, 45].
1.2 Control Algorithm Interpretation with Finite State Machines 5
The combinational circuit CC produces both input memory functions
Φ =Φ(T, X) (1.3)
and the output functions Y, which depend strongly on the FSM model in use [1]. In
case of the Mealy FSM, system Y is represented as
Y =Y(T, X), (1.4)
whereas in the case of Moore FSM these functions depend only on the states:
Y =Y(T). (1.5)
The method of FSM synthesis on the base of GSA Γ includes the following steps
[9]:
• construction of marked GSAΓ;
• encoding of the internal states (state assignment);
• construction of the structure table of FSM;
• construction of systems Φ and Y on the base of the structure table;
• implementation of FSM logic circuit using some logic elements.
Let us discuss some examples of FSM synthesis using GSA Γ
1
to represent the
control algorithm to be interpreted.
In case of Mealy FSM, marked GSA is constructed in the following way [9]:
• the output of the initial vertex b
0
and the input of the final vertex b
E
are marked
by an initial state a
1
(it is a final state, too);
• inputs of vertices b
t
∈ B, connected with outputs of operator vertices, are marked
by unique states a
2
, . . . , a
M
;
• any input can be marked only once.
Application of this procedure to GSA Γ
1
leads to the marked GSA Γ
1
(Fig. 1.5a),
corresponding to the graph of Mealy FSM S
1
(Fig. 1.5b). The vertices of this graph
correspond to the states of Mealy FSM S
1
, whereas its arcs correspond to the tran-
sitions among the states. Each arc is marked by a pair 'input signal, output signal`.
Input signal X
h
(h = 1, . . . , H) corresponds to conjunction of some variables from
the set X (or their complements). Output signal Y
h
⊆Y corresponds to some collec-
tion of microoperations y
n
∈Y, written into an operator vertex, which belongs to the
transition h of Mealy FSM (h = 1, . . . , H). Thus, Mealy FSM S
1
is described by sets
X =¦x
1
, x
2
¦, Y =¦y
1
, . . . , y
4
¦, A =¦a
1
, a
2
, a
3
¦ and has H = 5 transitions among its
states.
There are many methods of state assignment [1, 4, 7, 12, 13, 17, 18, 20, 21, 23, 25,
28–34, 36, 37, 39, 40, 42, 44, 46, 47, 51, 53,54, 56, 57, 59, 61–63, 65–67, 70], targeted on
optimization of hardware amount of the combinational circuit CC. These methods
depend strongly on logic elements in use. Let us use a trivial encoding of states first,
using minimum possible amount of state variable to encode the states. In case of
the Mealy FSM S
1
, we have M = 3, R = 2, T = ¦T
1
, T
2
¦. Let the states are encoded
6 1 Hardwired Interpretation of Control Algorithms
a
1
a
2
a
3
_ _
_
Fig. 1.5 Marked GSAΓ
1
(a) and graph of Mealy FSM S
1
(b)
using the following codes:K(a
1
) =00, K(a
2
) =01 and K(a
3
) =10. Let us point out
that the code K(a
1
) should include only zeros to simplify the circuit of setting FSM
into the initial state a
1
∈ A.
An FSM structure table (ST) can be viewed as the FSM graph represented by a
list of interstate transitions. This table includes a column Φ
h
with input memory
functions, which are equal to 1 in order to change the states of particular FSM
memory flip-flops. This table includes the following columns [9]: a
m
is the current
state of FSM; K(a
m
) is the code of the state a
m
∈ A; a
s
is the state of transition
(next state of FSM); K(a
s
) is the code of this state; X
h
is the input signal determined
the transition 'a
m
, a
s
`; Y
h
is the output signal produced during the transition'a
m
, a
s
`;
Φ
h
is the collection of input memory functions, which are equal to 1 to change the
register content from K(a
m
) into K(a
s
); h = 1, H is the number of transition.
Structure table is constructed in a trivial way using the automaton graph. In case
of Mealy FSM S
1
this table contains H = 5 lines (Table 1.1).
Functions (1.3) – (1.4) are derived from the FSM structure table as the sums of
products (SOP) depending on the following product terms
F
h
= A
m
X
h
(h = 1, . . . , H). (1.6)
In this formula, term A
m
is the conjunction of state variables T
r
∈ T corresponding
to the code of state a
m
∈ A from the line h of the structure table:
1.2 Control Algorithm Interpretation with Finite State Machines 7
Table 1.1 Structure table of Mealy FSM S
1
a
m
K(a
m
) a
s
K(a
s
) X
h
Y
h
Φ
h
h
a
1
00 a
2
01 1 y
1
y
2
D
2
1
a
2
01 a
3
10 x
1
y
3
D
1
2
a
3
10 ¯ x
1
x
2
y
2
y
3
D
1
3
a
1
00 ¯ x
1
¯ x
2
y
1
D
1
– 4
a
3
10 a
1
00 1 – – 5
A
m
= T
l
m
1
1
T
l
m
R
R
. (1.7)
In this formula, variable l
m
r
∈ ¦0, 1¦ is the value of bit r of the code K(a
m
), and
T
0
r
=
¯
T
r
, T
1
r
= T
r
(r = 1, . . . , R; m = 1, . . . , M). Systems (1.3) - (1.4) are represented
as the following SOPs:
φ
r
=
H

h=1
C
rh
F
h
(r = 1, . . . , R); (1.8)
y
n
=
H

h=1
C
nh
F
h
(n = 1, . . . , N). (1.9)
In these expressions, C
rh
(C
nh
) is a Boolean variable equal to 1, if and only if (iff)
the line of the ST includes the variable φ
r
(y
n
).
For example, from Table 1.1 we get the following equations: F
1
=
¯
T
1
¯
T
2
; F
2
=
¯
T
1
T
2
x
1
; F
3
=
¯
T
1
T
2
¯ x
1
x
2
; F
4
=
¯
T
1
T
2
¯ x
1
¯ x
2
, F
5
=
¯
T
1
¯
T
2
; y
1
= F
1
∨F
4
; y
2
= F
1
∨F
3
; y
3
=
F
2
∨F
3
; y
4
= F
4
; D
1
= F
2
∨F
3
; D
2
= F
1
.
Implementation of FSM circuit depends strongly on particular properties of logic
elements in use. This step will be discussed a bit later.
The marked GSA of Moore FSM is constructed using the following
procedure [9]:
• the vertices b
0
and b
E
are marked by the initial state a
1
;
• the operator vertices b
t
∈ B
1
are marked by unique states a
2
, . . . , a
M
.
Application of this procedure to the GSAΓ
1
leads to the marked GSAΓ
1
(Fig. 1.6a),
corresponding to the automaton graph of Moore FSM S
2
(Fig. 1.6b).
The vertices of Moore automaton graph are marked by output signals y
n
∈ Y,
because of it its arcs are marked only b
y
input signals determining the transitions
among the states. Thus, the Moore FSM S
2
is represented by the sets X = ¦x
1
, x
2
¦,
Y = ¦y
1
, . . . , y
4
¦, A = ¦a
1
, . . . , a
5
¦, and it has H = 7 transitions.
In case of the Moore FSM S
2
, we have R = 3, T = ¦T
1
, T
2
, T
3
¦. Let us encode its
states in the following manner:K(a
1
) =000, . . . , K(a
5
) =100. The structure table of
Moore FSM is constructed using the automaton graph (or the marked GSA). This
table has the following columns: a
m
, K(a
m
), a
s
, K(a
s
), X
h
, Φ
h
, h. Information about
output signals to be produced is placed into the column a
m
[9]. In case of the Moore
FSM S
2
, the structure table contains H = 7 lines (Table 1.2).
8 1 Hardwired Interpretation of Control Algorithms
a
1
a
2
a
3
_
-
a
4
a
5
-
-
-
-
Fig. 1.6 Marked GSAΓ
1
(a) and automaton graph of Moore FSM S
2
(b)
Boolean systems (1.3) and (1.5) are derived from the structure table; let us point
out that system (1.3) depends on terms (1.6) and its SOP is similar to system (1.8).
Functions (1.5) are represented in the form
y
n
=
M

m=1
C
nm
A
m
(n = 1, . . . , N), (1.10)
where C
nm
is a Boolean variable equal to 1 iff microoperations y
n
∈Y are executed,
when FSM is in the state a
m
∈ A.
For Moore FSM S
2
, we get from Table 1.2: F
1
=
¯
T
1
¯
T
2
¯
T
3
, F
1
=
¯
T
1
¯
T
2
¯
T
3
x
1
, . . . , F
7
=
T
1
¯
T
2
¯
T
3
; D
1
= F
5
∨F
6
; D
2
= F
2
∨F
3
; D
3
= F
1
∨F
3
; A
1
=
¯
T
1
¯
T
2
¯
T
3
; . . . , A
5
= T
1
¯
T
2
¯
T
3
;
y
1
= A
2
∨A
5
; y
2
= A
2
∨A
4
; y
3
= A
3
∨A
4
; y
4
= A
5
.
Automata S
1
and S
2
are equivalent in the sense that they interpret the same GSA
Γ
1
. Comparison of automata S
1
and S
2
leads to the following conclusions satisfied
for all equivalent Mealy and Moore automata:
• Moore FSM has, as a rule, more states and transitions than the equivalent Mealy
FSM;
• system of output signals of Moore FSM has regular form, because it depends
only on the states of FSM.
1.2 Control Algorithm Interpretation with Finite State Machines 9
Table 1.2 Structure table of Moore FSM S
2
a
m
K(a
m
) a
s
K(a
s
) X
h
Φ
h
h
a
1
(–) 000 a
2
001 1 D
3
1
a
2
(y
1
y
2
) 001 a
3
010 x
1
D
2
2
a
4
011 ¯ x
1
x
2
D
2
3
a
1
000 ¯ x
1
¯ x
2
- 4
a
3
y
3
) 010 a
5
100 1 D
1
5
a
4
(y
2
y
3
) 011 a
5
100 1 D
1
6
a
5
(y
1
y
4
) 100 a
1
000 1 - 7
Let us point out that model of Moore FSMis used more often in practical design [48]
because it offers more stable control than the control units based on the Mealy FSM
model. Moreover, system (1.5) is regular, what means that it is specified for more
than 50% of all possible input assignments. This regularity makes possible imple-
mentation of this system using either read-only memory (ROM) chips or random-
access memory (RAM) blocks [11].
The number of product terms in the input memory functions system can be re-
duced due to existence of the pseudoequivalent states of Moore FSM [14]. The
states a
m
, a
s
∈ A are called pseudoequivalent states of Moore FSM, if there exist the
arcs 'b
i
, b
t
`, 'b
j
, b
t
` ∈ E, where vertex b
i
∈ B
1
is marked by state a
m
∈ A and vertex
b
j
∈B
1
by state a
s
∈A. Thus, the states a
3
and a
4
of the Moore FSM S
2
are pseudoe-
quivalent states. They cannot be treated as equivalent states [9] because of different
output signals generated for these states. As follows from Table 1.2, the columns
a
s
−−Φ
h
of structure table for the states a
3
and a
4
contain the same information.
Let Π
A
= ¦B
1
, . . . , B
I
¦ be a partition of set A into the classes of pseudoequivalent
states . For example, in the case of Moore FSM S
2
we have Π
A
=¦B
1
, . . . , B
4
¦, with
B
1
= ¦a
1
¦, B
2
= ¦a
2
¦, B
3
= ¦a
3
, a
4
¦, B
4
= ¦a
5
¦. The number of terms in system
Φ can be reduced due to optimal state encoding [14], when the codes of pseudoe-
quivalent states from some class B
i
∈ Π
A
belong to a single generalized interval of
an R-dimensional Boolean space . For example, the well-known algorithms NOVA,
ASYL or ESPRESSO [47] can be used for the state encoding mentioned above .
The optimal state encoding for the Moore FSM S
2
is shown in the Karnaugh map
(Fig. 1.7).
As follows from Fig. 1.7, the class B
1
corresponds to the interval K(B
1
) = 000,
B
2
→ K(B
2
) = ∗01, B
3
→ K(B
3
) = ∗1∗, B
4
→ K(B
4
) = 1 ∗ ∗, where sign ”∗”
Fig. 1.7 Optimal state codes
for Moore FSM S
2
T1
a
1
a
2
a
3
a
4
a
5
0
1
00 01 11 10
T2T3
* * *
10 1 Hardwired Interpretation of Control Algorithms
determines ”don’t care” value of state variable T
r
∈ T. These intervals can be con-
sidered as the codes of classes B
i
∈ Π
A
. Let us construct a transformed structure
table of Moore FSM with the following columns:B
i
, K(B
i
), a
s
, K(a
s
), X
h
, Φ
h
, h. To
do this we replace the column a
m
by the column B
i
, and the column K(a
m
) by the
column K(B
i
). If the structure table transformed in this way contains equal lines,
only one of them should find place in the final transformed table. For example, the
transformed structure table of Moore FSM S
2
(Table 1.3) contains H = 6 lines.
The transformed structure table serves as the base to form product terms (1.6),
but now these terms include variables l
mr
∈ ¦0, 1, ∗¦, where T
0
r
=
¯
T
r
, T
1
r
= T
r
, T

r
=
1(m = 1, . . . , M; r = 1, . . . , R). Presence of "don’t care" input assignments makes
possible to reduce the number of product terms in system (1.8), which has only
H
0
terms. Thus, in case of the Moore FSM S
2
we have: F
1
=
¯
T
1
¯
T
2
¯
T
3
; F
1
=
¯
T
2
T
3
x
1
;
F
3
=
¯
T
2
T
3
¯ x
1
x
2
; F
4
=
¯
T
2
T
3
¯ x
1
¯ x
2
; F
5
= T
2
; F
6
= T
1
. We find that terms F
4
and F
6
are
not the parts of SOP (1.8).
Table 1.3 Transformed structure table of Moore FSM S
2
B
i
K(B
i
) a
s
K(a
s
) X
h
Φ
h
h
B
1
000 a
2
001 1 D
3
1
B
2
*01 a
3
011 x
1
D
2
D
3
2
a
4
010 ¯ x
1
x
2
D
2
3
a
1
000 ¯ x
1
¯ x
2
– 4
B
3
*1* a
5
100 1 D
1
5
B
4
1** a
1
000 1 – 6
It was shown in [14] that optimal state encoding permits to compress the trans-
formed structure table of Moore FSM up to corresponding size of the equivalent
Mealy FSM structure table.
As a rule, models of FSM are used for implementation of fast operational units
[1]. If system performance is not important for a project, the control unit can be
implemented as a microprogram control unit (MCU).
1.3 Control Algorithm Interpretation with Microprogram
Control Units
Microprogramcontrol units are based on the operational - address principle for pre-
sentation of control words (microinstructions) kept in a special control memory [1].
The typical method of MCU design includes the following steps [1]:
• transformation of initial graph-scheme of algorithm;
• generation of microinstructions with given format;
• microinstruction addressing;
1.3 Control Algorithm Interpretation with Microprogram Control Units 11
• encoding of operational and address parts of microinstructions;
• construction of control memory content;
• synthesis of logic circuit of MCU using given logic elements.
The mode of microinstruction addressing affected tremendously the method of
MCU synthesis [2, 3, 5]. Three particular addressing modes are used most often
nowadays:
• compulsory addressing of microinstructions ;
• natural addressing of microinstructions; ;
• combined addressing of microinstructions.;
As a rule, microinstruction formats include the following fields:FY, FX, FA
0
and
FA
1
. The field FY, operational part of the microinstruction, contains information
about microoperations y
n
∈Y (t = 0, 1, . . .), which are executed in cycle t of control
unit operation. The field FX contains information about logical condition x
t
l
∈ X,
which is checked at time t(t =0, 1, . . .). The field FA
0
contains next microinstruction
address A
t+1
(transition address), either in case of unconditional transition (go to
type), or if x
t
l
= 0. The field FA
1
contains next microinstruction address for the case
when x
t
l
= 1. The fields FX, FA
0
andFA
1
form the address part of microinstruction.
Consider an example of MCU design with compulsory microinstruction ad-
dressing S
3
interpreting GSA Γ
1
(Fig. 1.3). The microinstruction format is shown
in Fig. 1.8.
Fig. 1.8 Format of microin-
structions with compulsory
addressing
FY FX FA
0
FA
1
The address of next microinstruction A
t+1
is determined by contents of the fields
[FX]
t
, [FA
0
]
t
and [FA
1
]
t
(t = 0, 1, . . .) using the following rules:
A
t+1
=



[FA
0
]
t
, if [FX]
t
= / 0;
[FA
0
], if x
t
l
= 0;
[FA
1
], if x
t
l
= 1.
(1.11)
First line of expression 1.11 determines the address of transition in case of uncon-
ditional jump, whereas the second and third lines determine this address for the
conditional jump.
Structural diagram of MCU with compulsory microinstruction addressing
(Fig. 1.9) includes the following blocks [13]:
• sequencer CFA, calculating transition address from (1.11);
• register of microinstruction address RAMI, keeping address A
t
;
• control memory CM, keeping microinstructions;
• block of microoperation generation CMO;
• fetch flip-flop TF used to organize the stop mode of the MCU.
12 1 Hardwired Interpretation of Control Algorithms
Fig. 1.9 Structural diagram
of MCU with compulsory
addressing
CFA RAMI
CMO
CM
FA
1
FA
0
FX
FY
S TF
R
X
Start
Clock
Fetch
Y
y
E
A
t

The control unit S
3
operates as follows. The pulse "Start" is used to load the address
of first microinstruction to be executed (start address) into RAMI. At the same time
the flip-flop TF is set up; signal Fetch=1 initiates reading of a microinstruction from
the control memory. Let some address A
t
be located in the register RAMI at time
t (t = 0, 1, . . .). Corresponding microinstruction is then fetched from the memory
CM. The operational part of this microinstruction is next transformed by the block
CMO into microoperations y
n
∈ Y, which are directed to a system data-path. The
sequencer CFA processes both the microinstruction address part and logical condi-
tions X to produce the functions Φ, which form a transition address A
t+1
sent into
register RAMI. This address is loaded into RAMI by synchronization pulse "Clock".
If the end of microprogram is reached, then special signal y
E
is generated to clear
the flip-flop TF. It causes termination of microinstruction fetching from memory
CM, which means the end of MCU operation.
The transformation of initial GSA Γ is executed using the following rules [10]:
• if there is an arc 'b
q
, b
E
` ∈ E, such that b
q
∈ B
1
, the variable y
E
is assigned to the
vertex b
q
;
• if there is an arc 'b
q
, b
E
` ∈ E, such that b
q
∈ B
2
, an additional operator vertex
b
Q+1
(Q = [B[ −2) with the variable y
E
is inserted into GSA Γ, and the arc
'b
q
, b
E
` is replaced by arcs 'b
q
, b
Q+1
` and 'b
Q+1
, b
E
`.
Therefore, the transformation of GSA for MCU with compulsory addressing of mi-
croinstructions is necessary to organize the ending mode of the MCU. Thus, trans-
formation of the GSA Γ
1
is reduced to inserting the variable y
E
into the vertex
b
6
∈ B
1
and adding the vertex b
7
. The transformed GSA Γ
1
(S
3
) thus obtained is
shown in Fig. 1.10.
Generation of microinstructions with compulsory addressing is reduced to suc-
cessive analysis of pairs of vertices'b
q
, b
t
` ∈ E. All possible vertices pair configura-
tions are shown in Fig. 1.11
There are four possible configurations:
• b
q
, b
t
∈ B
1
(Fig. 1.11a). In this case the vertex b
q
∈ B corresponds to microin-
struction with empty fields FX and FA
1
, whereas its field FY contains the set
of microoperations Y
q
and field FA
0
contains the microinstruction address, cor-
responding to vertex b
t
∈ B
1
. The analysis should be continued for the vertex
1.3 Control Algorithm Interpretation with Microprogram Control Units 13
b
t
∈ B
1
. If, in such a pair, second vertex is the final vertex of GSA (b
t
= b
E
),
then the vertex b
q
corresponds to microinstruction with empty fields FX, FA
0
and FA
1
;
• b
q
∈ B
1
, b
t
∈ B
2
(Fig. 1.11b). In this case, the pair of vertices corresponds to one
microinstruction with all fields containing useful information;
• b
q
, b
t
∈ B
2
(Fig. 1.11c). In this case the vertex b
t
∈ B
2
corresponds to microin-
struction with empty field FY, and the analysis should be continued for the vertex
b
q
∈ B
2
;
• b
q
∈ B
2
, b
t
∈ B
1
(Fig. 1.11d). In this case the analysis should be continued for
the both vertices of the pair.
Let us denote microinstructions by symbols O
m
(m = 1, . . . , M); now the follow-
ing microinstructions can be generated using the transformed GSA Γ
1
(S
2
): O
1
=
'b
1
, b
2
`, O
2
= 'b
3
, / 0`, O
3
= '/ 0, b
4
`, O
4
= 'b
5
, / 0`, O
5
= 'b
6
, / 0`, O
6
= 'b
7
, / 0`.
Addresses of microinstructions with compulsory addressing can be appointed
in the following manner. Each microinstruction O
m
corresponds (one-to-one) to a
binary code A
m
with R = log
2
M| bits (m = 1, . . . , M). A microinstruction with
start address is determined by the arc 'b
0
, b
q
` ∈ E. In the case under consideration
there is the arc 'b
0
, b
1
` ∈ E (Fig. 1.10), and therefore the start address belongs to
the microinstruction O
1
, corresponding to the pair with vertex b
1
∈ B
1
. All other
microinstructions are addressed in arbitrary manner.
The microprogramof MCU S
3

1
) includes M =6 microinstructions, thus R =3;
it is clear that A
1
= 000. Let A
2
= 001, . . . , A
6
= 101.
Fig. 1.10 Transformed
GSAΓ
1
(S
3
)
y
1
y
2
b
1
x
1
1 0
b
2
y
3
b
3 x
2
1 0
b
4
y
2
y
3
b
5
y
1
y
4
y
E
b
6
End b
E
Start b
0
y
E
b
7
14 1 Hardwired Interpretation of Control Algorithms
Because the control memory can keep only some bit strings, the encoding of oper-
ational and address parts of microinstructions is necessary to load microinstructions
into the control memory. Addressing of microinstructions gives information, which
should be written into the fields FA
0
and FA
1
.There are many methods to encode
operational part of microinstructions [11]. Let us choose the one-hot encoding of
microoperations to design the control memory of MCU S
3

1
), where S
3

1
) means
that the GSA Γ
1
is interpreted by MCU with compulsory addressing of microin-
structions. In case of one-hot encoding the length (bit capacity) n
1
of the field FY is
determined by the following formula:
n
1
= N+1. (1.12)
For MCU S
3

1
) this formula gives the value n
1
= 5.
Let us encode logical conditions x
l
∈ X using binary codes with minimum length
(called sometimes minimal-length codes)
n
2
= log
2
(L+1)|. (1.13)
The value 1 is added into (1.13) in order to take into account the code for uncondi-
tional jump, when [FX] = / 0. For MCU S
3

1
) this formula gives the value n
2
= 2.
Let K(/ 0) = 00; K(x
1
) = 01; K(x
2
) = 10.
Construction of the control memory content results in construction of a table
with lines keeping microinstruction addresses and binary codes of particular mi-
croinstructions. Control memory of MCU S
3
keeps M microinstructions with
n
3
= n
1
+n
2
+2R (1.14)
bits. In case of MCU S
3

1
) this formula gives the value n
3
=13. The control mem-
ory content for MCU S
3

1
) is shown in Table 1.4.
In this table, microinstruction addresses are represented by variables from the set
A=¦a
1
, a
2
, a
3
¦, whereas the codes of microinstructions are represented by variables
x
I
1 0
b
t
y
q
b
q
y
t
b
t
y
q
b
q
x
I
1
0
b
q
x
I
1 0
b
t
x
I
1
0
b
q
y
t
b
t
a) c) b) d)
Fig. 1.11 Possible configurations for pairs of GSA vertices
1.3 Control Algorithm Interpretation with Microprogram Control Units 15
Table 1.4 Control memory content for MCU S
3

1
)
Address FY FX FA
0
FA
1
Formula of transition
a
1
a
2
a
3
v
1
v
2
v
3
v
4
v
5
v
6
v
7
v
8
v
9
v
10
v
11
v
12
v
13
000 11000 01 010 001 O
1
→ ¯ x
1
O
3
∨x
3
O
2
001 00100 00 100 000 O
2
→ O
5
010 00000 10 101 011 O
3
→ ¯ x
2
O
6
∨x
2
O
4
011 01100 00 100 000 O
4
→ O
5
100 10011 00 000 000 O
5
→ End
101 00001 00 000 000 O
6
→ End
from the set V =¦v
1
, . . . , v
13
¦, where [A[ =R, [V[ =n
3
. The last column of the table
contains formula of transitions for microinstructions, which are direct analogues of
the formulae of transitions for operators of GSA [9].
Analysis of this table shows the main drawbacks of MCU with compulsory
addressing of microinstructions, such as:
• an empty field FY for microinstructions, corresponding to the pairs '/ 0, b
t
`, where
b
t
∈ B
2
;
• empty fields FX and FA
1
for microinstructions, corresponding to the pairs
'b
t
, / 0`, where b
t
∈ B
1
.
It results in the inefficient use of control memory volume, but a positive feature of
compulsory addressing is the minimum number of microinstructions for the partic-
ular GSA, in comparison with MCU with other modes of microinstruction address-
ing [1]. Synthesis of the logic circuit of MCU S
3
is reduced to the implementation of
block CFA using standard multiplexers and control memory using standard memory
blocks, such as PROM or RAM chips [1]. Let us point out that some logic elements
should be used to implement the block CMO [1].
Assume that content of the field FA
1
is loaded into register RAMI if z
1
= 1,
otherwise (if z
1
=0) RAMI is loaded fromthe field FA
0
of current microinstruction.
Thus, expression (1.11) can be represented as
A
t+1
= ¯ z
1
[FA
0
] ∨z
1
[FA
1
]. (1.15)
The variable z
1
= 1, if a logical condition to be checked is equal to 1; it means that
z
1
=
L

l=1
V
l
x
l
, (1.16)
where V
l
is a conjunction of variables v
r
∈ V, corresponding to the code K(x
l
)
(l = 1, . . . , L).
In case of the MCU S
3

1
) expression (1.15) is represented as
a
1
= ¯ z
1
v
8
∨z
1
v
11
;
a
2
= ¯ z
1
v
9
∨z
1
v
12
; (1.17)
16 1 Hardwired Interpretation of Control Algorithms
a
3
= ¯ z
1
v
10
∨z
1
v
13
,
and expression (1.16) has now the form
z
1
= ¯ v
1
¯ v
2
0∨ ¯ v
1
v
2
x
1
∨v
1
¯ v
2
x
2
. (1.18)
This formula specifies standard multiplexer with two control inputs and three data
inputs in use. The first term of expression (1.18) corresponds to unconditional jump.
Symbol "0" represents the fact that logic 1 should be connected with informational
input of the multiplexer corresponding to code 00; variables a
r
from (1.17) coincide
with variables D
r
(r = 1, . . . , R). Expressions (1.17) – (1.18) determine the logic
circuit of sequencer CFA of the MCU S
3

1
), shown in Fig. 1.12. Operation of this
circuit can be easily deduced from Fig. 1.12.
Fig. 1.12 Logic circuit of
CFA of MCU S
3

1
)
0 MX
1
2
3
1
2
"0"
x
1
x
2
v
6
v
7
z
1
0 MX
1
1
1
D
1
v
8
v
11
.
.
.
0 MX
3
1
1
D
3
v
10
v
13
There are two microinstruction formats in case of natural microinstruction ad-
dressing [1, 12]: operational microinstructions corresponding to operator vertices of
GSA Γ and control microinstructions corresponding to conditional vertices of GSA
Γ (Fig. 1.13).
Fig. 1.13 Microinstruction
formats for MCU with nat-
ural addressing of microin-
structions
0 FY
1 FX FA
0
First bit of each format represents field FA, used to recognize the type of mi-
croinstruction. Let FA = 0 correspond to operational microinstruction and FA = 1
to control microinstruction. As follows from Fig. 1.13, next address is not included
into operational microinstructions. The same is true for the case, when a logical con-
dition to be checked is equal to 1. In both cases mentioned above current address A
t
is used to calculate next address:
A
t+1
= A
t
+1. (1.19)
1.3 Control Algorithm Interpretation with Microprogram Control Units 17
Hence the following rule is used for next address calculation:
A
t+1
=







A
t
+1, if [FA]
t
= 0;
A
t
+1, if (x
t
l
) ∧([FA]
t
= 1),
[FA
0
]
t
, if (x
t
l
= 0) ∧([FA]
t
= 1);
[FA
0
]
t
, if ([FX]
t
= / 0) ∧([FA]
t
= 1).
(1.20)
Analysis of (1.20) shows that MCU with natural addressing of microinstructions
should include a counter CAMI. Corresponding structure is shown in Fig. 1.14.
Fig. 1.14 Structural dia-
gram of MCU with natural
addressing of microinstruc-
tions
CFA CAM I
CMO
S TF
R
X
Start
Clock
Fetch
Y
y
E
A
t
FA
FX
CM
FA
+1
z
1
z
0
FY
FA
0
This MCU operates in the following manner. The pulse "Start" initiates loading
of start address into CAMI. At the same time flip-flop TF is set up. Let an address
A
t
be located in CAMI at time t (t = 0, 1, . . . , ). If this address determines an oper-
ational microinstruction, the block CMO generates microoperations y
n
∈Y, and the
sequencer CFAproduces signal z
1
. If this address determines a control microinstruc-
tion, microoperations are not generated, and the sequencer produces either signal z
0
(corresponding to an address loaded fromthe field FA
0
), or signal z
1
(it corresponds
to adding 1 to the content of CAMI). The content of counter CAMI can be changed
by pulse "Clock". If variable y
E
is generated by CMO, then the flip-flop TF is cleared
and operation of MCU terminated.
Let symbol S
4
stand for this kind of MCU. Now we use an example of MCU
S
4

1
) to discuss some particular problems of such a design.
The transformation of initial GSA is executed in two consecutive steps. First
step involves the same transformations as in case of MCU S
3
. Addressing conflicts
between microinstructions [1,12] are eliminated during the second step. Let us point
out that in case of MCU S
4
operational microinstructions correspond to operator
vertices b
q
∈ B
1
and control microinstructions correspond to conditional vertices
b
q
∈ B
2
. Nature of addressing conflicts is the consequence of implicit transition
addresses, as expressed by (1.19).
Let some GSA include two arcs 'b
i
, b
q
`, 'b
j
, b
q
` ∈ E, where b
i
, b
j
∈ B
1
(Fig. 1.15a). Let indexes of vertices, corresponding microinstructions and microin-
struction addresses be the same and take A
i
= 100. According to (1.19) we find that
18 1 Hardwired Interpretation of Control Algorithms
A
q
= 101, which means that the address A
j
should be equal to 100. Thus, microin-
structions O
i
and O
j
should have the same address. We call this situation addressing
conflict. Some conditional vertex b
t
with logical condition x
0
should be inserted in
the initial GSA to eliminate this conflict. This condition corresponds to the uncon-
ditional jump, when FX = / 0 (Fig. 1.16a).
x
I
1 0
b
q
y
j
b
j
x
i
1
0
b
i
x
j
1
0
b
j
y
q
b
q
b)
a)
y
i
b
i
Fig. 1.15 Addressing conflicts in MCU S
4
x
I
1
0
b
q
y
j
b
j
x
i
1
0
b
i
x
j
1
0
b
j
y
q
b
q
b) a)
y
i
b
i
x
0
0
b
t
1
x
0
0
b
t
1
Fig. 1.16 Elimination of addressing conflicts
Now, if A
i
= 100, we have A
q
= 101, and the field FA
0
of microinstruction O
t
contains address A
q
= 101. Addressing conflict is possible also between control mi-
croinstructions (Fig. 1.15b), and its elimination requires inserting of some additional
vertex (Fig. 1.16b).
Let us point out that GSA subgraphs, similar to ones shown in Fig. 1.15, can have
arbitrary number of vertices. Addressing conflicts can arise also among operational
microinstructions and control microinstructions [11].
The transformed GSAΓ
1
(S
4
) contains M =8 vertices (Fig. 1.17). As the result of
transformation, variable y
E
is inserted into vertex b
6
, vertex b
7
with y
E
is added, and
vertex b
8
is also added, to eliminate addressing conflict between microinstructions
corresponding to vertices b
3
and b
5
.
1.3 Control Algorithm Interpretation with Microprogram Control Units 19
Fig. 1.17 Transformed
GSAΓ
1
(S
4
)
y
1
y
2
b
1
x
1
1 0
b
2
y
3
b
3
x
2
1 0
b
4
y
2
y
3
b
5
y
1
y
4
y
E
b
6
End b
E
Start b
0
y
E
b
7
x
0
1 0
b
8
As it was mentioned above, each operator vertex corresponds to an operational
microinstruction and each conditional vertex corresponds to a control microinstruc-
tion. It means that microinstructions are generated in a very simple way. For exam-
ple, the microprogram of MCU S
4

1
) includes M = 8 microinstructions.
Generation of special microinstruction sequences is needed in case of natural ad-
dressing of microinstructions. These sequences are created as follows. Let us build
a set I(Γ), elements of which are inputs of the sequences. Vertex b
q
∈ B
1
∪B
2
is the
input of a sequence, if the input of this vertex is connected either with the output of
vertex b
0
or with the output of conditional vertex, marked as "0".
In case of the MCU S
4

1
), the set I(Γ) = ¦b
1
, b
4
, b
7
¦ and microinstruction
sequences are started by corresponding microinstructions. End points of these se-
quences are microinstructions corresponding to vertices connected with final vertex
b
E
, or conditional vertex with x
0
. Let α
g
denote a microinstruction sequence. There
are three such sequences in case of MCU S
4

1
), namely α
1
= 'O
1
, O
2
, O
3
, O
8
`,
α
2
= 'O
4
, O
5
, O
6
`, α
3
= 'O
7
`. The zero address is assigned to the microinstruction
corresponding to vertex b
t
, where 'b
0
, b
t
` ∈ E. Addresses of next microinstructions
belonging to this sequence are calculated according to (1.19). The address of cur-
rent sequence input is calculated by adding 1 to the address of last microinstruc-
tion from previous sequence, and so on. Application of this procedure to the case
of MCU S
4

1
), when R = 3, results in the microinstruction addresses shown in
Table 1.5.
Encoding of operational and address parts of microinstructions is executed in
the same manner as in case of MCU S
3
. Let us take the case of MCU S
4

1
), and
20 1 Hardwired Interpretation of Control Algorithms
Table 1.5 Microinstruction addresses of MCU S
4

1
)
O
m
A
m
O
m
A
m
O
m
A
m
O
m
A
m
O
1
000 O
3
010 O
4
100 O
6
110
O
2
001 O
8
011 O
5
101 O
7
111
use one-hot codes for microoperations (n
1
= 5), as well as minimal-length codes
for logical conditions (n
2
= 2). Let corresponding codes for both MCU S
3

1
) and
S
4

1
) be the same.
Construction of the control memory content is executed due to the fact that the
usage of microinstruction bits depends on microinstruction type. The control mem-
ory of MCU S
4
contains M microinstructions with
n
4
= max(n
1
+1, n
2
+R+1) (1.21)
bits; for example, for MCU S
4

1
) it can be found that n
4
= 6. The control memory
content of MCU S
4

1
) is shown in Table 1.6.
Table 1.6 Microinstruction addresses of MCU S
4

1
)
Address FA FX FA
0
Formula of transitions
FY
a
1
a
2
a
3
v
1
v
2
v
3
v
4
v
5
v
6
000 0 11000 O
1
→ O
2
001 1 01100 O
2
→ ¯ x
1
O
4
∨x
1
O
3
010 0 00100 O
3
→ O
8
011 1 00110 O
8
→ ¯ x
0
O
6
∨x
0
O
6
100 1 10111 O
4
→ ¯ x
2
O
7
∨x
2
O
5
101 0 01100 O
5
→ O
6
110 0 10011 O
6
→ End
111 0 00001 O
7
→ End
Let us discuss now the design of sequencer CFA for MCU S
4
. The variable
z
1
= 1 should be generated either if x
t
l
= 1 or when an operational microinstruc-
tion is executed at time t. Thus, the logical expression for calculation of z
1
can be
obtained by the following transformation of expression (1.16):
z
1
= (
L

l=1
V
l
x
l
) ∨ ¯ v
1
, (1.22)
where v
1
= 0 corresponds to FA=0. It is clear that z
0
= ¯ z
1
.
Let the counter CAMI have input C
1
, used to increment the counter content and
input C
2
to load the input parallel code into the counter under the influence of pulse
"Clock". The corresponding Boolean expressions for C
1
andC
2
have the form:
1.3 Control Algorithm Interpretation with Microprogram Control Units 21
C
1
= z
1
Clock,
C
2
= ¯ z
1
Clock.
(1.23)
Expressions (1.23) serve to design the logic circuit of sequencer CFA for MCU
S
4

1
) shown in Fig. 1.18.
Fig. 1.18 Implementation
of the block CFA for MCU
S
4

1
)
0
1
2
3
1
2
CS
"0"
x
1
x
2
v
2
v
3
C
2
Clock
v
1
MX
&
&
1
v
1
_
z
1
z
0
1
C
1
In this circuit multiplexer MX is active if v
1
= 1 is applied to the "enable" input
CS of the chip. It corresponds to a control microinstruction. Remaining elements
of this circuit follow directly from expressions (1.22) and (1.23). The methods of
control memory implementation will be discussed later.
The comparative analysis of Tables 1.4 and 1.6 shows that MCU S
4
is charac-
terized by longer microprogram, than the equivalent MCU S
3
. In case of MCU S
4
,
control algorithm execution requires more time, than in case of the equivalent MCU
S
3
. A positive feature of MCU S
4
is smaller microinstruction length. In case of our
example we find that n
3
= 2, 17n
4
.
Microprogram control units with combined microinstruction addressing
(Fig. 1.19) represent a compromise settlement with average number of microin-
structions, of bit capacity and of control algorithm execution time.
Fig. 1.19 Microinstruction
format with combined ad-
dressing
FY FX FA
0
In this case, transition address is described by the expression:
A
t+1
=



[FA
0
], if [FX[
t
= / 0;
[FA
0
]
t
, if x
t
l
= 0;
[FA
1
]
t
, if x
t
l
= 1.
(1.24)
It follows from (1.24), that addressing conflicts are possible only between microin-
structions with [FX] = / 0. A design method, which can be used for MCU with com-
bined microinstruction addressing, can be found in [1, 11].
Microprogramcontrol units were very popular in the past [1, 12, 13, 16, 19, 24, 27,
38, 41, 43, 52, 55, 58, 60, 64], but they have one serious disadvantage, namely infe-
rior performance in comparison with the equivalent finite state machines. As a rule,
only single logical condition is checked during one cycle of MCU operation. Thus,
multidirectional transitions depending on k >1 logical conditions need k >1 cycles
22 1 Hardwired Interpretation of Control Algorithms
for its execution, and the controlled data-path will have k −1 idle cycles, when its
resources are not in use. Positive feature of MCU is the use of regular control mem-
ory to implement the microinstruction system, because MCU are Moore FSM [1].
Besides, the sequencer CFA is very simple and can be implemented using standard
multiplexers. As a rule, any change in the control algorithm leads to the redesign of
corresponding FSM, but only small modifications of the control memory content in
the equivalent MCU are needed.
1.4 Organization of Compositional Microprogram Control
Units
The properties of the interpreted control algorithm have great influence on the hard-
ware amount of corresponding control unit [11]. One of such properties is the exis-
tence of operational linear chains corresponding to the paths of GSA, which include
operator vertices only. Let us call a GSA Γ the linear GSA (LGSA), if the number
of its operator vertices exceeds 75% of the total number of vertices. Existence of
operational linear chains allows simplification of input memory functions and re-
duction of hardware amount in the logic circuit of control unit. In this case either
shift register [50] or up counter [4, 49] is used to keep state codes.
One of the approaches for linear GSA interpretation is the use of compositional
microprogram control units (CMCU), which can be viewed as a composition of the
finite state machine and microprogram control unit [15]. These units have several
particularities, distinguishing them from other control units:
1. Microinstruction format includes the operational part only. It permits to mini-
mize the control word bit capacity. Thus control words kept in control memory
have minimum possible length in comparison with all organizations of MCU
mentioned above.
2. Microprograms have minimum possible length (the number of microinstruc-
tions), because the CMCU control memory is free from control microinstruc-
tions.
3. Multidirectional transitions are executed in one cycle of CMCU operation. It
provides minimum time of control algorithm interpretation. Thus, such control
units have similar performance, as compared with the equivalent FSM.
Let us introduce some definitions helping to understand the features of CMCU.
Definition 1.1. An operational linear chain (OLC) of GSA Γ is a finite vector of
operator vertices α
g
= 'b
g
1
, . . . , b
g
F
g
`, such that an arc 'b
g
i
, b
g
i+1
` ∈ E corresponds
to each pair of adjacent vertices b
g
i
, b
g
i+1
, where i is the component number of
vector α
g
.
Let D
g
be a set of operator vertices, which are components of OLC α
g
.
Definition 1.2. An operator vertex b
q
∈ D
g
is called an input of OLC α
g
, if there is
an arc 'b
t
, b
q
` ∈ E, such that b
t
/ ∈ D
g
.
1.4 Organization of Compositional Microprogram Control Units 23
Definition 1.3. An input b
q
∈ D
g
is called a main input of OLC α
g
, if GSA Γ does
not include an arc 'b
t
, b
q
` ∈ E such that b
t
∈ B
1
.
Definition 1.4. An operator vertex b
q
∈ D
g
is called an output of OLC α
g
, if there is
an arc 'b
q
, b
t
` ∈ E, where b
t
/ ∈ D
g
.
It follows from the basic properties of GSA [9] that each OLC α
g
corresponding to
definitions given above should have at least one input and exactly one output. Let I
j
g
stand for input j of OLC α
g
and O
g
for its output. Let inputs of OLC α
g
form a set
I(α
g
).
For GSA Γ we have the following sets:
1. A set of OLC C = ¦α
1
, . . . , α
G
¦, satisfying the following condition
D
1
∪. . . ∪D
G
= B
1
;
[D
i
∩D
j
[ = 0 (i = j; i, j ∈ ¦1, . . . , G¦);
G → min.
(1.25)
2. A set of inputs I(Γ) of the operational linear chains of GSA Γ:
I(Γ) =
G

g=1
I(α
g
). (1.26)
3. A set of outputs O(Γ) of the operational linear chains of GSA Γ:
O(Γ) = ¦O
1
, . . . , O
G
¦. (1.27)
Let the natural microinstruction addressing be executed for microinstructions corre-
sponding to the adjacent components of each OLC α
g
∈C:
A(b
g
i+1
) = A(b
g
i
) +1 (i = 1, . . . , F
g
−1). (1.28)
In expression (1.28) symbol A(b
g
i
) stands for the address of microinstruction corre-
sponding to component i of vector α
g
∈C, where i = 1, . . . , F
g
−1.
In this case GSA Γ can be interpreted by compositional microprogram control
unit with basic structure of Fig. 1.20 [15]. Let us denote it as unit U
1
.
Fig. 1.20 Structural di-
agram of compositional
microprogram control unit
with basic structure
CC
Start
Clock
Fetch
Y
CM
+1
CT
RG
R TF
S
Start
X
y
E
y
0
<
W
24 1 Hardwired Interpretation of Control Algorithms
In the unit U
1
, combinational circuit CC and register RG form a finite state ma-
chine S
1
, which will be called microinstruction addressing unit or FSM S
1
. Counter
CT, control memory CM and flip-flop TF form microprogram control unit S
2
with
natural microinstruction addressing. The unit U
1
operates in the following manner.
The pulse ”Start” initializes following actions: the zero code of FSM S
1
initial
state is loaded into register RG; start address of microprogramis loaded into counter
CT; flip-flop TF is set up (Fetch=1). If Fetch=1, microinstructions can be fetched out
of the control memory. Let at time t (t =0, 1, 2, . . .) the code of state a
m
∈ A
1
, where
A
1
is a set of FSM S
1
states, be loaded into the register RG and address A(I
j
g
) of the
input j of OLC α
g
∈ C be loaded into the counter CT. Current microinstruction is
read out of CM and its microoperations y
n
∈ Y initialize some actions of the data-
path. If this input is not the output of current OLC α
g
∈ C (I
j
g
= O
g
), additional
variable y
0
= 1 is generated by MCU S
2
. If y
0
= 1, the content of register RG is
unchangeable and 1 is added to the content of counter CT. It corresponds to a transi-
tion between adjacent components of OLC α
g
∈C. If the output O
g
is reached, then
y
0
= 0. In this case circuit CC generates Boolean functions:
Φ =Φ(τ, X), (1.29)
Ψ =Ψ(τ, X), (1.30)
where τ = ¦τ
1
, . . . , τ
R
1
¦ is a set of state variables encoding states a
m
∈ A
1
. The
minimum number of these variables is determined as
R
1
= log
2
M
1
|, (1.31)
where M
1
=[A
1
[. If there is a transition fromoutput O
g
to some input under influence
of some values of logical conditions, functions (1.29) determine the address of this
input I
j
i
∈ I(Γ) which is to be loaded into the counter. Functions (1.30) calculate
the code of next state a
s
∈ A
1
to be loaded into RG. Content of both CT and RG is
changed by the pulse ”Clock”. Outputs of the CT, T = ¦T
1
, . . . , T
R
2
¦ determine next
microinstruction address. This set includes
R
2
= log
2
M
2
| (1.32)
variables, where M
2
= [B
2
[. If CT contains the address of microinstruction corre-
sponding to vertex b
q
∈ B
1
such that 'b
q
, b
E
` ∈ E, some additional variable y
E
= 1
is generated. If y
E
= 1, the flip-flop TF is cleared. Thus Fetch=0 and microinstruc-
tion fetching from the control memory is terminated.
As follows from (1.29), FSM S
1
of unit U
1
implements any multidirectional mi-
croprogram transition between output O
g
∈ O(Γ) and input I
j
i
∈ I(Γ) in one cycle
of CMCU operation. At the same time MCU S
2
implements addressing rule (1.28),
used to organize transitions between microinstructions corresponding to adjacent
components of OLC α
g
∈C. Therefore, control memory CM should only keep mi-
crooperations y
n
∈Y and additional variables y
0
, y
E
. In other words, an address part
is absent in the microinstruction format in case of CMCU U
1
. The main disadvan-
tage of CMCU U
1
is the loss of universality, because changes in the interpreted
References 25
microprogram lead to the redesign of circuit CC. Fortunately, as it will be shown
below, current achievements in semiconductor technology permit to eliminate this
drawback.
There are two main methods used to decrease the number of outputs of the block
CC of CMCU U
1
[11]:
1. The counter CT is used to represent both address of microinstruction and code of
OLC. It results in CMCU with common memory [11].
2. Microinstruction address can be represented as concatenation:
A(b
t
) = K(α
g
) ∗ K(b
t
), (1.33)
where A(b
t
) is an address of microinstruction corresponding to the vertex b
t
∈B
1
,
K(α
g
) is a code of OLC, including the vertex b
t
, K(b
t
) is a code of the vertex
b
t
∈ B
1
, as a component of OLC. It leads to CMCU with code sharing [11].
In our book, the methods of synthesis are discussed, which target on application-
specific integrated circuits (ASIC) and standard programmable logic devices (PLD).
These methods depend strongly on logic elements in use. Because of it, we should
analyze main features of ASIC and PLD. In our book we use the terms control unit,
control automata and FSM as synonyms.
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Chapter 2
Matrix Realization of Control Units
Abstract. The chapter discusses some problems, connected with logic synthesis
and optimization of FSM implemented with custom matrix integrated circuits. The
primitive matrix implementation of FSM circuit is analyzed first. It is reduced to
direct interpretation of FSM structure table and is characterized by considerable
redundancy. Next, the methods of logical condition replacement and encoding of
collections of microoperations are considered. These methods allow decrease for
circuit redundancy due increase of the number of FSM model levels. Next, it is
shown that the model of Moore FSM offers an additional possibility for its circuit
optimization due to existence of the classes of pseudoequivalent states. Each such
class corresponds to one state of the equivalent Mealy FSM. Optimization methods
are introduced based on different approaches for state encoding, as well as on trans-
formation of state codes into class codes. The last part of the chapter is devoted to
optimization of the block generating microoperations.
2.1 Primitive Matrix Realization of FSM
In case of ASIC, two-level circuits of the FSM type are often realized in a form of
custom matrices [2, 3]. The conception of distributed logic [10] is used in custom
matrices; this conception can be explained as the following one.
Consider implementation of the following system of Boolean functions:
y
1
= abc ∨a
¯
b¯ c ∨ ¯ ab¯ c = F
1
∨F
2
∨F
3
,
y
2
= a
¯
b¯ c ∨ ¯ abc = F
2
∨F
4
(2.1)
System (2.1) is characterized by the following parameters: the number of inputs
L = 3, the number of functions N = 2, the number of product terms (conjunctions
of arguments) H = 4. This system can be implemented as a two-level matrix circuit
(Fig. 2.1).
The logic circuit shown in Fig. 2.1 can be viewed as a matrix M
1
, which includes
H AND gates (AND-plane), and a matrix M
2
, which includes N OR gates (OR-
plane). Each element of the matrix M
1
has up to L inputs (the number of inputs
A. Barkalov and L. Titarenko: Logic Synthesis for FSM-Based Control Units, LNEE 53, pp. 29–52.
springerlink.com c Springer-Verlag Berlin Heidelberg 2009
30 2 Matrix Realization of Control Units
Fig. 2.1 Matrix implemen-
tation of system (2.1)
a c b
y
1
1
y
2
1
&
&
&
&
can be less than L, if an implemented Boolean system can be minimized). Each el-
ement of the matrix M
2
has up to H inputs. Because realization of AND and OR
gates in modern technologies generally uses more transistors (and hence more de-
lays and chip area), then both matrices M
1
and M
2
are implemented using NAND or
NOR gates [10]. For the sake of simplification, let symbol AND stand for M
1
and
OR for M
2
.
Practical hardware implementation of such a circuit is very difficult because of
problems with routing wires and building of multi input gates. For example, if a
circuit has L = 16 inputs, then it should require up to 64 000 gates in the AND-
plane. Moreover, each input could be connected with each gate of the matrix M
1
(up to 64000 connections), whereas each gate of OR-plane should have up to 64K
inputs. Such an implementation is very space and time consuming because of large
gates and long lines of connections among them. To eliminate these drawbacks, the
gates are distributed along the rows and columns of the matrices [10].
The distributed NOR gate implementing the mintermF
1
is shown by the circuit in
Fig. 2.2a, whereas Fig. 2.2b depicts the distributed implementation of the function
y
1
from system (2.1).
Fig. 2.2 Distributed im-
plementation of terms and
functions
a c b a c b
F
1
a) b)
y
1
F
1
F
2
F
3
F
4
CMOS transistors shown in Fig. 2.2 are used for interconnections of rows and
columns of AND- and OR-planes (matrices M
1
and M
2
). Let us point out that all
ASIC are implemented using CMOS transistors [11]. We should add that techno-
logical aspects of logic circuits implementation are out the scope of this book.
Let us consider the matrix implementation of Mealy FSM represented by systems
(1.8) – (1.9), which are derived from FSM structure table (Fig. 2.3).
A matrix M
1
has 2(L+R) inputs and implements H conjunctive terms F
h
∈ F =
¦F
1
, . . . , F
H
¦, which are members of functions Y and Φ. A matrix M
2
has H inputs
and implements N+R functions, depended on terms (1.6). The complexity of matrix
2.1 Primitive Matrix Realization of FSM 31
Fig. 2.3 Primitive matrix
realization of Mealy FSM
M
2
Start
Clock
Y
RG
X
T
)
M
1
& 1
F
realization can be estimated as a total area of matrices M
1
and M
2
[3]. Let S(M
1
),
S(M
2
) and S(M
T
) denote respectively the areas of matrices M
1
, M
2
and total area of
the circuit shown in Fig. 2.3. These areas can be determined in the following way:
S(M
1
) = 2(L+R)H; (2.2)
S(M
2
) = H(R+N); (2.3)
S(M
T
)
1
= (3R+2L+N)H. (2.4)
Assessments (2.2) – (2.4) are rather theoretical, because they do not include tech-
nological coefficients to give real sizes of transistors, wires and spaces among these
components of the circuit. Let us analyze the parameters of matrix implementation
for the Mealy FSM S
5
, represented by its structure table (Table 2.1).
In this case there is the set of terms F = ¦F
1
, . . . , F
8
¦, where F
1
=
¯
T
1
¯
T
2
, F
2
=
¯
T
1
T
2
x
1
, . . . , F
8
= T
1
T
2
¯ x
4
. For the Mealy FSM S
5
, functions y
n
∈ Y and φ
r
∈ Φ are
represented as the following equations:
y
1
= F
1
∨F
4
∨F
5
∨F
8
;
y
2
= F
1
∨F
3
∨F
5
;
y
3
= F
2
∨F
4
∨F
8
;
y
4
= F
3
∨F
6
;
y
5
= F
4
∨F
7
∨F
8
;
D
1
= F
2
∨F
3
∨F
4
∨F
6
∨F
8
;
D
2
= F
1
∨F
4
∨F
8
.
(2.5)
The primitive matrix realization of FSM S
5
is shown in Fig. 2.4, where CMOS
transistors are replaced by the sign ”•”.
The following values can be found for FSMS
5
: S(M
1
) =2(4+2)8 =96, S(M
2
) =
8(5+2) =56 and S(M
T
) =152. The circuit shown in Fig. 2.4 includes two levels of
matrices on the path frominputs X to outputs Y. Let t
M
and t
RG
stand for propagation
delay of a combinational circuit and a register respectively, then the cycle time of
such a circuit is determined as
t(T) = 2t
M
+t
RG
. (2.6)
In expression (2.6), the symbol T stands for the primitive matrix realization of FSM
circuit.
32 2 Matrix Realization of Control Units
Table 2.1 Structure table of Mealy FSM S
5
a
m
K(a
m
) a
s
K(a
s
) X
h
Y
h
Φ
h
h
a
1
00 a
2
01 1 y
1
y
2
D
2
1
a
2
01 a
3
10 x
1
y
3
D
1
2
a
3
10 ¯ x
1
x
2
y
2
D
1
D
1
3
a
4
11 ¯ x
1
¯ x
2
y
1
y
3
y
5
D
1
D
2
4
a
3
10 a
1
00 x
3
y
1
y
2
– 5
a
3
10 ¯ x
3
D
1
D
1
6
a
4
11 a
1
00 x
4
y
5
– 7
a
4
11 ¯ x
4
y
1
y
3
y
5
D
1
D
2
8
x
1
x
3 x
2
x
4
T
2
T
1
F
1
F
2
F
3
F
4
F
5
F
6
F
7
F
8
y
1
T
1
y
2
y
3
y
4
y
5
RG
D
1
D
2
R
C
T
2
Start
Clock
Fig. 2.4 Primitive matrix realization of FSM S
5
The primitive realization leads to logic circuits with maximal possible perfor-
mance (minimal cycle time) among all possible matrix implementations of Mealy
FSM. But such an approach leads to very redundant logic circuits. For example,
an FSM with average complexity is characterized by the following values of pa-
rameters [3]:H ≈ 2000, R ≈ 8, N ≈ 5, L ≈ 30. It follows from (2.4), that such an
FSM has S(M
T
) = 268000. This parameter determines the number of possible in-
terconnections in both matrices M
1
and M
2
. Obviously, only some part of possible
interconnections is used for a particular FSM. Let a term F
h
include L
h
letters from
the input alphabet X, and let N
h
microoperations and R
h
input memory functions be
produced for each FSM transition. It means that the number of interconnections for
matrix M
i
are determined as S(M
i
)
R
, where i = 1, 2, T:
S(M
1
)
R
= (L
h
+R)H;
S(M
2
)
R
= (N
h
+R
h
)H;
S(M
T
)
R
= (L
h
+N
h
+R
h
+R)H.
(2.7)
2.1 Primitive Matrix Realization of FSM 33
Let the symbol E
T
stand for efficiency of use of matrix areas for matrices M
1
and
M
2
in the case of FSM primitive realization. For Mealy FSM, it is determined as:
E
T
= S(M
T
)
R
/S(M
T
). (2.8)
Let an FSM of average complexity be characterized by the values L
h
= N
h
= 6
and R
h
= 4, then E
T
= 16/134 ≈ 0, 12. It means that near 88% of matrix area is
wasted in case of the primitive realization. If a designer does not strive for ultimate
performance, then the primitive Mealy FSM matrix realization is not used.
Outputs of Moore FSM depend only on its states a
m
∈ A, as follows from (1.10).
Thus, functions y
n
∈Y are independent on terms F
h
, represented as (1.6). The terms
A
m
∈ A
0
, corresponding to states a
m
∈ A, are used as the minterms of output func-
tions y
n
∈ Y. Therefore, the primitive matrix realization of Moore FSM can be
represented as it is shown in Fig. 2.5.
Fig. 2.5 Primitive matrix
realization of Moore FSM
M
4
Start
Clock
Y
RG
X
T
)
M
3
& 1
F
A
0
A conjunctive matrix M
3
has 2(L+R) inputs; it implements H terms F
h
∈F from
systemΦ, and M terms A
m
∈ A
0
fromsystemY. A disjunctive matrix M
4
has H+M
inputs and implements N +R functions. Let us find the areas of matrices M
3
, M
4
and the total area occupied by the FSM circuit. By analogy with (2.2) – (2.4), these
areas can be found as the following:
S(M
3
) = 2(L+R)(H+M); (2.9)
S(M
4
) = (H +M)(R+N); (2.10)
S(M
T
)
2
= (3R+2L+N)(H+M). (2.11)
Consider an example of the primitive matrix realization for the Moore FSM S
6
,
represented by its structure table (Table 2.2).
For the FSM S
6
, we have L = 4, R = 3, H = 15, M = 5, N = 6, therefore,
S(M
3
) = 280, S(M
4
) = 180, S(M
T
)
2
= 460. In the case of FSM S
6
, as for any
Moore FSM, there are two sets of terms, namely the set F = ¦F
1
, . . . , F
15
¦, where,
for example, F
3
=
¯
T
1
¯
T
2
¯
T
3
¯ x
1
¯ x
2
, and the set A
0
= ¦A
1
, . . . , A
8
¦, where, for example,
A
3
=
¯
T
1
T
2
¯
T
3
. The Boolean expressions for functions y
n
∈Y and φ
r
∈ Φ are derived
from Table 2.2.
34 2 Matrix Realization of Control Units
Table 2.2 Structure table of Moore FSM S
6
a
m
K(a
m
) a
s
K(a
s
) X
h
Φ
h
h
a
1
(–) 000 a
2
001 x
1
D
3
1
a
3
010 ¯ x
1
x
2
D
2
2
a
4
011 ¯ x
1
¯ x
2
D
2
D
3
3
a
2
(y
1
y
3
D
1
y
5
y
6
) 001 a
2
001 x
1
x
3
D
3
4
a
1
000 x
1
¯ x
3
– 5
a
5
100 ¯ x
1
D
1
6
a
3
(y
1
y
2
D
1
y
5
) 010 a
2
001 x
1
x
3
D
3
7
a
1
000 x
1
¯ x
3
– 8
a
5
100 ¯ x
1
D
1
9
a
4
(y
2
y
6
) 011 a
1
000 x
3
x
4
– 10
a
4
011 x
3
¯ x
4
D
2
D
3
11
a
4
011 ¯ x
3
D
2
D
3
12
a
5
(y
1
y
3
D
1
y
6
) 100 a
1
000 x
3
x
4
– 13
a
4
011 x
3
¯ x
4
D
2
D
3
14
a
4
011 ¯ x
3
D
2
D
3
15
In the case of FSM S
6
, the matrix M
4
implements the following systems of
Boolean functions y
1
= A
2
∨A
3
∨A
5
, . . . , y
6
= A
2
∨A
4
∨A
5
, D
1
= F
6
∨F
9
, . . . , D
3
=
F
1
∨F
3
∨F
4
∨F
7
∨F
11
∨F
12
∨F
14
∨F
15
. The primitive matrix realization of FSM S
6
is shown in Fig. 2.6.
Fig. 2.6 Primitive matrix
realization of Moore FSM
S
6
M
4
Start
Clock
Y
RG
X
T
)
M
3
& 1
F
A
0
As follows from analysis of Fig. 2.6, both matrices M
3
and M
4
are used very
ineffectively. There are 280 possible interconnections for the matrix M
3
, but only 85
of them are in use (less than 30%). As well, only 31 from 180 interconnections are
used in the matrix M
4
, it gives us near 17% of all possible interconnections. Thus,
in whole only 116 from 460 possible interconnections are used, it means that 75%
of mutual area of matrices M
3
and M
4
is free. So, the primitive matrix realization
results in very redundant logic circuits of Moore FSM.
The real number of needed interconnections can be found from analysis of
Fig. 2.6, namely:
2.2 Optimization of Mealy FSM Matrix Realization 35
S(M
3
)
R
= (L
h
+R)H +RM;
S(M
4
)
R
= N
m
M+R
h
H;
S(M
T
)
R
= (L
h
+R
h
+R)H +(R+N
m
)M,
(2.12)
where N
m
is an average number of microoperations executed in one state of Moore
FSM. Using both expression (2.8) and parameters of an FSM with average com-
plexity, it could be found that E
T
≈ 0.13 (if H = 2000, L = 30, N = 50, L
h
= 6,
R
h
= N
m
= 4, M = 200, R = 8). Thus, approximately 87% of a chip area occupied
by logic circuit of Moore FSM is not used.
Thus, primitive matrix realizations of Moore and Mealy FSMs are redundant
considering use of a chip area. In both cases, only 12–13% is used to implement the
really needed interconnections. The value of parameter E
T
can be increased due to
the multilevel realization of FSM logic circuits [3].
2.2 Optimization of Mealy FSM Matrix Realization
Let X(a
m
) be a set of logical conditions determining transitions from the state a
m

A, and let
G = max([X(a
1
)[, . . . , [X(a
M
)[). (2.13)
If condition
G < L (2.14)
takes place, then the method of logical condition replacement [3] can be used to
improve the quality of the FSM matrix realization. The main idea of the method is
reduced to construction of some additional variables p
g
∈ P used for replacement of
logical conditions x
l
∈ X, where [P[ = G.
From analysis of Table 2.1, we can find for the Mealy FSM S
5
the following sets:
X(a
1
) = / 0, X(a
2
) = ¦x
1
, x
2
¦, X(a
3
) = ¦x
3
¦, X(a
4
) = ¦x
4
¦; it means that G = 2.
Therefore, the set X can be replaced by a set P =¦p
1
, p
2
¦. Let us construct the table
of logical condition replacement, having G columns marked by variables p
g
∈ P,
and M rows marked by states a
m
∈ A. If a variable p
g
replaces in a state a
m
a logical
condition x
l
, then the symbol x
l
is written on the intersection of the row a
m
and
column p
g
of the table. To minimize the hardware amount of logic circuit used for
the logical condition replacement, the distribution of logical conditions is executed
in such a manner that each variable x
l
∈ X is always placed in the same column
of the table for all states of FSM. In the case of Mealy FSM S
5
, above mentioned
distribution of logical conditions is shown in Table 2.3. There are formal methods
for execution of required distribution in cases of very complex FSM which can be
found in [3].
The following system of Boolean functions should be constructed to replace the
logical conditions:
P = P(X, T). (2.15)
In our particular case, this system is the following one: p
1
= A
2
x
1
∨A
3
x
3
, p
2
=
A
2
x
2
∨A
4
x
4
. Generally, system (2.16) is represented as:
36 2 Matrix Realization of Control Units
Table 2.3 Logical condition replacement for Mealy FSM S
5
a
m
p
1
p
2
a
1
– –
a
2
x
1
x
2
a
3
x
3

a
4
– x
4
p
g
=
M

m=1
C
ml
A
m
x
l
(g = 1, . . . , G), (2.16)
where C
ml
is a Boolean variable, which is equal to 1, iff the variable p
g
replaces
the logical condition x
l
for the state a
m
. For the FSM S
5
, system (2.16) can be
implemented as a two-level matrix circuit shown in Fig. 2.7.
Fig. 2.7 Matrix realization
of logical condition replace-
ment for Mealy FSM S
5
x
1 x
3
x
2
x
4
F
1
F
2
F
3
F
4
F
5
y
1
y
2
T
2
T
1
M
5
M
6
In this circuit, a matrix M
5
implements terms of the system(2.16), making a set of
terms V = ¦v
1
, . . . , v
I
¦, whereas a matrix M
6
implements functions p
g
∈ P as some
disjunctions from terms v
i
∈ V. After these transformations, the matrix realization
of Mealy FSM includes four matrices (Fig. 2.8).
Fig. 2.8 Matrix realization
of Mealy FSM with logical
condition replacement
M
8
Start
Clock
Y
RG
P
T
)
M
7
& 1
F
M
6
X
M
5
& 1
V
2.2 Optimization of Mealy FSM Matrix Realization 37
In Fig. 2.8, a matrix M
7
implements terms from the system
F = F(P, T), (2.17)
used to form functions Y and Φ. To construct the system (2.17), the initial structure
table of Mealy FSM should be transformed in such a way that its column X
h
is
replaced by a column P
h
. The column P
h
contains conjunctions of variables p
g
∈ P,
replaced the corresponding conjunctions of logical conditions x
l
∈ X. As a rule [1],
Mealy FSM shown in Fig. 2.3 are named P FSM, and the term MP FSM is used
to denote Mealy FSM shown in Fig. 2.8. In case of MP FSM, a block BM, used to
replace the logical conditions, is represented by matrices M
5
and M
6
.
The transformed structure table of Mealy MP FSM S
5
(Table 2.4) is constructed
using both Table 2.1 and Table 2.3.
Table 2.4 Transformed structure table of MP Mealy FSM S
5
a
m
K(a
m
) a
s
K(a
s
) P
h
Y
h
Φ
h
h
a
1
00 a
2
01 1 y
1
y
2
D
2
1
a
2
01 a
3
10 p
1
y
3
D
1
2
a
3
10 ¯ p
1
p
2
y
2
D
1
D
1
3
a
4
11 ¯ p
1
¯ p
2
y
1
y
3
y
5
D
1
D
2
4
a
3
10 a
1
00 p
1
y
1
y
2
– 5
a
3
10 ¯ p
1
D
1
D
1
6
a
4
11 a
1
00 p
2
y
5
– 7
a
4
11 ¯ p
2
y
1
y
3
y
5
D
1
D
2
8
System(2.17) is derived fromTable. 2.4, for example, F
1
=
¯
T
1
¯
T
2
, F
2
=
¯
T
1
T
2
p
1
, . . . ,
F
8
= T
1
T
2
¯ p
2
. The system of terms
V =V(X, T) (2.18)
is implemented by the matrix M
5
. For our example, this system is derived from
Table 2.3 as the following one: V
1
=
¯
T
1
T
2
x
1
, V
2
=
¯
T
1
T
2
x
2
, V
3
= T
1
¯
T
2
x
3
, V
4
= T
1
T
2
x
4
.
The matrix M
6
implements equations from the system (2.16), namely, p
1
= v
1
∨v
3
,
p
2
= v
2
∨v
4
.
Complexity of MP Mealy FSM can be estimated adding the matrix areas:
S(M
5
) = (L+2R)I;
S(M
6
) = IG;
S(M
7
) = 2(G+R)H;
S(M
8
) = H(N+R).
(2.19)
Analysis of system (2.19) shows that decrease for areas of both matrices M
5
and M
6
can be reached due to decrease of the value I. Obviously, its minimal value is equal
38 2 Matrix Realization of Control Units
to the number of logical conditions, L. In the considered example, this minimumwas
reached automatically, because there is no another variant of the logical condition
replacement. In common case, this problemis solved using two approaches from[3].
Let X(p
g
) be a set of logical conditions written in the column p
g
of replacement
table. Let A(x
l
) be a set of states which can be extracted fromterms (2.17) for logical
condition x
l
∈ X. First, the logical conditions should be distributed among the table
columns in such a manner, that the following condition takes place:
X(p
i
) ∩X(p
j
) = / 0 (i = j; i, j ∈ ¦1, . . . , G). (2.20)
Let B
l
be a disjunction of terms A
m
, corresponding to states a
m
∈ A(x
l
). The second
task is reduced to such a state assignment for states a
m
∈ A, that each disjunction B
l
is represented by a single conjunctive term.
For example, let the following solution of the first problem be obtained for some
FSM S:
p
1
= (A
2
∨A
12
∨A
13
)x
1
∨(A
1
∨A
8
)x
4
∨(A
7
∨A
9
∨A
10
)x
5
;
p
2
= (A
4
∨A
5
∨A
6
∨A
7
)x
2
∨(A
3
∨A
4
∨A
5
)x
3
∨(A
6
∨A
11
∨A
12
)x
6

(A
5
∨A
8
∨A
13
)x
7
.
Obviously, in this case value of parameter I can be any, from 21 (it is determined
by the number of terms for logical condition replacement) to L =7. The well-known
algorithm ESPRESSO [9] can be used for such an encoding, in this case sets A(x
l
)
are used as restrictions of the algorithm [12, 13]. For the FSM S, there are M = 13
states, and it is enough R = 4 state variables T
r
∈ T for their encoding. One of the
possible encoding variants is shown in Fig. 2.9, for this variant we can find the
following values: I = L = 7.
Fig. 2.9 Codes for Mealy
FSM S
00
01
00 01 11 10
4 3
T T
2 1
T T
11
10
Taking into account the ”don’t care” input assignments, the next system can be
derived from the Karnaugh map (Fig. 2.9): p
1
= T
3
¯
T
4
x
1
∨T
1
¯
T
3
¯
T
4
x
4
∨T
1
¯
T
2
x
5
; p
2
=
¯
T
3
T
4
x
2

¯
T
1
T
4
x
3
∨T
1
T
2
x
6

¯
T
1
T
2
x
7
. Thus, the appropriate state assignment allows
three times decrease for the number of terms in system (2.18).
The logical condition replacement targets in reducing of the area occupied by
the matrix M
1
(Fig. 2.3), which is replaced by matrices M
5
, M
6
, M
7
(Fig. 2.8). The
method of encoding of collections of microoperations [1, 3] is used to decrease the
area of matrix M
2
(Fig. 2.3); it leads to PY Mealy FSM [7]. Let the structure table
2.2 Optimization of Mealy FSM Matrix Realization 39
of Mealy FSM include T
0
different collections of microoperations Y
t
⊆ Y. Encode
each collection Y
t
by a binary code K(Y
t
) having
R
3
= log
2
T
o
| (2.21)
bits. Let us use variables z
r
∈ Z, where [Z[ = R
3
, for such an encoding. Let B(y
n
)
be a set of collections of microoperations containing the microoperation y
n
∈Y, and
C(Y
t
) be a conjunction of variables z
r
∈ Z, corresponding to the code K(Y
t
). Now,
systemY =Y(T, X) is transformed into the following systems:
Z = Z(T, X); (2.22)
Y = Y(Z). (2.23)
The matrix realization used for implementation of system (2.23) includes matrices
M
9
and M
10
(Fig. 2.10).
Fig. 2.10 Matrix realization
of system of microopera-
tions for PY Mealy FSM
In the circuit (Fig. 2.10), a matrix M
9
implements terms w
j
from a set of terms
W, and a matrix M
10
implements functions y
n
∈Y as some disjunctions of the terms
W
j
( j = 1, . . . , J). The complexity of matrix realization shown in Fig. 2.10 is deter-
mined as result of summation for areas of matrices M
9
and M
10
:
S(M
9
) = 2R
3
J, (2.24)
S(M
10
) = JN. (2.25)
Values of variables R
3
and N are determined by initial GSA to be interpreted,
whereas parameter J can be changed from T
0
to N (the value N corresponds to
such a situation when each microoperation is represented as a single term). Let us
point out that the matrix M
10
is disappeared if J = N [2, 3].
For the FSM S
5
, we have T
0
= 6, because the structure fable (Table 2.4) includes
the following collections of microoperations: Y
1
=¦y
1
, y
2
¦, Y
2
=¦y
3
¦, Y
3
=¦y
2
, y
4
¦,
Y
4
= ¦y
1
, y
3
, y
5
¦, Y
5
= ¦y
6
¦, Y
6
= ¦y
5
¦. Therefore, R
3
= 3 and Z = ¦z
1
, z
2
, z
3
¦. En-
code the collections Y
t
in a trivial way, namely: K(Y
1
) = 000, . . . , K(Y
6
) = 101. It
can be derived from the column Y
h
(Table 2.4) that: y
1
= Y
1
∨Y
4
, y
2
= Y
1
∨Y
3
,
y
3
= Y
2
∨Y
4
, y
4
= Y
3
∨Y
5
, y
5
= Y
4
∨Y
6
. To get system (2.22), the initial structure
table of Mealy FSM should be transformed by the replacement of the column Y
h
by
the column Z
h
(Table 2.5).
40 2 Matrix Realization of Control Units
Table 2.5 Transformed structure table of PY Mealy FSM S
5
a
m
K(a
m
) a
s
K(a
s
) X
h
Z
h
Φ
h
h
a
1
00 a
2
01 1 – D
2
1
a
2
01 a
3
10 x
1
z
3
D
1
2
a
3
10 ¯ x
1
x
2
z
2
D
1
3
a
4
¯ x
4
11 ¯ x
1
¯ x
2
z
2
z
3
D
1
D
2
4
a
3
10 a
1
00 x
3
– – 5
a
3
10 ¯ x
3
z
1
D
1
6
a
4
11 a
1
00 x
4
z
1
z
3
– 7
a
4
11 z
2
z
3
D
1
D
2
8
An approach for filling of the column Z
h
is the following one: if the row h of
initial ST contains a collection Y
t
, then the column Z
h
should contain variables z
r

Z, corresponding to 1 in the code K(Y
t
). The matrix realization of PY Mealy FSM
is shown in Fig. 2.11.
Fig. 2.11 Matrix realization
of PY Mealy FSM
To minimize the areas of matrices M
9
and M
10
, the problem of optimal encoding
of collections of microoperations [2, 3] should be solved, when each expression
(2.23) is represented by SOP with the minimal possible number of terms. The well-
known algorithmESPRESSO [9] can be applied to solve this problem. For the FSM
S
5
, optimal codes of collections of microoperations are represented by the Karnaugh
map shown in Fig. 2.12.
Fig. 2.12 Optimal codes of
collections of microopera-
tions for PY Mealy FSM
S
5
2.2 Optimization of Mealy FSM Matrix Realization 41
Taking these codes into account, the system (2.23) is represented as the following
one for FSM S
5
: y
1
= ¯ z
1
¯ z
2
, y
2
= ¯ z
1
z
3
, y
3
= ¯ z
1
¯ z
3
, y
4
= z
2
z
3
, y
5
= ¯ z
2
¯ z
3
. This system is
implemented by the matrix circuit shown in Fig. 2.13.
Fig. 2.13 Matrix realization
of microoperations for PY
Mealy FSM S
5
In the circuit from Fig. 2.13, the wire z
1
is not used, because of it the matrix
area can be calculated as 55 = 25. Let us point out that the initial values obtained
from (2.24) and (2.25) are equal to S(M
9
) = 2 3 6 = 36 and S(M
10
) = 6 5 = 30.
It gives the total area equal to 66. Thus, the application of optimal encoding results
in the block BY having 2.6 times less hardware, than in case of a straightforward
implementation of microoperations.
The joint application of logical condition replacement and encoding of collec-
tions of microoperations leads to MPY Mealy FSM (Fig. 2.14).
Fig. 2.14 Matrix realization
of MPY Mealy FSM
Functions of all matrices from this matrix realization are clear frompreceding in-
formation as well as formulae for their areas. The synthesis method of MPY Mealy
FSM includes the following steps:
42 2 Matrix Realization of Control Units
1. Construction of marked GSA.
2. Construction of transition table of Mealy FSM.
3. Construction of table of logical condition replacement.
4. State assignment targeted in reduction of hardware for the block BP.
5. Optimal encoding of collections of microoperations.
6. Construction of transformed structure table of Mealy FSM.
7. Construction of systems for realization of matrices M
1
– M
6
.
8. Design of FSM logic circuit using functions obtained in step 7.
The transformed structure table of MPY Mealy FSM S
5
(Table 2.6) is constructed
taking into account the codes of collections of microoperations from Fig. 2.12.
Table 2.6 Transformed structure table of MPY Mealy FSM S
5
a
m
K(a
m
) a
s
K(a
s
) P
h
Z
h
Φ
h
h
a
1
00 a
2
01 1 z
3
D
2
1
a
2
01 a
3
10 p
1
z
2
D
1
2
a
3
10 ¯ p
1
p
2
z
2
z
3
D
1
3
a
4
11 ¯ p
1
¯ p
2
– D
1
D
2
4
a
3
10 a
1
00 p
1
z
3
– 5
a
3
10 ¯ p
1
z
1
z
2
z
3
D
1
6
a
4
11 a
1
00 p
2
z
1
– 7
a
4
11 ¯ p
2
– D
1
D
2
8
It is really easy to design the logic circuit (matrix realization) of MPY Mealy
FSMS
5
, because all its components were already designed. Obviously, the discussed
method can be adapted to design either Mealy MP– or PY FSM. The results of
many researches show that application of the logical condition replacement and
optimal encoding of collections of microoperations results in significant hardware
amount reducing, especially for complex FSM having more than 2000 transitions.
This approach has one serious drawback, namely decrease in FSM performance in
comparison with the primitive matrix realization of Mealy FSM. It is an effect of
the cycle time increase due to increase for the number of levels in the resulting FSM
realization (in comparison with the primitive matrix realization of Mealy FSM).
2.3 Optimization of Moore FSM Logic Circuit
Analysis of systems (1.8) and (1.10) shows that the combinational part of Moore
FSM matrix realization (it is shown in Fig. 2.5) can be divided by two blocks. By
analogy with Mealy FSM, let us denote as P Moore FSM the device whose structure
is shown in Fig. 2.5 and let the denotation PY Moore FSM stand for the device from
Fig. 2.15.
In Fig. 2.15, a matrix M
1
implements terms F
h
∈ F, corresponding to rows of
Moore FSM structure table, while a matrix M
2
implements system (1.8). Matrices
2.3 Optimization of Moore FSM Logic Circuit 43
Fig. 2.15 Matrix realization
of PY Moore FSM
M
3
andM
4
form a block BY. In this block, the matrix M
3
implements terms A
m

A
0
from system (1.10), while the matrix M
4
implements microoperations y
n
∈ Y.
Complexity of PY Moore FSM matrix realization is determined as a total area for
matrices M
1
– M
4
, namely:
S(M
1
) = 2(L+R)H; S(M
2
) = HR;
S(M
3
) = 2RMS(M
4
) = MN;
S(M
PY
) = (2L+3R)H+(2R+N)M.
(2.26)
For an FSM with average complexity (L = 30, H = 2000, R = 8, L = 30, L = 30),
we can find that S(M
PY
) = 181200. In case of P Moore FSM, interpretation of
such kind GSA gives control units with the total area S(M
T
)
2
= 294800. There-
fore, the replacement of P Moore FSM by PY Moore FSM results in consid-
erable area decreasing (in 1.63 times). It means that the efficiency of chip area
usage increases too. If device shown in Fig. 2.6 is divided by blocks BP and BY,
then it could be found that only 70 from 210 possible interconnections are used
in the matrix M
1
, 16 interconnections from 45 are used in the matrix M
2
,and 15
interconnections from 30 are used in both matrices M
3
and M
4
. It gives the value
E
PY
= (70+16+15+15)/(210+45+30+30) = 0.37, that is 12% more, than for
the primitive matrix realization for Moore FSM S
6
.
A chip area for matrices M
1
and M
2
can be decreased due to decrease of parame-
ter H. It can be obtained if states of Moore FSM are encoded using the method from
Section 1.2. Remind, this approach is named as an optimal state encoding. Let us
discus application of this approach for the Moore FSM S
6
.
As follows from Table 2.2, the Moore FSM S
6
includes I = 3 classes of the
pseudoequivalent states, namely: B
1
= ¦a
1
¦, B
2
= ¦a
2
, a
3
¦, B
3
= ¦a
4
, a
5
¦. Let us
encode the states a
m
∈ A by the optimal codes (Fig. 2.16).
Fig. 2.16 Optimal state
codes for Moore FSM S
6
0
1
00 01 11 10
3 2
T T
1
T
44 2 Matrix Realization of Control Units
As follows from Fig. 2.16, the class B
1
corresponds to the generalized interval
'∗, 0, 0` of three-dimensional Boolean space, the class B
2
to '∗, ∗, 1`, and the class
B
3
to '∗, 1, ∗`. Thus, the class B
1
is determined by the code ∗00, the class B
2
by
the code ∗ ∗ 1, and the class B
3
by the code ∗1∗. The transformed structure table of
Moore FSM S
6
(Table 2.7) includes H
0
= 9 rows, where the symbol H
0
stands for
the number of structure table rows for an equivalent Mealy FSM [1].
Table 2.7 Transformed structure table of Moore FSM S
6
B
i
K(B
i
) a
s
K(a
s
) X
h
Φ
h
h
B
1
∗00 a
2
001 x
1
D
3
1
a
3
101 ¯ x
1
x
2
D
1
D
3
2
a
4
010 ¯ x
1
¯ x
2
D
2
3
B
2
∗∗1 a
2
001 x
1
x
2
D
3
4
a
1
000 x
1
¯ x
3
– 5
a
5
110 ¯ x
1
D
1
D
2
6
B
3
∗1∗ a
1
000 x
3
x
4
– 7
a
4
010 x
3
¯ x
4
D
2
8
a
4
010 ¯ x
3
D
2
9
From Table 2.7, for example, the following Boolean function D
1
= F
2
∨F
6
=
¯
T
2
¯
T
3
¯ x
1
x
2
∨T
3
¯ x
1
can be derived. The matrix circuit of Moore FSM S
6
is characterized
by the following areas of matrices: S(M
1
) = (4 +8) 9 = 108, S(M
2
) = 9 3 = 27,
S(M
3
) =6 5 =30, and S(M
4
) =5 6 =30. Therefore, the application of the optimal
state encoding results in considerable decrease of the total area in comparison with
PY Moore FSM. In considered example, the total area decreases from 315 to 195,
that is near 1.6 times less.
The total area for matrices M
3
and M
4
(Fig. 2.15) can be decreased using the state
encoding targeted in decrease for the number of terms in system Y. Let us name this
approach as a refined state encoding. For the FSM S
6
, one of the possible variants
for the refined state encoding is shown in Fig. 2.17.
Fig. 2.17 Refined state
codes for Moore FSM S
6
0
1
00 01 11 10
3 2
T T
1
T
As follows from Table 2.2, the system of microoperations for Moore FSM S
6
is
the following one: y
1
=y
4
= A
2
∨A
3
∨A
5
, y
2
= A
3
∨A
4
, y
3
=A
2
∨A
5
, y
5
=A
2
∨A
3
,
y
6
= A
2
∨ A
4
∨ A
5
. Taking into account the codes from Fig. 2.17, the system
of microoperations can be represented as: y
1
= y
4
= T
3
, y
2
= T
1
¯
T
2
, y
3
=
¯
T
1
T
3
,
2.3 Optimization of Moore FSM Logic Circuit 45
y
5
=
¯
T
2
T
3
, y
6
=
¯
T
1
T
3
∨T
1
¯
T
3
= y
3
∨T
1
¯
T
3
. This system is implemented using two
matrices (Fig. 2.18).
Fig. 2.18 Matrix realization
for microoperations of FSM
S
6
The total area of this matrix circuit can be calculated as S(M
3
)+S(M
4
) =5 4+2
1 = 22. It means that the matrix M
3
has 5 inputs (the input T
2
is absent) and realizes
4 terms, but only two of them are used by the matrix M
4
, implemented only the
microoperation y
6
. In case of the arbitrary state encoding, we have S(M
3
)+S(M
4
) =
60, that is 2.73 more than the area of these matrices for the refined state encoding.
Obviously, the aim of the optimal state encoding differs from the aim of the
refined state encoding. Simultaneous decrease for areas of matrices M
1
- M
4
can be
achieved by application of a combined state encoding [5, 6]. This method can be
explained as the following. Let us construct the following systems of functions:
Y = Y(A); (2.27)
B = B(A). (2.28)
Let system (2.27) be determined by expression (1.10), while the elements of system
(2.28) are represented as
B
i
=
M

m=1
C
im
A
m
(i = 1, . . . , I), (2.29)
where C
im
is a Boolean variable equal to 1, iff a
m
∈B
i
. The combined state encoding
is executed in such a manner, that the total number of terms is minimal for systems
(2.27) and (2.28). This problem can be solved using, for example, the algorithm
ESPRESSO [9].
For the FSM S
6
, system (2.27) is more than once shown in our book, whereas
system (2.28) can be derived from the partition Π
A
as the following one: B
1
= A
1
,
B
2
=A
2
∨A
3
, B
3
=A
4
∨A
5
. One of the possible variants for combined state encoding
is shown in Fig. 2.19.
From Fig. 2.19, it can be found that: B
1
=
¯
T
2
¯
T
3
, B
2
=
¯
T
2
T
3
, B
3
= T
2
, y
1
= y
4
=
A
2
∨A
3
∨A
5
= T
3
, y
2
= A
3
∨A
4
= T
1
, y
3
= A
2
∨A
5
=
¯
T
1
T
3
, y
5
= A
2
∨A
3
=
¯
T
2
T
3
,
y
6
= A
2
∨A
4
∨A
6
= y
3
∨T
3
. Obviously, the areas of matrices M
1
and M
2
are the
same for both combined and optimal state encoding, thus S(M
1
) +S(M
2
) = 135.
The matrix M
3
has 4 inputs (T
1
,
¯
T
1
,
¯
T
2
, T
3
), and only 3 outputs (y
3
, y
5
, T
3
). Let us
point out that microoperations y
1
, y
2
, y
4
are produced without additional transistors.
46 2 Matrix Realization of Control Units
Fig. 2.19 Combined state
codes for Moore FSM S
6
0
1
00 01 11 10
3 2
T T
1
T
The matrix M
4
has 2 inputs (y
3
and T
3
), used to generate the microoperation y
6
. The
total area for these matrices can be found as S(M
3
) +S(M
4
) = 4 3+2 1 = 14, and
the total area for matrices M
1
- M
4
is equal to 149 in the case of FSM S
6
. Therefore,
total area of matrix realization is decreased from 315 (in the case of arbitrary state
encoding) to 149, that is more than 2 times.
Let us point out that the combined state encoding could produce results, which
are far from optimal for one or both parts of the matrix realization of PY Moore
FSM. In this case the total area can be decreased using a transformer of state codes
into codes of the classes of pseudoequivalent states [4, 8]. It results in P
C
YMoore
FSM shown in Fig. 2.20.
Fig. 2.20 Structure of
P
C
YMoore FSM
In P
C
YMoore FSM, a block BP implements functions
Φ =Φ(τ, X), (2.30)
where τ is a set of variables used to code classes B
i
∈ Π
A
. A code transformer BTC
generates codes of classes B
i
∈ Π
A
on the base of codes for states a
m
∈ B
i
, so the
block BTC implements the Boolean system
τ =τ(T). (2.31)
Consider an example of the P
C
YMoore FSM S
7
design, where the FSM is set up by
its transition table (Table 2.8).
The following values and sets can be derived from Table 2.8: M = 8, R = 3,
Π
A
= ¦B
1
, B
2
, B
3
, B
4
¦, where B
1
= ¦a
1
¦, B
2
= ¦a
2
, a
3
, a
4
¦, B
3
= ¦a
5
, a
6
, a
7
¦, B
4
=
¦a
8
¦, I = 4. Obviously, there is no such a state encoding variant which gives the
transformed structure table with H
0
= 9 rows. Remind, this value corresponds to
the number of rows in the structure table of equivalent Mealy FSM. The method of
synthesis includes the following steps.
1. Construction of systems Y and B. For the Moore FSM S
7
, we can construct
the functions: y
1
= A
2
∨ A
3
, y
2
= A
5
∨ A
6
, y
3
= A
2
∨ A
4
∨ A
7
, y
4
= A
3
∨ A
6
,
2.3 Optimization of Moore FSM Logic Circuit 47
Table 2.8 Transition table of Moore FSM S
7
a
m
a
s
X
h
h
a
1
(–) a
2
x
1
1
a
3
¯ x
1
2
a
2
(y
1
y
3
y
5
y
7
) a
4
x
2
3
a
5
¯ x
2
4
a
3
(y
1
D
1
y
7
) a
4
x
2
5
a
5
¯ x
2
6
a
4
(y
3
) a
4
x
2
7
a
5
¯ x
2
8
a
5
(y
2
) a
7
x
3
9
a
6
¯ x
3
x
4
10
a
8
¯ x
3
¯ x
4
11
a
6
(y
2
D
1
y
7
) a
7
x
3
12
a
6
¯ x
3
x
4
13
a
8
¯ x
3
¯ x
4
14
a
7
(y
3
y
5
y
7
) a
6
x
3
15
a
7
¯ x
3
x
4
16
a
8
¯ x
3
¯ x
4
17
a
8
(y
6
) a
3
x
5
18
a
1
¯ x
5
19
y
5
= A
2
∨A
7
, y
6
= A
7
∨A
8
, y
7
= A
2
∨A
3
∨A
6
∨A
7
, B
1
= A
1
, B
2
= A
2
∨A
3
∨A
4
,
B
3
= A
5
∨A
6
∨A
7
, B
4
= A
8
.
2. State assignment. For P
C
YMoore FSM, the state encoding targets in hardware
decrease for block of microoperations. Thus, the refined state encoding should
be done. The outcome of this step is shown in Fig. 2.21.
Fig. 2.21 Refined state
codes for Moore FSM S
7
0
1
00 01 11 10
3 2
T T
1
T
3. Construction of functions describing the block BY. The codes represented by
Fig. 2.21 permit to get the following system:
y
1
=
¯
T
1
T
3

1
;
y
2
= T
1
¯
T
2

2
;
y
3
=
¯
T
1
T
2
∨T
2
T
3

3
∨Δ
4
;
y
4
=
¯
T
2
T
3

5
;
y
5
= Δ
4
;
y
6
= T
1
T
2

6
;
y
7
= T
3

7
.
(2.32)
The terms Δ
k
from the system (2.32) form a set F(Y).
48 2 Matrix Realization of Control Units
4. Construction of functions describing the block BTC. Besides, the codes rep-
resented by Fig. 2.21 permit to get the following system:
B
1
=
¯
T
1
¯
T
2
¯
T
3

8
;
B
2
=
¯
T
1
T
3

¯
T
1
T
2

1
∨Δ
3
;
B
3
= T
1
¯
T
2
∨T
1
T
3

2
∨Δ
10
;
B
4
= T
1
T
2
¯
T
3

9
.
(2.33)
Classes B
i
∈ Π
A
can be coded using
R
0
= log
2
I| (2.34)
variables τ
r
∈ τ, where [τ[ = R
0
. Encode the classes B
i
∈ Π
A
in a trivial way,
namely: K(B
1
) = 00, . . . , K(B
4
) = 11. Now we can find that τ
1
= B
3
∨B
4
, τ
2
=
B
2
∨B
4
. It gives the following system to represent the system (2.31):
τ
1
= Δ
2
∨Δ
9
∨Δ
10
;
τ
2
= Δ
1
∨Δ
3
∨Δ
9
.
(2.35)
The terms from the system (2.35) make up a set F(TC).
5. Construction of transformed structure table. Let us construct the transformed
structure table of the Moore FSM S
7
. This table includes the columns B
i
, K(B
i
),
a
s
, K(a
s
), X
h
, Φ
h
, h. For the FSM S
7
, the codes K(B
i
) can be derived from
Fig. 2.21.
The following form of system (2.30) is derived from Table 2.9:
D
1
= F
4
∨F
5
∨F
6
∨F
7
;
D
2
= F
1
∨F
3
∨F
5
∨F
7
;
D
3
= F
1
∨F
2
∨F
5
∨F
6
∨F
8
.
(2.36)
The terms of system (2.30) are determined as the following conjunctions:
F
h
=
R
0

r=1
τ
l
hr
r
X
h
(h = 1, . . . , H
0
). (2.37)
In (2.37), a variable l
hr
∈ ¦0, 1¦ is equal to the value of bit r for code K(B
i
),
which is written in the row h of the table. From Table 2.9, for example, it can
be found that: F
=
¯ τ
1
¯ τ
2
x
1
, F
2

1
¯ τ
2
¯ x
3
x
4
and so on. Let us point out that this table
includes H
0
= 9 rows, it is the absolute minimum for the Moore FSM S
7
.
6. Matrix realization of FSM circuit. It is necessary 6 matrices to implement the
logic circuit of P
C
YMoore FSM (Fig. 2.22).
In the matrix realization of P
C
YMoore FSM, the block BP is implemented by
matrices M
1
and M
2
, whereas matrices M
3
and M
4
implement the block BY, in the
same time the block BTC is implemented by matrices M
5
and M
6
. Obviously, the
blocks BTC and BY have the same inputs and, therefore, they can be combined
in a single block consisting from two matrices.
For the Moore FSM S
7
, the total area of matrices from Fig. 2.15 is equal to 361. For
the P
C
YMoore FSM S
7
, we can found that: S(M
1
) =10 8 =80, S(M
2
) = 8 3 =24,
S(M
3
) = 6 6 = 36, S(M
4
) = 2 1 = 2, S(M
5
) = 6 5 = 30, S(M
6
) = 5 2 = 10, thus,
2.3 Optimization of Moore FSM Logic Circuit 49
Table 2.9 Transformed structure table for P
C
YMoore FSM S
7
B
i
K(B
i
) a
s
K(a
s
) X
h
Φ
h
h
B
1
00 a
2
011 x
1
D
2
D
3
1
a
3
001 ¯ x
1
D
3
2
B
2
01 a
4
010 x
2
D
2
3
a
5
100 ¯ x
2
D
1
4
B
3
10 a
7
111 x
3
D
1
D
2
D
3
5
a
6
101 ¯ x
3
x
4
D
1
D
3
6
a
8
110 ¯ x
3
¯ x
4
D
1
D
2
7
B
4
11 a
3
001 x
5
D
3
8
a
1
000 ¯ x
5
– 9
Fig. 2.22 Matrix realization
of P
C
YMoore FSM
the total area is equal to 182. These calculations show that the total area is decreased
near two times due to replacement of the model PY by the model P
C
Y(in the case of
FSM S
7
).
The total area occupied by matrices M
1
and M
2
can be decreased using the ap-
proach of logical condition replacement. For the FSM S
7
, we have G = 2, thus
the logical conditions x
1
, . . . , x
5
can be replaced by the additional variables p
1
, p
2
(Table 2.10).
Table 2.10 Replacement of logical conditions for P
C
YMoore FSM S
7
a
m
p
1
p
2
a
m
p
1
p
2
a
1
x
1
– a
5
x
3
x
4
a
2
– x
2
a
6
x
3
x
4
a
3
– x
2
a
7
x
3
x
4
a
4
– x
2
a
8
x
5

50 2 Matrix Realization of Control Units
Analysis of this table shows that content of columns p
1
and p
2
is the same for
each state a
m
∈ B
i
. Thus, application of the optimal state encoding permits decrease
for the number of terms in system P = P(X, T). The logical condition replacement
turns P
C
YMoore FSM into MP
C
YMoore FSM (Fig. 2.23).
Fig. 2.23 Matrix realization
of MP
C
YMoore FSM
Functions of all matrices shown in Fig. 2.23 are clear from previous reading. But
now the matrices M
1
and M
2
implement the system
P = P(τ, X). (2.38)
In contrast to system (2.15), forming for MPY Moore FSM, the functions of sys-
tem (2.38) depend on variables τ
r
∈ τ. To form the system (2.38), it should be con-
structed the table of logical condition replacement, where states a
m
∈B
i
are replaced
by corresponding classes B
i
∈ Π
A
(Table 2.11).
Table 2.11 Transformed table of logical condition replacement for Moore FSM S
7
B
i
p
1
p
2
B
i
p
1
p
2
B
1
x
1
- B
3
x
3
x
4
B
2
- x
2
B
4
x
3

Using codes K(B
i
) from table 2.9, the following system (2.38) can be built for
our example:p
1
= ¯ τ
1
¯ τ
2
x
1
∨τ
1
¯ τ
2
x
3
∨τ
1
τ
2
x
5
, p
2
= ¯ τ
1
τ
2
x
2
∨τ
1
¯ τ
2
x
4
. The number of
terms in system (2.38) can be decreased due to an optimal class encoding approach.
Let the following system be found for some Moore FSM S
8
:
p
1
= (B
1
∨B
2
)x
1
∨(B
3
∨B
4
∨B
5
)x
2
;
p
2
= (B
1
∨B
2
∨B
6
)x
3
∨(B
3
∨B
4
)x
4
,
(2.39)
2.3 Optimization of Moore FSM Logic Circuit 51
Fig. 2.24 Optimal codes for
classes of Moore FSM S
8
0
1
00 01 11 10
3 2
1
having 10 terms. Let us encode the classes B
i
∈ Π
A
by analogy with the optimal
state encoding of Moore FSM. This encoding outcome is shown in Fig. 2.24.
Using the codes from Fig. 2.24, we can transform the system (2.39) and get the
following system of equations:
p
1
= ¯ τ
1
¯ τ
2
x
1
∨τ
1
x
2
;
p
2
= ¯ τ
1
x
3
∨τ
1
¯ τ
2
x
4
.
(2.40)
For implementation of system (2.39), the matrix M
1
has 2R
0
+L = 10 inputs and
10 outputs, whereas the matrix M
2
has 10 inputs and 2 outputs. The system (2.40)
depends on variables τ
1
, ¯ τ
1
, ¯ τ
2
, it means that now the matrix M
1
has 7 inputs and 4
outputs. The matrix M
2
has 4 inputs and 3 outputs. It means that the arbitrary class
encoding for MP
C
YMoore FSM S
8
leads to the block BM with the area equal to
10 10+10 2 = 120, whereas the optimal encoding for classes B
i
∈ Π
A
leads to the
same block with the area 7 4+4 2 = 36. Thus, applying of the optimal encoding
permits to decrease the total area of the block BM by 3.3 times.
Thus, the total area of FSM matrix realization can be decreased due to increase
for the number of levels and coding of some objects, such as states, classes of
pseudoequivalent states, or collections of microoperations. Let the first approach
be named as a structural decomposition, whereas the encoding belongs to algorith-
mic methods. As a rule, multilevel models of FSM include three different types of
circuits (blocks):
1. The number of implemented terms is considerably less, than their total possible
number. For example, structure tables for FSM with average complexity include
H ≈2000 rows, while there are 2
L+R
≈2
38
possible terms. Let us name these cir-
cuits and corresponding systems of functions as irregular circuits and irregular
functions respectively.
2. The number of implemented terms is near 50% from their total possible number.
This class of circuits includes, for example, blocks BY and BTC. Let us name
these circuits and corresponding systems of functions as regular circuits and reg-
ular functions respectively.
3. Only direct (or only complement) values of logical conditions are used. This
class of circuits includes, for example, the block BM. Let us name these circuits
and corresponding systems of functions as multiplexer circuits and multiplexer
functions respectively.
The methods of optimization discussed in this Chapter can be used for optimization
of matrix FSM circuits, as well as FSM circuits implemented with standard VLSI
52 2 Matrix Realization of Control Units
chips. Obviously, peculiarities of specific types of VLSI circuits significantly affect
the methods of FSM optimization. Let us discuss these features more thoroughly.
References
1. Adamski, M., Barkalov, A.: Architectural and Sequential Synthesis of Digital Devices.
University of Zielona Góra Press, Zielona Góra (2006)
2. Baranov, S.: Logic and System Design of Digital Systems. TUT Press, Tallinn (2008)
3. Baranov, S.I.: Logic Synthesis of Control Automata. Kluwer Academic Publishers,
Dordrecht (1994)
4. Barkalov, A., Titarenko, L., Chmielewski, S.: Decrease of hardware amount in logic cir-
cuit of moore FSM. Przegl´ zd Telekomunikacyjny i Wiadomo´ sci Telokomunikacyjne (6),
750–752 (2008)
5. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of moore control unit with
refined state encoding. In: Proc. of the 15th Inter. Conf. MIXDES 2008, Pozna´ n, Poland,
pp. 417–420. Departament of Microeletronics and Computer Science, Technical Univer-
sity of Łódz (2008)
6. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of moore fsm on system-
on-chip using pal technology. In: Proc. of the International Conference TCSET 2008,
pp. 314–317. Ministry of Education and Science of Ukraine, Lviv Polytechnic National
University, Lviv, Publishing House of Lviv Polytechnic, Lviv-Slavsko (2008)
7. Barkalov, A., W˛ egrzyn, M.: Design of Control Units With Programmable Logic. Univer-
sity of Zielona Góra Press, Zielona Góra (2006)
8. Barkalov, A.A.: Principles of optimization of logic circuit of Moore FSM. Cybernetics
and System Analysis (1), 65–72 (1998) (in Russian)
9. De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York
(1994)
10. Navabi, Z.: Embedded Core Design with FPGAs. McGraw-Hill, New York (2007)
11. Shriver, B., Smith, B.: The anatomy of a High-performance Microprocessor: A Systems
Perspective. IEEE Computer Society Press, Los Alamitos (1998)
12. Villa, T., Kam, T., Brayton, R., Sangiovanni-Vincentelli, A.: A Synthesis of Finie State
Machines: Logic Optimization. Kluwer Academic Publishers, Boston (1998)
13. Villa, T., Saldachna, T., Brayton, R., Sangiovanni-Vincentelli, A.: Symbolic two-level
minimization. IEEE Transactions on Computer-Aided Design 16(7), 692–708 (1997)
Chapter 3
Evolution of Programmable Logic
Abstract. The chapter discussed contemporary field-programmable logic devices
and their evolution, starting from the simplest programmable logic devices such
as PROM, PLA, PAL and GAL, and finishing with very sophisticated chips such
as CPLD and FPGA. This analysis shows particular features of different logic el-
ements and permits to optimize the FSM logic circuits, in which some particular
elements are used. The analysis is accompanied by some examples for systems of
Boolean functions implementation using PROM, PLA and PAL chips. The principle
of functional decomposition oriented on FPGA chips is analysed in the last part of
the chapter.
3.1 Simple Field-Programmable Logic Devices
This book deals mostly with synthesis methods oriented on logic devices, which
are programmed by the end user. Such devices are named field-programmable logic
devices (FPLD) [61, 62]. The programmability of FPLD is intended at the hardware
level contrary to microprocessors, which run programs but posses a fixed hardware.
A FPLD is a general purpose chip whose hardware can be configured by the end
user to implement a particular project. Such emphasis of our book is explained by
domination of FPLD for design of modern digital devices. Some researches treat
FPLD as representatives of Application Specific Integrated Circuits [81], but mostly
FPLD are marked out as a separate class of digital devices [61].
The first representatives of FPLD are programmable read-only memory chips
(PROM), which were produced by Harris Semiconductor in 1970 [61] They include
a fixed array of AND gates (AND-array) followed by a programmable array of OR
gates (OR-array) as it shown in Fig. 3.1.
In a PROM, the AND-array implements an address decoder DC, having S in-
puts and q = 2
S
outputs, where each output corresponds to an unique address of a
memory cell. The content of OR-array is programmable and the sign ”X” in Fig. 3.1
shows a programmable connection.
This architecture perfectly fits for implementation of a system of Boolean func-
tions Y = ¦y
1
, . . . , y
N
¦ on Boolean variables X = ¦x
1
, . . . , x
L
¦, which is represented
A. Barkalov and L. Titarenko: Logic Synthesis for FSM-Based Control Units, LNEE 53, pp. 53–75.
springerlink.com c Springer-Verlag Berlin Heidelberg 2009
54 3 Evolution of Programmable Logic
Fig. 3.1 Architecture of
PROM
DC
AND
1 S
OR
1
2
S
.
.
.
..
.
1 t
by a truth table [61]. In this case the system to be implemented can be viewed as a
table with
H = 2
L
(3.1)
rows, where each rowincludes L input columns and N output columns. Let us denote
this system of Boolean functions (SBF) as Y(L, N) and discuss its implementation
with PROM(S, t), where PROM(S, t) means that a PROM chip has S inputs and t
outputs. Combinations of parameters S, t, L, N lead to the following implementa-
tions of SBF.
1. In case when S ≥ L, t ≥ N a system Y(L, N) can be implemented in a triv-
ial way using only one chip of PROM(S, t). The implementation is shown in
Fig. 3.2, where logical variables X are connected with address inputs of PROM,
and functions Y are appeared on the outputs of PROM.
Fig. 3.2 Trivial implemen-
tation of SBF with PROM
x
1
PROM
1
N
t
.
.
.
.
.
.
1
L
S
.
.
.
.
.
.
.
.
.
x
L
y
1
.
.
.
y
N
2. In case when S ≥ L, t < N it is necessary
n
1
=

N
t

(3.2)
chips of PROM(S, t) to implement a system Y(L, N). Address inputs of all chips
are connected with logical variables x
l
∈ X, and each chip generates up to t out-
put functions y
n
∈ Y (Fig. 3.3). Such an approach sometimes is named as ”an
expansion of outputs of PROM” [13, 27].
The value of parameter i for Fig. 3.3 can be calculated as i =t(n
1
−1) +1.
3. If S < L, t ≥ N, then the approach of expansion of inputs of PROM [13] is used
and
n
2
=

2
L
/2
S

= H/q| (3.3)
chips of PROM is necessary to implement a system Y(L, N) (Fig. 3.4).
3.1 Simple Field-Programmable Logic Devices 55
Fig. 3.3 Implementation
of SBF with expansion of
PROM outputs
PROM
1
X
y
1
.
.
.
..
.
PROM
n
1
y
t
y
1
.
.
.
y
t
Fig. 3.4 Implementation
of SBF with expansion of
PROM inputs
PROM
1
. . .
PROM
n
2
OR
DC
X
2
X
2
X
1
Y
1
Y
n
2
Y
1 n
2
In this circuit the L−S leftmost bits of input assignment 'x
1
, . . . , x
L
` form a set
of variables X
1
, which are connected with inputs of a decoder DC having n
2
out-
puts. Outputs of the decoder are connected with enable inputs of corresponding
PROMs, address inputs of all chips are connected with S rightmost bits of input
assignment and these variables form a set X
2
. The partial functions Y
i
are gener-
ated as outputs of i-th microchip and these functions correspond to subtables of
the truth table with rows fromq(i −1) till q
i
. As it can be seen from Fig. 3.4, OR-
gates are used to produce the final values of functions y
n
∈Y. Such an approach
is rather a theoretical one, because this level of the circuit could be implemented
using three-stable outputs of PROM chips [61].
4. If S < L, t < N, then
n
3
= n
1
n
2
(3.4)
chips of PROM is necessary for implementation of a SBF. In this case both meth-
ods of expansions of outputs and inputs are used together.
There are many ways for programming of FPLD [66], but the following ones are
used mostly:
1. Programming on the base of mask. Programming is executed using a mask in a
manufacturing process. This ”program” cannot be changed. The memory devices
used this type of programming are named read-only memories (ROM). Such an
approach is used in case of ASIC, which targets on a mass production.
2. One-time programming. In this case programming is executed using a high volt-
age, it leads to PROM. This information cannot be altered or erased.
56 3 Evolution of Programmable Logic
3. Reprogramming with erasing of information. In this case initial information can
be completely erased and PROM can be reprogrammed. Such an approach is pos-
sible due to usage of floating-gate transistors. In case of PROM such devices are
named as Erasable PROM (EPROM). Previous content is deleted by EPROM
exposing to ultra-violet light (for several minutes). To do it, a device should be
taking out from a printing board. Writing information into an EPROM is about a
1000 times slower than reading from a device. To get a real value for reprogram-
ming time, the time of erasing should be taking into account.
4. Reprogramming with electrical erasing. In this case PROM can be electrically
erased; because of it such chips are named EEPROM (Electrically Erasable
PROM). An EEPROM can be erased and reprogrammed without removing from
a printed board (as it was necessary for all previous cases). This feature is very
useful for reconfiguring a design on-fly. An EEPROM can be reprogrammed
from 10 to 20 000 times. Because both EPROMs and EEPROMs save their in-
ternal data while not powered, they belong to the class of non-volatile memories.
Writing information into an EEPROM is about a 500 times slower than reading
from a device.
5. Partial reprogramming. Such PLDs are divided into smaller fixed-size blocks
that can be reprogrammed independently (erased and programmed). These de-
vices are named Flash Memory. As a rule, they are used to keep either a system
configuration (if they are internal devices) or to keep some temporary data (if
they are external devices).
Thanks to regularity of their structure, chips of PROM find a wide application for
implementation of tabular functions. The main drawback of PROM is doubling of
their capacity if the number of inputs is incremented by 1. Besides, PROMs cannot
be used for implementation of SBF satisfying to condition
H
1
< H, (3.5)
where H
1
is the number of input assignments, such that at least one of the functions
y
n
∈Y is equal to 1.
Programmable logic arrays (PLA) were introduced in the mid 1970s by Signetics
[61] and they were oriented on implementation of SBF, when condition (3.5) takes
place. The peculiarity of PLA is programmability of both AND- and OR-arrays
(Fig. 3.5), that determines greater flexibility than in case of PROM.
Fig. 3.5 Architecture of
PLA
OR
1
.
.
.
..
.
1 t
..
.
.
.
.
AND
S
1
2
q
3.1 Simple Field-Programmable Logic Devices 57
Thanks to programmability of both arrays, PLAcan be applied to implement SBF
represented as minimal sum-of-products [1,63]. But programmability of AND-array
leads to increase of a chip area and decrease of the both resulting circuit speed and
value of parameter q in comparison with PROM-implementations [61].
Let PLA with S inputs, t outputs and q terms be denoted as PLA(S, t, q) and let
us discuss how they can be used for implementation of SBF Y(L, N, H
1
). There are
the following combinations of SBF and PLA parameters, which are listed below.
1. If S ≥ L, t ≥ N, q ≥ H
1
, then SBF Y is implemented in a trivial way using one
PLA chip. The structure of resulting circuit is similar to the structure shown in
Fig. 2.2, where PLA should be used instead of PROM.
2. If S ≥ L, t < N, q ≥ H
1
, then a logic circuit is implemented with n
1
PLA chips,
where value n
1
is determined by (3.2), and the structure of this circuit is similar
to the structure from Fig. 3.3.
3. If S ≥ L, t ≥ N, q < H
1
, then the approach of ”expansion of PLA terms” should
be used [13, 27], and a circuit can be implemented using
n
4
=

H
1
q

(3.6)
chips of PLA(S, t, q). Implementation of logic circuit in this case (Fig. 3.6) is
similar to one, shown in Fig. 3.4, but decoder DC is absent, because inputs of all
microchips are connected with the same logical conditions X.
Fig. 3.6 Implementation of
SBF with expansion of PLA
terms
PLA
1
. . .
PLA
n
4
OR
X
Y
1
Y
n
4
Y
4. If S ≥ L, t < N, q < H
1
, then both abovementioned methods of expansion should
be applied simultaneously. Minimization of hardware amount can be made with
application of sophisticated design methods [27], based on the search of some
partitions on the set of SBF terms.
More complex synthesis methods are used to implement a SBF Y, when the follow-
ing condition holds:
S < L. (3.7)
In this case a synthesis method depends on condition
58 3 Evolution of Programmable Logic
F
max
≤ L, (3.8)
where F
max
is the maximal number of literals [1] in the terms of SBF Y. If this
condition takes place, then an initial SBF can be implemented by a single-level
circuit, which is shown in Fig. 3.7.
Fig. 3.7 Single-level imple-
mentation of SBF with PLA
PLA
1
. . .
PLA
U
OR
X
Y(E
1
) Y(E
U
)
Y
X(E
1
) X(E
U
)
To design the logic circuit, it should be found a partition Π
F
of a set of terms F,
where [F[ = H
1
, with the minimum number of blocks U [27]. Let X(E
u
) be a set
of logical conditions, which form in the terms from a set E
u
∈ Π
F
= ¦E
1
, . . . , E
U
¦,
and Y(E
u
) be a set of functions depending on the terms E
u
∈ Π
F
. The partition Π
F
should satisfy to the following condition:
[X(E
u
)[ ≤ S,
[Y(E
u
)[ ≤ t, (u = 1, . . . ,U)
[E
u
[ ≤ q,
U → min.
(3.9)
Many different approaches are known, oriented on solution of the problem (3.9)
with minimizing of value U [27]. If condition (3.8) is violated, then an SBF Y is im-
plemented as a multilevel circuit [1], and it is connected with decrease of a resulted
digital system performance.
It is clear, that PLA allows only the implementation of combinational circuits. If a
sequential circuit should be implemented, then outputs of PLA should be connected
with an external register. This disadvantage was eliminated with including of flip-
flops at each output of PLA inside the chip. Such chips are named registered PLA
or programmable logic sequencers (PLS) [61]. Design methods targeted on PLS
use a decomposition of initial GSA by subgraphs in such a manner, that an FSM
corresponding to each subgraph can be implemented using only one chip of PLS
[27].
It is known, that practical digital devices are specified by SBF with limited num-
ber of terms, where condition (3.10) holds, where
[H(y
n
)[ ≤ 16. (3.10)
3.1 Simple Field-Programmable Logic Devices 59
Here H(y
n
) is a set of terms, which are used as products of SOP of a Boolean
function y
n
∈Y. An analysis of this condition shows that PLA have redundancy of
connections, because any term of PLA can be connected with any output of a chip.
Programmable array logic (PAL) chips, which were introduced by Monolithic
Memories in 1978 [61], were oriented on implementation of SBF, satisfying (3.10).
The peculiarity of PAL is existence of programmable AND-arrays and t fixed OR-
arrays (Fig. 3.8). It results in increase for the number of inputs and outputs of PAL
in comparison with a PLA chip of the same size.
Fig. 3.8 Architecture of
PAL
1
.
.
.
1
t
..
.
.
.
.
S
1
q
.
.
.
1
q
OR
1
OR
t
.
.
.
One of the new conceptions connected with PAL was the conception of a macro-
cell. The macrocell is a part of a chip connected with a single PAL output. For
example, the chip shown in Fig. 3.8 includes t macrocells. To increase the area of
such chips application, some additional elements were added to each output of PAL,
such as flip-flops, logic gates and multiplexers. The macrocell has a feedback path
from the output of the cell to the AND-array. The connections inside a macrocell
were programmable too and it increases flexibility of PAL. Feedbacks in PAL chip
permit to implement the functions with parenthesis [5, 6]. Macrocells have tristate
outputs and there is a possibility to use the chip pins as bidirectional input-outputs.
Besides, the tristable outputs permit usage of either direct or complement Boolean
functions. Macrocells include a programmable embedded flip-flop, enabling FSM
implementation without external memory registers.
Design methods for PAL are oriented on minimizing of the value [H(y
n
)[ up to the
some fixed value q, determining the number of AND-arrays connected with single
OR-array [51–55, 55, 56, 58, 82, 83]. Appearance of PAL stimulated development of
FSM design methods [1], which were rather different from designed methods with
PLA chips [7, 9, 11, 43, 44, 74–77].
The growth of the number of PAL inputs results in drastic performance decrease
and, hence, in limitations for their usage in practical designs [61]. Appearance of
EECMOS (Electrically Erasable CMOS) technology permitted very simple repro-
gramming. Combining structure of PAL and EECMOS technology results in generic
array logic (GAL) chips, which were introduced by Lattice in 1985 [61]. Let us point
out, that chips of GAL are still manufactured in a standalone packages by Lattice,
Atmel, TI, etc. A typical example of GAL device is the GAL16V8 chip, which has
16 inputs, 8 outputs and 20 pins. This device has 8 input pins and 8 bidirectional
input/output pins, it means that these pins can be used either as inputs or as outputs.
60 3 Evolution of Programmable Logic
Such chips as PLA, PLS, PAL, GAL belong to the class of Simple Programmable
Logic Devices (SPLD), they have not more than 40 inputs/outputs and they are
equivalent not more than 500 NAND-gates with two inputs [69], named as system
gates [61].
3.2 Programmable Logic Devices Based on Macrocells
To implement complex logic controllers, it is necessary to have PAL chips with
large number of terms per a macrocell, as well as with very large number of macro-
cells. Unfortunately, such chips are notable for very big propagation time and very
small coefficient of chip area usage [66]. Development of semiconductor technol-
ogy allowed quite different solution of this problem, when a single chip includes a
collection of simple PAL macrocells connected using programmable connections.
Such chips belong to the class of CPLD (Complex Programmable Logic Devices);
the simplified structure of a typical CPLD is shown in Fig. 3.9.
Fig. 3.9 Simplified archi-
tecture of CPLD
PAL
1
. . .
SM
1
PAL
I
S
I/
O
1
. . .
1 S
I/O
I
.
.
.
In this CPLD each macrocell PAL
i
(i = 1, . . . , I) is connected with S fixed inputs
of a chip and with programmable input/outputs IO
i
. The block outputs can be used
as input information for a switch matrix SM. The first CPLD were devices Mega-
PAL of MMI [61]. Now several companies such as Altera, Xilinx, Cypress, Atmel,
Lattice manufacture CPLDs [61]. As example of a typical CPLD we can mention
the Xilinx XC9500, where PLD resembling a 36V18 GAL device are used. Modern
CPLDs contain some additional features, like JTAG support and interface to other
logic standards. For different CPLD vendors, macrocells have different configura-
tions [61]; it is interesting that different manufactures use different terminology to
name the same things.
Let us discuss as a typical example a family MAX of Altera [2], where acronym
MAX stands for Multiple Array Matrix. Let us choose a family MAX5000, based on
EPROM technology. Macrocells of this family are combined in blocks, named LAB
(Logic Array Block), which can interplay using programmable connections from
PIA (Programmable Interconnect Array). For example, CPLD EPM5032 includes
only single LAB. This chip includes a term expander ES to share terms among
3.2 Programmable Logic Devices Based on Macrocells 61
different macrocells, an input-output block I/O, a matrix of macrocells MCA, and a
block of internal interconnections BII. The number of logic blocks LAB is increased
with growth of chip complexity. This tendency is shown in Fig. 3.10, borrowed
from [61].
Fig. 3.10 Architecture of
MAX5000 family members
PIA
BII
MCA
ES
1
LAB A
Block
I/O
S
...
Link outputs
1
t
...
Depending on a chip, the input number S varies from 8 to 20, the number of
bidirectional input-outputs t from 4 to 16, and the number of blocks LAB from 1to
12. Internal expanders are used to increase the number of terms implemented by a
macrocell. The macrocell has the following structure (Fig. 3.11).
Fig. 3.11 Architecture of
CPLD MAX5000 macrocell
S
I/O
PAL
PIA ES
MX
Global
Clock
TT
R
S
D
C
Array
Clock
Output
Enable
MX
I/O
In Fig. 3.11, the block PAL includes three programmable AND gates, connected
with OR gate, as well as the AND gate to control both flip-flop TT and macrocell
output (Output Enable). Additionally, each macrocell includes two multiplexers.
The first of them is used to connect the macrocell output either with the combination
output of PAL or registered output of TT flip-flop. The second multiplexer together
with additional AND gate is used to control a synchronization mode of the flip-flop.
The synchronization mode can be either common for all macrocells (Global Clock),
or local for the given block (Array Clock). There are four types of macrocell inputs:
fixed chip inputs (up to S inputs), outputs of matrix PIA, outputs of block ES, and
outputs of input-output block I/O.
62 3 Evolution of Programmable Logic
The expander block is used for increasing the numbers of terms implemented by
the block PAL. For MAX5000 family, this block includes from 32 to 64 multi input
AND gates, their inputs are connected with fixed chip inputs, and outputs of blocks
PIA and BII.
With development of semiconductor technology, all parameters of CPLD (such as
the number of pins, the number of macrocells and so on) are increased. For example,
the chips of MAX7000S family are based on EEPROM technology and they can
replace from 600 to 5000 system gates. The typical representative of this family is
CPLD EMP7128S, having 8 LAB blocks, where each LAB includes 16 macrocells.
Logic complexity of a chip is about 2500 system gates; the maximum frequency of
its operation is 147,1MHz. The chip can operate with 5 V or 3.3 V. The CPLD of
MAX9000 family are even more complex. For example, EMP9560 chip includes
560 macrocells, 772 flip-flops, 216 input-outputs. It is equal to 12000 system gates
and operates with maximum frequency up to 118MHz.
One of the serious restrictions of CPLD based on PAL macrocells is the lim-
ited number of implemented product terms per macrocell. It restrains application of
CPLD in such areas as mobile phones, computer games, and personal digital assis-
tances. To overcome this drawback, the Cool Runner XPLA3 family was introduced
by Xilinx. This family is based on macrocells of PLA type [89]. General overview
of XPLA3 chip is shown in Fig. 3.12.
Fig. 3.12 Architecture of
CPLD XPLA3 family
Logic Block
I/O
Logic
PLA
Logic
ZIA
I/O
Logic
PLA
Logic
Logic Block
Interconnect
Array
I/O I/O
16
16
Different CPLD XPLA3 chips include up to 24 logic blocks, and each block
contains 16 macrocells. Blocks interconnect through block ZIA (Zero-power Inter-
connect Array). Each logic block has 36 inputs from ZIA, whereas the number of
inputs connected with a block of input-output logic (I/O Logic) can be different for
different logic blocks from the same chip.
Each logic block can be viewed as a PLA block, having 36 inputs (outputs of
ZIA) and 48 terms, which can be distributed among 16 OR gates. The outputs of
OR gates are connected with multiplexers VFM (Variable Function Multiplexer).
Thus, each logic block is equivalent to a PLA, having S = 36 inputs, t = 16 outputs,
and q =48 product terms. The terms of a logic block are generated by a matrix PTA
(product term array); some outputs of PTA are used for special purposes. Architec-
ture of the logic block is shown in Fig. 3.13.
The logic block generates 8 control terms PT[0–7] to asynchronous controlling
flip-flops of macrocells MC
i
(i = 1, . . . , 16), as well as states of their outputs. Inputs
of macrocells MC
i
are connected either with the term PTi +15, or the disjunction of
any terms from the set PT[0–47] using blocks OR
i
and VFM
i
(i = 1, . . . , 16). Terms
PT[32–47] can be used for synchronization of macrocell flip-flops, whereas outputs
PT[8–15] can be used to organize feedback as outputs of NAND gates.
3.2 Programmable Logic Devices Based on Macrocells 63
Fig. 3.13 Architecture of
logic block for XPLA3
family
PTA
.
.
.
VFM1
Clock
OR
1
VFM16
OR
16
Feedback
NAND
ZIA
36
PT[0-7]
PT16
PT31
PT[0-47]
PT[32-47]
PT[32-47]
PT[8-15]
MC
16
MC
1
Control
Terms
Macrocells of CoolRunner XPLA3 family include a memory element configured
either as D FF or T FF, or as a latch. The flip-flop synchronization has 8 modes,
including the global clock (system synchronization). The macrocell output can be
either combinational, or registered, which is used as a feedback signal for the ZIA.
The bidirectional macrocell input-output is connected with the block ZIAtoo. If this
pin is used as an input, then macrocell output is set up in the third state using a spe-
cial control term. In this case the combinational output cannot be used as feedback
for the block ZIA. The input-output logic allows disconnection of pins, which are
not used as inputs of ZIA.
Important features of the representatives of CoolRunner XPLA3 family are listed
in Table 3.1; this table is based on [89].
Table 3.1 Characteristics of CoolRunner XPLA3 family
Chip XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL
I 32 64 128 256 384 512
G 800 1600 3200 6400 9600 12800
t
p
5 6 6 7,5 7,5 7,5
f
max
200 145 145 140 127 127
In this table, the symbol I stands for the number of macrocells (the number of
blocks is obtained automatically, dividing the number of macrocells by 16); G is the
number of system (equivalent) gates; t
p
is a propagation time, measured in nanosec-
onds; f
max
is a maximal frequency of operation, measured in megahertz. The PLA-
based macrocells are used in CPLD chips of Cool Runner II family by Xilinx [89].
Macrocells based on both PAL and PLA architectures are very efficient in im-
plementing irregular and multiplexer functions, but they are not suitable enough for
implementing regular functions. The truth table is the best way for presentation of
regular functions (and their systems); it means that the best way for implementing
64 3 Evolution of Programmable Logic
regular functions is usage of memory blocks (PROM, RAM). Taking it into ac-
count, designers from Cypress use both PAL- and RAM-based macrocells in their
Delta 39K family [39, 40].
Architecture of Delta 39K family includes a collection of clusters, where each
cluster includes 8 logic blocks and 2 blocks of a cluster memory, named Cluster
RAM Blocks (CRB). Each CRB has 8 Kbit of memory and can be configured as a
memory block, operating in both synchronous or asynchronous modes and having
the following characteristics: 8K1, 4K2, 2K4, 1K8. All 10 cluster blocks
interplay through a matrix of programmable interconnections PIM (Programmable
Interconnect Matrix). Each logic block includes 16 macrocells, based on PAL archi-
tecture. Besides, each cluster includes an additional block of channel memory with
4K bits; the number of its outputs can be different, namely, it can be equal to 1, 2, 4,
and 8. There is a system of global interconnections, allowing interplay of different
clusters.
This family is characterized by impressive values of parameters. For example,
the Delta 39K200 chip includes 200000 system gates, 3072 macrocells, and 480Kb
of RAM. Then, chips of Delta 39K(TM) family include 350000 gates; they have
a propagation time around 7 nanoseconds, and operate with maximum frequency
233MHz. Obviously, these chips have effective tools for implementing all kind of
Boolean functions, namely for implementation of regular, irregular, and multiplexer
functions.
3.3 Programmable Devices Based on LUT Elements
Technology of field-programmable gate arrays (FPGA) is developed simultaneously
with technology of CPLD [31, 59, 61, 62]. These chips can replace millions 2NAND
gates; each logic block of FPGA is equivalent from 10 to 20 system gates [66]. They
were introduced by designers of Xilinx in 1985 [89].
Consider some representatives of FPGA family produced by Xilinx, which are
based on look-up table (LUT) elements. As a rule, LUT elements are based on
RAM, having in average 4 inputs. Single LUT can implement an arbitrary Boolean
function depended on S ≤ 4 input variables and represented as a truth table. To-
gether with reconfigurable flip-flops, LUT elements make a Configurable Logic
Block (CLB). A simplified architecture of CLB is shown in Fig. 3.14.
In such a circuit, the LUT-element implements an arbitrary Boolean function
y =y(x
1
, . . . , x
S
), the signal ”Select” uses a multiplexer MX and chooses either com-
binational or register mode of PLB output, the pulse ”Clock” is used for timing of
the flip-flop TT.
Typical representatives of FPGA produced by Xilinx are the chips from the Spar-
tan family, for example, Spartan-3. These chips are powered by 1,2V and they use
the 90-nanometre technology. In 2003, the price for chip with 17000 CLBs, which
is equivalent to 1000000 system gates, was only 20$.
On the one hand, LUT can be used as a 16-bit shift register. Separate registers
can be combined together forming a long shift register chain. Contrariwise, each
LUT element represents a RAM or PROM memory; these memory blocks can be
3.3 Programmable Devices Based on LUT Elements 65
Fig. 3.14 Architecture of
programmable logic block
LUT
Clock
.
.
.
D TT
C
MX
Select
f
1
S
y
combined together to create a memory block with an arbitrary configuration. The
chips of Spartan-3 family include up to 104 memory blocks, with 18Kb for each of
them. Thus, these chips include up to 1,87Mb in their embedded blocks of RAM
(BRAM). The frequency of operation for these chips can be variable (from 25 MHz
till 325 MHz). They support 23 different input-output standards; this specific feature
enables application of Spartan-3 chips in different fields of digital automatics, as
well as for video- and multimedia systems. Some characteristics of Spartan-3 family
are shown in Table 3.2.
Table 3.2 Characteristics of Spartan-3family
Device XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000
I 1728 4320 8064 17280 29952 46080 62208 74880
G 50K 20K 40K 1000K 1500K 2000K 4000K 5000K
BRAM 72K 216K 288K 432K 576K 720K 1728K 1872K
DRAM 12K 30K 56K 120K 208K 320K 432K 520K
In this table, the symbol I determines the number of macrocells per chip; the
symbol G determines the number of system gates per chip; the symbol BRAM de-
termines the number of embedded memory blocks; the symbol DRAM determines
the number of bits when LUT elements are treated as a distributed memory.
There are many FPGA families produced by Xilinx [89]: XC9500, XC9500XL,
XC9500XV, XCR3000XL (having up to 512 macrocells); Spartan, Spartan XL,
and Spartan-3 (having up to 5000000 system gates); Virtex, Virtex E, Virtex II,
and Virtex II Pro (having up to 4000000 system gates and up to 4 PowerPC
microprocessors).
The second large-scale producer of FPGA chips is Altera [2]. Typical represen-
tatives of its FPGA are chips FLEX10K, where acronym FLEX stands for Flexible
Logic Element MatriX. These devices can be reconfigured in 320 milliseconds. For
example, the chip EPF10K70 of FLEX family is equal to 70000 system gates (tak-
ing into account embedded blocks BRAM). Logic of a project is implemented using
blocks LAB; there are 468 blocks LAB arranged as a matrix having 52 columns and
9 rows. Each LAB block consists from 8 logic elements LE, that is the chip 3744
LEs. Moreover, the chip includes an additional column with 9 embedded memory
blocks EAB (Embedded Array Block), and each EAB includes 2048 bits. Totally,
the chip possesses up to 18432 bits of RAM.
66 3 Evolution of Programmable Logic
Obviously, blocks EABcan be used for implementing systems of regular Boolean
functions, where each EAB of FLEX10K family replaces up to 600 system gates.
These blocks can be used for implementing parallel multipliers, sequential circuits
(such as FSM), as well as different devices for signal processing, and so on. Each
block can be used either separately, or together with others blocks. These blocks
EAB can be viewed as an additional large LUT element. It permits to increase the
system performance if calculation of complex combinatorial functions is in need.
Blocks EAB can be used as synchronous blocks RAM, which can be adjusted to the
global chip synchronization. As for Delta 39K, blocks EAB can be configured as
2048x1, 1024x2, 512x4, or 256x8 devices.
Eight logic elements LE and a local interconnect form single block LAB (ob-
viously, the LAB of Altera corresponds to the CLB of Xilinx). Each LAB, as it
is shown in Fig. 3.15, represents up to 100 system gates. Each LE includes one
LUT element, having 4 inputs, a programmable flip-flop, and some additional logic
used for organizing adders (carry logic or carry chain) and cascading of functions
(cascade chain).
LUT
Cascade In
MX
Carry
chain
Cascade
chain
Carry In
Logic of
RG
Logic of
RG
RG
MX
Carry Out Cascade Out
O
LE
V
2 V
1
3
2
d
1
d
2
d
3
d
4
Fig. 3.15 Simplified architecture of logic element from FLEX10K family
Three variables are connected with an output O
LE
of the logic element, namely:
an input d
4
of the LE, a combinational output of the LUT, or a registered output of
a programmable flip-flop RG. The output O
LE
is connected with the matrix of local
interconnect. The register RG can be programmed for D, T, JK, or RS operation. To
control the RG (such as clear, preset, or synchronization), an internal logic repre-
sented by inputs d
1
and d
3
is used, or it is controlled by elements of a set V
1
, which
includes the global clear signal. Elements of the set V
2
including global and local
synchronization signals are used for synchronizing. A special block of Clock logic
is used to generate synchronization pulses. For combinatorial functions, the RG is
bypassed.
Technological progress leads to decrease of transistor sizes and, therefore, to in-
crease of their number in a chip. For example, FPGA chips of Cyclone family pro-
duced by Altera include up to 20060 logic elements and 288K bits of RAM. In
these devices, each LAB includes 10 logic elements. Different representatives of
the Cyclone family have from 2910 to 20060 logic elements.
3.4 Design of Control Units with FPLD 67
The embedded memory is represented by so called M4K RAM blocks; each of
them includes 4K bits of memory. These blocks are reconfigurable and their outputs
can include up to 36 bits (each word has 32 bytes and 4 bytes are used for parity con-
trol). Memory blocks operate with frequency up to 250 MHz. Some characteristics
of Cyclone family are shown in Table 3.3.
Table 3.3 Characteristics of Cyclone family
Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20
Number of LE 2910 4000 5980 12060 20060
Number of blocks RAM (128x36 bits) 13 17 20 52 64
Total capacity of RAM, bits 59904 78336 92160 239616 294912
Number of pins for a user 104 301 185 249 301
Examples of different representatives of FPGA family can be continued, but due
to rapid technological advance such information is going out of date very quickly. In
our opinion, a reader now has some preliminary knowledge about both CPLD and
FPGA. To keep pace with technical progress, it is necessary to visit the web sites of
such FPLD producers as Xilinx, Altera, Lattice, Atmel, Cypress [2, 4, 40, 59, 89].
3.4 Design of Control Units with FPLD
The main problem in design of control units is irregularity of their logic circuits.
It does not permit usage of large library cells, in contrary to design of operational
automata (data-path) having regular structures [5]. Thus, it is important to use mod-
els of control units having regular parts. In this case some part of a logic circuit
can be implemented using such library cells as memory blocks, multiplexers, or de-
coders. The second problem is lack of universal methods for minimizing the hard-
ware amount in logic circuits of control units. Optimization methods should take
into account peculiarities of both logic elements in use and a control algorithm to
be implemented. Let us discuss some of these features.
1. CPLD based on PLA macrocells. Design methods are reduced to modularization
an initial logic circuit, that is to partitioning an initial logic circuit by subcircuits
implemented using one PLA macrocell. It is necessary to perform the mutual
minimization of the system of Boolean functions to be implemented. The sub-
systems with limited amount of product terms should be found. Design methods
target in PLA can be found in [1,27,31,45]. To decrease the hardware amount, the
structural decomposition was used; it allows usage of multiplexers and PROM
chips jointly with PLA modules [27]. Reduction of combinational part could be
reached due to usage of a counter instead of a register to interpret the linear parts
of a control algorithm [8, 9, 12, 30, 67, 68]. Appearance of the chips CoolRunner
family should renew an interest for development of these design methods.
68 3 Evolution of Programmable Logic
2. CPLD based on PAL macrocells. Design methods are reduced to the sepa-
rate minimization of functions representing a logic circuit of a control unit. It
is desirable that the number of terms in the SOP of a Boolean function does
not exceed the number of product terms per a macrocell. Otherwise, either the
macrocell cascading should be executed, or logic expanders should be used.
Both approaches lead to slowdown of a resulted design. The design methods
have been developing starting from the first announcement about appearance of
PAL chips [3, 31, 41, 42, 49, 51–56, 58, 82–84]. Some methods targeted on struc-
tural decomposition leading to combined use of PAL chips together with PROM
chips [14–21, 28]. Now such methods can be used in designs connected with
CPLD Delta 39K family by Cypress.
3. FPLD based on LUT elements. Methods of digital devices design with FPGA
significantly distinguish from their counterparts targeted on CPLD. The prin-
ciple of functional decomposition is the base for designing logic circuits with
FPGA [33, 70, 72, 73, 78]. Design methods are developed permanently taking into
account features of particular FPGAfamilies (a practical approach), as well as the
abstract conception of FPGA (a theoretical approach) [31, 37, 48, 60, 61, 72–74].
Besides, some methods are developed, which are targeted on the joint use of
LUT elements and embedded memory blocks [33, 37, 72, 86]. Finally, a group
of methods deal with LUT elements, EMBs and counters for interpretation of
linear parts of control algorithms [10, 13, 22–26, 29, 31, 32, 86–88]. Consider the
method of functional decomposition in more details. It is based on representation
of a Boolean function F = F(X) in the following form:
F(X) = H(X
0
, G
1
(X
1
), . . . , G
I
(X
I
)). (3.11)
In (3.11), unification of the sets X
i
(i = 0, . . . , I) gives an initial set X, as it is shown
in Fig. 3.16.
Fig. 3.16 Illustration of
the principle of functional
decomposition
G
1
. . .
H
X
1
F
X
G
I
X
I
X
0
In such a representation, there are coding functions G
i
and a base function F.
Let us point out that the decomposition is executed in such a manner that each from
the functions G
i
(i = 0, . . . , I), as well as the function H, could be implemented by a
single LUT element.
Also, the functional decomposition can be used under the design of control units
with CPLD [48]. It is shown in [56] that optimization methods targeted on FPGA
3.4 Design of Control Units with FPLD 69
can decrease hardware amount in logic circuits with CPLD. Results of the investiga-
tions described in [37, 86] show that decrease for amount of terms in SBF of control
units yields in reduction of the number of LUT elements in logic circuits of these
control units. Thus, it is reasonable to develop optimization methods targeted on
some particular logic elements and then to check their usability for different types
of FPLD chips.
The exceptional complexity of both CPLD and FPGA chips requires use of
computer-aided design (CAD) tools for designing control units [49, 61]. It as-
sumes development of formal methods for synthesis and verification of control
units [5, 31, 46, 47, 50, 64, 66, 85, 91]. For example, a design process for FPLD from
Xilinx includes the following steps:
1. Specification of a project. A design entry can be executed using the schematic
editor (a design is represented by some circuit), or the state editor (a design is
represented by a state diagram), or some program written on a hardware de-
scription language (HDL). Both VHDL and Verilog are the most popular HDLs
[35, 36, 38, 71]. An initial specification should be verified using procedures of
syntax and semantic analysis. After such a verification, the initial specification
can be corrected and this step should be repeated.
2. Logic synthesis. During this step, the package FPGA Express executes synthesis
and optimization of a control unit logic circuit. As an outcome, an FPGA Netlist
file is generated with a list of chains for a control unit to be implemented. The
file can be represented using either EDIF or XNF formats. The library cells from
system and user libraries are used during this step.
3. Simulation. The functional correctness of a control unit is checked during this
step. The step of simulation is executed without taking into account real propa-
gation times in a chip. If an outcome of simulation is negative, then the previous
steps should be repeated.
4. Implementation of logic circuit. Now the Netlist is translated into an internal
format of CAD system and such physical objects as CLBs and chip pins are
assigned for initial logic elements. This step is named a mapping. Next, such
steps as placement and routing are executed. Now there are physical elements
and connections among them. It allows finding out the real values of propagation
times for an FPGA chip selected for implementation of a project with the control
unit. The final outcome of this step is some data used to program a chip named
as BitStream.
5. Project verification. The final simulation is performed, where the actual values
of delays among the physical elements of the chip are used. If outcome of this
step is negative (actual performance of control unit is less than it is needed), then
previous steps of design process should be repeated to get some new results.
6. Chip programming. Obviously, that step is connected with writing a final bit
stream into the chip.
Implementation of control units with CPLDs is as difficult, as in case of FPGA-
based designs. Each producer of FPGA and CPLD chips has its own CAD to sup-
port the design process. The most known packages are, for example, MAX+PLUS,
70 3 Evolution of Programmable Logic
MAX+PLUSII, WebPack, QuartusII. Some of themare free of charge and can be ob-
tained through Internet. Besides, there are CAD tools of some producers specialized
only on synthesis and verification, such as Symplicity Amplify Physical Synthesis
Support, Leonardo Spectrum, Synopsis FPGA Compiler II and so on. Information
about these tools can be found on the sites of corresponding producers.
Besides, there is a lot of different academic CAD tools, where can be found
various methods for design and optimization of control units. As a rule, some in-
termediate software should be developed to connect academic and industrial tools.
The intermediate software allows entering either Boolean systems describing some
parts of control units or VHDL-models of these parts.
For example, the system SIS from Berkeley, USA [79, 80] has tools for single-
level and multi-level design of digital devices. The well-known system MIS [34]
is a base for development of the SIS. This system uses a special language KISS to
specify a control unit. The language is an entry to the program ESPRESSO, exe-
cuted minimization of logic functions by appropriate state assignment. A special
algorithm STAMINA is used for minimizing the number of states. If control units
are implemented with FPGA, then the state assignment is executed by an algorithm
JEDI. Its counterpart for PLA case is an algorithm NOVA.
A design system DEMAIN [60, 73] is developed in Poland (Politechnika War-
czawska) by Professor T. Łuba. This system deals with FPGA-based designs. The
system generates some preliminary data used by the MAX+PLUSII of Altera. The
base of the system is a set of algorithms target on decomposition of a system of
Boolean functions describing a combinational part of a control unit.
Some other academic systems are known, such as ASYL [76, 77], targeting in
designs with PLA and ROM, or ZUBR, targeting in designs with CPLD [82], as
well as ATOMIC, targeting in designs of compositional microprogramcontrol units
with FPGA [86]. To compare design outcomes for different CAD, a standard set of
tests (benchmarks) [90] is used. The set contains practical examples of sequential
circuits, represented in the KISSII format.
In our book, either graph-schemes of algorithms [5, 6] or structure tables are
used for specification of control units. The first form gives clearness of presentation,
whereas the second form is very close to the KISSII format. As a rule, all presented
methods are accompanied by examples. The examples are completed by some ta-
bles, which can be used to derive the systems of Boolean functions specified some
parts of logic circuit of a control unit. We do not discuss the particular problems
of logic circuit implementation using some specific chips. We escape from particu-
lar types of microchips; because of it we use only the symbol PLD (Programmable
Logic Device) in logic circuits for discussed examples. This symbol can stand either
for a group of LUT elements (if FPGAs are used to implement a circuit), or for a
group of PAL- or PLA-based macrocells (if a circuit is implemented using CPLDs).
Among all known models of control units, the highest performance belongs to a
single-level model (Fig. 3.17). Let us denote it as a P FSM. A block BP of P FSM
can include more than one layer of logic elements; it depends on both complexity
of a control algorithm to be interpreted and parameters of logic elements in use.
But the P FSM is the single-level model because it includes only single block of
References 71
Fig. 3.17 Structural dia-
gram of P FSM
BP
Start
Clock
RG
X
)
T
Y
combinational logic. Design methods of similar FSMs are discussed thoroughly in
[27, 65, 66]; they are not the subject of our book.
In our book, the symbol S is used to denote any model of FSM. The symbol S(Γ)
emphasises the fact that FSM is synthesized to interpret some GSA Γ. Obviously,
both an FSM and a GSA can have their serial numbers.
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Chapter 4
Optimization for Logic Circuit of Mealy FSM
Abstract. The chapter is devoted to the hardware amount reduction in the logic cir-
cuit of Mealy FSM. The methods of logical condition replacement are analyzed,
as well as different methods of encoding of collections of microoperations (maxi-
mal encoding and encoding of the classes of compatible microoperations). Next, the
methods of structure table rows encoding are discussed. Each of these methods pro-
duces double-level circuit of Mealy FSM. The main part of the chapter is devoted
to joint application of these methods, the main advantage of whose is possibility of
standard library cells use for implementation of logic circuits for some blocks of an
FSM model. For example, the logical condition replacement allows application of
multiplexers, whereas the encoding of collections of microoperations permits to use
embedded memory blocks. Standard decoders can be used in case of encoding of
the classes of compatible microoperations. It increases FSM logic circuit regularity
and leads to simplification of its design process.
4.1 Synthesis of FSM with Replacement of Logical Conditions
Usage of the logical condition replacement transforms P Mealy FSM shown in Fig.
3.17 into MP Mealy FSM (Fig. 4.1).
Fig. 4.1 Structure diagram
of MP Mealy FSM
BM
Start
Clock
RG
X
Y
T
BP
P
Ժ
In MP Mealy FSM, a block BM replaces the matrices M
5
and M
6
shown in
Fig. 2.8; it replaces logical conditions x
l
∈ X by additional variables p
g
∈ P. A block
BP replaces the matrices M
7
and M
8
(Fig. 2.8) and implements the following systems:
A. Barkalov and L. Titarenko: Logic Synthesis for FSM-Based Control Units, LNEE 53, pp. 77–102.
springerlink.com c Springer-Verlag Berlin Heidelberg 2009
78 4 Optimization for Logic Circuit of Mealy FSM
Y = Y(P, T), (4.1)
Φ = Φ(P, T). (4.2)
The functions of these systems depend on variables
P = P(X, T), (4.3)
generated by the block BM. Analysis of system (4.3), represented as (2.16), shows
that system (4.3) uses only direct values of logical conditions. Therefore, functions
p
g
∈ P belong to the class of multiplexer functions and multiplexers can be used for
their implementation. Let us point out that multiplexers are standard library cells
implemented from basic cells of PLD in use and their usage accelerates the design
process for the logic circuit of a control unit. Obviously, functions (4.1) and (4.2)
are irregular and they are implemented using basic PLD cells. The synthesis method
for MP Mealy FSM includes the following steps [2]:
1. Construction of table for replacement of logical conditions.
2. Construction of transformed structure table for MP Mealy FSM.
3. Implementation of systems (4.1) – (4.3) using PLD cells.
Let us discuss application of this method for optimization of the Mealy FSM S
9
represented by its structure table (Table 4.1).
As follows from Table 4.1, the Mealy FSM S
9
has M = 10 states, L = 9 logical
conditions, and N = 8 microoperations. The transitions for states a
m
∈ A depend on
logical conditions forming the following subsets of the initial set of logical condi-
tions X: subsets X(a
1
) = X(a
4
) = X(a
9
) = / 0 (unconditional jumps), and X(a
2
) =
{x
1
x
2
x
3
}, X(a
5
) = {x
2
x
5
}, X(a
7
) = {x
1
x
7
}, X(a
6
) = {x
3
x
5
x
6
}, X(a
8
) = {x
5
x
8
},
X(a
1
0) = {x
3
x
9
} (conditional jumps). Thus, it is enough G = 3 variables p
g
∈ P
to replace the logical conditions x
l
∈ X. The principle of logical condition replace-
ment was discussed in Chapter 2. For our example, the table for logical condition
replacement includes G = 3 columns and 10 rows (Table 4.2).
This table is the base for deriving of system (4.3), in the case of FSM S
9
this
system is the following one:
p
1
= (A
2
∨A
7
)x
1
∨(A
5
∨A
6
∨A
8
)x
5
∨A
10
x
9
;
p
2
= (A
2
∨A
5
)x
2
∨A
3
x
4
∨A
6
x
6
;
p
3
= (A
2
∨A
6
∨A
10
)x
3
∨A
3
x
5
∨A
7
x
7
∨A
8
x
8
.
(4.4)
As it was mentioned a bit earlier, the transformed structure table of MP Mealy
FSM is constructed from its initial structure table. In this case the column X
h
of
initial structure table is replaced by the column P
h
. For example, some subtable
of transformed structure table for the state a
5
of the Mealy FSM S
9
is shown in
Table 4.3.
The transformed structure table is used for deriving systems (4.1) – (4.2),
depended on terms
F
h
= A
m
P
h
. (4.5)
4.1 Synthesis of FSM with Replacement of Logical Conditions 79
Table 4.1 Structure table of Mealy FSM S
9
a
m
K(a
m
) a
s
K(a
s
) X
h
Y
h
Φ
h
h
a
1
0000 a
2
0001 1 y
1
y
2
D
4
1
a
2
0001 a
3
0010 x
1
¯ x
2
D
1
D
3
2
a
4
0011 x
1
x
2
y
2
y
3
D
3
D
4
3
a
3
0010 ¯ x
1
x
3
y
5
D
3
4
a
5
0100 ¯ x
1
¯ x
3
y
6
D
2
5
a
3
0010 a
2
0001 x
4
y
3
D
4
6
a
3
0011 ¯ x
4
x
3
y
1
y
9
D
2
D
4
7
a
5
0100 ¯ x
4
¯ x
3
y
5
D
2
8
a
4
0011 a
6
0101 1 D
1
D
2
D
4
9
a
5
0100 a
3
0010 x
2
y
1
y
3
D
3
10
a
5
0100 ¯ x
2
x
5
y
5
D
2
11
a
6
0101 ¯ x
2
¯ x
5
y
1
y
6
D
2
D
4
12
a
6
0101 a
2
0001 x
3
x
6
D
1
D
4
13
a
5
0100 x
3
¯ x
6
y
2
y
3
D
2
14
a
7
0110 ¯ x
3
x
5
y
7
D
2
D
3
15
a
8
0111 ¯ x
3
¯ x
5
y
1
y
8
D
2
D
3
D
4
16
a
7
0110 a
8
0111 x
1
x
7
y
2
D
1
D
2
D
3
D
4
17
a
9
1000 x
1
¯ x
7
y
3
D
1
18
a
10
1001 ¯ x
1
y
1
y
2
D
1
D
4
19
a
8
0111 a
3
0010 x
5
– D
3
20
a
9
1000 ¯ x
5
x
8
y
2
D
1
D
1
21
a
1
0000 ¯ x
5
¯ x
8
y
6
– 22
a
9
1000 a
10
1001 1 y
1
y
8
D
1
D
4
23
a
10
1001 a
1
0000 x
9
y
5
– 24
a
2
0001 ¯ x
9
x
3
y
1
y
3
D
4
25
a
6
0101 ¯ x
9
¯ x
3
y
6
D
2
D
4
26
Table 4.2 Table for logical condition replacement of FSM S
9
a
m
p
1
p
2
p
3
a
m
p
1
p
2
p
3
a
1
– – – a
6
x
5
x
6
x
3
a
2
x
1
x
2
x
3
a
7
x
1
– x
7
a
3
– x
4
x
5
a
8
x
5
– x
8
a
4
– – – a
9
– – –
a
5
x
5
x
2
a
10
x
9
– x
3
Table 4.3 Fragment of transformed structure table for MP Mealy FSM S
9
a
m
K(a
m
) a
s
K(a
s
) P
h
Y
h
Φ
h
h
a
5
0100 a
3
0010 p
2
y
1
y
3
D
3
10
a
5
0100 ¯ p
2
p
1
y
5
D
2
11
a
6
0101 ¯ p
2
¯ p
1
y
1
y
6
D
2
D
4
12
80 4 Optimization for Logic Circuit of Mealy FSM
In our example, there are the terms F
10
= A
5
p
2
, F
11
= A
5
¯ p
2
p
1
, and F
12
= A
5
¯ p
2
¯ p
1
,
where A
5
=
¯
T
1
T
2
¯
T
3
¯
T
4
. Using these terms, the following parts of SOP can be derived
from Table 4.3: y
1
= F
10
∨F
11
, y
3
= D
3
= F
10
, y
5
= F
11
, y
6
= D
4
= F
12
, D
2
= F
11

F
12
.
The following approach can be used to implement the block BM:
1. Each function p
g
∈ P corresponds to one multiplexer MX
g
, having R control
inputs and 2
R
data inputs.
2. For all multiplexers, control inputs are connected with state variables T
r
∈ T of
Mealy FSM.
3. If a variable p
g
∈ P replaces a logical condition x
l
∈ X for a state a
m
∈ A, then
this logical condition is connected with data input of multiplexer MX
g
, activated
by the state code K(a
m
).
To design the logic circuit of the block BM, it is enough to replace states a
m
∈ A
by their codes in the table of logical condition replacement. After such a changing,
the table of replacement corresponds to G tables, where each table determines one
of the multiplexers MX
g
. For the MP Mealy FSM S
9
, the block BM includes three
multiplexers (Fig. 4.2).
T
1
MX
1
P
1
1 2 3 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
T
2
x
1
x
5
T
3
x
5
T
4
T
x
1
x
5
x
9
T
1
MX
2
P
2
1 2 3 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
T
2
x
2
x
4
T
3
x
2
T
4
x
6
T
1
MX
3
P
3
1 2 3 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
T
2
x
3
x
4
T
3
x
3
T
4
x
7
x
8
x
9
Fig. 4.2 Circuit of block BM for MP Mealy FSM S
9
There is obvious correspondence between the block BM (Fig. 4.2) and Table 4.2.
As follows from Fig. 4.2, only 6 from available 16 data inputs of the multiplexer
MX
1
are used (they are connected with logical conditions), whereas only 4 for MX
2
,
and only 6 for MX
3
. Thus, only 37% from potentials of both multiplexers MX
1
and
4.1 Synthesis of FSM with Replacement of Logical Conditions 81
MX
3
are used, whereas only 25% is used for MX
2
. Thus, only 33% of available data
inputs are used, that is a very poor outcome. To increase the rate of data inputs’
usage, it is necessary to decrease the number of control inputs per a multiplexer.
The following methods can be used to solve this problem [2, 4]:
1. Multiplexer state encoding.
2. State code transformation into multiplexer state codes.
3. State code transformation into codes of logical conditions.
Let us discuss the main idea of the multiplexer state coding. Let us split the set
of states A on classes A
C
and A
U
in such a manner, that sets X(a
m
) = / 0 for states
a
m
∈ A
C
, whereas X(a
m
) = / 0 for states a
m
∈ A
U
. Besides, the initial state a
1
always
belongs to the set A
C
. Binary codes of states a
m
∈ A
C
should correspond to decimal
equivalents from zero (for the state a
1
) till M
C
−1, where M
C
= |A
C
|. Remained
codes are used for states a
m
∈ A
U
, and they can be coded in an arbitrary order.
For the FSM S
9
, the sets A
C
= {a
1
, a
2
, a
3
, a
5
, . . . , a
8
, a
10
} and A
U
= {a
4
, a
9
} can
be found, that gives M
C
= 8. The value of parameter M
C
gives the number of data
inputs for multiplexers of the block BM. Encode states a
m
∈ A as it shown in the
Karnaugh map (Fig. 4.3).
Fig. 4.3 Multiplexer state
codes for MP Mealy FSM
S
9 00
01
00 01 11 10
4 3
T T
11
10
2 1
T T
Now the states a
m
∈ A
C
correspond to the part of Karnaugh map with T
4
= 0,
therefore these states are determined by variables T
1
– T
3
. It means that all multi-
plexers of the block BM for FSM S
9
have three control and eight data inputs per a
multiplexer. As it follows from Fig. 4.4, now it is used 6 from 8 data inputs of both
MX
1
and MX
3
(75% of data inputs), whereas only 50% out of data inputs is used for
MX
2
(that is, 4 out of 8 inputs). In average, 67% out of all data inputs is used.
If a method of state encoding in use targets on the hardware decrease for the
block BP, it is reasonable to use the methods from second group, which belong to
the methods of object code transformation indextransformation of!object codes. In
this case, a special state code transformer CCS (Fig. 4.5) should be used. It gener-
ates some additional variables z
r
∈ Z used as control inputs of multiplexers of the
block BM.
Let the model of Mealy FSM with transformation of state codes into multiplexer
state codes be denoted as MPC Mealy FSM, whereas the symbol MPL denotes FSM
with transformation of state codes into codes of logical conditions. In both models
of FSM, states a
m
∈ A are encoded to solve some other problems distinguished from
82 4 Optimization for Logic Circuit of Mealy FSM
Fig. 4.4 Block of logical
condition replacement for
MP Mealy FSM S
9
with
multiplexer state coding
T
1
MX
1
P
1
1 2 3 0 1 2 3 4 5 6 7
T
2
x
1
x
5 x
1
T
3
x
9
x
5
T
1
MX
2
P
2
1 2 3 0 1 2 3 4 5 6 7
T
2
x
2
x
4
T
3
x
6
x
2
T
1
MX
3
P
3
1 2 3 0 1 2 3 4 5 6 7
T
2
x
3 x
3
x
7
T
3
x
3
x
8
T
x
5
Fig. 4.5 Structural diagram
of Mealy FSM with state
code transformer BM
Start
Clock
RG
X
Y
T
BP
P
Ժ
ccs
Z
the hardware optimization for the block BM. In both cases, the initial state a
1
∈ A is
included into the set A
C
if and only if (iff ) X(a
1
) = / 0.
The synthesis method for MPC Mealy FSM includes the following additional
steps:
1. Coding of states a
m
∈ A
C
by multiplexer binary codes C(a
m
) with R
C
bits, where
R
C
=log
2
M
C
. (4.6)
2. Construction of a table for code transformer CCS.
3. Implementation of the block CCS using given logic elements.
In the discussed case, there are M
C
=7, R
C
= 3. It means that states are encoded us-
ing the variables fromthe set Z ={z
1
, z
2
, z
3
}. Coding can be executed in an arbitrary
order, though its outcome can decrease the number of control inputs for some multi-
plexers. Let A(MX
g
) be a set of states, such that the multiplexer MX
g
(g = 1, . . . , G)
4.1 Synthesis of FSM with Replacement of Logical Conditions 83
transforms logical conditions determining transitions from these states. In the dis-
cussed case, the following set A(MX
2
) = {a
2
, a
3
, a
5
, a
6
} can be found, such that
it is enough two variables for its components encoding. Let us encode the states
of FSM S
9
using the following multiplexer codes:C(a
2
) = 000, C(a
3
) = 001,
C(a
5
) = 010, C(a
6
) = 011, C(a
7
) = 100, C(a
8
) = 101, and C(a
10
) = 110. Now the
states a
m
∈ A(MX
2
) are determined by the variables z
2
, z
3
; it yields in the following
circuit for the logical condition replacement (Fig. 4.6).
Fig. 4.6 Block BMfor MPC
Mealy FSM S
9
Z
1
MX
1
P
1
1 2 3 0 1 2 3 4 5 6 7
Z
2
x
1
x
5 x
1
Z
3
x
9
x
5
MX
2
P
2
1 2 0 1 2 3
Z
2
x
2
x
6
Z
3
x
2
x
4
Z
1
MX
3
P
3
1 2 3 0 1 2 3 4 5 6 7
Z
2
x
3 x
3
x
7
Z
3
x
3
x
8
Z
x
5
In this circuit, the multiplexer MX
2
uses 100% of its data inputs, while both MX
1
and MX
3
only 75%. Therefore, average use of data inputs is increased up to 83%.
Of course, it is connected with introduction of the code transformer CCS consuming
some area of a chip.
The table of code transformer CCS includes columns a
m
, K(a
m
), C(a
m
), Z
m
, m.
In this table, the code K(a
m
) is used as an input of the block CCS, whereas the code
C(a
m
) is its output. For the FSM S
9
, this table (Table 4.4) includes M = 10 rows.
The column Z
m
includes variables z
r
∈ Z, equal to 1 in the code C(a
m
).
Obviously, the best way for implementation of this table is use of a PROM chip
having R inputs and R
C
outputs. If a PROM-based implementation is not possible
due to absence of free resources of a chip in use, then this table is used to derive the
following SOP represented the system Z = Z(T):
z
r
=
M

m=1
C
mr
A
m
(r = 1, . . . , R
C
). (4.7)
84 4 Optimization for Logic Circuit of Mealy FSM
Table 4.4 Table of code transformer CCS for FSM S
9
a
m
K(a
m
) C(a
m
) Z
m
m
a
1
0000 000 – 1
a
2
0001 001 z
3
2
a
3
0010 010 z
2
3
a
4
0011 – – 4
a
5
0100 011 z
2
z
3
5
a
6
0101 100 z
1
6
a
7
0110 101 z
1
z
3
7
a
8
0111 110 z
1
z
2
8
a
9
1000 – – 9
a
10
1001 111 z
1
z
2
z
3
10
In (4.7) , the variable C
mr
∈ {01}, let us point out that C
mr
= 1, iff the bit r of the
code C(a
m
) is equal to 1 (r =1, . . . , R
C
). Obviously, system (4.7) can be minimized.
For example, the following form can be derived from the Karnaugh map shown in
Fig. 4.7: z
1
= T
2
T
4
∨T
2
T
3
∨T
1
T
4
. Depending on logic elements in use, either joint
or separate minimization should be carried out for the system. The first approach is
applied if PLA -based macrocells are used, whereas the second one targets on PAL-
implementation. Obviously, such an approach is applied for any system of Boolean
functions; let us just remember about it.
Fig. 4.7 Karnaugh map for
function z
1
0 0 0 0 00
01
00 01 11 10
4 3
T T
11
10
2 1
T T
The logic circuit of MPC Mealy FSM S
9
is shown in Fig. 4.8. In this circuit,
the symbol MX shows that multiplexer functions are implemented, the symbol PLD
corresponds to implementation of irregular functions, whereas the symbol PROM
informs about implementation of regular functions. Obviously, in reality only LUT
elements (or PAL macrocells) are used to implement logic circuits for multiplexer
and irregular functions. We do not discuss the problems of logic circuits’ physical
realization. Remind, all examples discussed here are ended by construction of some
tables describing blocks of FSM and corresponding systems of Boolean functions.
It is quite enough to start using of commercial CAD.
Let X(P
g
) be a set of logical conditions from the column P
g
(g =1, . . . , G), where
L
g
=|X(P
g
)|. Obviously, it is enough
4.1 Synthesis of FSM with Replacement of Logical Conditions 85
Fig. 4.8 Logic circuit of
MPC Mealy FSM S
9
RG
D
1
D
2
D
3
D
4
R
C
1
2
3
4
22
23
24
25
10
11
17
12
x
1 1
x
2 2
x
3 3
T
1
T
2
T
3
10
12
17
Start
Clock
T
1
18
11
T
2
T
3
PLD
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
11
12
19
20
21
y
1
y
2
y
3
y
4
y
5
y
7
y
8
y
6
22
22
23
D
1
D
2
D
3 24
D
4 25
23
24
25
13
T
4
18
PROM
D
1
D
2
D
3
D
4
1
2
3
10
11
12
13
14
15
16
z
1
z
2
z
3
MX
1
0
1
2
3
4
5
6
7
1
2
3
9
1
14
5
5
1
5
15
16
12 P
1
x
4 4
x
5 5
x
6 6
x
7 7
x
8 8
x
9 9
13
T
4
15
14
z
1
z
2
16
z
3
MX
2
0
1
2
3
4
5
6
7
1
2
3
2
14
2
6
4
15
16
20 P
2
MX
3
0
1
2
3
4
5
6
7
1
2
3
3
3
14
3
3
7
8
15
16
21 P
3
R
g
=

log
2
L
g

(4.8)
variables to encode the logical conditions x
l
∈ X(P
g
). To encode the logical condi-
tions x
l
∈ X it is enough
R
L
= R
1
+. . . +R
G
(4.9)
variables, forming a set Z.
The method of state code transformation into the codes of logical conditions is
based on replacement of state variables T
r
∈ T by variables z
r
∈ Z, where |Z| = R
L
.
Let us denote such an FSM as MPL Mealy FSM. Structural diagrams are the same
for both MPL and MPC models of Mealy FSM. Additionally, the design method
for MPC Mealy FSM includes the step of encoding of logical conditions by some
binary codes K
g
(x
l
).
For the FSM S
9
, we can get the following sets: X(p
1
) = {x
1
x
5
x
9
}, L
1
= 3,
X(p
2
) ={x
2
x
4
x
6
}, L
2
=3, X(p
3
) ={x
3
, x
5
, x
7
, x
8
}, L
3
=4. It gives R
1
=R
2
=R
3
=
2 and R
L
= 6, Z = {z
1
, . . . , z
6
}. Let us encode the logical conditions for FSM S
9
as
shown in Table 4.5.
86 4 Optimization for Logic Circuit of Mealy FSM
Table 4.5 Codes of logical conditions for MPL Mealy FSM S
9
X(p
1
) z
1
z
2
X(p
2
) z
3
z
4
X(p
3
) z
5
z
6
x
1
0 0 x
2
0 0 x
3
0 0
x
5
0 1 x
4
0 1 x
5
0 1
x
9
1 0 x
6
1 0 x
7
1 0
– 1 1 – 1 1 x
8
1 1
The logic circuit of block BM for the MPL Mealy FSM S
9
is implemented using
three multiplexers (Fig. 4.9).
Fig. 4.9 Logic circuit of
block BM for MPL Mealy
FSM S
9
MX
2
P
2
1 2 0 1 2 3
Z
3
x
2
Z
4
x
6
x
4
Z
MX
1
P
1
1 2 0 1 2 3
Z
1
x
1
Z
2
x
9
x
5
MX
3
P
3
1 2 0 1 2 3
Z
5
x
3
x
8
Z
6
x
7
x
5
To implement the logic circuit for the block CCS, it is necessary to construct
a corresponding table with columns a
m
, K(a
m
), K
1
(x
l
), . . . , K
G
(x
l
), Z
m
, m. For the
MPL Mealy FSM S
9
, this block is specified by Table 4.6. Logic circuit of MPL
Mealy FSM can be implemented in the same way as it is done for MPC Mealy
FSM.
4.2 Synthesis of FSM with Encoding of Collections of
Microoperations
Two different approaches are possible under encoding of collections of microoper-
ations, namely:
4.2 Synthesis of FSM with Encoding of Collections of Microoperations 87
Table 4.6 Specification of block CCS for MPL Mealy FSM S
9
a
m
K(a
m
) K
1
(x
l
) K
2
(x
l
) K
3
(x
l
) Z
m
m
a
1
0000 – – – – 1
a
2
0001 00 00 00 – 2
a
3
0010 – 01 01 z
4
z
6
3
a
4
0011 – – – – 4
a
5
0100 01 00 – z
2
5
a
6
0101 01 10 00 z
2
z
3
6
a
7
0110 00 – 10 z
5
7
a
8
0111 01 – 11 z
2
z
5
z
6
8
a
9
1000 – – – – 9
a
10
1001 10 – 00 z
1
10
1. Collections Y
t
⊆ Y are encoded by binary codes K(Y
t
) having minimal bit ca-
pacity R
3
, determined by (2.21). This approach turns P Mealy FSM shown in
Fig. 3.17 into PY Mealy FSM (Fig. 4.10).
Fig. 4.10 Structural dia-
gram of PY Mealy FSM
Start
Clock BY
X
Y
BP
Ժ Z
RG
T
For PY Mealy FSM, a block BP corresponds to matrices M
11
and M
12
(Fig. 2.11); it generates functions Φ and Z determined by expressions (1.3) and
(2.22) respectively. A block BY replaces matrices M
9
and M
10
(Fig. 2.11); it
generates data-path microoperations represented as (2.23). Due to regularity of
system (2.23), the logic circuit of block BY can be implemented using either
PROM or RAM chips.
2. The set of microoperations Y is divided by the classes of compatible microoper-
ations [2] and represented as
Y =Y
1
∪. . . ∪Y
K
. (4.10)
Remind, microoperations y
i
, y
j
∈Y are compatible, iff they do not written in the
same operator vertex of an interpreted GSA [3]. Let N
k
=|Y
k
|, then microopera-
tions y
n
∈Y
k
are encoded by binary codes K(y
n
) having R
k
bits, where
R
k
=log
2
(N
k
+1). (4.11)
88 4 Optimization for Logic Circuit of Mealy FSM
If interpreted GSA includes some collections of microoperations without repre-
sentatives of the class k, then 1 is added to N
k
in (4.11).
To encode the microoperations, it is enough
R
D
= R
1
+. . . +R
K
(4.12)
variables forming a set Z = Z
1
∪. . . ∪Z
K
. The variables z
r
∈ Z
k
are used for
encoding of microoperations y
n
∈Y
k
; let us point out that
Z
i
∩Z
j
= / 0 (i = j; i, j ∈ {1, . . . , K). (4.13)
After encoding, the system Y can be represented as the following collection of
systems:
Y
1
= Y(Z
1
);
.
.
.
Y
K
= Y(Z
K
).
(4.14)
Microoperations y
n
∈ Y
k
are generated by a decoder DC
k
, having R
k
inputs and N
k
outputs (k = 1, . . . , K).
The totality of these decoders forms a block BD. It turns P Mealy FSM into PD
Mealy FSM [2] with the structural diagram shown in Fig. 4.11.
Fig. 4.11 Structural dia-
gram of PD Mealy FSM
Start
Clock BD
X
Y
BP
Ժ Z
RG
T
Let us discuss an example of synthesis for the PY Mealy FSM S
10
, represented
by its structure table (Table 4.7).
1. Encoding of collections of microoperations. As it can be found from Table 4.7,
there are T
0
= 8 collections of microoperations, where Y
1
= {y
1
, y
2
}, Y
2
= {y
3
},
Y
3
= {y
4
, y
5
}, Y
4
= {y
6
, y
7
}, Y
5
= {y
2
, y
8
}, Y
6
= {y
7
}, Y
7
= {y
7
, y
9
}, Y
8
= / 0. As
follows from (2.21), it is enough R
3
= 3 variables z
r
∈ Z for encoding of these
collections. Let us encode collections Y
t
⊆Y in a trivial way: K(Y
1
) = 000, . . . ,
K(Y
8
) = 111.
2. Construction of transformed structure table. As it was mentioned in Chapter
2, the transformed structure table includes the column Z
h
, replacing the column
Y
h
from the initial structure table. The column Z
h
contains variables z
r
∈ Z, equal
to 1 for the code K(Y
t
) from the row h of the initial structure table (h =1, . . . , H).
4.2 Synthesis of FSM with Encoding of Collections of Microoperations 89
Table 4.7 Structure table for Mealy FSM S
10
a
m
K(a
m
) a
s
K(a
s
) X
h
Y
h
Φ
h
h
a
1
000 a
2
001 x
1
y
1
y
2
D
3
1
a
3
010 ¯ x
1
x
2
y
3
D
2
2
a
4
011 ¯ x
1
¯ x
2
D
1
y
5
D
2
D
3
3
a
2
001 a
3
010 x
3
y
1
y
2
D
2
4
a
5
100 ¯ x
3
y
3
D
1
5
a
3
010 a
6
101 1 y
6
y
7
D
1
D
3
6
a
4
011 a
2
001 x
2
y
2
y
8
D
3
7
a
1
000 ¯ x
2
x
3
y
1
y
2
– 8
a
6
101 ¯ x
2
¯ x
3
y
7
D
1
D
3
9
a
5
100 a
2
001 x
1
x
2
D
1
y
5
D
3
10
a
3
010 x
1
¯ x
2
y
7
y
9
D
2
11
a
1
000 ¯ x
1
x
3
– – 12
a
5
100 ¯ x
1
¯ x
3
y
3
D
1
13
a
6
101 a
1
000 1 y
1
y
2
– 14
For the FSM S
10
, the transformed structure table is represented by Table 4.8.
Obviously, the number of rows for both tables is the same, only contents of some
columns are different.
Table 4.8 Transformed structure table of PY Mealy FSM S
10
a
m
K(a
m
) a
s
K(a
s
) X
h
Z
h
Φ
h
h
a
1
000 a
2
001 x
1
– D
3
1
a
3
010 ¯ x
1
x
2
z
3
D
2
2
a
4
011 ¯ x
1
¯ x
2
z
2
D
2
D
3
3
a
2
001 a
3
010 x
3
– D
2
4
a
5
100 ¯ x
3
z
3
D
1
5
a
3
010 a
6
101 1 z
2
z
3
D
1
D
3
6
a
4
011 a
2
001 x
2
z
1
D
3
7
a
1
000 ¯ x
2
x
3
– – 8
a
6
101 ¯ x
2
¯ x
3
z
1
z
3
D
1
D
3
9
a
5
100 a
2
001 x
1
x
2
z
2
D
3
10
a
3
010 x
1
¯ x
2
z
1
z
2
D
2
11
a
1
000 ¯ x
1
x
3
z
1
z
2
z
3
– 12
a
5
100 ¯ x
1
¯ x
3
z
3
D
1
13
a
6
101 a
1
000 1 – – 14
Using the transformed structure table, system (2.22) is constructed, which can be
represented as the following one:
90 4 Optimization for Logic Circuit of Mealy FSM
z
r
=
H

h=1
C
rh
A
m
X
h
(r = 1, . . . , R
3
). (4.15)
In expression (4.15), a Boolean variable C
rh
= 1, iff the variable z
r
presents in
the row h of transformed ST(h = 1, . . . , H). For example, the following SOP
z
1
= F
7
∨F
8
∨F
11
∨F
12
can be derived from Table 4.8. System (1.3) is used for
designing the block BP too. For example, the following equation can be derived
from Table 4.8: D
1
= F
5
∨F
6
∨F
9
∨F
13
.
3. Specification of block BY. This block is represented by a table reflected the
dependence of microoperations from variables z
r
∈ Z. This table is constructed
in a trivial way (Table 4.9) and can be used for programming of PROM.
Table 4.9 Specification of block BY PY Mealy FSM S
10
z
1
z
2
z
3
y
1
y
2
y
3
y
4
y
5
y
6
y
7
y
8
y
9
0 0 0 1 1 0 0 0 0 0 0 0
0 0 1 0 0 1 0 0 0 0 0 0
0 1 0 0 0 1 1 1 0 0 0 0
0 1 1 0 0 0 0 0 1 1 0 0
1 0 0 0 1 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0 1
1 1 1 0 0 0 0 0 0 0 0 0
If the logic circuit of block BY is implemented using some macrocells, then
systemY(Z) is represented as the following SOP:
y
n
=
T
0

t=o
C
nt
Z
t
(r = 1, . . . , R
3
). (4.16)
In (4.16), the Boolean variableC
nt
= 1, iff y
n
∈ Y
t
. For example, the following
SOP y
2
= Z
1
∨Z
5
= ¯ z
2
¯ z
3
can be derived from Table 4.9 (after minimization).
Logic circuit of PY Mealy FSM is implemented on the base of these tables (and
derived systems of minimized Boolean functions). The logic circuit of PY Mealy
FSM S
10
is shown in Fig. 4.12.
Now, let us discuss the example of logic synthesis for PD Mealy FSM S
11
,
represented by its structure table (Table 4.10).
1. Partitioning of the set of microoperations by classes of compatible microop-
erations. This step is executed using rather complex combinatorial algorithms
[1], which are programmed for some CAD systems. For FSM S
11
, it is easy to
get three following classes: Y
1
= {y
1
, y
4
, y
7
}, Y
2
= {y
2
, y
6
, y
8
}, Y
3
= {y
3
, y
5
}.
So, there are the following values and sets: R
1
= 2, Z
1
= {z
1
, z
2
}, R
2
= 2,
Z
2
={z
3
, z
4
}, R
3
= 2, Z
3
={z
5
, z
6
}, R
D
= 6, and Z ={z
1
, . . . , z
6
}.
4.2 Synthesis of FSM with Encoding of Collections of Microoperations 91
Fig. 4.12 Logic circuit of
PY Mealy FSM S
10
PLD
1
1
2
3
4
5
6
1
2
3
4
5
6
2
3
4
5
9
10
11
12
D
1
D
2
D
3
z
1
PROM
1
2
3
1
2
3
4
5
6
7
8
9
12
13
14
y
1
y
2
y
3
y
4
RG D
1
D
2
D
3
R
C
1
2
3
9
10
11
8
4
5
y
5
7
6
x
1 1
x
2 2
x
3 3
4
6
7
Start
Clock
T
1
8
5
13
z
2
14
z
3 6
T
2
T
3
T
1
T
2
T
3
y
7
y
8
y
9
y
6
Table 4.10 Structure table of Mealy FSM S
11
a
m
K(a
m
) a
s
K(a
s
) X
h
Y
h
Φ
h
h
a
1
000 a
2
001 x
1
y
1
y
2
y
3
D
3
1
a
3
010 ¯ x
1
y
1
y
6
D
2
2
a
2
001 a
3
010 x
2
y
3
D
1
y
6
D
2
3
a
4
011 ¯ x
2
¯ x
3
D
1
y
8
D
2
D
3
4
a
2
001 ¯ x
2
¯ x
3
y
5
y
7
D
3
5
a
3
010 a
5
100 1 y
1
y
5
D
1
6
a
4
011 a
3
010 x
2
y
8
D
2
7
a
5
100 ¯ x
2
x
4
y
3
D
1
D
1
8
a
6
101 ¯ x
2
¯ x
4
y
7
y
8
D
1
D
2
9
a
5
100 a
2
001 x
5
y
1
y
6
D
3
10
a
1
000 ¯ x
5
– – 11
a
6
101 a
1
000 1 y
5
y
7
– 12
2. Encoding of compatible microoperations. If standard decoders are used for
implementing the logic circuit of block BD, then compatible microoperations
can be encoded in a trivial way. It is true, because codes of microoperations
have no influence on the hardware amount in the logic circuit. For the FSM S
11
,
the outcome of trivial encoding is shown in Table 4.11. Obviously, the logic
circuit for block BD has the same hardware amount for any codes of compatible
microoperations.
In this table, the column K(Y
1
) contains codes K(y
n
) of microoperations y
n

Y
1
and so on. The symbol ”/ 0” corresponds to lack of microoperations of the
given class in some collection of microoperations Y
t
(t = 1, . . . , T
0
).
3. Transformation of initial structure table. This step is executed in the same
manner, as it was done for PY Mealy FSM. For the discussed example,
Table 4.12 can be formed.
92 4 Optimization for Logic Circuit of Mealy FSM
Table 4.11 Codes of compatible microoperations for PD Mealy FSM S
11
Y
1
K(Y
1
) Y
2
K(Y
2
) Y
3
K(Y
3
)
z
1
z
2
z
3
z
4
z
5
z
6
/ 0 0 0 / 0 0 0 / 0 0 0
y
1
0 1 y
2
0 1 y
3
0 1
y
4
1 0 y
6
1 0 y
5
1 0
y
7
1 1 y
8
1 1
Table 4.12 Transformed structure table of PD Mealy FSM S
11
a
m
K(a
m
) a
s
K(a
s
) X
h
Z
h
Φ
h
h
a
1
000 a
2
001 x
1
z
2
z
4
z
6
D
3
1
a
3
010 ¯ x
1
z
2
z
3
D
2
2
a
2
001 a
3
010 x
2
z
1
z
3
z
6
D
2
3
a
4
011 ¯ x
2
¯ x
3
z
1
z
3
z
4
D
2
D
3
4
a
2
001 ¯ x
2
¯ x
3
z
1
z
2
z
5
D
3
5
a
3
010 a
5
100 1 z
2
z
5
D
1
6
a
4
011 a
3
010 x
2
z
3
z
4
D
2
7
a
5
100 ¯ x
2
x
4
z
1
z
6
D
1
8
a
6
101 ¯ x
2
¯ x
4
z
1
z
2
z
3
z
4
D
1
D
2
9
a
5
100 a
2
001 x
5
z
2
z
3
D
3
10
a
1
000 ¯ x
5
– – 11
a
6
101 a
1
000 1 z
1
z
2
z
5
– 12
System (4.15) is derived from this table, having R
D
functions. For example, the
following SOP z
1
= F
3
∨F
4
∨F
5
∨F
8
∨F
9
can be derived from Table 4.12.
The logic circuit of PD Mealy FSM (in our case this circuit is shown in Fig.
4.13 is implemented using either obtained tables or systems of Boolean functions,
which can be derived from them.
As follows from Fig. 4.13, the decoder DC
1
is used for implementation of
microoperations y
n
∈Y
1
, the decoder DC
2
for y
n
∈Y
2
, whereas the decoder DC
3
is absent, because each from the microoperations of the third class depends only
on one variable (y
3
=z
6
, y
5
=z
5
). Because decoders are the standard library cells,
their application yields in simplification and acceleration of a design process.
4.3 Synthesis of FSM with Encoding of Rows of Structure
Table
The main outcome of encoding of collections of microoperations is decrease for
the number of the block BP outputs from R+N (P Mealy FSM) till R+R
3
(PY
Mealy FSM) or R+R
D
(PD Mealy FSM). It leads to decrease for the number
4.3 Synthesis of FSM with Encoding of Rows of Structure Table 93
Fig. 4.13 Logic circuit of
PD Mealy FSM S
11
PLD 1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
2
3
4
5
11
12
13
14
D
1
D
2
D
3
z
1
RG D
1
D
2
D
3
R
C
1
2
3
11
12
13
9
6
7
10
8
x
1 1
x
2 2
x
3 3
4
x
4
5
15
z
2
16
z
3
6
x
5
T
1
T
2
T
3
7
8
17
z
4
18
z
5
19
z
6
6
8
9
Start
Clock
T
1
10
7
T
2
T
3
DC
1
1
2
1
2
3
4
14
15
y
1
y
4
y
7
DC
2
1
2
1
2
3
4
16
17
y
6
y
2
y
8
y
5
y
3
18
19
of macrocells, used to implement irregular functions. The method of encoding of
structure table rows [3] targets on solution of this problem too.
Let us encode the row h of ST by a binary code K(F
h
) having R
F
bits, where
R
F
=log
2
H. (4.17)
Let us use variables z
r
∈ Z, where |Z| = R
F
, for such an encoding. It results in
the model of BF Mealy FSM, shown in Fig. 4.14.
Fig. 4.14 Structure diagram
of PF Mealy FSM
BP
Start
Clock
RG
X
Y
T
BF
P
Ժ
In PF Mealy FSM, the block BP implements system (4.15), which includes R
F
functions. A block PF implements systems Y and Φ, represented as:
y
n
=
H

h=1
C
nh
Z
h
(h = 1, . . . , N), (4.18)
φ
r
=
H

h=1
C
rh
Z
h
(r = 1, . . . , R). (4.19)
In systems (4.18)–(4.19) the symbol Z
h
stands for a conjunction of variables
z
r
∈ Z, corresponded to the code K(F
h
):
Z
h
=
R
F

r=1
z
l
rh
r
. (4.20)
94 4 Optimization for Logic Circuit of Mealy FSM
In (4.20), the symbol l
rh
∈ {0, 1} stands for value of the bit r of the code K(F
h
)
corresponded to the row h of ST, and z
0
r
= ¯ z
r
, z
1
r
= z
r
(r = 1, . . . , R
F
).
Let us discuss an example of PF Mealy FSM synthesis for the FSM S
10
, represented
by Table 4.7.
1. Encoding of structure table rows. As follows from Table 4.7, the ST includes
H =14 rows and, therefore, R
F
=4, and Z ={z
1
, . . . , z
4
}. Let us encode the rows
in a trivial way: K(F
1
) = 0000, . . . , K(F
14
) = 1101.
2. Construction of transformed structure table. The transformation is reduced
to moving away the columns a
s
– Φ
h
of initial ST and replacement them by the
columns K(F
h
) and Z
h
. The transformed ST of PF Mealy FSM S
10
is represented
by Table 4.13.
Table 4.13 Transformed structure table of PF Mealy FSM S
10
a
m
K(a
m
) K(F
h
) X
h
Z
h
h
a
1
000 0000 x
1
– 1
0001 ¯ x
1
x
2
z
4
2
0010 ¯ x
1
¯ x
2
z
3
3
a
2
001 0011 x
3
z
3
z
4
4
0100 ¯ x
3
z
2
5
a
3
010 0101 1 z
2
z
4
6
a
4
011 0110 x
2
z
2
z
3
7
0111 ¯ x
1
x
4
z
2
z
3
z
4
8
1000 ¯ x
2
¯ x
3
z
1
9
a
5
100 1001 x
1
x
2
z
1
z
4
10
1010 x
1
¯ x
2
z
2
z
3
11
1011 ¯ x
1
x
3
z
1
z
3
z
4
12
1100 ¯ x
1
¯ x
3
z
1
z
2
13
a
6
101 1101 1 z
1
z
2
z
4
14
This table is the base for deriving the system Z. For example, the following SOP
z
1
=
¯
T
1
T
2
T
3
¯ x
2
¯ x
3
∨T
1
¯
T
2
can be derived from Table 4.13 (after minimization).
3. Specification of block BF. This block can be specified by a table with the
columns K(F
h
), y
1
, . . . , y
N
, D
1
, . . . , D
R
, h (Table 4.14 for FSM S
10
). This table
in constructed in a trivial way.
Obviously, the simplest way for implementation of the logic circuit of the
block BF is usage either of PROM or RAM chips with inputs z
r
∈ Z.
4. Synthesis of FSM logic circuit is executed using the obtained tables and systems
of Boolean functions. For the PF Mealy FSM S
10
, the logic circuit is shown in
Fig. 4.15.
4.4 Synthesis of FSM Multilevel Logic Circuits 95
Table 4.14 Table of block BF for PF Mealy FSM S
10
K(F
h
) y
1
y
2
y
3
y
4
y
5
y
6
y
7
y
8
y
9
D
1
D
2
D
3
h
0000 1 1 1 0 0 0 0 0 1 0 0 1 1
0001 0 0 1 0 0 0 0 1 0 0 1 0 2
0010 0 0 1 1 0 0 0 1 1 0 1 1 3
0011 1 1 0 0 0 0 0 1 0 0 1 0 4
0100 0 0 1 0 0 0 1 0 0 1 0 0 5
0101 0 0 0 0 0 1 1 0 0 1 0 1 6
0110 0 1 0 0 0 0 0 1 0 0 0 1 7
0111 1 1 0 0 0 0 0 0 0 0 0 0 8
1000 0 0 0 0 0 0 1 0 0 1 0 1 9
1001 0 0 0 1 1 0 0 0 0 0 0 1 10
1010 0 0 0 0 0 0 1 0 1 0 1 0 11
1011 0 0 0 0 0 0 0 0 0 0 0 0 12
1100 0 0 1 0 0 0 0 0 0 1 0 0 13
1101 1 1 0 0 0 0 0 0 0 0 0 0 14
Fig. 4.15 Logic circuit of
PF Mealy FSM S
10
PLD
1
1
2
3
4
5
6
1
2
3
4
2
3
4
5
9
z
1
RG D
1
D
2
D
3
R
C
1
2
3
13
14
15
8
4
5
7
6
x
1 1
x
2 2
x
3 3
10
z
2
11
z
3
6
T
1
T
2
T
3
12
z
4
4
6
7
Start
Clock
T
1
8
5
T
2
T
3
PROM
1
2
3
4
1
2
3
4
5
6
7
8
9
10
11
12
9
10
11
y
1
y
2
y
3
y
4
y
5
y
7
y
8
y
9
y
6
12
13
14
D
1
D
2
D
3 15
4.4 Synthesis of FSM Multilevel Logic Circuits
Combined application of methods discussed in this Chapter allows obtaining three-
and four-levels models of Mealy FSM [2]. All possible multilevel models are repre-
sented by Table 4.15.
Table 4.15 Multilevel models of Mealy FSM
LA LB LC LD
M MC ML P F D Y
D Y
96 4 Optimization for Logic Circuit of Mealy FSM
The process of generation of three-level Mealy FSM logic circuit structures can
be interpreted as a word-formation process, where the level LA is a prefix of the
word, the level LB as its base, the level LC either as its suffix (for the block BF)
or ending (for blocks BF, BD, and BY), and the level LD as its ending (for some
particular cases of PF Mealy FSM). For example, the word LA*LB*LC can stand
for either MPY- or MLPD Mealy FSM. Four-level models are based on encoding of
ST rows; they always include all four levels. For example, the word LA*LB*LC*LD
determines MPFDMealy FSM. It means that synthesis method includes the methods
of logical condition replacement, encoding of structure table rows, and encoding of
the classes of compatible microoperations. Obviously, synthesis methods for multi-
level models can be viewed as combining of corresponding methods for two-level
model synthesis. Let us discuss some examples.
Let the Mealy FSM S
12
be specified by its structure table (Table 4.16). Let us
discuss an example of synthesis for the MPD Mealy FSM S
12
.
Table 4.16 Structure table of Mealy FSM S
12
a
m
K(a
m
) a
s
K(a
s
) X
h
Y
h
Φ
h
h
a
1
000 a
2
001 x
1
y
1
y
2
y
3
D
3
1
a
3
010 ¯ x
1
y
1
y
6
D
2
2
a
2
001 a
2
001 x
2
x
3
y
3
D
1
y
6
D
3
3
a
3
010 x
2
¯ x
3
D
1
y
8
D
2
4
a
4
011 ¯ x
2
y
5
y
7
D
2
D
3
5
a
3
010 a
5
100 1 y
1
y
5
D
1
6
a
4
011 a
5
100 x
3
¯ x
4
y
8
D
1
7
a
1
000 x
3
x
4
y
3
D
1
y
6
– 8
a
7
110 ¯ x
3
D
1
y
8
D
1
D
2
9
a
5
100 a
6
101 x
5
y
1
y
6
D
1
D
3
10
a
7
110 ¯ x
5
– D
1
D
2
11
a
6
101 a
1
000 1 y
5
y
7
– 12
a
7
110 a
2
001 x
5
x
6
y
1
y
6
D
3
13
a
5
100 x
5
¯ x
6
y
8
D
1
14
a
3
010 ¯ x
5
y
1
y
5
D
2
15
Obviously, the model of MPD Mealy FSM should include the blocks BM, BP,
and BD (Fig. 4.16).
The block BM implements logical condition replacement and generates functions
(4.3). The block BP generates functions (4.2), as well as functions
Z = Z(P, T). (4.21)
Functions (4.21) control the block BD, which implements functions (4.14). The
following procedure can be used to synthesize the logic circuit of MPD Mealy FSM.
1. Logical condition replacement. For the FSM S
12
, the following sets are de-
rived from Table 4.16: X(a
1
) = {x
1
}, X(a
2
) = {x
2
, x
3
}, X(a
3
) = X(a
6
) = / 0,
4.4 Synthesis of FSM Multilevel Logic Circuits 97
Fig. 4.16 Structural dia-
gram of MPD Mealy FSM
BM
Start
Clock
RG
X
Y
T
BP
P
Ժ
BD
Z
X(a
4
) = {x
3
, x
4
}, X(a
5
) = {x
5
}, and X(a
7
) = {x
5
, x
6
}. It means that G = 2
and determines the set P = {p
1
, p
2
}. The table of logical condition replacement
for FSM S
12
(Table 4.17) is constructed using all rules discussed in previous
Sections.
Table 4.17 Table of logical condition replacement for MPD Mealy FSM S
12
a
m
a
1
a
2
a
3
a
4
a
5
a
6
a
7
p
1
x
1
x
2
– x
4
x
5
– x
5
p
2
– x
3
– x
3
– – x
6
As it follows from Table 4.17, the multiplexer MX
1
has three control inputs,
whereas only two control inputs are enough for the multiplexer MX
2
. Thus, the
codes of states a
m
∈ A should be recoded using the method of multiplexer encod-
ing. The outcome of such a recoding is shown in Fig. 4.17.
Fig. 4.17 Multiplexer codes
for Mealy FSM S
12
T1
a
1
a
2
a
7
a
4
a
3
a
5
a
6
0
1
00 01 11 10
T2T3
*
2. Encoding of the classes of compatible microoperations. For the FSM S
12
, the
set Y can be divided by three classes of compatible microoperations, namely:
Y
1
= {y
1
, y
4
, y
7
}, Y
2
= {y
2
, y
6
, y
8
}, Y
3
= {y
3
, y
5
}. It is enough R
D
= 6 variables
z
r
∈ Z for encoding of microoperations; let us point out that microoperations
y
n
∈ Y
3
are encoded using one-hot codes. The final codes are represented by
Table 4.18.
3. Transformation of FSM structure table. To transforman initial structure table,
the column X
h
is replaced by the column P
h
, and the column Y
h
by the column Z
h
.
The first replacement is executed in the manner used for MP Mealy FSM, while
the second for PD Mealy FSM (Table 4.19).
98 4 Optimization for Logic Circuit of Mealy FSM
Table 4.18 Codes of microoperations for MPD Mealy FSM S
12
Y
1
K(Y
1
) Y
2
K(Y
2
) Y
3
K(Y
3
)
z
1
z
2
z
3
z
4
z
5
z
6
/ 0 0 0 / 0 0 0 / 0 0 0
y
1
0 1 y
2
0 1 y
3
0 1
y
4
1 0 y
6
1 0 y
5
1 0
y
7
1 1 y
8
1 1
Table 4.19 Transformed structure table of MP Mealy FSM S
12
a
m
K(a
m
) a
s
K(a
s
) P
h
Z
h
Φ
h
h
a
1
000 a
2
001 p
1
z
2
z
4
z
6
D
3
1
a
3
010 ¯ p
1
z
2
z
3
D
1
2
a
2
001 a
2
001 p
1
p
2
z
1
z
3
z
6
D
3
3
a
3
100 p
1
¯ p
2
z
1
z
3
z
4
D
1
4
a
4
010 ¯ p
1
z
1
z
2
z
5
D
2
5
a
3
100 a
5
101 1 z
2
z
5
D
1
D
3
6
a
4
010 a
5
101 p
2
¯ p
1
z
3
z
4
D
1
D
3
7
a
1
000 p
2
p
1
z
1
z
6
– 8
a
7
011 ¯ p
2
z
1
z
2
z
3
z
4
D
2
D
3
9
a
5
101 a
6
110 p
1
z
2
z
3
D
1
D
2
10
a
7
011 ¯ p
1
– D
2
D
3
11
a
6
110 a
1
000 1 z
1
z
2
z
5
– 12
a
7
011 a
2
001 p
1
p
2
z
2
z
3
D
3
13
a
5
101 p
1
¯ p
2
z
3
z
4
D
1
D
3
14
a
3
100 ¯ p
1
z
2
z
5
D
1
15
The table is used to derive functions z
r
∈ Z, D
r
∈ Φ. For example, the following
Boolean equations for functions z
1
= F
3
∨F
4
∨F
5
∨F
8
∨F
9
∨F
12
= A
2
∨A
3
p
2
p
1

A
3
¯ p
2
∨A
6
; D
1
= F
2
∨F
4
∨F
6
∨F
7
∨F
10
∨F
14
∨F
15
can be derived from Table 4.19.
The logic circuit of MPD Mealy FSM S
12
is shown in Fig. 4.18. In this circuit,
the block BP includes two multiplexers and is implemented using information from
Table 4.17, as well as codes shown in Fig. 4.16. The block BP is designed on the
base of transformed ST (Table 4.19); the block BD includes two decoders and is
implemented using Table 4.18.
Let us discuss an example of design for the MPFY Mealy FSM S
12
, represented
by its structure table (Table 4.16). The structural diagram of MPFY Mealy FSM is
shown in Fig. 4.19. In this model, the block BM replaces logical conditions and gen-
erates functions P(X, T); the block BP generates variables z
r
∈Z
P
used for encoding
of rows of transformed structure table; the block BF generates variables z
r
∈Z
F
used
for encoding of collections of microoperations, as well as input memory functions
φ
r
∈ Φ. The block BY implements the system Y depended on variables z
r
∈Z
F
. The
4.4 Synthesis of FSM Multilevel Logic Circuits 99
Fig. 4.18 Logic circuit of
MPD Mealy FSM S
12
x
1 1
x
2 2
x
3 3
7
9
10
Start
Clock
T
1
11
8
T
2
T
3
MX
1
0
1
2
3
4
5
6
7
1
2
3
9
1
14
5
5
1
5
15
16
12 P
1
x
4 4
x
5 5
x
6 6
MX
2
0
1
2
3
1
2
3
9
6
8
3
13 P
2
DC
1
1
2
1
2
3
4
14
15
y
1
y
4
y
7
DC
2
1
2
1
2
3
4
16
17
y
6
y
2
y
8
y
5
y
3
18
19
RG D
1
D
2
D
3
R
C
1
2
3
20
21
22
23
7
8
24
9
T
1
T
2
T
3
PLD 12
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9
13
7
8
9
20
21
22
14
D
1
D
2
D
3
z
1
15
z
2
16
z
3
17
z
4
18
z
5
19
z
6
Fig. 4.19 Structural dia-
gram of MPFY Mealy FSM
BM
Start
Clock
RG
X
Y
T
BF
P
Ժ
BY
Z
F
BP
Z
P
following systems of Boolean functions should be found to design the logic circuit
of MPFY Mealy FSM:
P = P(X, T), (4.22)
Z
P
= Z
P
(P, T), (4.23)
Z
F
= Z
F
(Z
P
), (4.24)
Φ = Φ(Z
P
), (4.25)
Y = Y(Z
F
). (4.26)
1. Logical condition replacement. This step has been discussed for the MPD
Mealy FSM S
12
. Obviously, the outcome for this step does not depend on the
model in use; instead, it is determined by the initial structure table. As in pre-
vious case, states codes are shown in Fig. 4.17, whereas Table 4.17 shows the
outcome of logical condition replacement. This table determines system (4.22).
100 4 Optimization for Logic Circuit of Mealy FSM
2. Encoding of structure table rows. For the Mealy FSM S
12
, the structure table
includes H =15 rows, therefore, it is enough R
F
=4 variables for encoding of its
rows. Thus, we have the set Z
P
= {z
1
, . . . , z
4
}. Let us encode the structure table
rows in a trivial way: K(F
1
) = 0000, . . . , K(F
15
) = 1110.
3. Encoding of collections of microoperations. The FSM S
12
includes T
0
= 8
collections of microoperations: Y
1
= / 0, Y
2
= {y
1
, y
2
, y
3
}, Y
3
= {y
1
, y
6
}, Y
4
=
{y
3
, y
4
, y
6
}, Y
5
= {y
4
, y
8
}, Y
6
= {y
5
, y
7
}, Y
7
= {y
1
, y
5
}, Y
8
= {y
8
}. It is enough
R
3
=3 variables for such an encoding, therefore, we have the set Z
F
={z
5
, z
6
, z
7
}.
In the discussed example, the block BY is represented by Table 4.20.
Table 4.20 Table of block BY for MPFY Mealy FSM S
12
z
5
z
6
z
7
Y(Z
F
) t z
5
z
6
z
7
Y(Z
F
) t
0 0 0 – 1 1 0 0 y
4
y
8
5
0 0 1 x
1
y
2
y
3
2 1 0 1 y
5
y
7
6
0 1 0 x
1
y
6
3 1 1 0 x
1
y
5
7
0 1 1 y
3
y
4
y
6
4 1 1 1 y
8
8
The simplest way for implementation of the block BY is use of PROM (or
RAM) chips with address inputs z
5
– z
7
. This table can be used for deriv-
ing SOP functions y
n
∈ Y. Let the symbol Z
t
stand for a conjunction of vari-
ables z
r
∈ Z
F
, corresponding to the code K(Y
t
). In this case, the following SOP
y
1
= Z
2
∨Z
3
∨Z
7
= ¯ z
5
¯ z
6
z
7
∨z
6
z
7
, for example, can be derived from Table 4.20.
4. Transformation of initial structure table. To construct such a table, the col-
umn X
h
should be replaced by the column P
h
(as it is for MP Mealy FSM), and
columns a
s
- Φ
h
are replaced by the column Z
h
(as it is for PF Mealy FSM). For
the FSM S
12
, the outcome of transformation is shown in Table 4.21.
This table is used for deriving system (4.23). For example, the following
Boolean function for the block BP z
1
= F
9
∨. . . ∨F
15
=
¯
T
1
T
2
¯
T
3
¯ p
2
∨A
5
∨A
6

∨A
7
=
¯
T
1
T
2
¯
T
3
¯ p
2
∨T
1
T
3
∨T
1
T
2
∨T
2
T
3
can be derived from Table 4.21.
5. Specification of block BF. The block BF is represented by the table with
columns K(F
h
) (inputs of memory blocks),Φ, Z
F
(outputs of memory blocks).
In the discussed case, this table includes H = 15 rows (Table 4.22). This table
is used for deriving systems (4.24) and (4.25). Obviously, these systems can be
represented as SOPs, as it is shown for the system (4.26).
6. Logic circuit implementation. Logic circuits for blocks BM, BP, BF, and BY
are implemented during this step. Next, these circuits are combined together to
form a final logic circuit. The logic circuit for block BM is implemented using
both Table 4.17 and state codes shown in Fig. 4.16. The logic circuit for block
BP is implemented using the transformed structure table (Table 4.21). The logic
circuit for block BF is implemented using Table 4.22. The logic circuit for block
BY is implemented using Table 4.20. Joining these circuits into the final logic
circuit is easy enough; we do not discuss this step.
4.4 Synthesis of FSM Multilevel Logic Circuits 101
Table 4.21 Transformed structure table of MPFY Mealy FSM S
12
a
m
K(a
m
) P
h
Z
h
h
a
1
000 p
1
– 1
¯ p
1
z
4
2
a
2
001 p
1
p
2
z
3
3
p
1
¯ p
2
z
3
z
4
4
¯ p
1
z
2
5
a
3
100 1 z
2
z
4
6
a
4
010 p
2
p
1
z
2
z
3
7
p
2
¯ p
1
z
2
z
3
z
4
8
¯ p
2
z
1
9
a
5
101 p
1
z
1
z
4
10
¯ p
1
z
1
z
3
11
a
6
110 1 z
1
z
3
z
4
12
a
7
011 p
1
p
2
z
1
z
2
13
p
1
¯ p
2
z
1
z
2
z
4
14
¯ p
1
z
1
z
2
z
3
15
Table 4.22 Specification of block BF for MPFY Mealy FSM S
12
K(F
h
) Φ Z
F
h
0000 D
3
z
7
1
0001 D
1
z
6
2
0010 D
3
z
6
z
7
3
0011 D
1
z
5
4
0100 D
2
z
5
z
7
5
0101 D
1
D
3
z
5
z
6
6
0110 D
1
D
3
z
5
z
6
z
7
7
0111 – z
6
z
7
8
1000 D
2
D
3
z
5
9
1001 D
1
D
3
z
6
10
1010 D
1
D
2
– 11
1011 – z
5
z
7
12
1100 D
3
z
6
13
1101 D
1
D
3
z
5
z
6
z
7
14
1110 D
1
z
5
z
6
15
102 4 Optimization for Logic Circuit of Mealy FSM
Logic circuits for any of FSM represented by Table 4.15 can be designed using
the same approach. Some examples of designs can be found in [2].
References
1. Adamski, M., Barkalov, A.: Architectural and Sequential Synthesis of Digital Devices.
University of Zielona Góra Press, Zielona Góra (2006)
2. Barkalov, A., Titarenko, L.: Synthesis of Operational and Control Automata. UNITECH,
Donetsk (2009)
3. Barkalov, A., W˛ egrzyn, M.: Design of Control Units With Programmable Logic.
University of Zielona Góra Press, Zielona Góra (2006)
4. Barkalov, A., Zelenjova, I.: Optimization of replacement of logical conditions for an au-
tomaton with bidirectional transitions. Automatic Control and Computer Sciences 34(5),
48–53
Chapter 5
Optimization for Logic Circuit of Moore FSM
Abstract. The chapter is devoted to original synthesis and optimization methods
oriented on Moore FSM logic circuit implemented with CPLD. These methods are
based on results of joint investigations conducted by the authors and their PhD stu-
dents Cololo S. (Ukraine) and Chmielewski S. (Poland). These methods deal with
both homogenous and heterogeneous CPLD chips. In the first case, only PAL- or
PLA- based macrocells are used for logic circuit implementation. In the second
case, the logic circuit is implemented using both PAL-based macrocells and em-
bedded memory blocks. The hardware amount reduction is based on use of several
sources (up to three) to represent the codes of classes of pseudoequivalent states.
The methods assume joint minimization of Boolean expressions for input memory
functions and microoperations of Moore FSM. The last part of the chapter is devoted
to joint application of proposed methods and logical condition replacement.
5.1 Optimization for Two-Level FSM Model
If logic circuit of Moore FSM is implemented using standard FPLD chips, then opti-
mization methods targeted on optimization of matrix FSM model should be adapted
to take into account some particular features of these microchips. Let us discuss a
two-level Moore FSM model shown in Fig. 5.1.
Fig. 5.1 Structural diagram
of PY Moore FSM
Start
Clock BY
X
Y
BP
Ժ Z
RG
T
A. Barkalov and L. Titarenko: Logic Synthesis for FSM-Based Control Units, LNEE 53, pp. 103–127.
springerlink.com c Springer-Verlag Berlin Heidelberg 2009
104 5 Optimization for Logic Circuit of Moore FSM
In PY Moore FSM, a block BP generates input memory functions
Φ =Φ(T, X), (5.1)
whereas a block BY generates microoperations
Y =Y(T). (5.2)
The block BP corresponds to matrices M
1
and M
2
(Fig. 2.15); functions (5.1) are
represented as the system (1.8). The block BY corresponds to matrices M
3
and M
4
(Fig. 2.15); functions (5.2) are represented as the system (1.10).
As it is shown in Chapter 2, the methods of optimal, refined, and combined state
encoding can be used to optimize a logic circuit of Moore FSM. This very problem
can be solved using the method of transformation of state codes into the codes of
classes of pseudoequivalent states. Let us discuss application of these methods for
the Moore FSM S
13
, represented by its structure table (Table 5.1).
Table 5.1 Structure table of Moore FSM S
13
a
m
K(a
m
) a
s
K(a
s
) X
h
Φ
h
h
a
1
(–) 000 a
2
001 1 D
3
1
a
2
(y
1
y
2
) 001 a
3
010 x
1
D
2
2
a
4
011 ¯ x
1
x
2
D
2
D
3
3
a
5
100 ¯ x
1
¯ x
2
D
1
4
a
3
(y
3
y
6
) 010 a
6
101 ¯ x
3
D
1
D
3
5
a
7
110 x
3
D
1
D
2
6
a
4
(y
2
y
4
) 011 a
6
101 ¯ x
3
D
1
D
3
7
a
7
110 x
3
D
1
D
2
8
a
5
(y
5
y
6
) 100 a
6
101 ¯ x
3
D
1
D
3
9
a
7
110 x
3
D
1
D
2
10
a
6
(y
1
y
2
) 101 a
1
000 1 – 11
a
7
(y
3
y
6
) 110 a
1
000 1 – 12
As follows from Table 5.1, the Moore FSM S
13
is described by the following
sets: X = ¦x
1
, x
2
, x
3
¦, Y = ¦y
1
, . . . , y
6
¦, A = ¦a
1
, . . . , a
7
¦, Φ = ¦D
1
, D
2
, D
3
¦, T =
¦T
1
, T
2
, T
3
¦. It gives the following values of its main parameters: L =3, N = 6, M =
7, R=3. As in case of Mealy FSM, the structure table is used for deriving systems of
Boolean functions y
n
∈Y and φ
r
∈Φ. For example, the following systems D
1
=F
1

. . . F
10
= A
3
∨A
4
∨A
5
=
¯
T
1
T
2
∨T
1
¯
T
2
¯
T
3
(after minimizing), and y
1
= A
2
∨A
6
=
¯
T
2
T
3
can be derived from Table 5.1. If logic circuit of the block BY is implemented using
some memory blocks such as PROM or RAM, then this block is specified by the
table with columns: a
m
, K(a
m
), Y(a
m
), and m, where m is the number of the table
row (it is Table 5.2 for the Moore FSM S
13
).
5.1 Optimization for Two-Level FSM Model 105
Table 5.2 Specification of block BY of Moore FSM S
13
a
m
K(a
m
) Y(a
m
) m
a
1
000 – 1
a
2
001 y
1
y
2
2
a
3
010 y
3
y
6
3
a
4
011 y
2
D
1
4
a
5
100 y
1
y
6
5
a
6
101 y
1
y
2
6
a
7
110 y
3
y
6
7
For PY Moore FSM, the logic circuit is implemented in a trivial way using the
structure table, as well as the table for block BY. The logic circuit of PY Moore
FSM S
13
is shown in Fig. 5.2.
Fig. 5.2 Logic circuit of PY
Moore FSM S
13
PLD
1
1
2
3
4
5
6
1
2
3
2
3
4
5
9
D
1
RG D
1
D
2
D
3
R
C
1
2
3
9
10
11
12
4
5
13
6
x
1 1
x
2 2
x
3 3
10
D
2
11
D
3
6
T
1
T
2
T
3
4
6
7
Start
Clock
T
1
8
5
T
2
T
3
PROM
1
2
3
1
2
3
4
5
6
4
5
6
y
1
y
2
y
3
y
4
y
5
y
6
As it is discussed in Chapter 2, the optimization methods for Moore FSM [4, 11]
are based on existence of the classes of pseudoequivalent states B
i
∈ Π
A
, where
Π
A
=¦B
1
, . . . , B
I
¦ is a partition of the state set A by the classes of pseudoequivalent
states. For the Moore FSM S
13
, there is the partition Π
A
= ¦B
1
, B
2
, B
3
, B
4
¦, where
B
1
= ¦a
1
¦, B
2
= ¦a
2
¦, B
3
= ¦a
3
, a
4
, a
5
¦, B
4
= ¦a
6
, a
7
¦.
Let the symbol P
0
Y stand for Moore FSM with optimal state encoding. Structure
diagrams are the same for both P
0
Y and PY Moore FSMs (Fig. 5.1). Let us construct
system (2.29), using the following equations for the Moore FSM S
13
:
B
1
= A
1
;
B
2
= A
2
;
B
3
= A
3
∨A
4
∨A
5
;
B
4
= A
6
∨A
7
.
(5.3)
In case of the optimal state encoding, the state assignment for states a
m
∈ A is ex-
ecuted in such a manner, that the number of terms in system (2.29) is minimal.
Obviously, the absolute minimum is equal to the number of classes in the partition.
106 5 Optimization for Logic Circuit of Moore FSM
Let us encode states a
m
∈ A by optimal codes shown in the Karnaugh map
(Fig. 5.3); the well-known algorithm ESPRESSO [12] can be used for the optimal
state encoding.
Fig. 5.3 Optimal state codes
for Moore FSM S
13
T1
a
1
a
2
a
6
a
7
a
3
a
4
a
5
0
1
00 01 11 10
T2T3
*
As follows from Fig. 5.3, the system (5.3) is represented as the following one:
B
1
=
¯
T
1
¯
T
2
¯
T
3
;
B
2
=
¯
T
1
¯
T
2
T
3
;
B
3
= T
1
;
B
4
=
¯
T
1
T
2
.
(5.4)
As follows from (5.4), the absolute minimal value of terms is reached. Now, the
class B
1
corresponds to the code K(B
1
) = 000, the class B
2
to K(B
2
) = 001, the
class B
3
to K(B
3
) = 1∗ ∗, and the class B
4
to K(B
4
) = 01∗.
The transformed structure table of P
0
Y Moore FSM includes columns B
i
, K(B
i
),
a
s
, K(a
s
), X
h
, Φ
h
, h. For the P
0
Y Moore FSM S
13
, this table includes H
0
= 7 rows
(Table 5.3).
Table 5.3 Transformed structure table of P
0
Y Moore FSM S
13
B
i
K(B
i
) a
s
K(a
s
) X
h
Φ
h
h
B
1
000 a
2
001 x
1
D
3
1
B
2
001 a
3
100 x
1
D
1
2
a
4
101 ¯ x
1
x
2
D
1
D
3
3
a
5
111 ¯ x
1
¯ x
2
D
1
D
2
D
3
4
B
3
1∗∗ a
6
011 x
3
D
2
D
3
5
a
7
010 ¯ x
3
D
2
6
B
4
01∗ a
1
000 1 – 7
Transformed ST is used to derive functions (5.1), represented in the following
manner:
D
r
=
H

h=1
C
rh
(
R

r=1
T
l
rh
r
)X
h
. (5.5)
In this expression, C
rh
is a Boolean variable equal to 1, iff the row h of the table
includes input memory function D
r
=1; l
rh
∈¦0, 1, ∗¦ is the value of the bit r for the
code K(B
i
) from the row h of the table, T
0
r
=
¯
T
r
, T
1
r
= T
r
, T

r
= 1 (r = 1, . . . , R; h =
1, . . . , H). In the discussed example, the following expression D
3
= F
1
∨F
3
∨F
4

F
5
=
¯
T
1
¯
T
2
¯
T
3

¯
T
1
¯
T
2
T
3
¯ x
1
∨T
1
x
3
can be derived from Table 5.3.The system (5.5) is
used for implementation of logic circuit of the block BP. A table similar to Table 5.2
5.1 Optimization for Two-Level FSM Model 107
is used for implementation of logic circuit of the block BY. Obviously, logic circuits
for both models of FSM S
13
(PY and P
0
Y) are identical, but the block BP includes
fewer terms in the second model.
This method has some drawbacks, namely [1]:
1. The number of the block BP inputs, as a rule, exceeds their minimal possible
number R
0
, determined by (2.24). Remind that R
0
= log
2
I| and this value is
equal to the number of bits for state codes of equivalent Mealy FSM.
2. The optimal state encoding does not guarantee an achievement of the minimal
number of terms I in system (2.29). Sometimes, it is not possible at all. For
example, there is no such optimal encoding variant for an FSM with the partition
B
1
= ¦a
1
¦, B
2
= ¦a
2
, a
3
, a
4
¦, when the system (2.29) includes only 2 terms. If
the absolute minimum is not reached, then the number of rows for transformed
ST is greater than for equivalent Mealy FSM.
The method of refined state encoding targets on optimization of logic circuit of the
block BY implemented without use of PROM or RAM chips. For the Moore FSM
S
13
, the system (5.2) is represented as:
y
1
= A
2
∨A
6
;
y
2
= A
2
∨A
4
∨A
6
;
y
3
= A
3
∨A
75
;
y
4
= A
4
;
y
5
= A
5
;
y
6
= A
3
∨A
5
∨A
7
.
(5.6)
Use of the refined state encoding leads to the model of P
R
YMoore FSM, let us point
out that its structural diagram is the same as for PY Moore FSM. As an outcome of
refined state encoding, there is the system (5.2) with the following features:
1. Each Boolean function y
n
∈ Y is implemented using only one LUT element (if
FPGA chips are used to implement the block BY).
2. The SOP for each Boolean function y
n
∈Y includes not more than q terms, where
q is the number of terms per one PAL macrocell (if CPLD chips with PAL-based
macrocells are used to implement the block BY).
3. The total number of terms in the system (5.2) is decreased up to the point, when
there is a partition of the set Y with the minimal number N/t| of subsystems
such that each of them is implemented using one PLA macrocell, where t is the
number of PLA outputs (if CPLD chips with PLA-based macrocells are used to
implement the block BY).
To get the above mentioned properties, well-known methods can be used presented
in [1, 12]. One of the possible variants of the refined state encoding is shown in
Fig. 5.4.
The following Boolean equations y
1
=
¯
T
1
T
3
, y
2
=
¯
T
1
T
3

¯
T
1
T
2
, y
3
= T
1
¯
T
2
, y
4
=
T
2
¯
T
3
, y
5
= T
1
T
2
, y
6
= T
1
can be derived from Fig. 5.4. Obviously, the minimal num-
ber of terms for system (5.2) coincides with the number of microoperations, N. In
the discussed example, the system (5.6) includes N = 6 terms; it means that the ab-
solute minimum is reached. Of course, there is no guarantee that this minimum will
be reached. It depends strongly on characteristics of the initial GSA.
108 5 Optimization for Logic Circuit of Moore FSM
Fig. 5.4 Refined state codes
for Moore FSM S
13
T1
a
1
a
2
a
6
a
4
a
3
a
7
a
5
0
1
00 01 11 10
T2T3
*
Because this method targets on minimization of the block BY, it does not guar-
antee decreasing the number of ST rows up to the point, which is possible for the
optimal state encoding. For example, the refined state codes from Karnaugh map
(Fig. 5.4) results in the following transformation of initial system (5.3):
B
1
=
¯
T
1
¯
T
2
¯
T
3
;
B
2
=
¯
T
1
¯
T
2
T
3
;
B
3
= T
1
¯
T
3
∨T
2
¯
T
3
∨T
1
T
2
;
B
4
=
¯
T
1
T
2
T
3
∨T
1
¯
T
2
T
3
.
(5.7)
As it can be found from the system (5.7), the transformed ST includes three subta-
bles with transitions from the states from class B
3
, and two subtables for the class
B
4
. It means that the transformed ST includes 12 rows.
The method of combined state encoding targets on joint minimization for systems
Y =Y(A) and B = B(A). There is no any effective method for this task solving. We
can suppose that it should be an iterative algorithm. For example, the states are
encoded by optimal codes, as the first step. Next, these codes are rearranged in cor-
responding subtables of the common Karnaugh map to optimize the system Y(A).
For the Moore FSM S
13
, one of the possible variants of combined state encoding is
shown in Fig. 5.5.
Fig. 5.5 Combined state
codes for Moore FSM S
13
T1
a
1
a
4
a
2
a
7
a
3
a
5
a
6
0
1
00 01 11 10
T2T3
*
Using these codes, the systems (5.3) and (5.6) can be transformed and represented
as the following:
B
1
=
¯
T
1
¯
T
2
¯
T
3
;
B
2
=
¯
T
1
T
2
¯
T
3
;
B
3
= T
3
;
B
4
= T
1
¯
T
3
;
y
1
= T
1
¯
T
3
;
y
2
=
¯
T
1
T
3
∨T
2
¯
T
3
;
y
3
= T
1
T
3
;
y
4
=
¯
T
1
T
3
;
y
5
= T
1
T
2
T
3
;
y
6
= T
1
¯
T
2
∨T
1
T
3
.
(5.8)
As it follows from system (5.8), the transformed ST includes H
0
= 7 rows (because
each function of the system (5.3) is represented by a SOP with only one term). In
the same time, the number of terms in the system (5.6) is equal to N +1 = 7, that
5.1 Optimization for Two-Level FSM Model 109
is only one term more, than it is in the case of refined state encoding shown in
Fig. 5.4.
If the approach of combined state encoding is used, then PY Moore FSM turns
into P
K
Y Moore FSM with the structure identical to the structure shown in Fig. 5.1.
Synthesis methods for each model (PY, P
0
Y, P
R
Y, and P
K
Y) includes the same steps,
namely:
1. Finding of partition Π
A
for the set of states A by the classes of pseudoequivalent
states.
2. Construction of Boolean systems B(A) and Y(A).
3. Appropriate state encoding (arbitrary, optimal, refined, or combined).
4. Specification of the block BY.
5. Construction of the transformed structure table.
6. Implementation of FSM logic circuit using the given logic elements.
Let us point out that the systemY(A) is not constructed, if logic circuit of the block
BY is implemented using embedded memory blocks. If the approach of arbitrary
state encoding is used, then steps 1, 2, and 5 of the synthesis method are eliminated.
All these methods have the same drawback, namely, they do not guarantee reduction
for the number of transformed ST rows up to H
0
simultaneously with decrease for
the number of terms in system of microoperations up to N. Such an outcome is
guaranteed if a designer uses the approach of transformation of state codes into
codes of the classes of pseudoequivalent states.
In this case PYMoore FSMturns into P
C
Y Moore FSM, with a structural diagram
shown in Fig. 2.20. Let us consider application of the design method for Moore FSM
S
14
represented by its structure table (Table 5.4). Let us use PAL macrocells with
two terms (q = 2) to implement logic circuits of blocks BP, BY, and BTC.
1. Construction of the partition Π
A
. As follows from Table 5.4, this set includes
I = 4 classes, that is Π
A
= ¦B
1
, . . . , B
4
¦. The pseudoequivalent states a
m
∈ A
are distributed among the classes B
i
∈ Π
A
in the following manner: B
1
= ¦a
1
¦,
B
2
= ¦a
2
, a
3
, a
4
¦, B
3
= ¦a
5
, a
6
, a
7
¦, B
4
= ¦a
8
, a
9
, a
10
¦.
Obviously, it is enough two variables (R
0
= 2) for encoding of the classes
B
i
∈ Π
A
and it determines the set τ = ¦τ
1
, τ
2
¦. Let us encode the classes in a
trivial way: K(B
1
) = 00, . . . , K(B
4
) = 11.
2. Construction of systems B(A) and Y(A). As follows from Table 5.4 and par-
tition Π
A
, systems (2.29) and (5.2) are represented in this particular case as the
following:
B
1
= A
1
;
B
2
= A
2
∨A
3
∨A
4
;
B
3
= A
5
∨A
6
∨A
7
;
B
4
= A
8
∨A
9
∨A
10
;
y
1
= A
2
∨A
5
∨A
10
;
y
2
= A
2
∨A
4
∨A
8
;
y
3
= A
3
∨A
5
∨A
9
;
y
4
= A
4
∨A
8
;
y
5
= A
6
;
y
6
= A
9
;
y
7
= A
10
.
(5.9)
110 5 Optimization for Logic Circuit of Moore FSM
Table 5.4 Structure table of Moore FSM S
14
a
m
K(a
m
) a
s
K(a
s
) X
h
Φ
h
h
a
1
(–) 0000 a
2
0001 x
1
D
4
1
a
3
0010 ¯ x
1
x
2
D
3
2
a
4
0011 ¯ x
1
¯ x
2
D
3
D
4
3
a
2
(y
1
y
2
) 0001 a
5
0100 x
2
D
2
4
a
6
0101 ¯ x
2
x
4
D
2
D
4
5
a
7
0110 ¯ x
2
¯ x
4
D
2
D
3
6
a
3
(y
3
) 0010 a
5
0100 x
2
D
2
7
a
6
0101 ¯ x
2
x
4
D
2
D
4
8
a
7
0110 ¯ x
2
¯ x
4
D
2
D
3
9
a
4
(y
2
y
4
) 0011 a
5
0100 x
2
D
2
10
a
6
0101 ¯ x
2
x
4
D
2
D
4
11
a
7
0110 ¯ x
2
¯ x
4
D
2
D
3
12
a
5
(y
1
y
3
) 0100 a
8
0111 x
1
D
2
D
3
D
4
13
a
9
1000 ¯ x
1
x
5
D
1
14
a
10
1001 ¯ x
1
¯ x
5
D
1
D
4
15
a
6
(y
5
) 0101 a
8
0111 x
1
D
2
D
3
D
4
16
a
9
1000 ¯ x
1
x
5
D
1
17
a
10
1001 ¯ x
1
¯ x
5
D
1
D
4
18
a
7
(y
3
) 0110 a
8
0111 x
1
D
2
D
3
D
4
19
a
9
1000 ¯ x
1
x
5
D
1
20
a
10
1001 ¯ x
1
¯ x
5
D
1
D
4
21
a
8
(y
2
y
4
) 0111 a
1
0000 1 1 22
a
9
(y
3
y
6
) 1000 a
1
0000 1 1 23
a
10
(y
1
y
7
) 1001 a
1
0000 1 1 24
3. Combined state encoding. This state assignment targets on maximal possi-
ble simplification for functions Y(A). Next, these state codes are rearranged to
optimize equations from B(A). One of the possible encoding variants is repre-
sented by the Karnaugh map shown in Fig. 5.6.
00
01
00 01 11 10
4 3
T T
2 1
T T
11
10
Fig. 5.6 Combined state codes for Moore FSM S
14
5.1 Optimization for Two-Level FSM Model 111
Taking these codes into account, we can minimize equations from initial sys-
tem (5.9). After minimization, we can get the following system corresponding to
initial system (5.9):
B
1
=
¯
T
2
¯
T
4
;
B
2
= T
2
T
3
T
4
∨T
1
T
2
T
4
;
B
3
=
¯
T
1
T
2
¯
T
3
∨T
1
¯
T
2
;
B
4
= T
1
¯
T
4

¯
T
1
¯
T
2
T
4
;
y
1
= T
1
¯
T
4
;
y
2
= T
2
T
3
;
y
3
= T
2
¯
T
3
;
y
4
= T
1
T
2
T
3
;
y
5
= T
1
¯
T
2
¯
T
3
;
y
6
= T
1
¯
T
3
¯
T
4
;
y
7
=
¯
T
1
¯
T
2
T
3
.
(5.10)
Each equation of the system (5.10) includes up to two terms and, therefore, can
be implemented using only one PAL-based macrocell with q = 2.
4. Specification of block BY. There is no need in such a table, because the sys-
tem of microoperations to be implemented in the discussed example has already
represented as a SOP.
5. Construction of transformed structure table. This step is executed using the
approach we have discussed in previous sections. For the P
C
Y Moore FSM S
14
,
the transformed ST includes H
0
= 10 rows (Table 5.5).
Table 5.5 Transformed structure table of P
C
Y Moore FSM S
14
B
i
K(B
i
) a
s
K(a
s
) X
h
Φ
h
h
B
1
00 a
2
0011 x
1
D
2
D
3
D
4
1
a
3
1101 ¯ x
1
x
2
D
1
D
2
D
4
2
a
4
1111 ¯ x
1
¯ x
2
D
1
D
2
D
3
D
4
3
B
2
01 a
5
0101 x
2
D
2
D
4
4
a
6
1001 ¯ x
2
x
4
D
1
D
4
5
a
7
1011 ¯ x
2
¯ x
4
D
1
D
3
D
4
6
B
3
10 a
8
1110 x
1
D
1
D
2
D
3
7
a
9
1100 ¯ x
1
x
5
D
1
D
2
8
a
10
0011 ¯ x
1
¯ x
5
D
3
D
4
9
B
4
11 a
1
0000 1 – 10
This table is used to derive Boolean equations from the system D
r
∈ Φ. For
example, the following equation D
4
= F
1
∨ . . . ∨F
6
∨F
9
can be derived from
Table 5.5. It can be minimized, and the final expression D
4
= ¯ τ
1
∨τ
1
¯ τ
2
¯ x
1
¯ x
5
is
used to design a corresponding part of FSM logic circuit.
6. Construction of Boolean system for block BCT. System (5.10) includes func-
tions B(T), whereas the block BCT generates functions τ(T). The following ap-
proach can be used for construction of the system τ(T). If a variable τ
r
is equal
to 1 for the class code K(B
i
), then the SOP of function τ
r
includes all terms
belonging to function B
i
(T), where r = 1, . . . , R
0
; i = 1, . . . , I.
112 5 Optimization for Logic Circuit of Moore FSM
For the Moore FSM S
14
, terms of the class B
1
are not included into SOPs of
functions τ
r
∈ τ because K(B
1
) = 00. The class codes K(B
2
) = 01, K(B
3
) = 10,
K(B
4
) = 11 determine the following SOPs: τ
1
= B
3
∨ B
4
, τ
2
= B
2
∨B
4
. Our
analysis of the Karnaugh map from Fig. 5.6 shows that the function τ
2
can be
minimized and represented as τ
2
= T
1
T
2

¯
T
1
T
3
. In the same time, the function τ
1
cannot be minimized.
Obviously, codes for classes B
i
∈ Π
A
can be assigned in such a way, that sys-
tem τ(T) includes the minimal possible number of terms. The well-known al-
gorithm ESPRESSO [12] can be used to solve this problem. For example, if the
classes are encoded as K(B
1
) = 11, K(B
2
) = 00, K(B
3
) = 01, K(B
4
) = 10, then
the following minimized SOPs can be represented as τ
1
= B
1
∨B
4
, τ
2
= B
1
∨B
3
.
Basing on Fig. 5.6, the following final SOPs can be obtained: τ
1
=
¯
T
1
¯
T
2
∨T
1
¯
T
4
,
τ
2
=
¯
T
1
¯
T
3
∨T
1
T
2
T
4
. Now a logic circuit for each function τ
r
∈ τ can be imple-
mented using only one PAL-based macrocell with the number of terms q = 2.
Let us point out that in the initial outcome of state encoding the logic circuit for
function τ
1
is implemented using one macrocell with q = 2, whereas function τ
2
includes 4 terms and its logic circuit consumes 3 macrocells with q = 2.
7. Implementation of FSM logic circuit. This step is executed using systems of
functions obtained for blocks BP, BY, and BCT. For the Moore FSM S
14
, this
circuit is shown in Fig. 5.7.
Fig. 5.7 Logic circuit of
P
C
Y Moore FSM S
14
PAL
1
1
2
3
4
5
6
7
1
2
3
4
2
3
4
5
10
D
1
RG
D
1
D
2
D
3
D
4
R
C
1
2
3
4
10
11
12
13
14
15
8
16
x
1 1
x
2 2
x
3 3
11
D
2
12
D
3
6
T
1
T
2
T
3
4
6
7
x
4
5
x
5
W
1
PAL
1
2
3
4
1
2
3
4
5
6
7
14
15
16
y
1
y
2
y
3
y
4
y
5
y
6
8
Start
Clock 9
W
2
7
13
D
4
17
y
7
9
17
T
4
PAL
14
1
2
3
4
1
2
15
16
17
6
7
W
1
W
2
The following section is devoted to application of this approach for CPLD chips
with PAL-based macrocells and embedded memory blocks BRAM.
5.2 FSM Synthesis for CPLD with Embedded Memory Blocks
The CPLDs produced by Cypress have two specific features:
1. Their PAL-based macrocells have many inputs, it means they are macrocells with
”wide fan-in” [1].
5.2 FSM Synthesis for CPLD with Embedded Memory Blocks 113
2. Their embedded memory blocks can be configured, changing the numbers of
outputs t and words q. The product of these numbers
Q = q t (5.11)
is a constant.
These specifics are used in [2–10] to minimize the hardware amount in logic circuit
of P
C
Y Moore FSM. The main idea of this approach is using more than one source
for codes of the classes of pseudoequivalent states. There are three possible code
sources, such as the register RG, the block BY, and the code transformer BCT. Let
us consider a binary vector 'RG, BY, BTC`, where 1 in some position means use
of the corresponding block as a source of the code K(B
i
). There are the following
vectors 'RG, BY, BTC`:
1. The vector '1, 0, 1`. In this case class codes are generated by blocks RG and BTC;
it leads to P
C1
Y Moore FSM (Fig. 5.8).
2. The vector '1, 1, 0`. In this case class codes are generated by blocks RG and BY;
it leads to P
C2
Y Moore FSM (Fig. 5.9).
Fig. 5.8 Structural diagram
of P
C1
Y Moore FSM
Start
Clock
RG
X
Y
T
BP
Ժ
W
BTC
BY
Fig. 5.9 Structural diagram
of P
C1
Y Moore FSM
Start
Clock
RG
X
Y
Z
BP
Ժ
BY
For P
C2
Y Moore FSM, variables z
r
∈ Z represent class codes for classes B
i
∈ Π
A
such that the block BY is their source.
3. The vector '0, 1, 1`. In this case class codes are generated by blocks BY and BTC;
it leads to P
C3
Y Moore FSM (Fig. 5.10).
4. The vector '1, 1, 1`. In this case class codes are generated by blocks RG, BY, and
BTC; it leads to P
C4
Y Moore FSM (Fig. 5.11).
114 5 Optimization for Logic Circuit of Moore FSM
Fig. 5.10 Structural dia-
gram of P
C3
Y Moore FSM
Start
Clock
RG
X
Y
T
BP
Ժ
W
BTC
BY
Z
Fig. 5.11 Structural dia-
gram of P
C4
Y Moore FSM
Start
Clock
RG
X
Y
T
BP
Ժ
W
BTC
BY
Z
Let Π
RG
⊆ Π
A
be a set of classes B
i
∈ Π
A
, represented by a single generalized
interval of the R - dimensional Boolean space. In this case the register RG is a
source for codes of classes B
i
∈ Π
RG
. Let Π
TC

A

RG
be a set of classes, such
that there is necessity of their state codes transformation. It is enough R
TC
variables
to encode classes B
i
∈ Π
TC
, where
R
TC
= log
2
I
TC
|. (5.12)
In (5.12), we use the number of classes B
i
∈ Π
TC
, namely I
TC
= [Π
TC
[.
As it is mentioned above, each block BRAM can be configured and possible fixed
numbers of outputs create some set T(BRAM). Up-to-day technology are charac-
terized by the set T(BRAM) =¦1, 2, 4, 8, 16, 32¦. The block BY has R inputs, there-
fore a standard block BRAM should be configured in such a way, that is includes 2
R
words. In theory, the word width is determined as
t
0
=

Q/2
R

. (5.13)
But in reality, the nearest number from the set T(BRAM) should be selected as a
real word width. This number should be less or equal to t
0
.
The block BY generates N microoperations. If Q ≥ 2
R
, then n
BY
blocks BRAM
is enough to implement the logic circuit of this block, where
n
BY
= N/t
F
|. (5.14)
In this case all BRAMs from the block BY have totally n
BY
t
F
outputs, though R
BY
outputs are not used for generation of microoperations, where
5.2 FSM Synthesis for CPLD with Embedded Memory Blocks 115
R
BY
= n
BY
t
F
−N. (5.15)
If condition
R
BY
≥ R
TC
(5.16)
takes place, then the block BTC is absent, because class codes for classes B
i

Π
TC
are generated by the block BY. If condition (5.16) is violated, then R
BY
bits
from total number of code bits for classes B
i
∈ Π
TC
are generated by the block BY,
whereas the remainder (R
BY
−R
TC
) bits are generated by the block BTC.
In general, the synthesis method for P
Cj
Y Moore FSM, where j = 1, . . . , 4,
includes the following steps:
1. Construction of partition Π
A
= ¦B
1
, . . . , B
I
¦ of the set of states A by the classes
of pseudoequivalent states.
2. Construction of the system B(A).
3. Optimal state encoding targets on minimizing the number of terms in system
B(A). Construction of the set Π
RG
.
4. If Π
RG

A
, then PY Moore FSM is designed. Otherwise, the set Π
TC
is formed
and values of parameters R
TC
and R
BY
are calculated.
5. If condition (5.16) takes place, then P
C2
Y Moore FSM is designed. In this case, if
the set Π
RG
= / 0, then there is no connections between the register RG and block
BY.
6. If condition (5.16) is violated and in the same time R
BY
= 0, then P
C4
Y Moore
FSM is designed. If R
BY
= 0, then P
C1
Y Moore FSM is designed.
7. If condition (5.16) is violated and Π
A
= / 0, then P
C3
Y Moore FSM is designed.
To design any from these models, a designer should construct the following items:
the transformed structure table (to specify the block BP), the table with content of
BRAM (to specify the block BY), and system τ = τ(T) to specify the block BCT.
Let us discuss some synthesis examples for the Moore FSM S
15
, represented by its
transformed table of transitions (Table 5.6). Let us point out that this table differ
from the classical table of transitions, because in the column ”a
m
” states a
m
∈ A are
replaced by the classes B
i
∈ Π
A
, where a
m
∈ B
i
.
Let the following partition Π
A
=¦B
1
, . . . , B
7
¦ be constructed for the Moore FSM
S
15
, where B
1
= ¦a
1
¦, B
2
= ¦a
5
, a
12
¦, B
3
= ¦a
11
, a
13
, a
14
¦, B
4
= ¦a
3
, a
6
¦, B
5
=
¦a
2
, a
4
¦, B
6
= ¦a
7
, a
8
¦, B
7
= ¦a
9
, a
10
¦. This partition can be represented by the
following system:
B
1
= A
1
;
B
2
= A
5
∨A
12
;
B
3
= A
11
∨A
13
∨A
14
;
B
4
= A
3
∨A
6
;
B
5
= A
2
∨A
4
;
B
6
= A
7
∨A
8
;
B
7
= A
9
∨A
10
.
(5.17)
As follows from Table 5.6, there is the set of states A = ¦a
1
, . . . , a
14
¦, it determines
the following values and sets: R = 4, T = ¦T
1
, . . . , T
4
¦, Φ = ¦D
1
, . . . , D
4
¦. Let us
use the method of optimal state encoding for the Moore FSM S
15
(Fig. 5.12).
116 5 Optimization for Logic Circuit of Moore FSM
Table 5.6 Transformed table of transitions of Moore FSM S
15
B
i
a
s
X
h
h B
i
a
s
X
h
h
B
1
a
2
x
1
1 B
5
a
3
x
3
11
a
3
¯ x
1
x
2
2 a
9
¯ x
3
12
a
5
¯ x
1
¯ x
2
3 B
6
a
2
x
4
13
B
2
a
1
x
3
4 a
1
1 ¯ x
4
x
5
14
a
10
¯ x
3
5 a
12
¯ x
4
¯ x
5
x
6
15
B
3
a
4
x
2
6 a
14
¯ x
4
¯ x
5
¯ x
6
16
a
7
¯ x
2
x
3
7 B
7
a
1
x
3
x
6
17
a
6
¯ x
2
¯ x
3
x
4
8 a
3
x
3
¯ x
6
18
a
13
¯ x
2
¯ x
3
¯ x
4
9 a
10
¯ x
3
x
2
19
B
4
a
8
1 10 a
12
¯ x
3
¯ x
2
20
Fig. 5.12 Optimal state
codes for Moore FSM S
15
00
01
00 01 11 10
4 3
T T
2 1
T T
11
10
Taking into account the codes from Fig. 5.12, the system (5.17) can be
transformed and represented as the following:
B
1
=
¯
T
1
¯
T
2
¯
T
4
;
B
2
= T
2
T
3
¯
T
4
;
B
3
= T
2
¯
T
3
¯
T
4

¯
T
1
T
2
¯
T
3
;
B
4
=
¯
T
1
¯
T
2
T
4
;
B
5
= T
1
¯
T
2
T
4
;
B
6
= T
1
¯
T
2
¯
T
3
¯
T
4
∨T
2
T
3
T
4
;
B
7
= T
1
T
2
¯
T
3
T
4

¯
T
2
T
3
¯
T
4
.
(5.18)
As our analysis of system (5.18) shows, there are the following sets of classes
Π
RG
= ¦B
1
, B
2
, B
4
, B
5
¦ and Π
TC
= ¦B
3
, B
6
, B
7
¦ for the Moore FSM S
15
. Let the
system of its microoperations be the following:
y
1
= A
3
∨A
5
∨A
6
∨A
14
;
y
2
= A
2
∨A
7
∨A
11
∨A
13
;
y
3
= A
2
∨A
4
∨A
8
∨A
9
∨A
10
;
y
4
= A
4
∨A
5
∨A
8
∨A
10
∨A
12
;
y
5
= A
3
∨A
6
∨A
8
∨A
9
∨A
14
;
y
6
= A
2
∨A
3
∨A
4
∨A
6
∨A
7
;
y
7
= A
2
∨A
3
∨A
10
∨A
12
∨A
13
.
(5.19)
It means that N = 7, whereas it is enough two variables (R
TC
= 2) for encoding
of classes B
i
∈ Π
TC
. Let us use the blocks BRAM having fixed outputs from the
set T(BRAM) = ¦1, 2, 4¦ and Q = 64 for implementing logic circuit of the block
BY. It determines the following fixed structures for a single BRAM: 64 1, 32
2, and 16 4. From formula (5.13), the value t
0
= 4 can be found for the Moore
5.2 FSM Synthesis for CPLD with Embedded Memory Blocks 117
FSM S
15
, it means that t
F
= 4. It follows from formula (5.14) that system (5.19)
can be implemented using n
BY
= 2 blocks BRAM with the configuration 64 1;
totally these blocks have 8 outputs. It can be found that R
BY
= 8−7 = 1, therefore,
condition (5.16) is violated. Thus, it is necessary to choose the model of P
C4
YMoore
FSM. Let us point out that this model is characterized by the equality [τ[ = [Z[ = 1.
One from the codes for classes B
i
∈ Π
TC
should be reserved to identify the
classesB
i
/ ∈ Π
TC
. Let the classes B
i
∈ Π
TC
have the following codes: K(B
3
) = 01,
K(B
6
) = 10, and K(B
7
) = 11, then the following equations can be obtained from
system (5.18):
τ
1
= B
6
∨B
7
= T
1
T
2
T
4
∨T
1
¯
T
2
¯
T
4
;
τ
2
= B
3
∨B
7
= T
2
¯
T
3

¯
T
2
T
3
¯
T
4
.
(5.20)
Obviously, the set τ should include those functions, which require fewer numbers
of PAL macrocells for their implementation. For the Moore FSM S
15
both functions
τ
1
and τ
2
are equivalent from this point of view, because each of them includes two
terms. Let us form the following set τ = ¦τ
1
¦. Let us point out that the code 00 is
used to identify the classes B
i
/ ∈ Π
TC
. Thus, we can use the Boolean equation τ
1
from system (5.20) to implement the logic circuit of block BTC.
For the P
C4
Y Moore FSM S
15
, the transformed structure table includes H
0
= 20
rows (Table 5.7).
For P
C4
Y Moore FSM, the block BP is specified by system
Φ =Φ(T, τ, X). (5.21)
This system is derived from the transformed structure table. For example, the fol-
lowing SOP D
4
=F
1
∨F
2
∨F
6
∨F
8
∨F
10
∨F
11
∨F
12
∨F
13
∨F
16
∨F
18
= ¯ τ
1
¯ τ
2
¯
T
1
¯
T
3
¯
T
4
x
1

. . . ∨τ
1
¯ τ
2
¯ x
4
¯ x
5
¯ x
6
∨τ
1
τ
2
x
3
¯ x
6
can be derived from Table 5.7.
If logic circuit of the block BY is implemented using embedded memory blocks,
then system (5.19) should be represented by Table 5.8.
Let H
i
be the number of transitions from the state a
m
∈ B
i
, whereas M
i
be the
number of states in the class B
i
∈ Π
A
. The following formula can be used to find the
number of ST rows for PY Moore FSM:
H =
I

i=1
H
i
M
i
. (5.22)
The logic circuit for P
C4
Y Moore FSMS
15
is shown in Fig. 5.13.
For the Moore FSM S
15
, the classes B
i
∈ Π
A
are characterized by the following
values: H
1
= 3, M
1
= 1; H
2
= 2, M
2
= 2; H
3
= 4, M
3
= 3; H
4
= 1, M
4
= 2; H
5
= 2,
M
5
= 2; H
6
= H
7
= 4, M
6
= M
7
= 2. Thus, the structure table of PY Moore FSM
includes H = 41 rows, as follows from (5.22). In contrary, the transformed ST of
P
C4
Y Moore FSM S
15
(Table 5.7) includes only H
0
= 20 rows.
Let H( f ) be the number of terms for SOP of some function f , q is the number of
terms for a PAL-based macrocell. Let n( f , q) be the number of macrocells having q
terms, necessary to implement the logic circuit for Boolean function f . This number
can be determined using the following formula:
118 5 Optimization for Logic Circuit of Moore FSM
Table 5.7 Transformed structure table of P
C4
Y Moore FSM S
15
B
i
K(B
i
) a
s
K(a
s
) X
h
Φ
h
h
τ
1
τ
2
T
1
T
2
T
3
T
4
B
1
00 0∗00 a
2
1001 x
1
D
1
D
4
1
a
3
0001 ¯ x
1
x
2
D
4
2
a
5
0110 ¯ x
1
¯ x
2
D
2
D
3
3
B
2
00 ∗110 a
1
0000 x
3
– 4
a
10
1010 ¯ x
3
D
1
D
3
5
B
3
10 ∗∗∗∗ a
4
1011 x
2
D
1
D
3
D
4
6
a
7
1000 ¯ x
2
x
3
D
1
7
a
6
0011 ¯ x
2
¯ x
3
x
4
D
3
D
4
8
a
13
0100 ¯ x
2
¯ x
3
¯ x
4
D
2
9
B
4
00 00∗1 a
8
1111 1 D
1
D
2
D
3
D
4
10
B
5
00 10∗1 a
3
0001 x
3
D
4
11
a
9
1101 ¯ x
3
D
1
D
2
D
4
12
B
6
10 ∗∗∗∗ a
2
1001 x
4
D
1
D
4
13
a
11
1100 ¯ x
4
x
5
D
1
D
2
14
a
12
1110 ¯ x
4
¯ x
5
x
6
D
1
D
2
D
3
15
a
14
0101 ¯ x
4
¯ x
5
¯ x
6
D
2
D
4
16
B
7
11 ∗∗∗∗ a
1
0000 x
3
x
6
– 17
a
3
0001 x
3
¯ x
6
D
4
18
a
10
1010 ¯ x
3
x
2
D
1
D
3
19
a
12
1110 ¯ x
3
¯ x
2
D
1
D
2
D
3
20
Table 5.8 Specification of block BY for P
C4
Y Moore FSM S
15
T
1
T
2
T
3
T
4
y
1
y
2
y
3
y
4
y
5
y
6
y
7
τ
2
a
m
0 0 0 0 0 0 0 0 0 0 0 0 a
1
0 0 0 1 1 0 0 0 1 1 1 0 a
3
0 0 1 0 0 0 0 0 0 0 0 0 ∗
0 0 1 1 1 0 0 0 1 1 0 0 a
6
0 1 0 0 0 1 0 0 0 0 1 1 a
13
0 1 0 1 1 0 0 0 1 0 0 1 a
14
0 1 1 0 1 0 0 1 0 0 0 0 a
5
0 1 1 1 0 0 0 0 0 0 0 0 ∗
1 0 0 0 0 1 0 0 0 1 0 0 a
7
1 0 0 1 0 1 1 0 0 1 1 0 a
2
1 0 1 0 0 0 1 1 0 0 1 1 a
10
1 0 1 1 0 0 1 1 0 1 0 0 a
4
1 1 0 0 0 1 0 0 0 0 0 1 a
11
1 1 0 1 0 0 1 0 1 0 0 1 a
9
1 1 1 0 0 0 0 1 0 0 1 0 a
12
1 1 1 1 0 0 1 1 1 0 0 0 a
8
5.2 FSM Synthesis for CPLD with Embedded Memory Blocks 119
Fig. 5.13 Logic circuit of
P
C4
Y Moore FSM S
15
PAL
1
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
2
3
4
5
15
D
1
RG
D
1
D
2
D
3
D
4
R
C
1
2
3
4
15
16
17
18
7
8
13
9
x
1 1
x
2 2
x
3 3
16
D
2
17
D
3
6
T
1
T
2
T
3
4
6
7
x
4
5
x
5
8
9
7
18
D
4
14
10
T
4
PAL
7
1
2
3
4
1
8
9
10
11
W
1
BRAM
7
1
2
3
4
1
2
3
4
8
9
10
12
W
2
y
1
y
2
y
3
y
4
BRAM
7
1
2
3
4
1
2
3
4
8
9
y
1
y
2
y
3
8
9
10
11
12
10
11
12
13
14
W
1
Start
Clock
W
2
x
6
T
1
T
2
T
3
T
4
n( f , q) =

H( f ) −q
q−1

+1. (5.23)
Using formulae (5.14) and (5.23), it is possible to calculate the hardware amount for
logic circuit of any Moore FSM model. If microoperation y
7
is eliminated from the
set Y of the Moore FSM S
15
, then we get N = 6, R
BY
= 2. It means that all code bits
for the classes B
i
∈ Π
TC
are generated by the block BY. In this case the block BTC
is absent and the P
C2
Y model is used for the Moore FSM S
15
. Transformed structure
tables are identical for models P
C4
Y and P
C3
Y.
If the set of microoperations for FSM S
15
includes some additional microopera-
tion y
8
, then N = 8, R
BY
= 0. It means that all code bits for classes B
i
∈ Π
TC
are
generated by the block BTC. In this case the P
C1
Y model is used for the Moore
FSM S
15
. Logic circuit of the block BTC is implemented using equations from sys-
tem (5.20). Transformed structure tables are identical for models P
C4
Y and P
C1
Y.
Some comparative characteristics are shown in Table 5.9. They are used to com-
pare logic circuit implementations for the Moore FSM S
15
based on different mod-
els, such as PY, P
C1
Y P
C2
Y, P
C4
Y, when the circuit is implemented using PAL-based
macrocells with q = 3.
Three columns are used in the table to characterize each FSM model, namely: the
number of terms for FSM functions; the number of macrocells used to implement
these functions; the number of levels for logic circuits. In the row BP, these numbers
are summed up for input memory functions D
1
- D
4
, whereas in the row BTC for
τ
1
and τ
2
. The row FSM contains final characteristics for the particular model. The
number of levels L( f , q) is determined as
L( f , q) =

log
q
n( f , q)

+1, (5.24)
while the total number of logic circuit levels are determined as the maximum from
the numbers obtained for functions D
r
∈ Φ and τ
r
∈ τ.
120 5 Optimization for Logic Circuit of Moore FSM
Table 5.9 Specification of block BY for P
C4
Y Moore FSM S
15
Model PY P
C1
Y P
C2
Y P
C4
Y P
0
Y
D
1
17 8 3 11 5 3 11 5 3 11 5 3 18 9 3
D
2
14 7 3 8 4 2 8 4 2 8 4 2 11 5 3
D
3
19 9 3 8 4 2 8 4 2 8 4 2 13 6 3
D
4
19 9 3 10 5 3 10 5 3 10 5 3 15 7 3
τ
1
0 0 0 2 1 1 0 0 0 2 1 1 0 0 0
τ
2
0 0 0 2 1 1 0 0 0 0 0 0 0 0 0
BP 69 33 3 37 18 3 37 18 3 37 18 3 57 27 3
BTC 0 0 0 4 2 1 0 0 0 2 1 1 0 0 0
FSM 69 33 3 41 20 3 37 18 3 39 19 3 57 27 3
Analysis of Table 5.9 shows that all models have better characteristics than the
model PY. All models have the same number of blocks BRAM; their performance
is equal. Let us point out that the discussed approach can be applied only if the
following condition takes place:
S ≥ L( f ) +R+R
TC
. (5.25)
In formula (5.25), the symbol S stands for the number of macrocell inputs, the sym-
bol L( f ) for the number of logical conditions used in the SOP of function f . For the
P
0
Y Moore FSM S
15
, where H = 32, the required number of macrocells is fewer,
than for the PY Moore FSM S
15
. But this number is always bigger than for any from
P
C
Y models.
5.3 Synthesis of Moore FSM with Logical Condition
Replacement
As in case of Mealy FSM, the hardware amount for Moore FSM logic circuit can be
decreased if the method of logical condition replacement is used. Let us discuss the
basic model of MPY Moore FSM (Fig. 5.14).
Fig. 5.14 Structural dia-
gram of MPY Moore FSM
BM
Start
Clock
RG
X
Y T
BP
P
Ժ
BY
For MPY Moore FSM, a block BM generates system (4.3) including variables
for logical condition replacement, a block BP generates functions (4.2), and a block
5.3 Synthesis of Moore FSM with Logical Condition Replacement 121
BY implements functions (5.2). Obviously, the logic circuit of block BM can be
optimized using methods of state code transformation into either refined codes for
classes of pseudoequivalent states, or codes of logical conditions. The first approach
leads to MPCY Moore FSM, whereas the second method turns Moore FSM into
MPLY Moore FSM. Decrease for the block BP hardware amount is possible due to
application of the optimal state encoding, as well as various state code transforma-
tions (Table 5.10).
Table 5.10 Models of Moore FSM with logical condition replacement
LA LB LC
M MC ML P P
C1
P
C4
Y
P
0
P
C2
P
C3
P
C
This table represents 15 different Moore FSM models with logical condition re-
placement. Each of them corresponds to a word LA ∗ LB ∗ LC. Let us discuss an
example of the MP
0
LY Moore FSM S
16
, which is represented by the structure table
of corresponding P
0
Y Moore FSM (Table 5.11).
The method of optimal state encoding is used for encoding of states a
m
∈ A of the
Moore FSM S
16
. The following partition Π
A
= ¦B
1
, . . . , B
4
¦ can be constructed for
the Moore FSM S
16
, where B
1
= ¦a
1
¦, B
2
= ¦a
2
, a
3
¦, B
3
= ¦a
4
, a
5
, a
6
¦, and B
4
=
¦a
7
¦. The class B
1
corresponds to the code K(B
1
) = ∗00 (taking into account the
unused input assignment 100), the class B
2
corresponds to the code K(B
2
) = 0∗ 1,
the class B
3
corresponds to the code K(B
3
) = 1∗ ∗, and the class B
4
corresponds to
the code K(B
4
) = 010.
The structural diagram of MP
0
LY Moore FSM is shown in Fig. 5.15.
Fig. 5.15 Structural dia-
gram of MP
0
LY Moore
FSM BM
Start
Clock
RG
X
Y T
BP
P
Ժ
BY
CCS
Z
Functions of blocks for this model have been discussed already. Let us point out
that a block CCS generates functions Z(T). The following sets of logical conditions
can be derived from Table 5.11: X(a
1
) = ¦x
1
¦, X(a
2
) = ¦x
2
, x
3
¦, X(a
3
) = X(a
2
),
X(a
4
) = X(a
5
) = X(a
6
) =¦x
3
, x
4
¦, and X(a
7
) = / 0. It means that G = 2 and P =
¦p
1
, p
2
¦. Let us distribute these logical conditions as it is shown in Table 5.12.
The following equation p
2
=x
3
can be derived fromTable 5.12; it means that only
logical conditions from the set X(p
1
) = ¦x
1
, x
2
, x
3
¦ should be encoded. It is enough
122 5 Optimization for Logic Circuit of Moore FSM
Table 5.11 Structure table of P
0
Y Moore FSM S
16
a
m
K(a
m
) a
s
K(a
s
) X
h
Φ
h
h
a
1
(–) 000 a
2
001 x
1
D
3
1
a
3
011 ¯ x
1
D
2
D
3
2
a
2
(y
1
y
2
) 001 a
6
110 x
2
D
1
D
2
3
a
4
101 ¯ x
2
x
3
D
1
D
3
4
a
5
111 ¯ x
2
¯ x
3
D
1
D
2
D
3
5
a
3
(y
1
y
3
) 011 a
6
110 x
2
D
1
D
2
6
a
4
101 ¯ x
2
x
3
D
1
D
3
7
a
5
111 ¯ x
2
¯ x
3
D
1
D
2
D
3
8
a
4
(y
4
y
5
) 101 a
1
000 x
3
– 9
a
7
010 ¯ x
3
x
4
D
2
10
a
5
111 ¯ x
3
¯ x
4
D
1
D
2
D
3
11
a
5
(y
3
y
5
) 111 a
1
000 x
3
– 12
a
7
010 ¯ x
3
x
4
D
2
13
a
5
111 ¯ x
3
¯ x
4
D
1
D
2
D
3
14
a
6
(y
6
y
2
) 110 a
1
000 x
3
– 15
a
7
010 ¯ x
3
x
4
D
2
16
a
5
111 ¯ x
3
¯ x
4
D
1
D
2
D
3
17
a
7
(y
4
y
5
) 010 a
6
110 1 D
1
D
2
18
Table 5.12 Logical condition replacement for P
0
Y Moore FSM S
16
a
m
a
1
a
2
a
3
a
4
a
5
a
6
a
7
p
1
x
1
x
2
x
2
x
4
x
4
x
4

p
2
– x
3
x
3
x
3
x
3
x
3

two variables for their encoding, thus we have the set Z = ¦z
1
, z
2
¦. Let us encode
the logical conditions by the following codes K(x
1
) = 00, K(x
2
) = 01, K(x
4
) = 10,
then the following equations represent these variables z
1
and z
2
:
z
1
= B
2
=
¯
T
1
T
3
;
z
2
= B
3
= T
1
(5.26)
System (5.26) is used to implement the logic circuit of block CCS.
As an outcome of logical condition encoding, the following multiplexer function
can be obtained:
p
1
= ¯ z
1
¯ z
2
x
1
∨ ¯ z
1
z
2
x
2
∨z
1
¯ z
2
x
4
. (5.27)
System (5.27) is used to implement the logic circuit of block BM. Obviously, in our
particular case this block is represented by a single multiplexer having two control
inputs.
5.3 Synthesis of Moore FSM with Logical Condition Replacement 123
Table 5.13 Transformed structure table of MP
0
LY Moore FSM S
16
B
i
K(B
i
) a
s
K(a
s
) P
h
Φ
h
h
B
1
∗00 a
2
001 p
1
D
3
1
a
3
011 ¯ p
1
D
2
D
3
2
B
2
0∗1 a
6
110 p
1
D
1
D
2
3
a
4
101 ¯ p
1
x
2
D
1
D
3
4
a
5
111 ¯ p
1
¯ x
3
D
1
D
2
D
3
5
B
3
1∗∗ a
1
000 x
3
– 6
a
7
010 ¯ x
3
p
1
D
2
7
a
5
111 ¯ x
3
¯ p
1
D
1
D
2
D
3
8
B
4
010 a
6
110 1 D
1
D
2
9
System (4.2) can be derived fromthe transformed structure table. For the MP
0
LY
Moore FSM S
16
, this table includes 9 rows (Table 5.13). Let us point out that the
column P
h
includes both the logical condition x
3
and the newvariable p
1
determined
by equation (5.27).
To specify the block BY, it is necessary to construct the table of microoperations.
This step is executed in a trivial way. For the Moore FSM S
16
block BY is specified
by Table 5.14.
Table 5.14 Specification of block BY for MP
0
LY Moore FSM S
16
T
1
T
2
T
3
y
1
y
2
y
3
y
4
y
5
y
6
m
0 0 0 0 0 0 0 0 0 1
0 0 1 1 1 0 0 0 0 2
0 1 1 1 0 1 0 0 0 3
1 0 1 0 0 1 1 0 0 4
1 1 1 0 0 1 0 1 0 5
1 1 0 0 1 0 0 0 1 6
0 1 0 0 0 1 1 0 0 7
The transformed ST is used to derive system (4.2); for example, the following
equation can be found from Table 5.13: D
1
= F
3
∨ ∨F
4
∨ F
5
∨F
8
∨F
9
=
¯
T
1
T
3

T
1
¯ x
3
¯ p
1

¯
T
1
T
2
¯
T
3
. The logic circuit of MP
0
LY Moore FSM S
16
is shown in Fig. 5.16.
This example shows that synthesis method for a three-level model of Moore FSM
includes the following steps:
1. Construction of the partition Π
A
of state set A by the classes of pseudoequivalent
states.
2. Appropriate state encoding without logical condition replacement.
3. Logical condition replacement.
4. Construction of the transformed structure table.
5. Construction of tables specified FSM blocks.
124 5 Optimization for Logic Circuit of Moore FSM
Fig. 5.16 Logic circuit of
MP
0
LY Moore FSM S
16
MX
1
0
1
2
3
1
2
2
4
5
RG D
1
D
2
D
3
R
C
1
2
3
10
11
12
7
13
14
8
15
x
1 1
x
2 2
x
3 3
9
P
1
6
T
1
T
2
T
3
4
6
7
Start
Clock
x
4
8
5
z
1
z
2
PROM 1
2
3
1
2
3
4
5
13
14
15
y
1
y
2
y
3
y
4
y
5
PLD 1
2
3
4
5
1
2
3
9
3
13
14
10
11
15
12
D
1
D
2
D
3
6. Construction of Boolean systems specified FSM blocks.
7. Logic circuit implementation using given logic elements.
Let us discuss an example of synthesis for the MP
C4
CY Moore FSM S
15
represented
by its transformed structure table (Table 5.6). Let us construct sets X(B
i
) includ-
ing logical conditions x
l
∈ X(a
m
), where a
m
∈ B
i
. The following sets can be found
from Table 5.6: X(B
1
) = ¦x
1
, x
2
¦, X(B
2
) = ¦x
3
¦, X(B
3
) = ¦x
2
, x
3
, x
4
¦, X(B
4
) = / 0,
X(B
5
) = ¦x
3
¦, X(B
6
) = ¦x
4
, x
5
, x
6
¦, X(B
7
) = ¦x
2
, x
3
, x
6
¦. Let us construct the table
for logical condition replacement (Table 5.15), taking into account that G = 3.
Table 5.15 Specification of block BY for MP
0
LY Moore FSM S
16
a
m
B
1
B
2
B
3
B
4
B
5
B
6
B
7
p
1
x
1
– x
4
– – x
4
x
5
p
2
x
2
– x
2
– – x
6
x
6
p
3
– x
3
x
3
– x
3
x
5
x
3
The structural diagram for model of MP
C4
LY Moore FSM includes four logic
blocks and the register RG (Fig. 5.17).
Fig. 5.17 Structural dia-
gram of MP
C4
LY Moore
FSM
BM
Start
Clock
RG
X
Y
T
BP
P
Ժ
BY
BTC
Z
0
Z
W
5.3 Synthesis of Moore FSM with Logical Condition Replacement 125
In this model, the block BCT generates functions τ(T), as well as functions
Z
0
(T) used as control inputs for the multiplexers of block BM. The following
sets of logical conditions can be derived from Table 5.15: X(p
1
) = ¦x
1
, x
2
, x
4
¦,
X(p
2
) = ¦x
2
, x
6
¦, X(p
3
) = ¦x
3
, x
5
¦. The logical conditions x
l
∈ X(p
1
) can be en-
coded using two variables (z
1
and z
2
), whereas only single variable can be used for
other logical conditions (z
3
for x
l
∈ X(p
2
) and z
4
for x
l
∈ X(p
3
)). Let us encode the
logical conditions in the following manner: K(x
1
) = 00, K(x
2
) = 01, K(x
4
) = 10,
K(x
2
) = 0, K(x
6
) = 1, K(x
3
) = 0, K(x
5
) = 1. In this case, the block BY is repre-
sented by the following system of Boolean functions:
p
1
= ¯ z
1
¯ z
2
x
1
∨ ¯ z
1
z
2
x
2
∨z
1
¯ z
2
x
4
;
p
2
= ¯ z
3
x
2
∨z
3
x
6
;
p
3
= ¯ z
4
x
3
∨z
4
x
5
.
(5.28)
To design the logic circuit of block BP, the transformed ST should be transformed
once more. After this transformation, logical conditions x
l
∈ X are replaced by vari-
ables p
g
∈ P (as it follows from Table 5.15), and the column X
h
is replaced by the
column P
h
(Table 5.16).
This table is used to construct system (5.12), which is the base for design of the
logic circuit of block BP. The following Boolean equation D
4
= = F
1
∨F
2
∨F
6

F
8
∨F
10
∨F
11
∨F
12
∨F
13
∨F
16
∨F
18
= ¯ τ
1
¯ τ
2
¯
T
1
¯
T
3
¯
T
4
p
1
∨. . . ∨τ
1
τ
2
p
3
¯ p
2
can be derived
from Table 5.16.
PAL
9
1
2
3
4
5
6
7
8
9
1
2
3
4
10
11
12
13
12
D
1
RG
D
1
D
2
D
3
D
4
R
C
1
2
3
4
12
13
14
15
16
17
7
18
x
1 1
x
2 2
x
3 3
13
D
2
14
D
3
14
T
1
T
2
T
3
4
6
x
4
5
x
5
15
15
D
4
8
19
T
4
MX
1
0
1
2
3
1
2
2
4
9
P
1
BRAM
16
1
2
3
4
1
2
3
4
17
18
19
20
W
2
y
1
y
2
y
3
y
4
BRAM
1
2
3
4
1
2
3
4
y
1
y
2
y
3
16
17
7
8
Start
Clock
x
6
16
17
18
19
PAL
16
1
2
3
4
1
2
3
4
5
17
18
19
21
z
1
22
z
2
23
z
3
24
z
4
25
W
1
21
22
MX
2
0
1
1
6
21
10
P
2
MX
3
0
1
1
5
24
11
P
3
Fig. 5.18 Logic circuit of MP
C4
LY Moore FSM S
15
Systems τ(T) and Z
0
(T)should be constructed for implementation of the logic
circuit of block BCT. In the discussed example, the system τ(T) has been derived
already, whereas the system Z
0
(T) is the following one:
126 5 Optimization for Logic Circuit of Moore FSM
Table 5.16 Transformed structure table of MP
C4
CY Moore FSM S
15
B
i
K(B
i
) a
s
K(a
s
) P
h
Φ
h
h
τ
1
τ
2
T
1
T
2
T
3
T
4
B
1
00 0∗00 a
2
1001 p
1
D
1
D
4
1
a
3
0001 ¯ p
1
p
2
D
4
2
a
5
0110 ¯ p
1
¯ p
2
D
2
D
3
3
B
2
00 ∗110 a
1
0000 p
3
– 4
a
10
1010 ¯ p
3
D
1
D
3
5
B
3
10 ∗∗∗∗ a
4
1011 p
2
D
1
D
3
D
4
6
a
7
1000 ¯ p
2
p
3
D
1
7
a
6
0011 ¯ p
2
¯ p
3
p
1
D
3
D
4
8
a
13
0100 ¯ p
1
¯ p
2
¯ p
3
D
2
9
B
4
00 00∗1 a
8
1111 1 D
1
D
2
D
3
D
4
10
B
5
00 10∗1 a
3
0001 p
3
D
4
11
a
9
1101 ¯ p
3
D
1
D
2
D
4
12
B
6
10 ∗∗∗∗ a
2
1001 p
1
D
1
D
4
13
a
11
1100 ¯ p
1
p
3
D
1
D
2
14
a
12
1110 ¯ p
1
p
2
¯ p
3
D
1
D
2
D
3
15
a
14
0101 ¯ p
1
¯ p
2
¯ p
3
D
2
D
4
16
B
7
11 ∗∗∗∗ a
1
0000 p
2
p
3
– 17
a
3
0001 p
3
¯ p
2
D
4
18
a
10
1010 ¯ p
3
p
1
D
1
D
3
19
a
12
1110 ¯ p
3
¯ p
1
D
1
D
2
D
3
20
z
1
= B
3
∨B
6
= A
11
∨A
13
∨A
14
∨A
7
∨A
8
;
z
2
= B
7
= A
9
∨A
10
;
z
3
= B
6
∨B
7
= A
7
∨A
8
∨A
9
∨A
10
;
z
4
= B
6
= A
7
∨A
8
.
(5.29)
Using the state codes from Karnaugh map (Fig. 5.12), we can get the final formu-
lae for functions (5.29). For example, the following final equation z
3
= T
1
T
2
T
3

T
1
¯
T
2
¯
T
4
can be obtained. To specify the block BY, Table 5.8 can be used for the
MP
C4
CY Moore FSM S
15
.The logic circuit of MP
C4
CY Moore FSM S
15
is shown in
Fig. 5.18.
These examples show the ways for design of logic circuits for multilevel Moore
FSM models, represented by Table 5.10.
References
1. Barkalov, A., Titarenko, L.: Synthesis of Operational and Control Automata. UNITECH,
Donetsk (2009)
2. Barkalov, A., Titarenko, L.: Moore fsm synthesis with coding of compatible micro-
operations fields. In: Proc. of IEEE East-West Design & Test Symposium - EWDTS
2007, Yerevan, Armenia, pp. 644–646. Kharkov National University of Radioelectronics
(2007)
References 127
3. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of logic circuit of moore fsm
on CPLD. Pomiary Automatyka Kontrola 53(5), 18–20 (2007)
4. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of moore fsm on cpld. Inter-
national Journal of Applied Mathematics and Computer Science 17(4), 565–675 (2007)
5. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of moore fsm on cpld. In:
Proceedings of the Sixth Inter. conf. CAD DD 2007, Minsk, vol. 2, pp. 39–45 (2007)
6. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of moore fsm on system-on
chip. In: Proc. of IEEE East-West Design & Test Symposium – EWDTS 2007 (2007)
7. Barkalov, A., Titarenko, L., Chmielewski, S.: Decrease of hardware amount in logic cir-
cuit of moore FSM. Przegl´ zd Telekomunikacyjny i Wiadomo´ sci Telokomunikacyjne (6),
750–752 (2008)
8. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of moore control unit with
refined state encoding. In: Proc. of the 15th Inter. Conf. MIXDES 2008, Pozna´ n, Poland,
pp. 417–420. Departament of Microeletronics and Computer Science, Technical Univer-
sity of Łódz (2008)
9. Barkalov, A., Titarenko, L., Chmielewski, S.: Optimization of moore fsm on system-on-
chip using pal technology. In: Proc. of the International Conference TCSET 2008, Lviv-
Slavsko, Ukraina, pp. 314–317. Ministry of Education and Science of Ukraine, Lviv
Polytechnic National University, Publishing House of Lviv Polytechnic, Lviv (2008)
10. Barkalov, A., Wêgrzyn, A., Barkalov Jr., A.: Synthesis of control units with transfor-
mation of the codes of objects. In: Proc. of the IXth Inter. Conf. CADSM 2007, Lviv -
Polyana, Ukraine, pp. 260–261. Lviv Polytechnic National University, Publishing House
of Lviv Polytechnic National University, Lviv (2007)
11. Barkalov, A.A.: Principles of optimization of logic circuit of Moore FSM. Cybernetics
and System Analysis (1), 65–72 (1998) (in Russian)
12. De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York
(1994)
Chapter 6
FSM Synthesis with Transformation of GSA
Abstract. The chapter is devoted to design methods based on transformation of an
interpreted graph-scheme of algorithm. The methods of decrease for the number of
logical conditions per FSM state are discussed. In extreme case, all FSM transitions
depend on single logical condition; it allows use of embedded memory blocks for
implementation of FSM input memory functions. In this case all FSM blocks are
implemented using standard library cells (not just macrocells of a particular FPLD
chip). The second part of the chapter is devoted to hardware optimization for block
of microoperations, based on verticalization of an interpreted GSA. It permits to
decrease the number of decoders (up to 1) and bit capacity of microinstruction word,
but this optimization is connected with increase for the number of cycles required
for a control algorithm interpretation. At last, the models based on joint application
of these methods are discussed.
6.1 Optimization of Logical Condition Replacement Block
As it was discussed before, the hardware amount of block BP logic circuit can be de-
creased due to replacement of logical conditions x
l
∈X by some additional variables
p
g
∈ P, where |P| = G. The value of parameter G is determined by characteristics
of a GSA Γto be interpreted. This value can be diminished due to introducing some
additional operator vertices into the GSA Γ [8, 9].
It can be found that G=3 for a subgraph Γ
0
(Fig. 6.1a). If the vertex b
2
is brought
in (Fig. 6.1b), then the value of G is decreased up to 2, whereas bringing in the vertex
b
3
(Fig. 6.1c) decreases G up to 1.
Thus, the introduction of additional operator vertices decreases the value of pa-
rameter G (the limit is equal to 1), but it increases the number of FSM states. Be-
sides, introduction of additional operator vertices results in increase for the number
of FSM models. Different Mealy FSM models are shown in Table 6.1.
In this table, the lower index g (g = 1, . . . , G) stands for the number of variables
used for the logical condition replacement. This table describes Mealy FSM models
with different number of levels (1, 2, 3, and 4). All these models can be used to
interpret the same GSA.
A. Barkalov and L. Titarenko: Logic Synthesis for FSM-Based Control Units, LNEE 53, pp. 129–154.
springerlink.com c Springer-Verlag Berlin Heidelberg 2009
130 6 FSM Synthesis with Transformation of GSA
x
1
1
0
a)
y
1
y
3
b
1
x
2
1 0
x
3
1 0
x
1
1
0
b)
y
1
y
3
b
1
x
2
1 0
x
3
1 0
- b
2
x
1
1
0
y
1
y
3
b
1
x
2
1 0
x
3
1 0
- b
2
c)
- b
3
Fig. 6.1 Transformation of subgraph Γ
0
Table 6.1 Multilevel models of Mealy FSM
LA LB LC LD
M
1
M
1
C M
1
L P F DY
. . . DY
M
G
M
G
C M
G
L
Let the symbol NL
i
stand for the number of models having i levels (i = 1, . . . , 4).
Table 6.1 determines the following numbers of different models:
1. NL
1
= 1 (There is only one single-level model, namely, P Mealy FSM).
2. NL
2
= 3G+3 (The first term of equation corresponds to models with logical
condition replacement, whereas the second determines PF-, PD- and PY Mealy
FSMs).
3. NL
3
= 3G∗3+2 (The first term of equation corresponds to models determined
by words LA∗ LB∗ LC, whereas the second determines the models described by
words LB∗LC∗ LD).
4. NL
4
=3G∗2 (These Mealy FSM models are determined by the following words:
M
g
PFD, M
g
PFY, . . . , M
g
LPFY).
Therefore, Table 6.1 represents totally 18G+6 different models for the same GSA.
For an FSM with average complexity [4], where G = 6, there are 114 different
models. Let us point out that each model can differ in its logic circuit hardware
amount from other models. This statement is true for resulted FSM performance
too.
Different Moore FSM models are shown in Table 6.2. This table determines the
following numbers of different models:
1. NL
1
= 7 (This model corresponds to the word LB).
2. NL
2
=3G∗7+7 (These models correspond either to words LA∗LB, or LB∗LC).
3. NL
3
= 3G∗ 7.
6.1 Optimization of Logical Condition Replacement Block 131
Table 6.2 Multilevel models of Moore FSM
LA LB LC
M
1
M
1
C M
1
L P P
C1
P
C4
Y
. . . P
0
P
C2
P
C3
M
G
M
G
C M
G
L P
C
So, Table 6.2 represents 42G+14 different models of Moore FSM. For FSMs with
average complexity, we can get up to 266 different models.
Let us discuss an example of logic synthesis for the M
2
PLFY Mealy FSM S
19
,
specified by the GSA Γ
3
(Fig. 6.2).
The FSM to be synthesized is represented by its model shown in Fig. 6.3. In this
model, a block BM implements the logical condition replacement and generates the
functions
p
1
= p
1
(Z
0
, X);
p
2
= p
2
(Z
0
, X).
(6.1)
A block BP generates functions used for the encoding of transformed structure table
rows, namely, functions
Z = Z(p
1
, p
2
, T). (6.2)
A block BF generates variables used for encoding of the collections of microopera-
tions, as well as input memory functions:
Z
1
= Z
1
(Z);
Φ =Φ(Z).
(6.3)
A block BY generates microoperations
Y =Y(Z
1
). (6.4)
At last, a code transformer CCS generates variables used as control inputs of multi-
plexers from the block BM:
Z
0
= Z
0
(T). (6.5)
Design of this FSM is reduced to construction of systems (6.1) – (6.5) and imple-
mentation of logic circuits for corresponding blocks using some macrocells.
As follows from Fig. 6.2, the states a
2
and a
5
are characterized by |X(a
m
)| > 2.
Thus, the corresponding subgraphs of GSAΓ
3
should be transformed. The transfor-
mation is reduced to introduction of three additional operator vertices into the GSA
Γ
3
(Fig. 6.4).
In the FSM S
17
, the number of states is increased from 5 to 7 after the transfor-
mation of the GSA Γ
3
. But the transformation permits to get the value G = 2, that
corresponds to the member M
2
in the formula M
2
PLFY. In both cases, it is enough
R = 3 variables T
r
∈ T for the state encoding. Let us encode the states in a trivial
132 6 FSM Synthesis with Transformation of GSA
y
2
y
5 y
2
y
3
x
1
1 0
x
4
1 0
End
Start
a
1
y
4
y
1
y
2
a
2
x
2
1 0
x
3
1 0
x
5
1 0
x
7
1 0
x
3
1 0
x
6
1 0
y
1
y
2
y
1
y
2
y
1
y
2
y
1
y
2
x
1
1 0
a
3
a
5
a
1
Fig. 6.2 Initial graph-scheme of algorithmΓ
3
Fig. 6.3 Structural diagram
of M
2
PLFY Mealy FSM
BM
Start
Clock
RG
X
Y
T
BF
P
2
Ժ
BY
Z
1
BP
Z
Z
0
P
1
CCS
way, namely:K(a
1
) = 000, . . . , K(a
7
) = 110. Using these codes, let us construct the
structure table of Mealy FSM S
17
(Table 6.3).
As it was mentioned above, it is enough G = 2 variables to replace the logical
conditions, thus, there is a set P = {p
1
, p
2
}. Let us construct the table of logical
6.1 Optimization of Logical Condition Replacement Block 133
condition replacement for FSM S
17
(Table 6.4). As it can be found from the table,
it is enough two variables z
r
∈ Z
0
to replace the logical conditions x
l
∈ X(P
g
). It is
true, because there are only four pairs of logical conditions into Table 6.4, namely:
x
1
, x
2
, x
4
, x
5
, x
3
, x
6
, and / 0, x
7
. If the pair x
1
, x
2
corresponds to the code
K(x
1
) = K(x
2
) = 00, then the equalities p
1
= x
1
, p
2
= x
2
take place for the state a
5
.
Because the logical condition x
2
does not affect transitions from the state a
5
, then
a real value of this logical condition is not important. Therefore, the following set
Z
0
= {z
1
, z
2
} can be used in this particular case. Let us encode the remained pairs
by the following codes:K(x
4
) = K(x
5
) = 01, K(x
3
) = K(x
4
) = 10, and K(x
7
) = 11.
As a result, the following system of equations can be constructed:
p
1
= ¯ z
1
¯ z
2
x
1
∨ ¯ z
1
z
2
x
4
∨z
1
¯ z
2
x
3
;
p
2
= ¯ z
1
¯ z
2
x
2
∨ ¯ z
1
z
2
x
5
∨z
1
¯ z
2
x
4
∨z
1
z
2
x
7
.
(6.6)
For the FSM S
17
, the structure table includes H = 16 rows, therefore, it is enough
R
F
= 4 variables to encode the rows of this table. It gives the set of variables
Z = {z
3
, . . . , z
6
}. Let us encode the rows of Table 6.3 in the following way:
Table 6.3 Structure table of Mealy FSM S
17
a
m
K(a
m
) a
s
K(a
s
) X
h
Y
h
Φ
h
h
a
1
000 a
2
001 1 y
1
y
2
D
3
1
a
2
001 a
3
010 x
1
x
2
y
2
y
3
D
2
2
a
3
010 x
1
¯ x
2
y
4
D
2
3
a
6
101 ¯ x
1
– D
1
D
3
4
a
3
010 a
5
100 x
4
x
5
y
1
y
2
D
1
5
a
7
110 x
4
¯ x
5
– D
1
D
2
6
a
4
011 ¯ x
4
– D
2
D
3
7
a
4
011 a
1
000 x
3
y
2
y
5
– 8
a
1
000 ¯ x
3
x
6
y
4
– 9
a
4
011 ¯ x
3
¯ x
6
y
2
y
5
D
2
D
3
10
a
5
100 a
5
100 x
1
– – 11
a
1
000 ¯ x
1
– – 12
a
6
101 a
3
010 x
3
y
4
D
2
13
a
4
011 ¯ x
3
y
2
y
5
D
2
D
3
14
a
7
110 a
5
100 x
7
y
4
y
6
D
1
15
a
1
000 ¯ x
7
y
2
y
5
– 16
Table 6.4 Table of logical condition replacement for FSM S
17
a
m
a
1
a
2
a
3
a
4
a
5
a
6
a
7
p
1
– x
1
x
4
x
3
x
1
x
3

p
2
– x
2
x
5
x
6
– – x
7
134 6 FSM Synthesis with Transformation of GSA
y
2
y
5 y
2
y
3
x
1
1 0
x
4
1 0
End
Start
a
1
y
4
y
1
y
2
a
2
x
2
1 0
x
3
1 0
x
5
1 0
x
7
1 0
x
3
1 0
x
6
1 0
y
1
y
2
y
4
y
6
y
2
y
5
y
4
x
1
1 0
a
3
a
5
a
1
-
-
-
a
6
a
7
a
4
Fig. 6.4 Transformed GSAΓ
3
K(F
1
) = 0000, . . ., K(F
16
) = 1111. Let us construct the transformed ST for Mealy
FSM S
17
(Table 6.5). The transformation is reduced to replacement of the column
X
h
by the column P
h
, replacement of columns Y
h
and Φ
h
by the column Z
h
, and dele-
tion the columns a
s
and K(a
s
) from the initial ST. This table is used to derive the
6.1 Optimization of Logical Condition Replacement Block 135
equations of system (6.2), for example, the Boolean equation z
3
= F
9
∨. . . ∨F
16
=
¯
T
1
T
2
T
3
¯ p
1
∨T
1
¯
T
2
∨T
1
¯
T
3
can be derived from Table 6.5 (this equation is written after
some minimization of initial expression extracted from the table).
For the FSM S
17
, the structure table includes T
0
= 6 collections of microop-
erations, namely: Y
1
= / 0, Y
2
= {y
1
, y
2
}, Y
3
= {y
2
, y
3
}, Y
4
= {y
4
}, Y
5
= {y
2
, y
5
},
Y
6
= {y
6
}. These collections can be encoded using R
0
= 3 variables; it gives the set
Z
1
= {z
7
, z
8
, z
9
}. Let us encode the collections in the following way: K(Y
1
) = 000,
. . ., K(Y
6
) = 101. To design the logic circuit for block BY, it is enough to construct
the Karnaugh map (Fig. 6.5). This map differs from the classical one, because each
its cell can include more than one microoperation.
Fig. 6.5 Codes for collec-
tions of microoperations of
Mealy FSM S
17
- y
1
y
2
y
4
y
2
y
3
y
2
y
5
y
6
0
1
00 01 11 10
* *
z
8
z
9
z
7
Table 6.5 Transformed structure table of Mealy FSM S
17
a
m
K(a
m
) P
h
Z
h
h
a
1
000 1 – 1
a
2
001 p
1
p
2
z
6
2
p
1
¯ p
2
z
5
3
¯ p
1
z
5
z
6
4
a
3
010 p
1
p
2
z
4
5
p
1
¯ p
2
z
4
z
6
6
¯ p
1
z
4
z
5
7
a
4
011 p
1
z
4
z
5
z
6
8
¯ p
1
p
2
z
3
9
¯ p
1
¯ p
2
z
3
z
6
10
a
5
100 p
1
z
3
z
5
11
¯ p
1
z
3
z
5
z
6
12
a
6
101 p
1
z
3
z
4
13
¯ p
1
z
3
z
4
z
6
14
a
7
110 p
2
z
3
z
4
z
5
15
¯ p
2
z
3
z
4
z
5
z
6
16
If embedded memory blocks BRAM are used to implement the logic circuit of
block BY, then an input assignment z
7
z
8
z
9
is treated as an address of correspond-
ing memory word. Word contents are determined by contents of corresponding cells
of the Karnaugh map. If some macrocells are used to implement the logic circuit of
block BY, then collections Y
t
⊆Y should be encoded in the optimal way and min-
imization of functions y
n
∈ Y should be executed. Different types of macrocells
136 6 FSM Synthesis with Transformation of GSA
determine different approaches for the collection encoding. Obviously, all these ap-
proaches have the same aim, which is decrease for the number of macrocells in
logic circuit of the block BY. For the Mealy FSM S
17
, the following equations, for
example, can be derived from Fig. 6.5: y
1
= ¯ z
7
¯ z
8
z
9
, y
2
= z
7
¯ z
9
∨z
8
¯ z
9
∨ ¯ z
7
¯ z
8
z
9
, and so
on. If the collections are recoded as it shown in Fig. 6.6, then each microoperation
y
n
∈Yis represented by the SOP with only single term, namely:
y
1
= ¯ z
7
¯ z
8
z
9
;
y
2
= z
9
;
y
3
= z
8
z
9
;
y
4
= z
1
¯ z
9
;
y
5
= z
1
z
9
;
y
6
= z
8
¯ z
9
.
(6.7)
Fig. 6.6 Optimal codes for
collections of microopera-
tions of Mealy FSM S
17
- y
1
y
2
y
2
y
3
y
6
y
4
y
2
y
5
0
1
00 01 11 10
* *
z
8
z
9
z
7
To implement the logic circuit of block BF, it is necessary to construct corresponding
table with columns Z, Z
1
, Φ
h
, h. In case of the Mealy FSM S
17
, this table includes
16 rows (Table 6.6). Obviously, the number of rows is equal for both the initial
structure table and the table specified the block BF.
In Table 6.6, the column Z includes row codes K(F
h
), determined by vectors
z
3
z
4
z
5
z
6
; the column Φ
h
is taken from the structure table (in our example, from
Table 6.6 Specification for block BF of Mealy FSM S
17
Z Z
1
Φ
h
h
0000 z
9
D
3
1
0001 z
8
D
2
2
0010 z
8
z
9
D
2
3
0011 – D
1
D
3
4
0100 z
9
D
1
5
0101 – D
1
D
2
6
0110 – D
2
D
3
7
0111 z
7
– 8
1000 z
8
z
9
– 9
1001 z
7
D
2
D
3
10
1010 z
9
D
1
11
1011 – – 12
1100 z
8
z
9
D
2
13
1101 z
7
D
2
D
3
14
1110 z
8
z
9
D
1
15
1111 z
7
– 16
6.1 Optimization of Logical Condition Replacement Block 137
Table 6.7 Specification of block CCS for Mealy FSM S
17
a
m
K(a
m
) x
l
K(x
l
) Z
0
m
a
1
000 – – – 1
a
2
001 x
1
x
2
00 – 2
a
3
010 x
4
x
5
01 z
2
3
a
4
011 x
3
x
6
10 z
1
4
a
5
100 x
1
00 – 5
a
6
101 x
3
10 z
1
6
a
7
110 x
7
11 z
1
z
2
7
Table 6.3). The following procedure is executed to fill the column Z
1
: 1) to take a
collection of microoperations Y
t
from the row h of initial ST; 2) to find the code of
collection of microoperations K(Y
t
); 3) to write in the row h of table for block BF
the variables from vector z
7
z
8
z
9
, which are equal to 1 in the code K(Y
t
). For the
Mealy FSM S
17
, codes K(Y
t
) are taken from Fig. 6.5.
If the logic circuit of block BF is implemented using macrocells, then functions
(6.3) and (6.4) are derived from the table specified the block BF. The following SOP
z
7
= F
8
∨F
10
∨F
14
∨F
16
= z
4
z
5
z
6
∨z
3
¯ z
5
z
6
can be derived, for example, from Table
6.6. Obviously, structure table rows can be encoded in such a way, that the logic
circuit of block BF includes minimal number of corresponding macrocells.
To form system (6.6), a table specified the block CCS should be constructed. For
the Mealy FSM S
17
, this block is specified by Table 6.7.
In common case, this table includes columns a
m
, K(a
m
), X(p
1
), K(x
e
)
1
, . . . ,
X(p
G
), K(x
e
)
G
, Z
0
, m. The purposes of these columns are clear. If the logic cir-
cuit of block CCS is implemented using embedded memory blocks, then the code
K(a
m
) is considered as the word address. This word contains data Z
0
and corre-
sponds to the row m of the table. If the logic circuit of block CCS is implemented
using some macrocells, then system (6.6) is represented as a SOP. For example, the
following SOP z
1
=A
4
∨A
6
∨A
7
can be derived for block CCS from Table 6.7. Tak-
ing into account the unused input assignment 111, this equation can be transformed
into z
1
=T
2
T
3
∨T
1
T
3
∨T
1
T
2
. Obviously, states a
m
∈ A can be encoded in the optimal
way to minimize system (6.6). For example, the encoding shown in Fig. 6.7 results
in the following equations: z
1
= T
3
, z
2
= T
1
T
2
.
These tables and equations (6.1) – (6.6) allow implementation of the logic circuit
for M
2
PLFY Mealy FSM S
17
(Fig. 6.8).
Fig. 6.7 Optimal state codes
for Mealy FSM S
17
0
1
00 01 11 10
3 2
T T
1
T
138 6 FSM Synthesis with Transformation of GSA
Fig. 6.8 Logic circuit of
M
2
PLFY Mealy FSM S
17
PLD
10
1
2
3
4
5
1
2
3
4
11
24
25
26
12
z
3
RG
D
1
D
2
D
3
R
C
1
2
3
18
19
20
8
24
25
9
26
x
1 1
x
2 2
x
3 3
13
z
4
14
z
5
T
1
T
2
T
3
8
9
BRAM
1
2
3
1
2
3
4
5
6
21
22
23
y
1
y
2
y
3
y
4
y
5
y
6
Start
Clock
15
z
6
BRAM
24
1
2
3
1
2
25
26
16
17
z
1
z
2
BRAM
12
1
2
3
4
1
2
3
4
5
6
13
14
18
D
1
19
D
2
20
D
3
21
z
7
22
z
8
23
z
9
15
MX
1
0
1
2
3
1
2
4
3
16
10
P
1
17
MX
2
0
1
2
3
1
2
5
6
16
11
P
2
17
x
4 4
x
5 5
x
6 6
x
7 7
In Fig. 6.8, the logic circuits for blocks BF, BY, CCS are implemented using em-
bedded memory blocks; the logic circuit of block BM is implemented using multi-
plexers; the logic circuit of block BP is implemented using macrocells. This example
leads to the following general conclusion: the structural decomposition of FSMlogic
circuit increases the number of regular functions. It allows use of standard memory
blocks for implementation of systems of Boolean functions represented a particular
FSM. In turn, it simplifies the design process if FSM logic circuit is implemented
using FPLD chips.
Next, the discussed example permits to formulate the general approach for design
of FSM multilevel logic circuits, where FSM models are specified by Tables 6.1 and
6.2. To design a particular FSM circuit it is necessary:
1. To construct an FSM model, as well as general Boolean functions corresponding
to each block of the model.
2. To transform an initial GSA (if necessary).
3. To construct tables corresponding to each block of the model. If some block
is implemented using macrocells, then input variables of the block should be
encoded in the optimal way. The criterion of optimality depends on the type of
macrocells in use.
4. To implement the general logic circuit as a composition of the circuits for each
block of FSM model to be designed.
6.2 Optimization for Block for Decoding of Microoperations
Because decoders are standard library elements, their use accelerates the process
of a control unit design. Decoders are used for generation of microoperations in
6.2 Optimization for Block for Decoding of Microoperations 139
PD Mealy FSM (Fig. 4.10). As we know, to design the PD Mealy FSM the set of
microoperations Y should be divided by the classes of compatible microoperations
(Y
1
, . . . ,Y
K
). It means that a partition Π
Y
should be found, such that each element
of Π
Y
corresponds to one class of compatible microoperations. Microoperations of
each class are encoded using codes K(y
n
). The number of bits R
k
for each microop-
eration encoding is determined by (4.12). The sum of these numbers gives the total
number of bits R
D
, required for microoperation encoding and determined by (4.13).
Each class Y
k
∈Π
Y
corresponds to decoder DC
k
, the totality of these decoders forms
the block BD (Fig. 4.10).
If all microoperations y
n
∈ Y are compatible, then such a GSA Γ is named a
vertical GSA (VGSA) [5]. The following condition
N
t
≤ 1 (6.8)
takes place for VGSA, where N
t
is the number of microoperations in collection Y
t

Y(t = 1, . . . , T
0
). If this condition takes place, then PD Mealy FSM turns into PD
1
Mealy FSM, in which the block BD includes only one decoder having N outputs.
The number of classes K in the partition Π
Y
can be varied due to application of the
procedure of verticalization to the initial GSA [5, 7]. The verticalization produces
the family of PD Mealy FSMs with different amount of decoders implementing the
block BD, namely PD
1
−, PD
2
−, . . ., and PD
k
Mealy FSMs. The value of parameter
K depends on characteristics of a GSA to be interpreted, namely on distribution
of microoperations among GSA operator vertices. Let us discuss some problems
connected with synthesis of PD Mealy FSM [1, 5]. Let us use for this discussion
the fragment of GSA Γ
0
(Fig. 6.9a). Obviously, condition (6.8) is violated for this
subgraph.
The sense of verticalization consists in presentation of each vertex b
t
∈ B
1
as a
sequence of operator vertices b
1
t
, b
2
t
, . . ., including up to N
t
elements. Two different
approaches are possible for state marking:
1. The standard marking shown in Fig. 6.9b.
2. Saving of initial marks for FSM states (Fig. 6.9c, d).
The marked GSA shown in Fig. 6.9d corresponds to PD
2
Mealy FSM. One from its
vertices includes an additional microoperation y
0
, but we discuss it a bit latter. The
drawback of PD
k
FSMis decrease for digital systemperformance due to increase for
the number of cycles needed to accomplish an algorithm to be interpreted. Besides,
the successive execution of microoperations written in the same operator vertex is
not always possible because of the data dependence among the microoperations
y
n
∈Y
t
. Let, for example, microoperations written in the vertex b
5
(Fig. 6.9a) stand
for the following actions: y
1
#A := B+C;y
2
#B := A+B;y
3
#C := A+B. Obviously,
outcomes are different for parallel and successive modes of these microoperations
execution. Let operands have the following values:A = 5, B = 6, and C = 8. The
outcomes of parallel execution are the values A = 14, B = 11, C = 11. But if the
microoperations are executed as a sequence y
1
, y
2
, y
3
, then the incorrect results
A = 14, B = 14 +6 = 20, and C = 14 +20 = 34 are obtained.
140 6 FSM Synthesis with Transformation of GSA
a)
y
1
y
2
y
3
b
5
x
1
1 0
a
4
a
3
b)
y
1
b
5
x
1
1 0
a
5
a
3
1
y
2
b
5
a
6
2
y
3
b
5
a
4
3
c)
y
1
b
5
x
1
1 0
a
3
1
y
2
b
5
2
y
3
b
5
a
4
3
d)
y
1
y
2
b
5
x
1
1 0
a
3
1
y
0
y
3
b
5
a
4
2
Fig. 6.9 Fragment of GSA Γ
0
before (a) and after (b, c, d) verticalization
To eliminate these drawbacks, a special variable y
0
is introduced, as well as a
register RY. This variable controls the data-path synchronization, and the register is
used to transformthe sequence of microoperation into a parallel code corresponding
to initial collection of microoperations. Let the symbol T(y
n
) stand for a flip-flop
corresponding to microoperationy
n
∈Y. The flip-flop T(y
n
) is set up, iff y
n
= 1. If
all microoperations y
n
∈ Y
t
are written into the register RY, then the variable y
0
is
generated and the system data-path executes the collection Y
t
⊆ Y(t = 1, . . . , T
0
).
This mode can be organized quite easily, because all modern FPLD have a prop-
erty of independent synchronization for flip-flops, which are registered outputs of
macrocells [2, 10].
If states a
m
∈ A are marked in the standard way [3, 4], then the verticalization of
GSA results in PD
1
V
Mealy FSM (Fig. 6.10).
In Fig. 6.10, outputs of the register RY are denoted as Y
R
, where the symbol Y
R
stands for a set of registered microoperations. Let us discuss an example of synthesis
for the PD
1
V
Mealy FSM S
18
specified by an initial GSA Γ
4
(Fig. 6.11).
1. Verticalization of initial GSA. This step is reduced to the successive splitting
of operator vertices, if condition (6.8) for them is violated. The execution of
verticalization causes no difficulties. The vertical GSA V(Γ
4
) with a standard
Fig. 6.10 Structural dia-
gram of PD
1
V
Mealy FSM
Start
Clock
RG
X
Y
T
BP y
0
Ժ
BD
Z Y
R
BD
6.2 Optimization for Block for Decoding of Microoperations 141
state marking is shown in Fig. 6.12. To simplify the symbols, the vertices of
VGSAV(Γ
4
) are renumbered.
Fig. 6.11 Initial graph-
scheme of algorithmΓ
4
y
1
y
4
y
7
x
1
1 0
End
Start
y
2
y
5
x
2
1 0
x
3
1 0
a
2
a
1
y
3
y
6
y
7
y
1
y
5
y
2
y
7
y
1
y
4
y
7
y
2
y
5
b
1
b
2
b
3
b
5
b
7
b
6
b
4
a
1
Comparison of Fig. 6.11 and Fig. 6.12 shows that the FSM S
18

4
) has three
state variables, whereas its counterpart S
18
(V(Γ
4
)) has four state variables.
2. Microoperation encoding. For the PD
1
V
Mealy FSM S
18
, there are seven micro-
operations (N = 7), thus it is enough three variables for their encoding. It means
that R
D
= 3 and Z = {z
1
, z
2
, z
3
}.
In the common case, the number of encoding variables is determined as
R
D
= log
2
(N +1). (6.9)
In (6.9), the number of microoperations is increased by 1 iff there is a collec-
tion Y
t
= / 0 in the GSA to be interpreted. Let us use the following approach for
microoperation coding: the more times microoperation y
n
∈ Y appears in op-
erator vertices of initial GSA, the more zeros its code includes. This approach
is adaptation of the well-known algorithm for state assignment according with
a frequency of their appearance in the FSM structure table [3, 4]. Let us name
this approach as a frequency encoding. Let the symbol f
n
stand for frequency
of appearance for microoperation y
n
∈ Y. For the Mealy FSM S
18
, there are
142 6 FSM Synthesis with Transformation of GSA
End
Start
x
1
1 0
a
1
y
1
y
2
y
4
y
0
y
5
y
0
y
7
b
1
b
3
b
5
b
4
b
2
a
1
x
2
1 0
a
5
x
3
1 0
a
2
a
3
a
4
y
3
y
1
b
6
b
7
a
6
a
12
y
6
y
0
y
5
b
8
b
9
a
7
a
13
y
0
y
7
y
1
b
10
b
11
a
8
a
14
y
2
y
4
b
12
b
13
a
9
a
15
y
0
y
7
y
0
y
7
b
14
b
15
a
10
y
2
b
16
a
11
y
0
y
5
b
18
Fig. 6.12 Vertical graph scheme of algorithm V(Γ
4
)
frequencies f
1
= f
2
= f
5
= 3, f
3
= f
6
= 1, f
4
= 2, f
7
= 4. It leads to the out-
come of frequency encoding shown in Fig. 6.13.
Fig. 6.13 Frequency micro-
operation codes for Mealy
FSM S
18
y
7
y
1
y
4
y
2
y
5
y
6
y
3
0
1
00 01 11 10
*
z
2
z
3
z
1
The system of equations y
1
= ¯ z
1
¯ z
2
z
3
, . . . , y
7
= ¯ z
1
¯ z
2
¯ z
3
can be derived from the
Karnaugh map (Fig.6.13). This system specifies the block BD.
3. Construction of transformed structure table. The table is constructed after the
state encoding stage. Let the states a
m
∈ A be encoded in a trivial way, namely:
K(a
1
) = 0000, . . . , K(a
15
) = 1110. The transformed ST is constructed using
VGSA. It includes the following columns: a
m
, K(a
m
), a
s
, K(a
s
), X
h
, Z
h
, Φ
h
, h.
6.2 Optimization for Block for Decoding of Microoperations 143
Table 6.8 Transformed structure table of PD
1
V
Mealy FSM S
18
a
m
K(a
m
) a
s
K(a
s
) X
h
Z
h
Φ
h
h
a
1
0000 a
2
0001 x
1
z
3
D
4
1
a
4
0011 ¯ x
1
z
2
D
3
D
4
2
a
2
0001 a
3
0010 1 z
2
z
3
D
3
3
a
3
0010 a
5
0100 1 y
0
D
2
4
a
4
0011 a
5
0100 1 y
0
z
1
D
2
5
a
5
0100 a
2
0001 x
2
z
3
D
4
6
a
6
0101 ¯ x
2
x
3
z
1
z
2
D
2
D
4
7
a
12
1011 ¯ x
2
¯ x
3
z
3
D
1
D
2
D
3
8
a
6
0101 a
7
0110 1 z
1
z
3
D
2
D
3
9
a
7
0110 a
8
0111 1 y
0
D
2
D
3
D
4
10
a
8
0111 a
9
1000 1 z
1
D
1
11
a
9
1000 a
10
1001 1 y
0
D
1
D
4
12
a
10
1001 a
11
1010 1 z
2
D
1
D
3
13
a
11
1010 a
1
0000 1 y
0
z
1
– 14
a
12
1011 a
13
1100 1 y
0
z
1
D
1
D
2
15
a
13
1100 a
14
1101 1 z
3
D
1
D
2
D
4
16
a
14
1101 a
15
1110 1 z
2
z
3
D
1
D
2
D
3
17
a
15
1110 a
1
0000 1 y
0
– 18
The column Z
h
includes variables z
r
∈ Z equal to 1 for the code K(y
n
) of mi-
crooperation formed for transition a
m
, a
s
. Besides, this column includes the
variable y
0
. In the discussed example, the transformed ST includes H = 18 rows
(Table 6.8). The column Z
h
is filled in the following way. For example, the mi-
crooperation y
6
is generated for transition from a
6
into a
7
(the row 9). Because
K(y
6
) = 101, then the row 9 of column Z
h
contains the variables z
1
and z
3
. Next,
both y
0
and y
7
are generated for transition from a
7
into a
8
(the row 10). Because
K(y
7
) = 000 (Fig. 6.13), then the row 10 of column Z
h
contains only y
0
. Using
the same approach, all rows of transformed ST (Table 6.8) are filled.
This table is used to derive systems Z(X, T), y
0
(X, T), and Φ(X, T). For
example, the following functions z
1
= F
5
∨F
7
∨F
9
∨F
11
∨F
14
∨F
15
=
¯
T
1
T
3
T
4


¯
T
1
T
2
¯
T
3
¯
T
4
¯ x
2
x
3

¯
T
1
T
2
¯
T
3
¯
T
4
∨T
1
¯
T
2
T
3
; y
0
=F
4
∨F
5
∨F
10
∨F
12
∨F
14
∨F
15
∨ ∨F
18
=
¯
T
1
¯
T
2
T
3
∨T
2
T
3
¯
T
4
∨T
1
¯
T
2
¯
T
4
∨T
1
¯
T
2
T
3
; D
4
=F
1
∨F
2
∨F
6
∨F
7
∨F
8
∨∨F
10
∨F
12
∨F
16
=
¯
T
2
¯
T
3
¯
T
4

¯
T
1
T
2
¯
T
4
∨T
1
¯
T
3
¯
T
4
can be derived from Table 6.8.
Obviously, states a
m
∈ A can be encoded in the optimal way to minimize the
number of macrocells (or LUT elements) in the logic circuit of block BP.
4. Design of FSM logic circuit. Logic circuit of FSM is designed using systems
of equations obtained previously. For our example, the logic circuit is shown in
Fig. 6.14.
In this circuit, the additional block PLD generates signals R
0
(to clear the register
RY) and C
0
(to synchronization of the register RY). The outputs of register RY are
denoted as y
Rn
, because they correspond to registered outputs of microoperations
144 6 FSM Synthesis with Transformation of GSA
Fig. 6.14 Logic circuit of
PD
1
V
Mealy FSM S
18
PLD
BP
1
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
2
3
14
15
6
z
1
RG
D
1
D
2
D
3
D
4
R
C
1
2
3
4
10
11
12
13
14
15
4
16
x
1 1
x
2 2
x
3 3
7
z
2
8
z
3
16
T
1
T
2
T
3
4
5
RG
RY
D
1
D
2
D
3
D
4
D
5
D
6
D
7
R
C
1
2
3
4
5
6
7
18
19
20
y
R1
y
R2
y
R3
y
R4
y
R5
y
R6
Start
Clock
17
9
y
0 21
y
R7
5
17
T
4
PLD
4
1
2
3
1
2
5
6
25
26
R
0
C
0
10
D
1
11
D
2
12
D
3
13
D
4
22
23
24
25
26
PLD
BD
6
1
2
3
1
2
3
4
5
6
7
7
8
18
y
1
19
y
2
20
y
3
21
y
4
22
y
5
23
y
6
24
y
7
y
n
∈ Y. A practical circuit of the register RY , as well as the block of its control,
depends on microchips in use; we do not discuss this step in the book.
The number of inputs for block BP can be decreased, if both an initial GSAand an
equivalent VGSA have the same marks of the states. It is possible due to use of some
method, which is an analogue of the code sharing method used in compositional
microprogram control units [6]. These methods can be found in [1, 5], so we do
not discuss them here. In our book we assume that PD
k
Mealy FSM is synthesized
using the standard marking of the interpreted GSA. To minimize the number of
states for PD
k
Mealy FSM (1 < k < K), it is necessary to find the best distribution
of microoperations y
n
∈Y among the classes of compatible microoperationsY
k
. For
example, there is no changing in the fragment Γ
0
(Fig. 6.15a) after its verticalization,
if PD
2
Mealy FSM is synthesized and y
1
∈Y
1
, y
2
∈Y
2
.
Fig. 6.15 Influence of com-
patibility of microoperations
on the number of states
a)
y
1
y
2
b
3
a
4
a
3
b)
y
1
b
3
a
5
a
3
1
y
2
b
3
a
4
2
But if both microoperations belong to the same class of compatibility (for exam-
ple, if y
1
, y
2
∈Y
1
), then the vertex b
3
is transformed into the vertices b
1
3
and b
2
3
(as
shown in Fig. 6.15b). Obviously, the second case is connected with increase for the
state number of FSM to be designed in comparison with initial P Mealy FSM.
6.3 Synthesis of Multilevel FSM Models 145
6.3 Synthesis of Multilevel FSM Models
Jointed use of previously discussed methods results in multilevel models of Mealy
and Moore FSMs. The multilevel models of Mealy FSM are represented in Table
6.9. In this table, the symbol D
k
informs that the procedure of verticalization was
applied to the initial GSA and the final partition Π
Y
includes k classes(k =1, . . . , K).
Obviously, the value K is determined by characteristics of GSA to be interpreted.
Table 6.9 Multilevel models of Mealy FSM
LA LB LC LD
M
1
M
1
C M
1
L P F Y
. . . Y D
1
M
G
M
G
C M
G
L D
1
.
.
.
.
.
. D
K
D
K
The following numbers of Mealy FSM models with different number of levels
can be derived from Table 6.9:
1. NL
1
= 1 (It is P Mealy FSM).
2. NL
2
=3G+K+2 (The first member of this formula determines the models with
logical condition replacement, the second member corresponds to models with
verticalization of initial GSA, and the third member determines PF and PY Mealy
FSM).
3. NL
3
= 3G∗ (K+2) +K +1 (The first member of this formula determines the
models with logical condition replacement and encoding of collections of micro-
operations, the second member corresponds to PFD Mealy FSM with vertical-
ization of initial GSA, and the third member determines PFY Mealy FSM).
4. NL
4
= 3G∗ (K+1) (This formula determines the number of FSM including the
block BF used for encoding of structure table rows).
Totally, Table 6.9 determines 6GK+12G+2K+4 different models of Mealy FSM.
For FSM with average complexity (G = K = 6) [4], there are 304 different models.
If G=K =8, then the number of models is increased up to 628. A synthesis method
for multilevel model is a collection of methods for designing corresponding models
with less number of levels. Let us discuss an example of the M
2
PFD
2
Mealy FSM
S
19
, represented by a GSA Γ
5
(Fig. 6.16).
For this GSA, it is necessary G = 3 variables for the logical condition replace-
ment. But according to the task, G should be equal 2. Thus, some additional opera-
tor vertices should be introduced into the GSA Γ
5
to replace the logical conditions
x
l
∈ X = {x
1
, . . . , x
7
} by new variables p
g
∈ P = {p
1
, p
2
}. Next, some operator
vertices of the GSA Γ
5
include more, than two microoperations. But according to
146 6 FSM Synthesis with Transformation of GSA
Fig. 6.16 Initial graph-
scheme of algorithmΓ
5
y
2
y
5 y
2
y
3
x
1
1 0
End
Start
y
4
x
2
1 0
x
3
1 0
y
4
x
1
1 0
x
2
1 0
x
3
1 0
y
4
y
4
x
1
1 0
y
4
y
4
y
4
b
1
b
2 b
3
b
4
b
5
b
6
b
7
b
8
b
9
a
2
a
1
a
4
a
1
a
3
a
5
Fig. 6.17 Structural dia-
gram of M
2
PFD
2
Mealy
FSM
BM
Start
Clock
RG
X
Y
2
T
BF
P
2
Ժ
DC
2
Z
1
BP
Z
P
1
Y
1
DC
1
the task, K should be equal 2. Thus, the procedure of verticalization should be ap-
plied for the GSA Γ
5
.The structural diagram of M
2
PFD
2
Mealy FSM is shown in
Fig. 6.17.
In this model, the block BM generates functions
p
1
= p
1
(X, T),
p
2
= p
2
(X, T),
(6.10)
6.3 Synthesis of Multilevel FSM Models 147
Table 6.10 Logical condition replacement for Mealy FSM S
19
a
m
a
1
a
2
a
3
a
4
a
5
a
6
a
7
a
8
a
9
a
10
a
11
a
11
p
1
x
1
– x
3
– – x
4
x
6
– – – – –
p
2
x
2
– – – – x
5
– – x
7
– – –
the block BP generates functions (6.2), the block BF generates functions (6.3) and
(6.4). The block BD consists from two decoders, DC
1
and DC
2
, implementing mi-
crooperations y
n
∈Y
k
, where k = 1, 2:
Y
k
=Y
k
(Z
1
). (6.11)
1. Transformation of initial GSA. To satisfy the condition G = 2, the operator
vertices b
10
and b
11
should be introduced into the initial GSA Γ
5
. It leads to
transformed GSA V(Γ
5
) shown in Fig. 6.18. To satisfy the condition K = 2, it is
necessary to distribute microoperations y
n
∈Y between two classes of compati-
bility, namely Y
1
and Y
2
.
The distribution should be executed in such a way, that transformed GSA in-
cludes minimal possible amount of new operator vertices. There is no any known
algorithm for solution of this problem, because of it let us distribute the mi-
crooperations using some heuristics. Finally, we can get the distribution:Y
1
=
{y
1
, y
3
, y
5
, y
7
} and Y
2
= {y
2
, y
4
, y
6
}. In this case, new vertices b
12
– b
16
are in-
troduced into the transformed GSA V(Γ
5
) (Fig. 6.18).
2. Logical condition replacement. This step is executed using the well-known pro-
cedure and the results are shown in in Table 6.10.
According to the task (determined by the formula of FSM model), the states
should be assigned using the approach of multiplexer encoding. Let us remind
that this approach decreases the parameters of multiplexers (the number of their
control and data inputs) from the block BM. The multiplexer codes for Mealy
FSM S
19
are shown in Fig. 6.19.
Analysis of Fig. 6.19 shows that the logical conditions x
l
∈ X(p
1
) are iden-
tified by state variables T
3
and T
4
, whereas the logical conditions x
l
∈ X(p
2
) are
identified by state variables T
2
and T
3
. The following system can be constructed
using the codes from Fig. 6.19:
p
1
=
¯
T
3
¯
T
4
x
1

¯
T
3
T
4
x
3
∨T
3
¯
T
4
x
4
∨T
3
T
4
x
6
;
p
2
=
¯
T
2
¯
T
3
x
2

¯
T
2
T
3
x
5
∨T
2
¯
T
3
x
7
.
(6.12)
Let us point out that the authors do not know an algorithm of multiplexer state
encoding resulted in the minimal hardware amount for the block BM, so it can
be a subject for further research.
3. Construction of FSM structure table. This step is executed using the standard
approach [3, 4]. In the discussed case, the structure table includes H = 19 rows
(Table 6.11).
148 6 FSM Synthesis with Transformation of GSA
Fig. 6.18 Transformed
GSAV(Γ
5
)
End
Start
x
1
1 0
a
1
-
y
3
y
4
y
1
b
10
b
3
b
4
a
1
a
3
a
4
a
5
x
2
1 0
x
3
1 0
y
6
y
7
b
2
y
5
y
3
b
13
b
14
a
6
y
1
y
2
b
1
a
2
y
3
y
4
b
12
x
4
1 0
-
y
6
y
7
y
3
y
4
b
11
b
6
b
7
a
7
a
10
a
11
x
5
1 0
x
6
1 0
y
1
y
2
b
5
y
5
b
15
y
1
y
2
y
3
y
6
b
8
b
9
a
12
x
7
1 0
y
3
y
4
b
16
a
9
a
8
4. Encoding of structure table rows. Obviously, it is enough R
F
= 5 variables
from the set Z = {z
1
, . . . , z
5
} to encode H =19 rows of the structure table. Let us
encode the rows in a trivial way: K(F
1
) = 00000, . . . , K(F
19
) = 10100.
5. Construction of transformed structure table. This step is reduced to replace-
ment of logical conditions x
l
∈ X by the variables p
1
and p
2
, as well as replace-
ment of columns K(a
s
) - Φ
h
of initial ST by the column Z
h
. As in the case of PF
Mealy FSM, this column contains only the variables z
r
∈ Z equal to 1 in the code
K(F
h
) (h = 1, . . . , 19). The transformed structure table of M
2
PFD
2
Mealy FSM
S
19
includes 19 rows too (Table 6.12).
6.3 Synthesis of Multilevel FSM Models 149
Fig. 6.19 Multiplexer state
codes of Mealy FSM S
19
00
01
00 01 11 10
4 3
T T
2 1
T T
11
10
Table 6.11 Structure table of M
2
PFD
2
Mealy FSM S
19
a
m
K(a
m
) a
s
K(a
s
) X
h
Y
h
Φ
h
h
a
1
0000 a
2
1000 x
1
x
2
y
1
y
2
D
1
1
a
6
0010 x
1
¯ x
2
y
6
y
7
D
3
2
a
3
0001 ¯ x
1
– D
4
3
a
2
1000 a
6
0010 1 y
3
y
4
D
3
4
a
3
0001 a
4
1001 x
3
y
1
D
1
D
4
5
a
5
1010 ¯ x
3
y
3
y
4
D
1
D
3
6
a
4
1001 a
6
0010 1 y
3
D
3
7
a
5
1010 a
8
1011 1 y
5
D
1
D
3
D
4
8
a
6
0010 a
2
1000 x
4
x
5
y
1
y
2
D
1
9
a
9
0100 x
4
¯ x
5
y
1
y
2
D
2
10
a
7
0011 ¯ x
4
– D
3
D
4
11
a
7
0011 a
10
1100 x
6
y
3
y
4
D
1
D
2
12
a
11
1101 ¯ x
6
y
6
y
7
D
1
D
2
D
4
13
a
8
1011 a
11
1101 1 y
6
y
7
D
1
D
2
D
4
14
a
9
0100 a
1
0000 x
7
y
3
y
6
– 15
a
12
1110 ¯ x
7
y
1
y
2
D
1
D
2
D
3
16
a
10
1100 a
9
0100 1 y
5
D
2
17
a
11
1101 a
12
1110 1 y
1
y
2
D
1
D
2
D
3
18
a
12
1110 a
1
0000 1 y
3
y
4
– 19
This table is used to derive system (6.2). For example, the following functions
z
1
=F
17
∨F
18
∨F
19
=T
1
T
2
, z
2
=F
9
∨. . . ∨F
16
=
¯
T
1
T
3
∨T
3
T
4

¯
T
1
T
2
can be derived
from Table 6.12 (after minimization).
6. Encoding of the classes of compatible microoperations. This step is executed
using the rules applied for PDMealy FSM. Obviously, it is enough three variables
(z
6
, z
7
, z
8
) for encoding of the microoperations y
n
∈Y
1
, whereas the microoper-
ations y
n
∈Y
2
are encoded using only two variables (z
9
, z
10
).
Therefore, the set of encoding variables Z
1
= {z
6
, . . . , z
10
} is constructed. Let
zero codes be used to represent a case when microoperations from a particular
class (Y
1
, or Y
2
, or both) are absent in some collection of microoperations. Let
us encode microoperations y
n
∈Y as it is shown in Table 6.13.
150 6 FSM Synthesis with Transformation of GSA
Table 6.12 Transformed structure table of M
2
PFD
2
Mealy FSM S
19
a
m
K(a
m
) P
h
Z
h
h
a
1
0000 p
1
p
2
– 1
p
1
¯ p
2
z
5
2
¯ p
1
z
4
3
a
2
1000 1 z
4
z
5
4
a
3
0001 p
1
z
3
5
¯ p
1
z
3
z
5
6
a
4
1001 1 z
3
z
4
7
a
5
1010 1 z
3
z
4
z
5
8
a
6
0010 p
1
p
2
z
2
9
p
1
¯ p
2
z
2
z
5
10
¯ p
1
z
2
z
4
11
a
7
0011 p
1
z
2
z
4
z
5
12
¯ p
1
z
2
z
3
13
a
8
1011 1 z
2
z
3
z
5
14
a
9
0100 p
2
z
2
z
3
z
4
15
¯ p
2
z
2
z
3
z
4
z
5
16
a
10
1100 1 z
1
17
a
11
1101 1 z
1
z
5
18
a
12
1110 1 z
1
z
4
19
Table 6.13 Transformed structure table of M
2
PFD
2
Mealy FSM S
19
Y
1
K(y
n
) Y
2
K(y
n
)
/ 0 0 0 0 / 0 0 0
y
1
0 0 1 y
2
0 1
y
3
0 1 0 y
4
1 0
y
5
0 1 1 y
6
1 1
y
7
1 0 0 – –
This table defines unambiguously the block BD, for example, y
1
= ¯ z
6
¯ z
7
z
8
,
y
2
= ¯ z
9
z
10
and so on. Functions (6.11) can be minimized using ”don’t care” input
assignments. For example, the function y
7
can be minimized up to the term y
7
=
z
6
¯ z
8
taking into account the unused input assignment 110.
7. Specification of block BF. This block is specified by the table with columns
K(F
h
), Z
h
, Φ
h
, h. The column K(F
h
) contains code of the row h, the column
Φ
h
includes input memory functions D
r
∈ Φ from the row h of initial ST. To
fill the column Z
h
, it is necessary to take the codes of microoperations y
n
∈ Y
k
from corresponding table and to write in the row h of column Z
h
the variables
z
r
∈ Z
1
corresponding to the bits equal to 1 in the codes of microoperations.
Obviously, the table specifying the block BF includes H rows (Table 6.14 for our
6.3 Synthesis of Multilevel FSM Models 151
example). Embedded memory blocks are the best elements for implementing the
logic circuit of block BF.
8. Implementation of FSM logic circuit. This step is reduced to implementation
of the circuit on the base of tables and systems of equations obtained from the
previous steps. For the M
2
PFD
2
Mealy FSM S
19
, the logic circuit is shown in
Fig. 6.20.
Acting in the same way, the logic circuit can be designed for any model from
Table 6.9. For Moore FSM, there is no sense in verticalization. Because of it,
Table 6.14 Specification of block BF of M
2
PFD
2
Mealy FSM S
19
K(F
h
) Z
h
Φ
h
h K(F
h
) Z
h
Φ
h
h
00000 z
8
z
10
D
1
1 01010 – D
3
D
4
11
00001 z
6
z
9
z
10
D
3
2 01011 z
7
z
9
D
1
D
2
12
00010 – D
4
3 01100 z
6
z
9
z
10
D
1
D
2
D
4
13
00011 z
7
z
9
D
3
4 01101 z
6
z
9
z
10
D
1
D
2
D
4
14
00100 z
8
D
1
D
4
5 01110 z
7
z
9
z
10
– 15
00101 z
7
z
9
D
1
D
3
6 01111 z
8
z
10
D
1
D
2
D
3
16
00110 z
7
D
3
7 10000 z
7
z
8
D
2
17
00111 z
7
z
8
D
1
D
3
D
4
8 10001 z
8
z
10
D
1
D
2
D
3
18
01000 z
8
z
10
D
1
9 10010 z
7
z
9
– 19
01001 z
8
z
10
D
2
10 – – – 20
multilevel models of Moore FSM are still represented by Table 6.2. There is a very
important particular case with G = 1. In this case all model blocks can be imple-
mented using only standard library cells, because the systems of equations for FSM
logic circuit belong to classes of multiplexer and regular functions [7]. Let us dis-
cuss an example of the M
1
PY Moore FSM S
20
logic circuit design, where the FSM
is specified by its structure table (Table 6.15). For the Moore FSM S
20
, all transi-
tions depend on G = 1 variable, it determines the set P = {p
1
}. Thus, there is no
need in distribution of logical conditions. The following equation can be found from
Table. 6.15:
p
1
=
¯
T
1
¯
T
2
x
1

¯
T
1
T
2
x
2
∨T
1
T
2
x
3
. (6.13)
If the logic circuit of block BY is implemented with some macrocells, then the cor-
responding equations are derived from Table 6.15. But it is enough to use their truth
table, if the logic circuit is implemented with embedded memory blocks BRAM
(Table 6.16 in the example).
To specify the block BP, it is necessary to construct the table with columns K(a
m
),
p
1
, Φ
h
, h, having H = 2M rows. Let a transition from state a
m
∈ A be executed
unconditionally and let this transition be represented by the row h of the initial
structure table. In this case the row is duplicated for both p
1
= 0 and p
1
= 1. Af-
ter such duplication, the transition does not depend on values of logical conditions
152 6 FSM Synthesis with Transformation of GSA
PLD
10
1
2
3
4
5
6
1
2
3
4
5
11
26
27
28
12
z
1
RG
D
1
D
2
D
3
D
4
R
C
1
2
3
4
22
23
24
25
25
27
8
28
x
1 1
x
2 2
x
3 3
13
z
2
14
z
3
T
1
T
2
T
3
8
9
DC
1
2
3
0
1
2
3
4
5
6
7
17
18
19
y
1
y
3
y
5
y
7
Start
Clock
15
z
4
BRAM
12
1
2
3
4
5
1
2
3
4
5
6
7
8
9
13
14
17
z
6
18
z
7
19
z
8
20
z
9
21
z
10
22
D
1
15
MX
1
0
1
2
3
1
2
4
3
28
10
P
1
29
MX
2
0
1
2
3
1
2
5
7
27
11
P
2
28
x
4 4
x
5 5
x
6 6
x
7 7
29
T
4
9
29
16
z
5
16
23
D
2
24
D
3
25
D
4
DC
1
2
0
1
2
3
20
21
y
2
y
4
y
6
6
Fig. 6.20 Logic circuit of M
2
PFD
2
Mealy FSM S
19
Table 6.15 Structure table of Moore FSM S
20
a
m
K(a
m
) a
s
K(a
s
) X
h
Φ
h
h
a
1
(–) 00 a
2
01 x
1
D
2
1
a
3
10 ¯ x
1
D
1
2
a
2
(y
1
y
2
) 01 a
2
01 x
2
D
2
3
a
4
11 ¯ x
2
D
1
D
2
4
a
3
(y
2
y
3
y
4
) 10 a
1
00 1 – 5
a
4
(y
1
y
3
y
5
) 11 a
3
10 x
3
D
1
6
a
2
01 ¯ x
3
D
2
7
a
7
(y
3
y
6
) 11 a
1
000 1 – 8
Table 6.16 Specification of block BY for Moore FSMS
20
T
1
T
2
y
1
y
2
y
3
y
4
y
5
0 0 0 0 0 0 0
0 1 1 1 0 0 0
1 0 0 1 1 1 0
1 1 1 0 1 0 1
References 153
x
l
∈ X. For the Moore FSM S
20
, the transitions are duplicated for the rows 5 and 6
of Table 6.17.
For an FSM with G = 1, the vector K(a
m
), p
1
is treated as a memory address,
where a word content is taken from the corresponding row of initial ST. For the
Moore FSM S
20
, the second row of Table 6.17 corresponds to the first row of Table
6.15, the first row of Table 6.17 corresponds to the second row of Table 6.15, rows 5
and 6 correspond to the row 5 of the initial Moore FSM structure table (Table 6.15).
The logic circuit of M
1
PY Moore FSM (Fig. 6.21 in the discussed case) is con-
structed in a trivial way. The circuit of block BM is determined by equation (6.13);
the logic circuit of block BP is implemented using BRAMs and it is determined by
Table 6.17; the logic circuit of block BY is implemented using BRAMs too and it is
determined by Table 6.16.
Table 6.17 Specification of block BP for M
1
PY Moore FSM S
20
K(a
m
) p
1
Φ
h
h
00 0 D
1
1
00 1 D
2
2
01 0 D
1
D
2
3
01 1 D
2
4
10 0 – 5
10 1 – 6
11 0 D
2
7
11 1 D
1
8
Fig. 6.21 Logic circuit of
M
1
PY Moore FSM S
20
RG
D
1
D
2
R
C
1
2
7
8
4
5
9
10
x
1 1
x
2 2
x
3 3
T
1
T
2
BRAM
1
2
1
2
3
4
5
9
10
y
2
y
3
y
4
y
5
Start
Clock
BRAM
9
1
2
3
1
2
10
6
7
D
1
8
D
2
MX
1
0
1
2
3
1
2
2
3
9
10
P
1
10 4
5
y
1
References
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& Test Workshop, EWDTW 2005. Kharkov National University of Radioelectronics,
Kharkov (2005)
2. Altera Corporation Webpage, http://www.altera.com
154 6 FSM Synthesis with Transformation of GSA
3. Baranov, S.: Logic and System Design of Digital Systems. TUT Press, Tallinn (2008)
4. Baranov, S.I.: Logic Synthesis of Control Automata. Kluwer Academic Publishers,
Dordrecht (1994)
5. Barkalov, A., Bukowiec, A.: Synthesis of mealy finite states machines for interpretation
of verticalized flow-charts. Informatyka Teoretyczna i Stosowana 5(8), 39–51 (2005)
6. Barkalov, A., Titarenko, L.: Logic Synthesis for Compositional Microprogram Control
Units. Springer, Berlin (2008)
7. Barkalov, A., Titarenko, L.: Synthesis of Operational and Control Automata. UNITECH,
Donetsk (2009)
8. Barkalov, A., W˛ egrzyn, M.: Design of Control Units With Programmable Logic. Univer-
sity of Zielona Góra Press, Zielona Góra (2006)
9. Minns, P., Elliot, I.: FSM-based digital design using Verilog HDL. John Wiley and Sons,
Chichester (2008)
10. Xilinx Corporation Webpage, http://www.xilinx.com
Chapter 7
FSM Synthesis with Object Code
Transformation
Abstract. The chapter is devoted to original optimization methods oriented on de-
crease of the number of outputs for FSM block generating input memory functions.
These methods are based on the object code transformation. The FSM objects are
either states or collections of microoperations. Sometimes, some additional identi-
fiers are needed for one-to-one representation of different objects. Such optimiza-
tion methods are discussed for both Mealy and Moore finite state machines. At
last, the multilevel models of FSM with object code transformation, logical condi-
tion replacement and encoding of collections of microoperations are discussed. This
chapter is written together with employee of "Nokia-Siemens Network" Alexander
Barkalov (Ukraine).
7.1 Principle of Object Code Transformation
As it was mentioned before, the hardware reduction for FSM logic circuit is con-
nected with the structural decomposition, which in turn is connected with increase
for the number of levels in the FSM model. To optimize the hardware amount in
block BY, it is necessary to generate some additional variables for encoding of mi-
crooperations (or collections of microoperations). The methods discussed in this
Chapter are taken from [2–6]. These methods are based on one-to-one match among
collections of microoperations and states. Let us name as objects of FSM its in-
ternal states a
m
∈ A and collections of microoperations Y
t
⊆ Y. Let us point out
that states and collections of microoperations are heterogeneous objects respectively
each other, whereas different states, for example, are homogenous respectively each
other. The optimization methods discussed in this Chapter are based on identifi-
cation of one-to-one match among heterogeneous objects. If this match is found,
then the block BP generates only codes for one object (which is a primary object),
while a special code transformer generates the codes of another object (which is a
secondary object).
Let us find a one-to-one match A → Yamong the states as primary objects and
the microoperations as secondary objects. In this case, the block BP generates input
A. Barkalov and L. Titarenko: Logic Synthesis for FSM-Based Control Units, LNEE 53, pp. 155–191.
springerlink.com c Springer-Verlag Berlin Heidelberg 2009
156 7 FSM Synthesis with Object Code Transformation
Fig. 7.1 Structural diagram
of Mealy FSM1
Start
Clock
RG
X
Z
BP
Ժ
TSM
T Y
BY
memory functions T
r
∈ T = {T
1
, . . . , T
R
} to encode the states, whereas a special
state code transformer block TSM generates variables z
r
∈ Z used for encoding
of collections of microoperations. The structural diagram of Mealy FSM based on
this principle is shown in Fig. 7.1. Let the symbol PC
A
Y stand for this model if
collections of microoperations are encoded, whereas the symbol PC
A
D stands for
encoding of the classes of compatible microoperations. Let us name such models as
FSM1.
Let us find a one-to-one match Y → A among the microoperations as primary
objects and the states as secondary objects. In this case, the block BP generates
variables z
r
∈ Z, whereas a special microoperation code transformer block TMS
generates input memory functions T
r
∈ T. This approach results in the models of
FSM2, denoted as PC
Y
Y (if collections of microoperations are encoded) or as PC
Y
D
(if classes of compatible microoperations are encoded). Their structural diagram is
shown in Fig. 7.2.
Fig. 7.2 Structural diagram
of Mealy FSM2
Start
Clock
RG
X
Z BP
Ժ
TMS
T
Y
BY
These models correspond to cases when an FSM has the same numbers of states
and collections of microoperations. If this condition is violated, then some addi-
tional identifiers should be used belonging to a set of identifiers V. In common case,
the block BP generates variables T and V (Fig. 7.3) or variables Z and V (Fig. 7.4).
All these variables are the outputs of the register RG.
Thus, in common case the number of bits in the register RG for Mealy FSM
with object code transformation exceeds this number for equivalent PY or PD
Mealy FSM. Obviously, the proposed approach can be applied iff the total hard-
ware amount for blocks BP and TSM (TMS) is less, than the hardware amount for
block BP of PY (PD) Mealy FSM. The same approach can be applied for Moore
FSM. Let us point out that only application of the proposed approaches allows the
economical implementation of PD Moore FSM.
7.2 Logic Synthesis for Mealy FSM with Object Code Transformation 157
Fig. 7.3 Refined structural
diagram of Mealy FSM1
Start
Clock
RG
X
Z
BP
Ժ
TMS
T
Y
BY
V
Fig. 7.4 Refined structural
diagram of Mealy FSM2
Start
Clock
RG
X
Z
BP
Ժ
TMS
T
Y
BY
V
7.2 Logic Synthesis for Mealy FSM with Object Code
Transformation
Let the Mealy FSM S
21
be specified by its structure table (Table 7.1). Consider logic
synthesis for models of PC
A
Y, PC
A
D, PC
Y
Y and PC
Y
D Mealy FSM, based on the
Mealy FSM S
21
.
The following procedure is proposed for logic synthesis Mealy FSM1:
1. One-to-one identification of collections of microoperations. Let T(a
s
) be a
set of collections of microoperations generated under transitions into the set
a
s
∈ A, where n
s
= |Y(a
s
)|. In this case, it is necessary n
s
identifiers for one-
to-one identifications of collections Y
t
⊆ Y(a
s
). In common case, it is enough
K = max(n
1
, . . . , n
M
) identifiers for one-to-one identification of all collections
Y
t
⊆Y, these identifiers form the set I = {I
1
, . . . , I
K
}. Let us encode each iden-
tifier I
k
∈ I by a binary code K(I
k
) having R
V
= log
2
K bits. Let us use the
variables v
r
∈V = {v
1
, . . . , v
RV
} for encoding of the identifiers.
Let each collection Y
t
∈Y(a
s
) correspond to the pair β
st
=I
k
, a
s
, where I
k

I. Of course, an identifier I
k
∈Ishould be different for different collections. In this
case, a code K(I
k
) of set Y
t
∈Y(a
s
) is determined by the following concatenation
K(Y
t
) = K(I
k
) ∗ K(a
s
). (7.1)
In (7.1) the symbol ∗ stands for concatenation of these codes.
2. Encoding of collections of microoperations. If the method of maximal encod-
ing of collections of microoperations is applied, then let a collection Y
t
⊆ Y be
determined by a binary code C(Y
t
) having Q = log
2
T
0
bits, where T
0
is the
number of collections. If the method of encoding of the classes of compatible
microoperations is used, then any collection Y
t
is represented as the following
vector [4]:
Y
t
=

y
1
t
, y
2
t
, . . . , y
J
t

. (7.2)
158 7 FSM Synthesis with Object Code Transformation
Table 7.1 Structure table of Mealy FSM S
21
a
m
K(a
m
) a
s
K(a
s
) X
h
Y
h
Φ
h
h
a
1
000 a
2
010 x
1
y
1
y
2
D
1
D
2
1
a
3
011 ¯ x
1
y
3
D
3
2
a
2
010 a
2
010 x
2
y
1
y
2
D
2
3
a
3
011 ¯ x
2
x
3
D
1
D
2
4
a
4
100 ¯ x
2
¯ x
3
y
1
y
2
D
1
D
3
5
a
3
011 a
4
100 x
1
y
2
y
5
D
1
6
a
5
101 ¯ x
1
y
6
D
1
D
3
7
a
4
100 a
5
101 1 y
3
y
7
D
1
D
3
8
a
5
101 a
2
010 x
2
x
3
y
1
y
2
D
2
9
a
3
011 x
2
¯ x
3
y
3
D
2
D
3
10
a
5
101 ¯ x
2
x
4
y
3
y
7
D
1
D
3
11
a
1
000 ¯ x
2
¯ x
4
– – 12
In (7.2), the symbol J stands for the number of the classes of compatible mi-
crooperations, whereas the symbol y
j
t
denotes microoperation y
n
∈Y
t
, belonged
to the class j of compatible microoperations ( j = 1, . . . , J). Therefore, a code of
collection Y
t
is represented as a concatenation of microoperation codes.
3. Construction of transformed structure table. For FSM1, the transformed ST
is used to generate input memory functions Φ and additional functions of iden-
tification V. These systems depend on the same terms and are represented as the
following:
φ
r
=
H

h=1
C
rh
A
h
m
X
h
(r = 1, . . . , R), (7.3)
v
r
=
H

h=1
C
rh
A
h
m
X
h
(r = 1, . . . , R). (7.4)
Obviously, to represent system (7.4) the column Y
h
of initial ST should be re-
placed by columns: I
h
is an identifier of the collection Y
h
from pair β
s,h
; K(I
h
) is
a code of identifier I
k
; V
h
are variables v
r
∈V, equal to 1 in the code K(I
h
).
4. Specification of block TSM. The block TSM generates variables z
q
∈ Z repre-
sented as the following functions
Z = Z(V, T). (7.5)
To construct system (7.5), it is necessary to built a table with columns a
s
, K(a
s
),
I
k
, K(I
k
), Y
h
, Z
h
, h. The table includes all pairs β
t,s
, determined the collection Y
1
,
next all pairs determined the collection Y
2
, and so on. The number of their rows
(H
0
) is determined as a result of summation for numbers n
s
(S = 1, . . . , H). The
column Z
h
of the table includes variables z
q
∈ Z, equal to 1 in the code K(Y
h
).
The system (7.5) can be represented as the following:
7.2 Logic Synthesis for Mealy FSM with Object Code Transformation 159
z
q
=
H
0

h=1
C
qh
X
h
A
h
s
(q = 1, . . . , Q). (7.6)
In (7.6), the symbol V
h
stands for conjunction of variables v
r
∈V, corresponded
to the code K(I
k
) of identifier from the row h of this table.
5. Specification of block for generation microoperations. This step is executed
in the same manner, as it is done for PY or PD Mealy FSM.
6. Synthesis of FSM logic circuit. For the Mealy FSM1, there is no need in keep-
ing codes of identifiers in the register RG. Therefore, these FSM models should
be refined. The structural diagram of PC
A
Y Mealy FSM is shown in Fig. 7.5,
whereas Fig. 7.6 shows the structural diagram of PC
A
D Mealy FSM. In both
cases, the block BP implements functions (7.3) – (7.4), the block TSM generates
functions (7.6), blocks BY or BD implements microoperations Y =Y(Z).
Fig. 7.5 Structural diagram
of PC
A
Y Mealy FSM
Start
Clock
RG
X
Z
BP
Ժ
TSM
T
Y
BY
V
Fig. 7.6 Structural diagram
of PC
A
D Mealy FSM
Start
Clock
RG
X
Z
BP
Ժ
TSM
T
Y
BD
V
In Table 7.1, there are the following collections of microoperations Y
1
= / 0,
Y
2
= {y
1
, y
2
}, Y
3
= {y
3
}, Y
4
= {y
4
}, Y
5
= {y
5
}, Y
6
= {y
6
}, Y
7
= {y
7
}, T
0
= 7.
Let us consider an example of logic synthesis for the PC
A
Y Mealy FSM S
21
. The
following sets can be derived from Table 7.1:Y(a
1
) = {Y
1
},Y(a
2
) = {Y
2
}, Y(a
3
) =
{Y
3
,Y
4
}, Y(a
4
) = {Y
2
,Y
5
}, Y(a
5
) = {Y
6
,Y
7
}. It gives the value K = 2. Thus, it is
enough two identifiers creating the set I ={I
1
, I
2
}; they can be encoded using R
V
=1
variables from the set V = {v
1
}. Let K(I
1
) = 0, K(I
2
) = 1, then the following codes
can be obtained using formula (7.1): K(Y
1
) = ∗000, K(Y
1
2
) = ∗010, K(Y
2
2
) = 0100,
K(Y
3
) =0011, K(Y
4
) =1011, K(Y
5
) =1100, K(Y
6
) =0101, and K(Y
7
) =1101. This
example shows that there are m
t
different codes determined a collection Y
t
⊆ Y if
this collection belongs to m
t
different sets Y(a
s
). For example, for the collection
Y
2
∈ Y(a
2
) ∩Y(a
1
) we have m
2
= 2, thus the collection Y
2
corresponds to codes
K(Y
1
2
) and K(Y
2
2
).
There are T
0
= 7 different collections, thus Q = 3 and Z = {z
1
, z
2
, z
3
}. Let the
collections Y
t
⊆ Y be encoded in the following way: K(Y
1
) = 000,
160 7 FSM Synthesis with Object Code Transformation
Table 7.2 Transformed structure table of PC
A
Y Mealy FSM S
21
a
m
K(a
m
) a
s
K(a
s
) X
h
I
h
K(I
k
) V
h
Φ
h
h
a
1
000 a
2
010 x
1
– – – D
1
D
2
1
a
3
011 ¯ x
1
I
1
0 – D
3
2
a
2
010 a
2
010 x
2
– – – D
2
3
a
3
011 ¯ x
2
x
3
I
2
1 v
1
D
2
4
a
4
100 ¯ x
2
¯ x
3
I
1
0 – D
1
D
3
5
a
3
011 a
4
100 x
1
I
2
1 v
1
D
1
6
a
5
101 ¯ x
1
I
1
0 – D
1
D
3
7
a
4
100 a
5
101 1 I
2
1 v
1
D
1
D
3
8
a
5
101 a
2
010 x
2
x
3
– – – D
2
9
a
3
011 x
2
¯ x
3
I
1
0 – D
2
D
3
10
a
5
101 ¯ x
2
x
4
I
2
1 v
1
D
1
D
3
11
a
1
000 ¯ x
2
¯ x
4
– – – – 12
K(Y
2
) = 001, . . . , K(Y
7
) = 110. The transformed structure table (Table 7.2) should
be constructed to find functions (7.3) – (7.4).
If the condition n
s
=1 takes place for some collection Y
t
∈Y(a
s
), then there is no
need in identifier code for this collection. This situation is marked as the symbol ”–”
in the corresponding row of transformed structure table. As it was mentioned, we
can derive systems (7.3) – (7.4) from Table 7.2. For example, the following SOPs
can be found: v
1
=F
4
∨F
5
∨F
8
∨F
11
=A
2
¯ x
2
x
3
∨A
3
x
4
∨. . . =
¯
T
1
T
2
¯
T
3
¯ x
2
x
3

¯
T
1
T
2
T
3
x
4

. . . , D
2
= F
2
∨F
3
∨F
4
∨F
9
∨F
10
= A
1
¯ x
1
∨A
2
x
2
∨. . . =
¯
T
2
¯
T
3
x
2

¯
T
1
T
2
¯
T
3
x
2
. . .. Both
systems are irregular, thus they are implemented using some macrocells.
Table 7.3 specifies the block TSM, it includes H
0
=8 rows. This number is equal
to the outcome of summation for the numbers n
s
(S = 1, . . . , 5). System (7.6) is
irregular and it is implemented using macrocells. For example, the SOP z
1
= F
6

F
7
∨F
8
= A
4
v
1
∨A
5
¯ v
1
= T
1
¯
T
2
¯
T
3
v
1
∨T
1
¯
T
2
T
3
¯ v
1
∨T
1
T
2
T
3
¯ v
1
∨T
1
¯
T
2
T
3
v
1
can be derived
from the table specified the block TSM in our example.
The block BY is specified by the table of microoperations. For the PC
A
Y Mealy
FSM S
21
, this table includes T
0
= 8 rows (Table 7.4). Let us point out that codes
C(Y
t
) are used as codes of collections Y
t
.
The logic circuit of PC
A
Y Mealy FSM S
21
is shown in Fig. 7.7. In this circuit,
systems (7.3) and (7.4) are implemented using some macrocells creating the block
BP; system(7.6) is implemented using some macrocells creating the block TSM; the
system of microoperations Y(Z) is implemented using embedded memory blocks
PROM creating the block BY.
Let us consider an example of the logic synthesis for the PC
A
D Mealy FSM
S
21
. Obviously, the outcome of one-to-one identification is the same for equivalent
PC
A
Y and PC
A
D Mealy FSM. To encode the collections of microoperations, it is
necessary to find the partition Π
Y
of the set of microoperations Y by the classes
of pseudoequivalent microoperations [48]. For the FSM S
21
, the following partition
7.2 Logic Synthesis for Mealy FSM with Object Code Transformation 161
Table 7.3 Specification of block TSM of PC
A
Y Mealy FSM S
21
a
s
K(a
s
) I
h
K(I
k
) Y
h
Z
h
h
a
1
000 – – Y
1
– 1
a
2
010 – – Y
2
z
3
2
a
3
011 I
1
0 Y
3
z
2
3
a
3
011 I
2
1 Y
4
z
2
z
3
4
a
4
100 I
1
0 Y
2
z
3
5
a
4
100 I
2
1 Y
5
z
1
6
a
5
101 I
1
0 Y
6
z
1
z
3
7
a
5
101 I
2
1 Y
7
z
1
z
2
8
Table 7.4 Table of microoperations for PC
A
Y Mealy FSM S
21
Y
t
C(Y
t
) y
1
y
2
y
3
y
4
y
5
y
6
y
7
Y
1
000 0 0 0 0 0 0 0
Y
2
001 1 1 0 0 0 0 0
Y
3
010 0 0 1 0 0 0 0
Y
4
011 0 0 0 1 0 0 0
Y
5
100 0 1 0 0 1 0 0
Y
6
101 0 0 0 0 0 1 0
Y
7
110 0 0 1 0 0 0 1
Fig. 7.7 Logic circuit of
PC
A
Y Mealy FSM S
21
PAL
1
1
2
3
4
5
6
7
1
2
3
4
2
3
4
5
10
D
1
RG
D
1
D
2
D
3
R
C
1
2
3
11
12
13
8
5
6
9
7
x
1 1
x
2 2
x
3 3
11
D
2 12
D
3
6
T
1
T
2
T
3
4
6
7
x
4
5
T
1
T
2
PAL
1
2
3
1
2
3
4
5
6
7
14
15
16
y
1
y
2
y
3
y
4
y
5
y
6
8
Start
Clock 9
T
3
7
13
y
7
PAL
5
1
2
3
4
1
2
3
6
7
10
14
15
v
1
D
1
D
2
v
1
16
Π
Y
= {Y
1
,Y
2
} with two classes can be found, where Y
1
= {y
1
, y
3
, y
4
, y
5
}, Y
2
=
{y
2
, y
6
, y
7
}. It is enough Q
1
= 3 variables to encode the microoperations y
n
∈ Y
1
,
and Q
2
= 2 variables for the microoperations y
n
∈ Y
2
. It means that there is the
set Z = {z
1
, . . . , z
5
}, its cardinality is found as Q = Q
1
+Q
2
= 5. Let us encode
microoperations y
n
∈Y in the way shown in Table 7.5. It leads to the codes C(Y
t
) of
collections Y
t
∈Y shown in Table 7.6. Let us point out that if some microoperation
y
j
n
/ ∈Y
t
, then the field j of code C(Y
t
) contains only zeros.
The transformed structure table of PC
A
D Mealy FSM S
21
is identical to the cor-
responding table of PC
A
Y Mealy FSM S
21
(Table 7.2). The table specifying the
162 7 FSM Synthesis with Object Code Transformation
Table 7.5 Codes of microoperations for PC
A
YMealy FSM S
21
Y
1
K(y
1
n
) Y
2
K(y
2
n
)
z
1
z
2
z
3
z
4
z
5
y
1
0 0 1 y
2
0 1
y
3
0 1 0 y
6
1 0
y
4
0 1 1 y
7
1 1
y
5
1 0 0 – –
Table 7.6 Codes of collections of microoperations for PC
A
D Mealy FSM S
21
t Y
1
C(Y
t
) t Y
2
C(Y
t
)
1 / 0 0 0 0 0 0 5 y
2
y
5
1 0 0 0 1
2 y
1
y
2
0 0 1 0 1 6 y
6
0 0 0 1 0
3 y
3
0 1 0 0 0 7 y
3
y
7
0 1 0 1 1
4 y
4
0 1 1 0 0
Table 7.7 Specification of block TSM for PC
A
DMealy FSM S
21
a
s
K(a
s
) I
h
K(I
k
) Y
h
Z
h
h
a
1
000 – – Y
1
– 1
a
2
010 – – Y
2
z
3
z
5
2
a
3
011 I
1
0 Y
3
z
2
3
a
3
011 I
2
1 Y
4
z
2
z
3
4
a
4
100 I
1
0 Y
2
z
3
z
5
5
a
4
100 I
2
1 Y
5
z
1
z
5
6
a
5
101 I
1
0 Y
6
z
1
z
4
7
a
5
101 I
2
1 Y
7
z
1
z
4
z
5
8
block TSM for both models is constructed in the same way. As a rule, this table for
PC
A
D Mealy FSM includes more variables z
r
∈ Z (Table 7.7 in our example), than
its counterpart for PC
A
Y Mealy FSM.
There is no need in a table specifying microoperations, because Table 7.5 con-
tains inputs and outputs for decoders of the block BD. The logic circuit of PC
A
D
Mealy FSM S
21
is shown in Fig. 7.8.
The following procedure is proposed to design a Mealy FSM2:
1. One-to-one identification of states. Let A(Y
t
) be a set of states, such that a
collection Y
t
⊆Y is generated under some transitions in these states, and let m
t
=
|A(Y
t
)|. In this case, it is enough m
t
identifiers for one-to-one identifications of the
states a
m
∈ A(Y
t
). It is necessary K = max(m
1
, . . . , m
T
) variables for one-to-one
identification of the states a
m
∈ A, let these identifiers form a set I. Let us encode
an identifier I
k
∈ I by a binary code K(I
K
) and let us construct a set of variables
7.2 Logic Synthesis for Mealy FSM with Object Code Transformation 163
Fig. 7.8 Logic circuit of
PC
A
D Mealy FSM S
21
PAL
1
1
2
3
4
5
6
7
1
2
3
4
2
3
4
5
10
D
1
RG
D
1
D
2
D
3
R
C
1
2
3
11
12
13
8
5
6
9
7
x
1 1
x
2 2
x
3 3
11
D
2 12
D
3
6
T
1
T
2
T
3
4
6
7
x
4
5
T
1
T
2
PAL
1
2
3
0
1
2
3
4
5
6
7
14
15
16
y
1
y
3
y
4
y
5
8
Start
Clock 9
T
3
7
13
PAL
10
1
2
3
4
1
2
3
4
5
11
12
13
14
15
v
1
z
2
z
3
z
1
16
PAL
17
1
2
0
1
2
3
18
y
2
y
6
y
7
17
z
4
z
5 18
V ={v
1
, . . . , v
R1
} used for encoding of identifiers, where R
1
=log
2
K. Let each
state a
s
∈ A(Y
t
) correspond to a pair α
t,s
= I
k
,Y
t
, then the code for state a
s
is
determined by the following concatenation:
C(a
s
) = K(Y
t
) ∗ K(I
k
). (7.7)
2. Encoding of collections of microoperations. This step is executed using the
approach discussed before.
3. Construction of transformed structure table. This table is used to derive func-
tions (7.4) and Z = Z(T, X). To construct it, the columns a
s
, K(a
s
), Φ
h
are elim-
inated from the initial structure table, in the same time the column Y
h
is replaced
by columns V
h
and Z
h
. The column Z
h
contains variables z
q
∈ Z equal to 1 in the
code K(Y
h
). The system Z includes the following equations:
z
q
=
H

h=1
C
qh
A
h
m
X
h
(q = 1, . . . , Q). (7.8)
4. Specification of code transformer. The code transformer TMS generates
functions
Φ =Φ(V, Z). (7.9)
This system can be specified by a table with the following columns: Y
t
, K(Y
t
), I
k
,
K(I
k
), a
s
, K(a
s
), Φ
h
, h. The table includes all pairs I
k
,Y
t
for the state a
1
, next,
all pairs for a
2
, and so on. The number of rows H
0
in this table is determined
as a result of summation for the numbers m
t
(t = 1, . . . , T). The system of input
memory functions is represented as the following one:
φ
r
=
H
0

h=1
C
rh
V
h
Z
h
(r = 1, . . . , R). (7.10)
164 7 FSM Synthesis with Object Code Transformation
Fig. 7.9 Structural diagram
of PC
A
Y Mealy FSM
Start
Clock
RG
X
Z
BP
Ժ
TMS
V
Y
BY
T
Fig. 7.10 Structural dia-
gram of PC
A
D Mealy FSM
Start
Clock
RG
X
Z
BP
Ժ
TMS
V
Y
BD
T
In (7.10), the symbol Z
h
stands for conjunction of variables z
r
∈ Z corresponded
to the collection of microoperations Y
t
⊆Y from the row h of the table specifying
block TMS.
5. Construction of the table of microoperations. This step is executed using the
same approach as the one applied for PC
A
Y Mealy FSM.
6. Synthesis of FSM logic circuit. For structural diagram shown in Fig. 7.2, the
number of bits in the register RG is equal to Q+R
V
. This number can be de-
creased up to R, using the structural diagrams shown in Fig. 7.9 and Fig. 7.10.
In both these cases, the block TMS generates input memory functions instead of
state variables T. Due to such approach, it is enough R flip-flops in the register RG.
Let us discus an example of logic synthesis for the PC
A
Y Mealy FSM S
21
. For
FSM S
21
, there are T
0
= 7 collections of microoperations, namely: Y
1
= / 0, Y
2
=
{y
1
, y
2
}, Y
3
= {y
3
}, Y
4
= {y
4
}, Y
5
= {y
2
, y
5
}, Y
6
= {y
6
}, Y
7
= {y
3
, y
7
} (Table 7.1).
Let us construct the sets A(Y
t
) and define their cardinality numbers: A(Y
1
) = {a
1
},
m
1
= 1; A(Y
2
) = {a
2
, a
4
}, m
2
= 2; A(Y
3
) = {a
3
}, m
3
= 1; A(Y
4
) = {a
3
}, m
4
= 1;
A(Y
5
) = {a
4
}, m
5
= 1; A(Y
6
) = {a
5
}, m
6
= 1, and A(Y
7
) = {a
5
}, m
7
= 1. Thus,
it is enough K = 2 identifiers, that is I = {I
1
, I
2
}. The identifiers I
k
∈ I can be en-
coded using R
V
= 1 variable, that is V = {v
1
}. Let the identifiers be encoded in
the following way: K(I
1
) = 0 and K(I
2
) = 1. Let us find the pairs α
t,s
for each
element from the sets A(Y
t
). If m
t
= 1, then the first component of correspond-
ing pair is represented by the symbol / 0. This symbol corresponds to uncertainty
in the code C(a
s
)
t
, where the superscript t means that the code of state a
s
be-
longs to the pair α
t,s
. The following pairs can be constructed in the discussed
7.2 Logic Synthesis for Mealy FSM with Object Code Transformation 165
Table 7.8 State codes of PC
A
Y Mealy FSM S
21
a
m
C(a
s
)
t
α
t,m
h a
m
C(a
s
)
t
α
t,m
h
a
1
000∗ α
1,1
1 a
4
100∗ α
5,4
5
a
2
0010 α
2,2
2 a
4
0011 α
2,4
6
a
3
010∗ α
3,3
3 a
5
101∗ α
6,5
7
a
3
011∗ α
4,3
4 a
5
110∗ α
7,5
8
example: α
1,1
= / 0,Y
1
, α
2,2
= I
1
,Y
2
, α
2,4
= I
2
,Y
2
, α
3,3
= / 0,Y
3
, α
4,3
=/ 0,Y
4
,
α
5,4
= / 0,Y
5
, α
6,5
= / 0,Y
6
, α
7,5
= / 0,Y
7
. Using these pairs together with (7.7),
we can get the codes C(a
s
) shown in Table 7.8.
This table includes H
0
= m
1
+ . . . +m
T
rows. As follows from Table 7.8, each
from the states a
3
, a
4
, and a
5
have two different codes of the type (7.7). In common
case, the number of codes C(a
s
)
t
for some state a
m
∈ A is equal to the number of
different sets A(Y
t
), including this state a
m
. The codes of collections of microopera-
tions shown in Table 7.8 are the same as they were obtained before. The codes are
placed in the three most significant positions of the column C(a
m
).
Using the known method, we can construct the transformed structure table of
PC
A
Y Mealy FSM S
21
(Table 7.9) on the base of the initial structure table (Table
7.1). Using Table 7.9, we can derive systems (7.8) and (7.4), for example, z
1
=
F
6
∨F
7
∨F
8
∨F
11
= A
3
x
4
∨A
3
¯ x
4
∨A
4
∨A
5
¯ x
5
x
4
=
¯
T
1
T
2
¯
T
3
x
4
∨. . .; v
1
=F
5
= A
2
¯ x
2
¯ x
3
=
¯
T
1
¯
T
2
T
3
¯ x
2
¯ x
3
.
The table used for specification of the block TMS (Table 7.10) includes H
2
=
2
R
0
−H
1
rows, where R
0
= log
2
H
0
. It is necessary if the logic circuit of TMS
is implemented with embedded memory blocks. In this case all possible addresses
should be present. Let us point out that at least H
1
= (2
Q
−T)2
R
1
rows contain zero
output codes corresponded to unused collections of microoperations. For the FSM
Table 7.9 Transformed structure table of PC
A
Y Mealy FSM S
21
a
m
K(a
m
) X
h
Z
h
V
h
h
a
1
000 x
1
z
3
– 1
¯ x
1
z
2
– 2
a
2
010 x
2
z
3
– 3
¯ x
2
x
3
z
2
z
3
– 4
¯ x
2
¯ x
3
z
3
v
1
5
a
3
011 x
1
z
1
– 6
¯ x
1
z
1
z
3
– 7
a
4
100 1 z
1
z
2
– 8
a
5
101 x
2
x
3
z
3
– 9
x
2
¯ x
3
z
2
– 10
¯ x
2
x
4
z
1
z
2
– 11
¯ x
2
¯ x
4
– – 12
166 7 FSM Synthesis with Object Code Transformation
Table 7.10 Specification of block TMS for PC
A
Y Mealy FSM S
21
Y
t
K(Y
t
) I
k
K(I
k
) a
s
K(a
s
) Φ
h
h
Y
1
000 – 0 a
1
000 – 1
000 – 1 a
1
000 – 2
Y
2
001 I
1
0 a
2
010 D
2
3
001 I
2
1 a
4
100 D
1
4
Y
3
010 – 0 a
3
011 D
2
D
3
5
010 – 1 a
3
011 D
2
D
3
6
Y
4
011 – 0 a
3
011 D
2
D
3
7
011 – 1 a
3
011 D
2
D
3
8
Y
5
100 – 0 a
4
100 D
1
9
100 – 1 a
4
100 D
1
10
Y
6
101 – 0 a
5
101 D
1
D
3
11
101 – 1 a
5
101 D
1
D
3
12
Y
7
110 – 0 a
5
101 D
1
D
3
13
110 – 1 a
5
101 D
1
D
3
14
S
21
, there is H
1
= 2, it means that only 14 rows are in use, whereas there are totally
2
R
0
= 16 rows.
For the PC
A
Y Mealy FSM S
21
, table of microoperations is represented by Table
7.4; its logic circuit is shown in Fig. 7.11. This circuit corresponds to the model
shown in Fig. 7.9. The logic circuit of block TMS is implemented using embedded
memory blocks on the base of Table 7.10.
Let us point out that the logic circuit of block TMS can be implemented using
some macrocells. In this case the following system of Boolean functions should be
constructed:
D
r
=
H
2

h=1
C
rk
Z
h
V
h
(r = 1, . . . , R). (7.11)
If the column I
k
contains the symbol ”–” in the row h of the table specified block
TMS, then V
h
= 1. It allows minimizing system (7.11). For example, D
1
=F
4
∨F
9

F
10
∨F
11
∨F
12
∨F
15
∨F
14
= ¯ z
1
¯ z
2
z
3
v
1
∨z
1
¯ z
2
¯ z
3
∨z
1
¯ z
2
z
3
∨z
3
¯ z
2
z
1
.
Fig. 7.11 Logic circuit of
PC
A
Y Mealy FSM S
21
PAL
1
1
2
3
4
5
6
7
1
2
3
4
2
3
4
5
10
z
2
RG D
1
D
2
D
3
R
C
1
2
3
14
15
16
8
5
6
9
7
x
1 1
x
2 2
x
3 3
11
z
3 12
v
1
6
T
1
T
2
T
3
4
6
7
x
4
5
T
1
T
2
PROM
1
2
3
1
2
3
4
5
10
11
12
y
1
y
2
y
3
y
4
y
5
8
Start
Clock 9
T
3
7
13
PROM
10
1
2
3
4
1
2
3
11
12
13
14
15
z
1
D
2
D
3
D
1
16
7.2 Logic Synthesis for Mealy FSM with Object Code Transformation 167
Let us discuss an example of logic synthesis for the PC
A
D Mealy FSM S
21
, hav-
ing the structural diagram shown in Fig. 7.10. The codes for its collections of mi-
crooperations are shown in Table 7.6. Using these codes of collections as well as
the state codes from Table 7.8, it is possible to construct the table for state codes of
PC
A
D Mealy FSM S
21
(Table 7.11).
Table 7.11 State codes for PC
A
D Mealy FSM S
21
a
m
C(a
s
)
t
α
t,m
h a
m
C(a
s
)
t
α
t,m
h
a
1
00000∗ α
1,1
1 a
4
10001∗ α
5,4
5
a
2
001010 α
2,2
2 a
4
001011 α
2,4
6
a
3
01000∗ α
3,3
3 a
5
00010∗ α
6,5
7
a
3
01100∗ α
4,3
4 a
5
01011∗ α
7,5
8
The transformed structure table of PC
A
D Mealy FSM S
21
(Table 7.12) is con-
structed in the same way, as it is done for PC
A
Y Mealy FSM.
Table 7.12 Transformed structure table of PC
A
D Mealy FSM S
21
a
m
K(a
m
) X
h
Z
h
V
h
h
a
1
000 x
1
z
3
z
5
– 1
¯ x
1
z
2
– 2
a
2
010 x
2
z
3
z
5
– 3
¯ x
2
x
3
z
2
z
3
– 4
¯ x
2
¯ x
3
z
3
z
5
v
1
5
a
3
011 x
4
z
1
z
5
– 6
¯ x
1
z
4
– 7
a
4
100 1 z
2
z
4
z
5
– 8
a
5
101 x
2
x
3
z
3
z
5
– 9
x
2
¯ x
3
z
2
– 10
¯ x
2
x
4
z
2
z
4
z
5
– 11
¯ x
2
¯ x
4
– – 12
For PD Mealy FSM, the number of bits used in the code K(Y
t
) is much more
than for equivalent PY Mealy FSM [8]. It means that the logic circuit of block TSM
for PD Mealy FSM should be implemented using some macrocells. For the PC
A
D
Mealy FSM S
21
, the table of block TSM includes H
0
= 8 rows (Table 7.13).
To implement the logic circuit of PC
A
D Mealy FSM, its transformed ST is used
to derive systems (7.4) and (7.8), whereas its table for block TSM is the base to
derive system (7.11). For example, the following Boolean equation can be derived
D
1
= F
7
∨F
8
= ¯ z
1
¯ z
2
¯ z
3
z
4
¯ z
5
∨ ¯ z
1
z
2
¯ z
3
z
4
z
5
from Table 7.13. The logic circuit of PC
A
D
Mealy FSM S
21
is shown in Fig. 7.12.
168 7 FSM Synthesis with Object Code Transformation
Table 7.13 Specification of block TSM for PC
A
D Mealy FSM S
21
Y
t
K(Y
t
) I
k
K(I
k
) a
s
K(a
s
) Φ
h
h
Y
1
00000 – 0 a
1
000 – 1
Y
2
00101 I
1
0 a
2
001 D
3
2
I
2
1 a
4
011 D
2
D
3
3
Y
3
01000 – 0 a
3
010 D
2
4
Y
4
01100 – 0 a
3
010 D
2
5
Y
5
10001 – 0 a
4
011 D
2
D
3
6
Y
6
00010 – 0 a
5
100 D
1
7
Y
7
01011 – 0 a
5
100 D
1
8
Fig. 7.12 Logic circuit of
PC
A
D Mealy FSM S
21
PLD
1
1
2
3
4
5
6
7
1
2
3
4
5
6
2
3
4
5
10
z
2
RG
D
1
D
2
D
3
R
C
1
2
3
16
17
18
8
5
6
9
7
x
1 1
x
2 2
x
3 3
11
z
3 12
z
4
6
T
1
T
2
T
3
4
6
7
x
4
5
T
1
T
2
DC
1
1
2
3
0
1
2
3
4
5
6
7
10
11
12
y
1
y
3
y
4
y
5
8
Start
Clock 9
T
3
7
13
z
1
PAL
13
1
2
0
1
2
3
14
y
2
y
6
y
7
14
v
1 15
z
5
PLD
10
1
2
3
4
5
6
1
2
3
11
12
13
14
16
D
2 17
D
3 18
15
D
1
7.3 Logic Synthesis for Moore FSM with Object Code
Transformation
Let us discuss some synthesis examples using the Moore FSM S
22
, specified by its
structure table (Table 7.14). There are T =4 different collections of microoperations
in this table, namely collections:Y
1
= / 0, Y
2
= {y
1
, y
2
}, Y
3
= {y
3
}, Y
4
= {y
3
, y
4
}.
These collections can be encoded using Q = 2 variables from the set Z = {z
1
, z
2
}.
First of all, let us discuss an example of the PC
A
Y Moore FSM S
22
synthesis.
The method for PC
A
Y Moore FSM synthesis includes the following steps:
1. Encoding of collections of microoperations. Each collection Y
t
⊆Y is encoded
by a binary code K(Y
t
) having Q = log
2
T
0
bits, where T
0
is the number of
different collections in GSA to be interpreted. The set of additional variables
Z = {z
1
, . . . , z
Q
} should be built for encoding of collections Y
t
⊆Y.
2. Construction of table of microoperations. This table includes the columns Y
t
,
K(Y
t
), y
1
,. . . , y
N
, t; it specifies embedded memory blocks from the block BY.
7.3 Logic Synthesis for Moore FSM with Object Code Transformation 169
Table 7.14 Specification of block TSM for PC
A
D Mealy FSM S
21
a
m
K(a
m
) a
s
K(a
s
) X
h
Φ
h
h
a
1
(–) 000 a
2
001 x
1
D
3
1
a
3
010 ¯ x
1
x
2
D
2
2
a
4
011 ¯ x
1
¯ x
2
D
2
D
3
3
a
2
(y
1
y
2
) 001 a
5
100 x
3
D
1
4
a
6
101 ¯ x
3
D
1
D
3
5
a
3
(y
3
) 010 a
5
100 x
3
D
1
6
a
6
101 ¯ x
3
D
1
D
3
7
a
4
(y
1
y
2
) 011 a
5
100 x
3
D
1
8
a
6
101 ¯ x
3
D
1
D
3
9
a
5
(y
3
y
4
) 100 a
7
110 x
4
D
1
D
2
10
a
1
000 ¯ x
4
– 11
a
6
(y
1
y
2
) 101 a
7
110 x
4
D
1
D
2
12
a
1
000 ¯ x
4
– 13
a
7
(y
3
y
4
) 110 a
5
100 x
3
D
1
14
a
6
101 ¯ x
3
D
1
D
3
15
3. Specification of block TSM. This block is specified by the table having the
following columns: a
m
, Y
t
, K(Y
t
), Z
m
, m. The table is used for deriving functions
z
q
∈ Z.
4. Synthesis of FSM logic circuit. The structural diagram of PC
A
Y Moore FSM is
shown in Fig. 7.1. In this model, the block BP generates functions Φ =Φ(T, X),
derived from initial structure table, whereas the block BY generates output func-
tions Y =Y(Z), specified by the table of microoperations.
The collections of microoperations for the discussed example were found in the
beginning of this Section. Let these collections of microoperations for the Moore
FSM S
22
be encoded in the following way: K(Y
1
) =00, K(Y
2
) =01, . . . , K(Y
4
) =11.
It allows to construct the tables for specification of microoperations (Table 7.15) and
presentation of the block TSM (Table 7.16). The logic circuit of PC
A
Y Moore FSM
S
22
is shown in Fig. 7.13.
Obviously, the model of PC
A
Y Moore FSM can be applied if the following con-
dition takes place:
R > Q. (7.12)
Table 7.15 Table of microoperations for PC
A
Y Moore FSM S
22
Y
t
K(Y
t
) y
1
y
2
y
3
y
4
t
Y
1
00 0 0 0 0 1
Y
2
01 1 1 0 0 2
Y
3
10 0 0 1 0 3
Y
4
11 0 0 1 1 4
170 7 FSM Synthesis with Object Code Transformation
Table 7.16 Specification of block TSM for PC
A
Y Moore FSM S
22
a
m
K(a
m
) Y
t
K(Y
t
) Z
m
m
a
1
000 Y
1
00 – 1
a
2
001 Y
2
01 z
2
2
a
3
010 Y
3
10 z
1
3
a
4
011 Y
2
01 z
2
4
a
5
100 Y
4
11 z
1
z
2
5
a
6
100 Y
2
01 z
2
6
a
7
101 Y
4
11 z
1
z
2
7
Fig. 7.13 Logic circuit of
PC
A
Y Moore FSM S
22
PAL
1
1
2
3
4
5
6
7
1
2
3
2
3
4
5
10
D
2
RG D
1
D
2
D
3
R
C
1
2
3
10
11
12
8
5
6
9
7
x
1 1
x
2 2
x
3 3
11
D
3 12
6
T
1
T
2
T
3
4
6
7
x
4
5
T
1
T
2
PROM 1
2
1
2
3
4
14
15
y
1
y
2
y
3
y
4
8
Start
Clock 9
T
3
7
PROM
5
1
2
3
1
2
6
7
13
14
D
1
z
2
z
1
If this condition is satisfied, then the complexity of block BY for PC
A
Y Moore
FSM is 2
R−Q
times less in comparison with this block complexity for equivalent PY
Moore FSM. The main drawback of PC
A
Y Moore FSM is increase for the number
of levels; it results in decrease for performance in comparison with equivalent PY
Moore FSM.
The number of macrocells in logic circuit of PC
A
Y Moore FSM can be decreased
due to taking into account existence of the pseudoequivalent states [7]. For exam-
ple, the following partition Π
A
={B
1
, B
2
, B
3
} can be found for the Moore FSM S
22
,
where B
1
= {a
1
}, B
2
= {a
2
, a
3
, a
4
, a
7
}, B
3
= {a
5
, a
6
}. Obviously, there are I = 3
classes of the pseudoequivalent states. If the method of optimal state encoding is
used, then it results in the model P
E
C
A
Y Moore FSM, having the same structural
diagram as the one shown in Fig. 7.1. For the P
E
C
A
Y Moore FSMS
22
, the optimal
state codes are shown in the Karnaugh map (Fig. 7.14). It allows obtaining the fol-
lowing codes for classes B
i
∈ Π
A
:K(B
1
) = 0 ∗ 0, K(B
2
) = 1 ∗ ∗ and K(B
3
) = 0 ∗ 1.
Fig. 7.14 Optimal state
codes of Moore FSM S
22
T
1
a
1
a
5
a
6
a
2
a
3
a
4
a
7
0
1
00 01 11 10
T
2
T
3
*
7.3 Logic Synthesis for Moore FSM with Object Code Transformation 171
Table 7.17 Transformed structure table of P
E
C
A
Y Moore FSM S
22
B
i
K(B
i
) a
s
K(a
s
) X
h
Φ
h
h
B
1
a
2
100 x
1
D
1
1
a
3
101 ¯ x
1
x
2
D
1
D
3
2
a
4
111 ¯ x
1
¯ x
2
D
1
D
2
D
3
3
B
2
1∗∗ a
5
001 x
3
D
3
4
a
6
011 ¯ x
3
D
2
D
3
5
B
3
0∗1 a
7
110 x
4
D
1
D
2
6
a
1
000 ¯ x
4
– 7
Fig. 7.15 Structural di-
agram of P
E
C
A
Y Moore
FSM
Start
Clock
RG
X
Z
BP
Ժ
TSM
T Y
BY
W
The transformed structure table of P
E
C
A
Y Moore FSM S
22
includes only H
0
= 7
rows (Table 7.17).
The logic circuit of P
E
C
A
Y Moore FSM S
22
differs from the circuit shown in
Fig. 7.13 only in absence of the input T
2
for macrocells of the block BP. It is con-
nected with the identity T
2
≡ ∗ taking place for all codes of the classes B
i
∈ Π
A
.
If the method of transformation of the state codes into the codes of the classes
B
i
∈ Π
A
is applied, it leads to the model of P
E
C
A
Y Moore FSM shown in Fig. 7.15.
The synthesis method for P
E
C
A
Y Moore FSM includes the following steps:
1. Construction of the partition Π
A
and encoding of the classes of pseudoequivalent
states B
i
∈ Π
A
.
2. Encoding of collections of microoperations.
3. Construction of the table of microoperations.
4. Construction of an expanded table specifying the block TSM.
5. Construction of transformed structure table.
6. Synthesis of FSM logic circuit.
For the Moore FSM S
22
, there are I = 3 classes B
i
∈ Π
A
, thus they can be encoded
using R
0
= 2 variables from the set τ = {τ
1
, τ
2
}. Let us encode the classes B
i
∈ Π
A
in the following way: K(B
1
) = 00, K(B
2
) = 01, K(B
3
) = 10. Let us encode the col-
lections of microoperations using the same codes as for the PC
A
Y Moore FSM S
22
.
In this case table of microoperations is represented by Table 7.17. The expanded
table for block TSM (Table 7.18) includes additional columns B
i
and τ
m
. The col-
umn τ
m
contains variables τ
r
∈ τ, used to encode states a
m
∈ B
i
. The transformed
structure table of P
C
C
A
Y Moore FSM is constructed in a trivial way. In case of the
P
C
C
A
Y Moore FSM S
22
, this table is represented by Table 7.19.
172 7 FSM Synthesis with Object Code Transformation
Table 7.18 Expanded table for block TSM of P
C
C
A
Y Moore FSM S
22
a
m
K(a
m
) Y
t
K(Y
t
) Z
m
B
i
τ
m
m
a
1
000 Y
1
00 – B
1
– 1
a
2
001 Y
2
01 z
2
B
2
τ
2
2
a
3
010 Y
3
10 z
1
B
2
τ
2
3
a
4
011 Y
2
01 z
2
B
2
τ
2
4
a
5
100 Y
4
11 z
1
z
2
B
3
τ
1
5
a
6
101 Y
2
01 z
2
B
3
τ
1
6
a
7
110 Y
4
11 z
1
z
2
B
3
τ
2
7
The transformed structure table is used to derive the system of input memory
functions, represented in the following form:
φ
r
=
H
0

h=1
C
rh
B
h
X
h
(r = 1, . . . , R). (7.13)
The next SOP D
3
=F
1
∨F
3
∨F
5
=B
1
x
1
∨B
1
¯ x
1
¯ x
2
∨B
2
¯ x
3
= ¯ τ
1
¯ τ
2
x
1
∨ ¯ τ
1
¯ τ
2
¯ x
1
¯ x
2
∨ ¯ τ
1
τ
2
¯ x
3
can be derived, for example, from Table 7.19. The logic circuit of P
C
C
A
YMoore
FSM S
22
is shown in Fig. 7.16.
Table 7.19 Transformed structure table of the P
C
C
A
Y Moore FSM S
22
B
i
K(B
i
) a
s
K(a
s
) X
h
Φ
h
h
B
1
a
2
001 x
1
D
3
1
a
3
010 ¯ x
1
x
2
D
2
2
a
4
011 ¯ x
1
¯ x
2
D
2
D
3
3
B
2
1∗∗ a
5
100 x
3
D
1
4
a
6
101 ¯ x
3
D
1
D
3
5
B
3
0∗1 a
7
110 x
4
D
1
D
2
6
a
1
000 ¯ x
4
– 7
The similar approaches are used to synthesize logic circuits of PC
A
D, P
E
C
A
D,
and P
C
C
A
D Moore FSMs. The only difference consists in the encoding method for
collections of microoperations. For example, let us discuss a method for logic circuit
design in case of the P
C
C
A
D Moore FSM S
23
(Table 7.20).
For the Moore FSM S
23
, the following partition Π
A
= {B
1
, B
2
, B
3
} can be
found, where B
1
= {a
1
}, B
2
= {a
2
, a
3
}, B
3
= {a
4
, a
5
, a
6
}. It means that I = 3,
R
0
= 2, and τ = {τ
1
, τ
2
}. Let us encode the classes B
i
∈ Π
A
in the following way:
K(B
1
) =00, K(B
2
) =01, K(B
3
) =10. For the Moore FSM S
23
, there are two classes
of compatible microoperations, namely the class Y
1
= {y
1
, y
3
, y
5
} and the class
Y
2
= {y
2
, y
4
, y
6
}. Let us use variables z
1
and z
2
for encoding of microoperations
y
n
∈Y
1
, whereas microoperations y
n
∈Y
2
are encoded using variables z
3
and z
4
. It
determines the following set Z = {z
1
, . . . , z
4
}, used to construct Table 7.21.
7.3 Logic Synthesis for Moore FSM with Object Code Transformation 173
Fig. 7.16 Logic circuit of
P
C
C
A
Y Moore FSM S
22
x
1 1
x
2 2
x
3 3
4
6
7
x
4
5
T
1
T
2
PROM 1
2
1
2
3
4
15
16
y
1
y
2
y
3
y
4
8
Start
Clock 9
T
3
PROM
12
1
2
3
1
2
3
4
13
14
15
16
z
2
z
1
PLD
1
1
2
3
4
5
6
1
2
3
2
3
4
5
9
D
1
RG D
1
D
2
D
3
R
C
1
2
3
9
10
11
7
12
13
8
14
10
D
2
11
D
3
6
T
1
T
2
T
3
5
6
W
2
W
1
Table 7.20 Structure table of Moore FSM S
23
a
m
K(a
m
) a
s
K(a
s
) X
h
Φ
h
h
a
1
(–) 000 a
2
001 x
1
D
3
1
a
3
010 ¯ x
1
D
2
2
a
2
(y
1
y
2
) 001 a
6
101 x
2
D
1
D
3
3
a
5
100 ¯ x
2
x
3
D
1
4
a
4
011 ¯ x
2
¯ x
3
D
2
D
3
5
a
3
(y
3
y
4
) 010 a
6
101 x
2
D
1
D
3
6
a
5
100 ¯ x
2
x
3
D
1
7
a
4
011 ¯ x
2
¯ x
3
D
2
D
3
8
a
4
(y
5
y
6
) 011 a
1
000 x
4
– 9
a
5
100 ¯ x
4
D
1
10
a
5
(y
1
y
6
) 100 a
1
000 x
4
– 11
a
5
100 ¯ x
4
D
1
12
a
6
(y
2
y
3
) 101 a
1
000 x
4
– 13
a
5
100 ¯ x
4
D
1
14
Table 7.21 Codes of microoperations for Moore FSM S
23
Y
1
K(y
1
n
) Y
2
K(y
2
n
)
z
1
z
2
z
3
z
4
/ 0 0 0 / 0 0 0
y
1
0 1 y
2
0 1
y
3
1 0 y
4
1 0
y
5
1 1 y
6
1 1
The block TSM of P
C
C
A
Y Moore FSMS
23
is represented by its expanded table
(Table 7.22). This table is constructed using the same approach as the one used in
design of P
C
C
A
Y Moore FSM.
The system of input memory functions is constructed using the FSM transformed
structure table. This table is constructed using the replacement of the states by
corresponding classes of pseudoequivalent states. The transformed ST of P
C
C
A
Y
174 7 FSM Synthesis with Object Code Transformation
Table 7.22 Expanded table for block TSM of P
C
C
A
Y Moore FSM S
23
a
m
K(a
m
) Y
t
K(Y
t
) Z
m
B
i
τ
m
m
a
1
000 Y
1
0000 – B
1
– 1
a
2
001 Y
2
0101 z
2
z
4
B
2
τ
2
2
a
3
010 Y
3
1010 z
1
z
3
B
2
τ
2
3
a
4
011 Y
4
1111 z
1
z
2
z
3
z
4
B
3
τ
1
4
a
5
100 Y
5
0111 z
2
z
3
z
4
B
3
τ
1
5
a
6
101 Y
6
1001 z
1
z
4
B
3
τ
1
6
Table 7.23 Transformed structure table of P
C
C
A
Y Moore FSM S
23
B
i
K(B
i
) a
s
K(a
s
) X
h
Φ
h
h
B
1
00 a
2
001 x
1
D
3
1
a
3
010 ¯ x
1
D
2
2
B
2
01 a
6
100 x
2
D
1
D
3
3
a
5
101 ¯ x
2
x
3
D
1
4
a
4
011 ¯ x
2
¯ x
3
D
2
D
3
5
B
3
10 a
1
110 x
4
– 6
a
5
000 ¯ x
4
D
1
7
Moore FSM S
23
includes only H
0
=7 rows (Table 7.23). It is twice less than in case
of its initial ST (Table 7.20).
The logic circuit of P
C
C
A
Y Moore FSM S
23
is shown in Fig. 7.17.
Fig. 7.17 Logic circuit of
P
C
C
A
Y Moore FSM S
23
PLD
1
1
2
3
4
5
6
1
2
3
2
3
4
5
9
D
2
RG D
1
D
2
D
3
R
C
1
2
3
9
10
11
7
12
13
8
14
x
1 1
x
2 2
x
3 3
10
D
3 11
6
T
1
T
2
T
3
4
6
7
x
4
5
W
1
W
2
DC 1
2
0
1
2
3
15
16
y
1
y
3
y
5
8
Start
Clock
D
1
DC 1
2
0
1
2
3
17
18
y
2
y
6
y
7
PLD
1
1
2
3
1
2
3
4
5
6
2
3
15
z
2 16
z
3 17
z
4 18
z
1
5
W
2 6
W
1
Models of Moore FSM2 have structural diagrams similar to the one shown in
Fig. 7.4. Synthesis methods for PC
Y
Yand PC
Y
Dmodels include the following steps:
1. Encoding of collections of microoperations.
2. One-to-one identification of FSM states by collections of microoperations Y
t
and
identifiers I
k
∈ I.
7.3 Logic Synthesis for Moore FSM with Object Code Transformation 175
3. Construction of transformed structure table.
4. Specification of code transformer for collections of microoperations.
5. Construction of table of microoperations.
6. Implementation of FSM logic circuit using some particular macrocells and em-
bedded memory blocks.
Let us discus application of this method for logic synthesis of the PC
Y
Y Moore FSM
S
22
, represented by its ST (Table 7.14).
Let us encode the collections of microoperations Y
t
⊆ Y in the following way:
K(Y
1
) = 00, K(Y
2
) = 01, K(Y
3
) = 10, and K(Y
4
) = 11. Remind, that Y
1
= / 0, Y
2
=
{y
1
, y
2
}, Y
3
= {y
3
}, and Y
4
= {y
3
, y
4
}. Let us find the sets of states A(Y
t
) ⊆ A, such
that they include the set Y
t
⊆Y. For the Moore FSM S
22
, there are the following sets:
A(Y
1
) = {a
1
}, A(Y
2
) = {a
2
, a
4
, a
6
}, A(Y
3
) = {a
3
}, and A(Y
4
) = {a
5
, a
7
}, having the
following numbers of states m
1
= m
3
=1, m
2
= 3, and m
4
=2. It determines the set
of identifiers I = {I
1
, I
2
, I
3
}. It is enough R
V
= 2 variables from the set V = {v
1
, v
2
}
for encoding of identifiers. Let us encode the identifiers I
k
∈ I in the following way:
K(I
1
) =00, K(I
2
) =01, K(I
3
) =10. Now the states a
m
∈A are one-to-one identified
by pairs α
1,1
= Y
1
, / 0, α
2,4
= Y
2
, I
2
, α
2,6
= Y
2
, I
3
, α
3,3
= Y
3
, / 0, α
4,5
= Y
4
, I
1
,
and α
4,7
= Y
4
, I
2
. The codes C(a
m
)
t
of states a
m
∈ A are shown in Table 7.24. In
this table, two the most-significant bits of code C(a
m
)
t
correspond to variables z
1
and z
2
, whereas the variables v
1
and v
2
correspond to the least-significant bits of the
state code.
The following two rules are used to construct the transformed ST of PC
Y
Y Moore
FSM. First, the column K(a
s
) is replaced by the column C(a
s
)
t
. Second, the column
Φ
h
contains Q+R
V
input memory functions, determined by the codes C(a
s
)
t
. For
the PC
Y
Y Moore FSM S
22
, its transformed ST is represented by Table 7.25.
This table is used for deriving of input memory functions Φ =Φ(T, X). The fol-
lowing Boolean equation D
4
=F
3
∨F
10
∨F
12
=A
1
¯ x
1
¯ x
2
∨A
5
x
4
∨A
6
x
4
=
¯
T
1
¯
T
2
¯
T
3
¯ x
1
¯ x
2

T
1
¯
T
2
¯
T
3
x
4
∨T
1
¯
T
2
T
3
x
4
,for example, is derived from Table 7.25.
The block TMS is specified by the table having columns α
t
, m, C(a
m
)
t
, a
m
,
K(a
m
), T
m
, m. The column T
m
includes state variables T
r
∈ Tequal to 1 in state
codes K(a
m
). For the PC
Y
Y Moore FSM S
22
, this table is represented by Table 7.26.
The table of block TMS is used to derive state variables
T
r
=
M

m=1
C
rm
Z
t
V
k
(r = 1, . . . , R). (7.14)
Table 7.24 State codes for PC
Y
Y Moore FSM S
22
a
m
C(a
m
)
t
α
t,m
a
m
C(a
m
)
t
α
t,m
a
1
00∗∗ α
1,1
a
5
1100 α
4,5
a
2
0100 α
2,2
a
6
0110 α
2,6
a
3
10∗∗ α
3,3
a
7
1101 α
4,7
a
4
0101 α
2,4
176 7 FSM Synthesis with Object Code Transformation
Table 7.25 Transformed structure table of PC
Y
Y Moore FSM S
22
a
m
K(a
m
) a
s
C(a
s
)
t
X
h
Φ
h
h
a
1
000 a
2
0100 x
1
D
2
1
a
3
10∗∗ ¯ x
1
x
2
D
1
2
a
4
0101 ¯ x
1
¯ x
2
D
2
D
4
3
a
2
001 a
5
1100 x
3
D
1
D
2
4
a
6
0110 ¯ x
3
D
2
D
3
5
a
3
010 a
5
1100 x
3
D
1
D
2
6
a
6
0110 ¯ x
3
D
2
D
3
7
a
4
011 a
5
1100 x
3
D
1
D
2
8
a
6
0110 ¯ x
3
D
2
D
3
9
a
5
100 a
7
1101 x
4
D
1
D
2
D
4
10
a
1
00∗∗ ¯ x
4
– 11
a
6
101 a
7
1101 x
4
D
1
D
2
D
4
12
a
1
00∗∗ ¯ x
4
– 13
a
7
110 a
5
1100 x
3
D
1
D
2
14
a
6
0110 ¯ x
3
D
2
D
3
15
Table 7.26 Specification of block TMS for PC
Y
Y Moore FSM S
22
a
m
C(a
m
)
t
α
t,m
K(a
m
) T
m
m
a
1
00∗∗ α
1,1
000 – 1
a
2
0100 α
2,2
001 T
3
2
a
3
10∗∗ α
3,3
010 T
2
3
a
4
0101 α
2,4
011 T
2
T
3
4
a
5
1100 α
4,5
100 T
1
5
a
6
0110 α
2,6
101 T
1
T
3
6
a
7
1101 α
4,7
110 T
1
T
2
7
In (7.14), the symbol C
rm
stands for a Boolean variable, equal to 1 iff the bit r
of code K(a
m
) is equal to 1; the symbol Z
t
determines a conjunction of variables
z
q
∈ Z, corresponded to code K(Y
t
); the symbol V
k
determines a conjunction of
variables v
r
∈ V, corresponded to code K(I
k
). For the PC
Y
Y Moore FSM S
22
, we
can find the SOP T
3
= F
2
∨F
4
∨F
6
= ¯ z
1
z
2
¯ v
1
¯ v
2
∨ ¯ z
1
z
2
¯ v
1
v
2
∨ ¯ z
1
z
2
v
1
¯ v
2
, for example,
from Table 7.26. The block of microoperations is specified by Table 7.15. The logic
circuit of PC
Y
Y Moore FSM S
22
is shown in Fig. 7.18.
Obviously, the block used for generation of functions (7.14) can also generates
variables τ
r
∈ τ, encoded the classes of pseudoequivalent states. Such an approach
yields in P
C
C
Y
Y Moore FSM (Fig. 7.19). Obviously, there is no sense in optimal
state encoding for this model.
Let us discuss an example of logic circuit design for the P
C
C
Y
Y Moore FSM S
22
.
The design method differs from the previous one because of necessity for finding
partition Π
A
and encoding the classes of pseudoequivalent states B
i
∈ Π
A
. For the
7.3 Logic Synthesis for Moore FSM with Object Code Transformation 177
Fig. 7.18 Logic circuit of
P
C
C
Y
Y Moore FSM S
22
PLD
1
1
2
3
4
5
6
7
1
2
3
4
2
3
4
5
10
D
2
RG
D
1
D
2
D
3
D
4
R
C
1
2
3
4
10
11
12
13
14
15
8
16
x
1 1
x
2 2
x
3 3
11
D
3 12
D
4
6
z
1
z
2
v
1
4
6
7
x
4
5
T
1
T
2
PROM
1
2
1
2
3
4
14
15
y
1
y
2
y
3
y
4
8
Start
Clock 9
T
3
7
13
D
1
PLD
14
1
2
3
4
1
2
3
15
16
17
16
T
2 17
T
3 18
T
1
17
v
2
9
Fig. 7.19 Structural dia-
gram of P
C
C
Y
Y Moore
FSM
Start
Clock
RG
X
Z
BP
Ժ
TMS
W
Y
BY
V
Table 7.27 Transformed structure table of P
C
C
Y
Y Moore FSM S
22
B
i
K(B
i
) a
s
C(a
s
)
t
X
h
Φ
h
h
B
1
00 a
2
0100 x
1
D
3
1
a
3
10∗∗ ¯ x
1
x
2
D
1
2
a
4
0101 ¯ x
1
¯ x
2
D
2
D
4
3
B
2
01 a
5
1100 x
3
D
1
D
2
4
a
6
0110 ¯ x
3
D
2
D
3
5
B
3
10 a
7
1101 x
4
D
1
D
2
D
4
6
a
1
00∗∗ ¯ x
4
– 7
P
C
C
Y
YMoore FSMS
22
, it could be constructed the partition Π
A
={B
1
, B
2
, B
3
} with
classes B
1
= {a
1
}, B
2
= {a
2
, a
3
, a
4
, a
7
}, and B
3
= {a
5
, a
6
}. Let us use the variables
τ
r
∈ τ = {τ
1
, τ
2
} for encoding of the classes B
i
∈ Π
A
. Let us encode the classes
B
i
∈ Π
A
in the following way:K(B
1
) = 00, K(B
2
) = 01, K(B
3
) = 10. These codes
allow to construct the transformed ST (Table 7.27) used to design the logic circuit
of block BP for the P
C
C
Y
Y Moore FSM S
22
.
The code transformer TMS is represented by Table 7.28. In this table, states a
m

B
i
are replaced by corresponding classes B
i
, whereas state codes K(a
m
) are replaced
by corresponding code K(B
i
). Obviously, this replacement leads to replacement of
the column T
m
by the column τ
m
.
The transformed ST is used to derive the functions Φ = Φ(τ, X). For example,
the SOP D
4
= B
1
¯ x
1
¯ x
2
∨B
3
x
4
= ¯ τ
1
¯ τ
2
¯ x
1
¯ x
2
∨τ
1
¯ τ
2
x
4
can be derived from Table 7.27.
The system τ = τ(Z,V) is derived from the table of block TMS. For example, the
178 7 FSM Synthesis with Object Code Transformation
Table 7.28 Specification of block TMS for P
C
C
Y
Y Moore FSM S
22
B
i
C(a
m
)
t
α
t,m
K(B
i
) τ
m
m
B
1
00∗∗ α
1,1
00 – 1
B
2
0100 α
2,2
01 τ
2
2
B
2
10∗∗ α
3,3
01 τ
2
3
B
2
0101 α
2,4
01 τ
2
4
B
3
1100 α
4,5
10 τ
1
5
B
3
0110 α
2,6
10 τ
1
6
B
2
1101 α
4,7
01 τ
2
7
Fig. 7.20 Logic circuit of
P
C
C
Y
Y Moore FSM S
22
PLD
1
1
2
3
4
5
6
1
2
3
4
2
3
4
5
9
D
2
RG
D
1
D
2
D
3
D
4
R
C
1
2
3
4
9
10
11
12
13
14
7
15
x
1 1
x
2 2
x
3 3
10
D
3 11
D
4
6
z
1
z
2
v
1
4
6
7
x
4
5
W
1
W
2
PROM
1
2
1
2
3
4
13
14
y
1
y
2
y
3
y
4
8
Start
Clock
12
D
1
PLD
13
1
2
3
4
1
2
14
15
16
5
W
2 6
W
1
16
v
2
8
Fig. 7.21 Structural dia-
gram of PC
Y
Y Moore FSM
Start
Clock
RG
X
Z
BP
Ժ
TMS
Y
BD
V
T
SOP τ
1
= F
5
∨F
6
= z
1
z
2
¯ v
1
¯ v
2
∨ ¯ z
1
z
2
v
1
¯ v
2
can be derived from Table 7.28. The logic
circuit of P
C
C
Y
Y Moore FSM S
22
is shown in Fig. 7.20.
If the method of encoding of the classes of compatible microoperations is used,
then it results in models of PC
Y
D Moore FSM (Fig.7.21). If this approach is used
simultaneously with transformation of the classes of pseudoequivalent states, then
it leads to models of P
C
C
Y
D Moore FSM (Fig. 7.22).
The model of PC
Y
D Moore FSM can be viewed as a particular case of P
C
C
Y
D
Moore FSM. Let us discuss the method for model P
C
C
Y
D Moore FSM synthesis.
There are the following steps in P
C
C
Y
D Moore FSM logic synthesis:
1. Finding of the classes of compatible microoperations and their codes.
2. Identification of states a
m
∈ A by pairs α
t
, m = Y
t
, I
k
.
3. Finding of the partition of the state set A by the classes of pseudoequivalent states
and encoding of classes B
i
∈ Π
A
.
7.3 Logic Synthesis for Moore FSM with Object Code Transformation 179
Fig. 7.22 Structural dia-
gram of P
C
C
Y
D Moore
FSM
Start
Clock
RG
X
Z
BP
Ժ
TMS
W
Y
BD
V
4. Construction of transformed structure table and functions Φ =Φ(τ, X).
5. Specification of block TMS and construction of system τ =τ(Z,V).
6. Implementation of FSM logic circuit using given logic elements.
Let us discuss an example of this method application for logic synthesis of the PC
Y
Y
Moore FSM S
24
(Table 7.29). In this case, the set of microoperations Y is divided
by two classes, namely Y
1
= {y
1
, y
3
, y
5
} and Y
2
= {y
2
, y
4
, y
6
}. The microoperations
from the first class are encoded by variables z
1
and z
2
, whereas variables z
3
and
z
4
are used to encode microoperations from the second class. These four variables
form the set Z. Let us encode microoperations y
n
∈ Y
i
in the way shown in Table
7.21, it leads to the following codes: K(Y
1
) = 0000, where Y
1
= / 0; K(Y
2
) = 0101,
where Y
2
={y
1
, y
2
}; K(Y
3
) =1010, where Y
3
={y
3
, y
4
}; K(Y
4
) =1111, where Y
4
=
{y
5
, y
6
}; K(Y
5
) = 1011, where Y
5
= {y
3
, y
6
}.
The following sets of states A(Y
t
) can be found for the Moore FSM S
24
: A(Y
1
) =
{a
1
}, A(Y
2
) ={a
2
, a
5
}, A(Y
3
) ={a
3
}, A(Y
4
) ={a
4
}, A(Y
5
) ={a
6
}. Therefore, there
is a set of identifiers I = {I
1
, I
2
} and its elements can be coded using only one
variable from the set V = {v
1
}. Let us construct the set of pairs α
t,m
used for one-
to-one identification of the FSM states. There are the following pairs for the Moore
FSM S
24
: α
1,1
=Y
1
, / 0, α
2,2
=Y
1
, I
1
, α
2,5
=Y
1
, I
2
, α
3,3
=Y
3
, / 0, α
4,4
=Y
4
, / 0,
Table 7.29 Structure table of Moore FSM S
24
a
m
K(a
m
) a
s
K(a
s
) X
h
Φ
h
h
a
1
(–) 000 a
2
001 x
1
D
3
1
a
3
010 ¯ x
1
D
2
2
a
2
(y
1
y
2
) 001 a
5
100 x
1
D
1
3
a
4
011 ¯ x
1
x
2
D
1
D
3
4
a
1
000 ¯ x
1
¯ x
2
– 5
a
3
(y
3
y
4
) 010 a
5
100 x
1
D
1
6
a
4
011 ¯ x
1
x
2
D
1
D
3
7
a
1
000 ¯ x
1
¯ x
2
– 8
a
4
(y
5
y
6
) 011 a
2
001 x
3
D
3
9
a
6
101 ¯ x
3
D
1
D
3
10
a
5
(y
1
y
2
) 100 a
2
001 x
3
D
3
11
a
6
101 ¯ x
3
D
1
D
3
12
a
6
(y
3
y
6
) 101 a
2
001 x
3
D
3
13
a
6
101 ¯ x
3
D
1
D
3
14
180 7 FSM Synthesis with Object Code Transformation
Table 7.30 State codes for Moore FSM S
24
a
m
C(a
m
)
t
m a
m
C(a
m
)
t
m
z
1
z
2
z
3
z
4
∗ z
1
z
2
z
3
z
4
v
1
a
1
0 0 0 0 ∗ 1 a
4
1 1 1 1 ∗ 4
a
2
0 1 0 1 0 2 a
5
0 1 0 1 1 5
a
3
1 0 1 – ∗ 2 a
6
1 0 1 1 ∗ 6
and α
5,6
= Y
5
, / 0. Let the identifiers for the Moore FSM S
24
have the following
codes: K(I
1
) = 0, K(I
2
) = 1. It allows finding the codes C(a
m
)
t
of the states shown
in Table 7.30.
The state set A includes three classes of pseudoequivalent states, namely B
1
=
{a
1
}, B
2
= {a
2
, a
3
}, and B
3
= {a
4
, a
5
, a
6
}. It is enough R
0
= 2 elements from the
set τ = {τ
1
, τ
2
} for encoding of the classes B
i
∈ Π
A
. Let the classes be encoded in
a trivial way:K(B
i
) = 00, . . ., K(B
3
) = 10. To construct the transformed structure
table, it is necessary to replace the column a
m
by the column B
i
, the column K(a
m
)
by the column K(B
i
), and the column K(a
s
) by the column C(a
s
)
t
. Besides, the
column Φ
h
includes input memory functions for loading of variables z
q
∈ Z and
v
r
∈V into the register RG. The block TMS is specified by its table having columns
a
m
, C(a
m
)
t
, B
i
, K(B
i
), τ
m
, and m. For both these tables, the codes C(a
m
)
t
of states
a
m
∈ A are taken from a table similar to Table 7.30.
For the P
C
C
Y
D Moore FSM S
24
, its transformed ST and table specified the block
TMS are shown in Table 7.31 and Table 7.32 respectively. Table 7.31 is used to
derive the equations of system Φ =Φ(τ, X). For example, the following SOP D
1
=
F
2
∨F
5
= B
1
¯ x
1
∨B
2
¯ x
2
¯ x
3
= ¯ τ
1
¯ τ
2
¯ x
1
∨¯ τ
1
τ
2
¯ x
2
¯ x
3
can be derived from the transformed
structure table of the P
C
C
Y
D Moore FSM S
24
.
Table 7.32 is used to derive the system τ = τ(Z,V), for example, the following
SOP τ
2
= A
2
∨A
3
= ¯ z
1
z
2
¯ z
3
z
4
v
1
∨z
1
¯ z
2
z
3
¯ z
4
. The logic circuit of P
C
C
Y
D Moore FSM
S
24
is shown in Fig. 7.23. In this circuit, the logic circuit of block BP is implemented
using some macrocells, it implements input memory functions Φ = Φ(τ, X), load-
ing variables z
q
∈ Z and v
r
∈Vinto the register RG. The logic circuit of block BD is
implemented using standard decoders; it implements functions Y =Y(Z), specified
Table 7.31 Transformed structure table of P
C
C
Y
D Moore FSM S
24
B
i
K(B
i
) a
s
C(a
s
)
t
X
h
Φ
h
h
B
1
00 a
2
01010 x
1
D
2
D
4
1
a
3
1010∗ ¯ x
1
D
1
D
3
2
B
2
01 a
6
1011∗ x
2
D
1
D
3
D
4
3
a
5
01011 ¯ x
2
x
3
D
2
D
4
D
5
4
a
4
1111∗ ¯ x
2
¯ x
3
D
1
D
2
D
3
D
4
5
B
3
10 a
7
0000∗ x
4
– 6
a
1
01011 ¯ x
4
D
2
D
4
D
5
7
7.4 Multilevel Models of FSM with Object Code Transformation 181
Table 7.32 Specification of block TMS for P
C
C
Y
D Moore FSM S
24
a
m
C(a
m
)
t
B
i
K(B
i
) τ
m
m
a
1
0000∗ B
1
00 – 1
a
2
01010 B
2
01 τ
2
2
a
3
1010∗ B
2
01 τ
2
3
a
4
1111∗ B
3
10 τ
1
4
a
5
01011 B
3
10 τ
1
5
a
6
1011∗ B
3
10 τ
1
6
Fig. 7.23 Logic circuit of
P
C
C
Y
D Moore FSM S
24
PLD
1
1
2
3
4
5
6
1
2
3
4
5
2
3
4
5
9
D
2
RG
D
1
D
2
D
3
D
4
D
5
R
C
1
2
3
4
5
9
10
11
12
14
15
13
16
x
1 1
x
2 2
x
3 3
10
D
3 11
D
4
6
z
1
z
2
z
3
4
6
7
x
4
5
W
1
W
2
8
Start
Clock
12
D
1
PLD
14
1
2
3
4
5
1
2
15
16
17
5
W
2 6
W
1
17
z
4
7
D
5 12
8
18
v
1
18
DC
1
2
0
1
2
3
14
15
y
1
y
3
y
5
DC
1
2
0
1
2
3
16
17
y
2
y
4
y
6
by Table 7.21. The logic circuit of block TMS is implemented using macrocells, it
generates functions τ =τ(Z,V).
7.4 Multilevel Models of FSM with Object Code
Transformation
The FSM models discussed in previous Sections are used to construct the multilevel
models of FSM with object code transformation. Let the symbol G stand for the
number of variables p
g
∈ P, used for replacement of logical conditions x
l
∈ X. In
this case, the replacement of logical conditions leads to 3G different FSM models.
Let the symbol K stand for the number of classes of compatible microoperations,
then there are K models including the block D
k
forming microoperations y
n
∈ Y.
Let us point out that there is no sense in using the method of encoding of struc-
ture table rows, because the transformed table in this case contains both codes of
states and microoperations. Therefore, multilevel models of Mealy FSM with object
code transformation can include up to four levels. These models are represented by
Table 7.33.
For Mealy FSM1, there are:
1. n(BC) = (K+1) models with three levels;
2. n(ABC) = 3G(K+1) models with four levels.
182 7 FSM Synthesis with Object Code Transformation
Table 7.33 Multilevel models of Mealy FSM with transformation of object codes
LA LB LC
M
1
M
1
C M
1
L
.
.
.
M
G
M
G
C M
G
L
PC
A
PC
Y
Y
D
1
.
.
.
D
K
For Mealy FSM2, there are:
1. n(BC) = (K+1) models with two levels;
2. n(ABC) = 3G(K+1) models with three levels.
In common case there are n
1
=6GK+6G+2K+2 different models of Mealy FSM
with object code transformation. If G = K = 6, then there are n
1
= 268 different
models.
Let us discuss an example of logic synthesis for the MPLC
Y
D
K
Mealy FSM S
21
(Table 7.7). This model is shown in Fig. 7.24.
Fig. 7.24 Structural dia-
gram of MPLC
Y
D
K
Mealy
FSM
Start
Clock
RG
P
Z
BP
Ժ
TMS
V
Y
BD
T
X
BM
W
Լ
In this model, the block TMS generates input memory functions loading codes of
states a
m
∈ A into the register RG, as well as functions Ψ =Ψ(Z,V), used as vari-
ables for encoding of logical conditions x
l
∈ X. Synthesis method for MPLC
Y
D
K
Mealy FSM includes the following steps:
1. Logical condition replacement and construction of the set P.
2. Logical condition encoding and construction of the set τ.
3. Finding of the classes of compatible microoperations, encoding of microopera-
tions and construction of the set Z.
4. Identification of states a
m
∈ A by pairs α
t,m
= Y
t
, I
k
and construction of the
set V.
5. Construction of transformed structure table and systems Z = Z(T, P) and Z =
Z(T, P).
6. Specification of the block TMS and deriving systems Φ and τ.
7. Implementation of the FSM logic circuit.
7.4 Multilevel Models of FSM with Object Code Transformation 183
For the MPLC
Y
D
K
Mealy FSM S
21
, there are the following sets of logical con-
ditions: X(a
1
) = {x
1
}, X(a
2
) = {x
2
, x
3
}, X(a
3
) = {x
4
}, X(a
4
) = / 0, and X(a
5
) =
{x
2
, x
3
, x
4
}. It means that G = 3 and logical conditions are replaced by variables
fromthe set P={p
1
, p
2
, p
3
}. The outcome of logical condition distribution is shown
in Table 7.34.
Table 7.34 Replacement of logical conditions for FSM S
21
a
m
a
1
a
2
a
3
a
4
a
5
p
1
x
1
x
2
– – x
2
p
2
– x
3
– – x
3
p
3
– – x
4
– x
4
As follows from Table 7.34, the identities p
2
= x
3
and p
3
= x
4
take place. It
means that there is only one multiplexer in the block BM. To encode the logical
conditions x
l
∈ X(p
1
), it is enough only one variable from the set τ = {τ
1
}. Let
K(x
1
) = 0 and K(x
2
) = 1. There are two classes of compatible microoperations,
namely Y
1
= {y
1
, y
3
, y
4
, y
5
} and Y
2
={y
2
, y
6
, y
7
}. The codes of microoperations are
shown in Table 7.5. From this table we can find the set of variables Z = {z
1
, . . . , z
5
}.
To identify the states, let us find sets A(Y
t
), where Y
1
= / 0, Y
2
= {y
1
, y
2
}, Y
3
=
{y
3
}, Y
4
= {y
4
}, Y
5
= {y
2
, y
5
}, Y
6
= {y
6
}, Y
7
= {y
3
, y
7
}. For the MPLC
Y
D
K
Mealy
FSM S
21
, the following sets can be found: A(Y
1
) = {a
1
}, A(Y
2
) = {a
2
, a
4
}, A(Y
3
) =
{a
3
}, A(Y
4
) = {a
3
}, A(Y
5
) = {a
4
}, A(Y
6
) = {a
5
}, and A(Y
7
) = {a
5
}. Now we can
find the pairs α
t,m
for identification of states a
m
∈ A, namely: α
1,1
= Y
1
, / 0, α
2,2
=
Y
2
, I
1
, α
2,4
= Y
2
, I
2
, α
3,3
= Y
3
, / 0, α
4,3
= Y
4
, / 0, α
5,4
= Y
5
, / 0, α
6,5
= Y
6
, / 0,
and α
7,5
= Y
7
, / 0. Obviously, there are two identifiers included into the set I =
{I
1
, I
2
}; it is enough only one variable v
1
for their encoding (V ={v
1
}). Let K(I
1
) =
0 and K(I
2
) = 1.
The transformed structure table of MPLC
Y
D
K
Mealy FSM includes the columns
a
m
, K(a
m
), P
h
, Z
h
, V
h
, h. The column Z
h
contains variables z
q
∈ Z, equal to 1 in the
code K(Y
h
). The column V
h
contains variables v
r
∈ V, equal to 1 in the identifier
code for state a
s
from the row h of initial ST. For the MPLC
Y
D
K
Mealy FSM S
21
,
this table is shown in Table 7.35.
The systems Z = Z(T, P) and Z = Z(T, P) can be derived from the trans-
formed ST. For example, the following systems z
1
= F
6
= A
3
p
3
=
¯
T
1
T
2
T
3
p
3
and
v
1
= F
5
=A
2
¯ p
1
¯ p
2
=
¯
T
1
T
2
¯
T
3
¯ p
1
¯ p
2
can be derived from Table 7.35.
The code transformer is specified by a table having columns α
t,m
, C(a
m
)
t
, a
m
,
K(a
m
), Φ
m
, K(x
1
), Ψ
m
, m. The column C(a
m
)
t
contains the code of state a
m
, deter-
mined by the concatenation K(Y
t
) ∗ K(I
k
). The column Φ
m
includes input memory
functions D
r
, equal to 1 for loading the code K(a
m
) into register RG . The column
Ψ
m
includes variables ψ
r
∈Ψ, equal to 1 in the code K(x
1
) of logical condition de-
termined the transition into state a
m
∈ A. For the MPLC
Y
D
K
Mealy FSM S
21
, the
block TMS is specified by Table 7.36.
184 7 FSM Synthesis with Object Code Transformation
Table 7.35 Transformed structure table of MPLC
Y
D
K
Mealy FSM S
21
a
m
K(a
m
) P
h
Z
h
V
h
h
a
1
000 p
1
z
2
z
5
– 1
¯ p
1
z
2
– 2
a
2
010 p
1
z
3
z
5
– 3
¯ p
1
p
2
z
2
z
3
– 4
¯ p
1
¯ p
2
z
3
z
5
v
1
5
a
3
011 p
3
z
1
z
5
– 6
¯ p
3
z
4
– 7
a
4
100 1 z
2
z
4
z
5
– 8
a
5
101 p
1
p
2
z
3
z
5
– 9
p
1
¯ p
2
z
2
– 10
¯ p
1
p
3
z
2
z
4
z
5
– 11
¯ p
1
¯ p
3
– – 12
Table 7.36 Specification of block TMS for MPLC
Y
D
K
Mealy FSM S
21
a
m
C(a
m
)
t
α
t,m
K(a
m
) Φ
m
K(x
1
) Ψ
m
m
a
1
00000∗ α
1,1
000 – 0 – 1
a
2
001010 α
2,2
010 D
2
1 ψ
1
2
a
3
01000∗ α
3,3
011 D
2
D
3
– – 3
a
3
01100∗ α
4,3
011 D
2
D
3
– – 4
a
4
001011 α
2,4
100 D
1
– – 5
a
4
10001∗ α
5,4
101 D
1
– – 6
a
5
00010∗ α
6,5
110 D
1
D
3
– – 7
a
5
01011∗ α
7,5
110 D
1
D
3
– – 8
This table is used to derive the systems and Ψ. The SOPs D
2
= F
2
∨F
3
∨F
4
=
¯ z
1
¯ z
2
z
3
¯ z
4
z
5
¯ v
1
∨¯ z
1
z
2
z
3
¯ z
4
¯ z
5
∨¯ z
1
z
2
¯ z
3
¯ z
4
¯ z
5
andΨ
1
=F
2
can be derived, for example, from
Table 7.36. The logic circuit of MPLC
Y
D
K
Mealy FSM S
21
is shown in Fig. 7.25.
Let us discuss an example of logic synthesis for the MPC
A
Y Mealy FSM S
21
,
represented by its structure table (Table 7.7). The structural diagram for this model
is shown in Fig. 7.26. This model includes four combinational blocks (BM, BP,
TSM, and BY) and the register RG. For this model, state codes are transformed into
microoperations of FSM.
Synthesis method for MPC
A
Y Mealy FSM includes the following steps:
1. Logical condition replacement and construction of the set P.
2. Encoding of collections of microoperations and construction of set Z.
3. Construction of the set with pairs α
t,m
, identified collections of microoperations,
and finding the set V of variables, encoding identifiers I
k
∈ I.
4. Construction of the transformed ST and deriving functions Φ = Φ(Z,V) and
V =V(T, P).
5. Specification of the block TSM and construction of the system Z = Z(T, P).
7.4 Multilevel Models of FSM with Object Code Transformation 185
Fig. 7.25 Logic circuit of
MPLC
Y
D
K
Mealy FSM S
21
PLD
11
1
2
3
4
5
6
1
2
3
4
12
13
14
15
17
D
2
x
1 1
x
2 2
x
3 3
18
D
3 19
Լ
1
16
4
6
7
x
4
5
W
1
W
2
8
Start
Clock
20
D
1
MX
0
1
1
1
2
PLD
8
1
2
3
4
5
6
1
2
3
4
5
6
9
10
21
22
11
z
2 12
z
3 13
23
z
1
14
z
5 15
v
1 16
z
4
DC
1
1
2
3
0
1
2
3
4
5
6
7
11
12
13
y
1
y
3
y
4
y
5
DC
2
1
2
0
1
2
3
14
15
y
2
y
6
y
7
RG
D
1
D
2
D
3
D
4
R
C
1
2
3
4
17
18
19
20
21
22
8
23
T
1
T
2
T
3
5
T
4
9
5
P
1
8
P
2
9 3
P
3
10 4
Fig. 7.26 Structural dia-
gram of MPC
A
Y Mealy
FSM
Start
Clock
RG
P
Z
BP
Ժ
TSM
T
Y
BY
V
X
BP
6. Construction of the table of microoperations and system Y =Y(Z).
7. Implementation of FSM logic circuit.
As it was found before for the FSM S
21
, the set P includes three elements, distri-
bution of logical conditions x
l
∈ X among elements of the set P = {p
1
, p
2
, p
3
} is
shown in Table 7.34.
The initial ST includes T
0
= 7 collections of microoperations, namely: Y
1
= / 0,
Y
2
={y
1
, y
2
}, Y
3
={y
3
}, Y
4
={y
4
}, Y
5
= {y
2
, y
5
}, Y
6
={y
6
}, and Y
7
={y
3
, y
7
}. It is
enough Q = 3 variables from the set Z = {z
1
, z
2
, z
3
} for these collections encoding.
Let the collections have the following codes:K(Y
1
) = 000, . . ., K(Y
7
) = 110.
The initial ST determines pairs α
1,1
=a
1
, / 0 α
2,2
=a
2
, I
1
α
3,3
=a
3
, I
1
α
3,4
=
a
3
, I
2
α
4,2
= a
4
, I
1
, α
4,5
= a
4
, I
2
, α
5,6
= a
5
, I
1
, α
5,7
= a
5
, I
2
. Thus, there is
a set I = {I
1
, I
2
}, such that its elements can be encoded using one variable v
l
∈V. If
K(I
1
) = 0 and K(I
2
) = 1, then the codes C(Y
t
)
m
of collections Y
t
⊆Y are shown in
Table 7.37.
There is only one difference between transformed structure tables of MPC
A
Y
and MC
A
YMealy FSMs. Namely, in the first case the column X
h
is replaced by the
column P
h
(Table 7.38).
This table is used to derive functions Φ =Φ(P, X) and V =V(P, X). For example,
the equations D
3
= F
2
∨F
4
∨F
9
∨F
10
= A
1
¯ p
1
∨. . . =
¯
T
1
¯
T
2
¯
T
3
p
1
∨. . ., v
1
= F
4
∨F
6

∨F
8
∨F
11
= A
2
¯ p
1
p
2
∨. . . =
¯
T
1
T
2
¯
T
3
¯ p
1
p
2
∨. . .can be derived from Table 7.38.
186 7 FSM Synthesis with Object Code Transformation
Table 7.37 Codes of collections of microoperations for MPC
A
Y Mealy FSM S
21
Y
t
α
t,m
C(Y
t
)
m
h Y
t
α
t,m
C(Y
t
)
m
h
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
Y
1
α
1,1
0 0 0 ∗ 1 Y
4
α
3,4
1 1 0 * 5
Y
2
α
2,2
0 1 0 ∗ 2 Y
5
α
4,5
1 0 0 1 6
α
4,2
1 0 0 0 3 Y
6
α
5,6
1 0 1 0 7
Y
3
α
3,3
0 1 1 0 4 Y
7
α
5,7
1 0 1 1 8
Table 7.38 Transformed structure table of MPC
A
Y Mealy FSM S
21
a
m
K(a
m
) a
s
K(a
s
) P
h
I
h
K(I
h
) V
h
Φ
h
h
a
1
000 a
2
010 ∗ ∗ – D
2
1
a
3
011 ¯ p
1
I
1
0 – D
2
D
3
2
a
2
010 a
2
010 ∗ ∗ – D
2
3
a
3
011 ¯ p
1
p
2
I
2
1 v
1
D
2
D
3
4
a
4
100 ¯ p
1
¯ p
2
I
1
0 – D
1
5
a
3
011 a
4
100 p
3
I
2
1 v
1
D
1
6
a
5
101 ¯ p
3
I
1
0 – D
1
D
3
7
a
4
100 a
5
101 1 I
2
1 v
1
D
1
D
3
8
a
5
101 a
2
010 p
2
∗ ∗ – D
2
9
a
3
011 ¯ p
2
I
1
0 – D
2
D
3
10
a
5
101 ¯ p
1
p
3
I
2
1 v
1
D
1
D
3
11
a
1
000 ¯ p
1
¯ p
3
∗ ∗ – – 12
For the MPC
A
Y Mealy FSM S
21
, the table of block TSM agrees with Table 7.3,
whereas the table of microoperations with Table 7.4. The logic circuit of the MPC
A
Y
Mealy FSM S
21
is shown in Fig. 7.27.
PLD
10
1
2
3
4
5
6
1
2
3
4
11
12
5
6
13 D
1
RG
D
1
D
2
D
3
R
C
1
2
3
13
14
15
8
5
6
9
7
x
1 1
x
2 2
x
3 3
14
D
2
15 D
3
7
T
1
T
2
T
3
4
6
7
x
4
5
T
1
T
2
PROM
1
2
3
1
2
3
4
5
6
7
17
18
19
y
1
y
2
y
3
y
4
8
Start
Clock 9
T
3
16
PLD
5
1
2
3
4
1
2
3
6
7
16
17
18
v
1
z
2
z
3
z
1
19
y
5
y
6
y
7
MX
0
1
2
3
4
5
6
7
8
1
2
3
1
2
2
P
1
10
P
2
9 3
P
3
10 4
5
6
7
Fig. 7.27 Logic circuit of the MPC
A
Y Mealy FSM S
21
7.4 Multilevel Models of FSM with Object Code Transformation 187
Table 7.39 Multilevel models of Moore FSM with transformation of object codes
LA LB LC
M
1
M
1
C M
1
L
.
.
.
M
G
M
G
C M
G
L
PC
A
P
0
C
A
P
C1
C
A
. . . P
C4
C
A
P
C1
C
Y
. . . P
C4
C
Y
PC
Y
P
0
C
Y
Y
D
1
.
.
.
D
K
To reduce the hardware amount in logic circuit of Moore FSM with object code
transformation, the following methods can be used: the transformation of initial
GSA, the refined state encoding, the transformation of state codes into the codes of
logical conditions, and the verticalization of initial GSA. All possible Moore FSM
models are shown in Table 7.39.
The following numbers of Moore FSM multilevel models can be found from
Table 7.39:
1. NL
3
= 12(K +1). It is the number of models with encoding of collections of
microoperations.
2. NL
4
= 36G(K+1). It is the number of models with both encoding of collections
of microoperations and logical condition replacement.
Thus, the total number of different models of Moore FSM with object code trans-
formation is equal to 36G+12K+36GK+12. For interpretation of some GSA Γ,
there are 1596 different models for Moore FSM with average complexity, that is
G = I = 6 [1].
In common case, there are n
1
= 268 different models of Mealy FSM and n
2
=
1596 different models of Moore FSM for interpretation of the same GSA Γhaving
G = I = 6. It means that such a control algorithm can be implemented using at least
n =n
1
+n
2
=1864 different models of FSMwith object code transformation. Such a
huge plurality of possible solutions increases importance of the problem connected
with a-priory choice of the optimal solutions. This problem can be solved using
some rules and characteristics of both a GSA to be interpreted and logic elements to
be used.
Let us discuss an example of logic synthesis for the MP
0
LC
A
Y Moore FSM S
22
specified by its ST (Table 7.14). The structural diagram of MP
0
LC
A
Y Moore FSM
is shown in Fig. 7.28.
In this model, the block BM implements functions P = P(τ, X) and it is used
for the replacement of logical conditions x
e
∈ X the block BP generates functions
Φ =Φ(T, P) used for loading of the code of collections of microoperations C(Y
t
)
m
into the register RG; the block CCS generates variables τ =τ(T) used for encoding
of logical conditions x
l
∈ X; the block TSM generates variables Z = Z(T) used for
encoding of collections of microoperations; the block BY generates microoperations
Y =Y(Z). The synthesis method for MP
0
LC
A
Y Moore FSM includes the following
steps:
188 7 FSM Synthesis with Object Code Transformation
Start
Clock
RG
P
Z
BP
Ժ
TSM
T
Y
BY
W
X
BM
CCS
Fig. 7.28 Structural diagram of MP
0
LC
A
Y Moore FSM
1. Optimal encoding for states a
m
∈ A.
2. Encoding of logical conditions x
l
∈ X.
3. Logical condition replacement and construction of functions P.
4. Identification of collections of microoperations by states a
m
∈ A.
5. Construction of transformed structure table and functions Φ.
6. Specification of block CCS and construction of system τ.
7. Encoding of collections and specification of block BY.
8. Specification of block TSM and construction of system Z.
9. Implementation of FSM logic circuit using some logic elements.
For the MP
0
LC
A
Y Moore FSM S
22
, there is the partition Π
A
of the state set A by the
three classes of pseudoequivalent states, namely: B
1
= {a
1
}, B
2
= {a
2
, a
3
, a
4
, a
7
},
and B
3
= {a
5
, a
6
}. One of the possible variants for the optimal state encoding is
shown in Fig. 7.29.
Fig. 7.29 Optimal state
codes for Moore FSM S
22
T
1
a
1
a
2
a
3
a
5
a
4
a
7
a
6
0
1
00 01 11 10
T
2
T
3
*
The following codes of the classes can be found from Fig. 7.29:K(B
1
) = ∗00,
K(B
2
) = ∗ ∗ 1 and K(B
3
) = ∗10. As it follows from these codes, there is no con-
nection between the block BP and the state variable T
1
. For the MP
0
LC
A
Y Moore
FSM S
22
, the outcome of distribution of the logical conditions for their replacement
is shown in Table 7.40.
As follows from Table 7.40, the block BM of MP
0
LC
A
Y Moore FSM S
22
is
characterized by the sets P = {p
1
, p
2
}, X(p
1
) = {x
1
, x
4
}, and X(p
2
) = {x
2
, x
3
}. It
is enough the variable τ
1
for encoding of logical conditions x
l
∈ X(p
1
), whereas the
variable τ
2
can be used for encoding of logical conditions x
l
∈ X(p
2
). Thus, there
is the set τ = {τ
1
, τ
2
}. Let us encode the logical conditions in the following way:
K(x
1
) = 0, K(x
4
) = 1, K(x
2
) = 0, and K(x
3
) = 1.
There are T
0
= 4 different collections of microoperations in Table 7.14, namely:
Y
1
= / 0, Y
2
= {y
1
, y
2
}, Y
3
= {y
3
}, and Y
4
= {y
3
, y
4
}. As it is found before, these
7.4 Multilevel Models of FSM with Object Code Transformation 189
Table 7.40 Distribution of logical conditions for Moore FSM S
22
a
m
a
1
a
2
a
3
a
4
a
5
a
6
a
7
p
1
x
1
– x
4
– x
4
x
4

p
2
x
2
x
3
x
3
x
3
– – x
3
Table 7.41 Transformed ST of MP
0
LC
A
Y Moore FSM S
22
B
i
K(B
i
) a
s
K(a
s
) P
h
Φ
h
h
B
1
∗00 a
2
001 D
3
1
a
3
011 ¯ p
1
p
2
D
2
D
3
2
a
4
101 ¯ p
1
¯ p
2
D
1
D
3
3
B
2
∗01 a
5
010 p
2
D
2
4
a
6
110 ¯ p
2
D
1
D
2
5
B
3
∗10 a
7
111 D
1
D
2
D
3
6
a
1
000 ¯ p
1
– 7
collections are identified by the following codes:C(Y
1
)
1
= 000, C(Y
2
)
2
= 001,
C(Y
2
)
4
= 101, C(Y
2
)
6
= 110, C(Y
3
)
3
= 010, C(Y
4
)
5
= 010, and C(Y
4
)
7
= 111. The
transformed ST of MP
0
LC
A
Y Moore FSM S
22
includes H
0
= 7 rows (Table 7.41).
This table is used to derive the system of input memory functions. For example,
the following Boolean equation can be derived fromTable 7.41: D
1
=F
3
∨F
5
∨F
6
=
B
1
¯ p
1
¯ p
2
∨B
2
¯ p
2
∨B
3
p
1
=
¯
T
1
¯
T
3
¯ p
1
¯ p
2
∨T
3
¯ p
2
∨T
2
¯
T
3
p
1
.
The table for block CCS includes columns a
m
, K(a
m
), p
1
, p
2
, K(p
1
), K(p
2
), τ
m
,
m. In this table, the column K(p
q
) contains the code K(x
l
) of some logical condition
x
l
∈ X, replaced by the variable p
q
for the state a
m
. The column τ
m
of the table
includes variables τ
r
∈ τ equal to 1 in the row m. For the MP
0
LC
A
YMoore FSM
S
22
, the block CCS is specified by Table 7.42.
It is enough Q = 2 variables from the set Z = {z
1
, z
2
} for encoding of collec-
tions Y
t
⊆Y. If K(Y
1
) = 00, . . ., K(Y
4
) = 11, then the table of microoperations for
discussed example is the same as Table 7.15.
Table 7.42 Specification of block CCS for MP
0
LC
A
Y Moore FSMS
22
a
m
K(a
m
) p
1
p
2
K(p
1
) K(p
2
) τ
m
m
a
1
000 x
1
x
2
0 0 – 1
a
2
001 – x
3
– 1 τ
2
2
a
3
011 – x
3
– 1 τ
2
3
a
4
101 – x
3
– 1 τ
2
4
a
5
101 x
2
– 1 – τ
1
5
a
6
110 x
2
– 1 – τ
1
6
a
7
111 – x
3
– 1 τ
2
7
190 7 FSM Synthesis with Object Code Transformation
Table 7.43 Specification of block TSM for MP
0
LC
A
Y Moore FSM S
22
a
m
Y
t
C(Y
t
)
m
K(Y
t
) Z
m
m
a
1
Y
1
000 00 – 1
a
2
Y
2
001 01 z
2
2
a
3
Y
3
011 10 z
1
3
a
4
Y
2
101 01 z
2
4
a
5
Y
4
010 11 z
1
z
2
5
a
6
Y
2
110 01 z
1
6
a
7
Y
4
111 11 z
1
z
2
7
Fig. 7.30 Logic circuit of
MP
0
LC
A
Y Moore FSM S
22
RG D
1
D
2
D
3
R
C
1
2
3
11
12
13
7
14
15
8
16
x
1 1
x
2 2
x
3 3
T
1
T
2
T
3
4
6
7
Start
Clock
x
4
8
5
W
1
W
2
PROM
1
2
1
2
3
4
17
18
y
1
y
2
y
3
y
4
PROM
14
1
2
3
1
2
3
4
15
16
17
18
z
2
W
3
z
1
5
W
4 6
PLD
10
1
2
3
4
1
2
3
10
11
12
D
2
D
3
D
1
13
15
16
MX
0
1
1
1
4
5
P
1
8
MX
0
1
1
2
3
6
P
2
10
The table of block TSM includes columns a
m
, Y
t
, C(Y
t
)
m
, K(Y
t
), Z
m
, m. The
column Z
m
includes variables z
q
∈Z, equal to 1 in the code K(Y
t
). For the MP
0
LC
A
Y
Moore FSM S
22
, the block TSM is specified by Table 7.43. Obviously, this table can
be viewed as a truth table for functions Z. The best way for its implementation is
use of embedded memory blocks. As follows from Table 7.42 and Table 7.43, both
code transformers have the same inputs. It means that both systems τ and Z can be
implemented using the common block TSM.
The logic circuit of MP
0
LC
A
Y Moore FSM S
22
is shown in Fig. 7.30. The dis-
cussed examples give a key for logic synthesis of any multilevel FSM model repre-
sented by Table 7.33 and Table 7.39.
References
1. Baranov, S.I.: Logic Synthesis of Control Automata. Kluwer Academic Publishers,
Dordrecht (1994)
2. Barkalov, A., Barkalov Jr., A.: Design of mealy finite-state machines with the transfor-
mation of object codes. International Journal of Applied Mathematics and Computer
Science 15(1), 151–158 (2005)
References 191
3. Barkalov, A., Barkalov, A.: Synthesis of finite state machines with transformation of the
object’s codes. In: Proc. of the Inter. Conf. TCSET 2004, Lviv, Ukraina, pp. 61–64. Lviv
Polytechnic National University, Publishing House of Lviv Polytechnic, Lviv (2004)
4. Barkalov, A., Titarenko, L.: Synthesis of Operational and Control Automata. UNITECH,
Donetsk (2009)
5. Barkalov, A., Titarenko, L., Barkalov Jr., A.: Moore fsm synthesis with coding of com-
patible microoperations fields. In: Proc. of IEEE East-West Design & Test Symposium -
EWDTS 2007, Yerevan, Armenia, pp. 644–646. Kharkov National University of Radio-
electronics, Kharkov (2007)
6. Barkalov, A., Wêgrzyn, A., Barkalov Jr., A.: Synthesis of control units with transformation
of the codes of objects. In: Proc. of the IXth Inter. Conf. CADSM 2007, Lviv - Polyana,
Ukraine, pp. 260–261. Lviv Polytechnic National University, Publishing House of Lviv
Polytechnic National University, Lviv (2007)
7. Barkalov, A.A.: Principles of optimization of logic circuit of Moore FSM. Cybernetics
and System Analysis (1), 65–72 (1998) (in Russian)
8. Minns, P., Elliot, I.: FSM-based digital design using Verilog HDL. John Wiley and Sons,
Chichester (2008)
Chapter 8
FSM Synthesis with Elementary Chains
Abstract. The chapter is devoted to original methods oriented on optimization of
Moore FSM interpreting graph-schemes of algorithms with long sequences of op-
erator vertices having only one input. These sequences are named elementary op-
erational linear chains (EOLC). These FSM models include the counter keeping,
either microinstruction addresses or code of EOLC component. In the beginning
the Moore FSM models with code sharing are analysed, where the register keeps
EOLC codes. The methods of EOLC encoding and transformation are discussed;
these methods permit to decrease the number of macrocells in the block generat-
ing input memory functions. The second part of the chapter is devoted to reduction
of the number of embedded memory blocks in the FSM block generating micro-
operations. These methods are based on transformation of microinstruction address
represented as concatenation of EOLC code and code of its component into either
linear microinstruction address or code of collection of microoperations. The last
part of the chapter discusses synthesis methods for multilevel FSM models with
EOLC.
8.1 Basic Models of FSM with Elementary Chains
Definitions of the OLC, its input and output can be found in Section 1.4. An ele-
mentary operational linear chain (EOLC) is a particular case of OLC. Such a chain
has only one input. These control units are known as compositional microprogram
control units [2], but they are based on the model of Moore FSM. Let us name such
control units as P
EC
Y Moore FSM. The structural diagram of P
EC
Y Moore FSM is
shown in Fig. 8.1.
In P
EC
Y Moore FSM, the block BP generates input memory functions to change
the content of a counter CT
Φ =Φ(T, X), (8.1)
whereas the block BY keeps collections of microoperations (microinstructions)
Y(b
t
) ⊆Y, as well as variables y
0
(to control the mode of counter synchronization)
A. Barkalov and L. Titarenko: Logic Synthesis for FSM-Based Control Units, LNEE 53, pp. 193–227.
springerlink.com c Springer-Verlag Berlin Heidelberg 2009
194 8 FSM Synthesis with Elementary Chains
Fig. 8.1 Structural diagram
of P
EC
Y Moore FSM
ͳ΁
΄ΥΒΣΥ
ʹΝΠΔΜ
Ή
Ί
ʹ΅
͜͢
Ժ
Ί
͡
ͳΊ
΅
΃
΄
΅ͷ
΄ΥΒΣΥ
ͷΖΥΔΙ
and y
E
(to control the fetching of microinstructions). These functions are repre-
sented as
Y = Y(T), (8.2)
y
0
= y
0
(T), (8.3)
y
E
= y
E
(T). (8.4)
Let C
E
= ¦α
1
, . . . , α
G
E
¦ be a set of EOLC. If a transition is executed between the
elements of the same EOLC, then the counter is incremented according with (1.28).
If a transition is executed between the output of EOLC α
i
∈ C
E
and the input of
EOLC α
j
∈C
E
(of course, it can be the same EOLC), then an address of transition
is generated by the block BP as it is determined by (1.29). This FSM operates in the
following manner.
The pulse ”Start” initializes the following actions: the zero address of the first
microinstruction is loaded into counter CT; the flip-flop TF is set up (Fetch=1). A
current microinstruction is read out the block BY. If y
0
=1 for this microinstruction,
then 1 is added to the content of counter CT. Otherwise, the output of current EOLC
is reached and the block BP generates the next microinstruction address. If y
E
= 1,
then the output of control algorithm(correspondingto the microprogram) is reached.
In this case the flip-flop TF is cleared and microinstruction fetching is terminated.
The synthesis method of P
EC
Y Moore FSM includes the following steps [2]:
1. Transformation of the initial GSAΓ.
2. Construction of the EOLC set for transformed GSA Γ.
3. Natural addressing of microinstructions.
4. Construction of FSM structure table.
5. Specification of block BY.
6. Synthesis of logic circuit with given logic elements.
Let us discuss an example of design for the Moore FSM S
25
represented by the
graph-scheme of algorithmΓ
6
(Fig. 8.2).
1. Transformation of initial GSAΓ is executed in the following manner [2]:
• if there is an arc 'b
0
, b
q
` ∈E, where b
q
∈B
2
, some vertex b
t
∈B
1
is introduced
into GSA Γ, where Y(b
t
) = / 0, and the initial arc is replaced by a pair of new
arcs 'b
0
, b
t
` and 'b
t
, b
q
`;
8.1 Basic Models of FSM with Elementary Chains 195
ͶΟΕ
΄ΥΒΣΥ
Ω
͢
͢ ͡
Ϊ
͢
Ϊ
ͥ
Γ
ͤ
Ϊ
ͤ
Ϊ
ͣ
Ϊ
ͤ
Γ
ͨ
Γ
ͥ͢
Ϊ
ͣ
Ϊ
ͦ
Ϊ
ͦ
Γ
ͩ
Γ
ͦ͢
Ϊ
͢
Ϊ
ͥ
Ϊ
ͦ
Ϊ
͢
Ϊ
ͤ
Γ
ͪ
Γ
ͧ͢
Ϊ
ͥ
Ϊ
ͣ
Ϊ
ͦ
Γ
͢͡
Γ
ͨ͢
Ϊ
͢
Ϊ
ͣ
Ϊ
ͥ
Γ
͢͢
Ϊ
ͦ
Γ
ͣ͢
Ϊ
͢
Ϊ
ͥ
Γ
ͤ͢
Ϊ
͢
Ϊ
ͣ
Ϊ
ͤ
Γ
͢
Γ
ͣ
Γ
͡
Ω
ͣ
͢ ͡
Ϊ
ͤ
Γ
ͥ
Ϊ
ͣ
Ϊ
ͦ
Γ
ͦ
Ϊ
͢
Ϊ
ͣ
Γ
ͧ
Ω
ͣ
͢ ͡
Ω
ͤ
͢ ͡
Ω
ͥ
͢ ͡
Ϊ
͢
Ϊ
Ͷ
Γ
ͩ͢
Γ
Ͷ
Fig. 8.2 Initial graph-scheme of algorithmΓ
6
196 8 FSM Synthesis with Elementary Chains
• if there is an arc 'b
t
, b
E
` ∈ E, where b
t
∈ B
2
, then some vertex b
q
∈ B
1
with
y
E
is introduced into GSA and the initial arc is replaced by two arcs 'b
t
, b
q
`
and 'b
q
, b
E
`;
• if there is an arc 'b
t
, b
E
` ∈ E, where b
t
∈ B
1
, then the variable y
E
is inserted
into the vertex b
t
.
2. Construction of the set of EOLC. There are two stages in this step exe-
cution. The first stage is reduced to construction of the set of EOLC inputs
I(Γ). The second stage is connected with construction of EOLC for each ele-
ment of the set I(Γ). In the discussed example, this set includes eight elements
I(Γ
6
) = ¦b
1
, b
3
, b
4
, b
7
, b
10
, b
11
, b
14
, b
18
¦. The EOLC α
1
is constructed in the fol-
lowing manner. Let us take the vertex b
1
∈I(Γ
6
), which is treated as the input I
1
of
EOLC α
1
. Let us analyze transitions from the vertex b
1
. There is the arc 'b
1
, b
2
`
in the GSA Γ
6
. The vertex b
2
∈ B
1
and this vertex does not belong to the set
of inputs. Therefore, the vertex b
2
is the second component of EOLC α
1
. Let us
analyze transitions from the vertex b
2
. There is the arc 'b
2
, b(x
1
)`in the GSA Γ
6
,
such that b(x
1
) ∈ B
2
. Thus, the vertex b
2
is the output O
1
of EOLC α
1
='b
1
, b
2
`.
Construction of any EOLC is terminated, if an analyzed vertex belongs to the
set I(Γ), or if it is the final vertex b
E
. Let the symbol L
g
stand for the number
of components in EOLC α
g
. In case of the GSA Γ
6
, the following set of EOLC
C
E
= ¦α
1
, . . . , α
8
¦ can be found, where α
1
= 'b
1
, b
2
`, I
1
= b
1
, O
1
= b
2
, L
1
= 2;
α
2
= 'b
3
`, I
2
= O
2
= b
3
, L
2
= 1; α
3
= 'b
4
, b
5
, b
6
`, I
3
= b
4
, O
3
= b
6
, L
3
= 3;
α
4
= 'b
7
, b
8
, b
9
`, I
4
= b
7
, O
4
= b
9
, L
4
= 3; α
5
= 'b
10
`, I
5
= O
5
= b
10
, L
5
= 1;
α
6
= 'b
11
, b
12
, b
13
`, I
6
= b
11
, O
6
= b
13
, L
6
= 3; α
7
= 'b
14
, . . . , b
17
`, I
7
= b
14
,
O
7
= b
17
, L
7
= 4; α
8
= 'b
18
`, I
8
= O
8
= b
18
, L
8
= 1.
3. Natural addressing of microinstructions. This step is reduced to construction
of the table of addressing, similar to Karnaugh map. The number of address vari-
ables is determined as
R
E
= log
2
M
E
|. (8.5)
In (8.5), the symbol M
E
denotes the number of operator vertices in the trans-
formed GSA. In the discussed example, we have R
E
= 5 and T = ¦T
1
, . . . , T
5
¦.
The addresses of microinstructions are shown in Fig. 8.3.
T1T2
b
1
b
2
b
3
b
8
b
9
b
10
b
11
b
16
b
17
b
18
b
7
b
15
b
6
b
14
b
5
b
13
b
4
b
12
00
01
11
10
000 001 010 011
T1T2T3
100 101 110 111
* * *
* * *
* * *
* * *
* *
Fig. 8.3 Microinstruction addresses for P
EC
Y Moore FSM S
25
8.1 Basic Models of FSM with Elementary Chains 197
4. Construction of FSM structure table assumes finding the system of general-
ized formulae of transition (GFT) for EOLC outputs α
g
∈ C
E
. In the discussed
case, this system includes G
E
−1 = 7 following formulae:
α
1
→ x
1
I
2
∨ ¯ x
1
x
2
I
3
∨ ¯ x
1
¯ x
2
I
4
;
α
2
→ I
3
;
α
3
→ x
2
x
4
I
3
∨x
2
¯ x
4
I
5
∨ ¯ x
2
x
3
I
6
∨ ¯ x
2
¯ x
3
I
7
;
α
4
→ x
2
x
4
I
3
∨x
2
¯ x
4
I
5
∨ ¯ x
2
x
3
I
6
∨ ¯ x
2
¯ x
3
I
7
;
α
5
→ I
6
;
α
6
→ I
8
;
α
7
→ I
8
.
(8.6)
This system serves to construct the FSM structure table having the following
columns: O
g
is an output of EOLC α
g
∈ C
E
; A(O
g
) is an address of the output
O
g
; I
j
is an input of EOLC α
j
∈C
E
; A(I
j
) is an address of input I
j
; X
h
is a set of
logical conditions determined the transition from O
g
into I
j
; Φ
h
is a set of input
memory functions. For the P
EC
Y Moore FSM S
25
, the structure table is shown in
Table 8.1.
Table 8.1 Structure table of P
EC
Y Moore FSM S
25
O
g
A(O
g
) I
j
A(I
j
) X
h
Φ
h
h
O
1
00001 I
2
00010 x
1
D
4
1
I
3
00011 ¯ x
1
x
2
D
4
D
5
2
I
4
00110 ¯ x
1
¯ x
2
D
3
D
4
3
O
2
00010 I
3
00011 1 D
4
D
5
4
O
3
00101 I
3
00011 x
2
x
4
D
4
D
5
5
I
5
01101 x
2
¯ x
4
D
2
D
3
D
5
6
I
6
01010 ¯ x
2
x
3
D
4
D
5
7
I
7
01101 ¯ x
2
¯ x
3
D
2
D
3
D
5
8
O
4
01000 I
3
00011 x
2
x
4
D
4
D
5
9
I
5
01101 x
2
¯ x
4
D
2
D
3
D
5
10
I
6
01010 ¯ x
2
x
3
D
4
D
5
11
I
7
01101 ¯ x
2
¯ x
3
D
2
D
3
D
5
12
O
5
01001 I
6
01010 1 D
2
D
4
13
O
6
01100 I
8
10101 1 D
1
D
3
D
5
14
O
7
10000 I
8
10101 1 D
1
D
3
D
5
15
This structure table is the base to construct functions of system (8.1). For
example, the following Boolean expression can be extracted from Table 8.1:
D
1
= F
14
∨F
15
=
¯
T
1
T
2
T
3
¯
T
4
¯
T
5
∨T
1
¯
T
2
¯
T
3
¯
T
4
¯
T
5
.
5. Specification of block BY is reduced to the replacement of vertices b
t
∈ B
1
by
collections of microoperations Y(b
t
). If a vertex b
t
= O
g
, then the variable y
0
is
inserted into the corresponding set Y(b
t
). For example, let us discuss execution
of this step for the EOLC α
6
='b
11
, b
12
, b
13
`. In this case the microoperations y
0
,
y
1
, y
2
, and y
4
are written into the cell with address 01010, the microoperations
y
0
, y
5
are written into the cell with address 01011, and the microoperations y
1
, y
4
198 8 FSM Synthesis with Elementary Chains
Table 8.2 Specification of block BY for P
EC
Y Moore FSM S
25
A(b
t
) Y(b
t
) t A(b
t
) Y(b
t
) t A(b
t
) Y(b
t
) t
00000 y
0
y
1
y
2
1 00110 y
0
y
3
7 01100 y
1
y
4
13
00001 y
3
2 00111 y
0
y
2
y
5
8 01101 y
0
y
2
y
3
14
00010 y
0
y
1
y
4
3 01000 y
1
y
4
y
5
9 01110 y
0
y
5
15
00011 y
0
y
3
4 01001 y
0
y
3
10 01111 y
0
y
1
y
3
16
00100 y
0
y
2
y
5
5 01010 y
0
y
1
y
2
y
4
11 10000 y
2
y
5
17
00101 y
1
y
2
6 01011 y
0
y
5
12 10001 y
1
y
E
18
are written into the cell with address 01100. The outcome of this step is shown
in Table 8.2.
Obviously, functions of systems (8.2) – (8.4) belong to the class of regular
functions and the best way for their implementation is use of embedded memory
blocks BRAM. If there are no BRAMs in FPLDs in use, then some table similar
to Table 8.2 is used to construct N +2 Karnaugh maps. These maps are used
to get minimized forms of functions y
n
∈ Y, y
0
and y
E
. For example, from the
Karnaugh map for the function y
1
∈Y the following minimized sum-of-products
y
1
=
¯
T
1
¯
T
3
¯
T
4
∨T
1
T
3
∨T
2
T
3
T
4
T
5

¯
T
2
T
3
¯
T
4
T
5
∨T
2
¯
T
4
¯
T
5
can be derived (taking into
account the "don’t care" input assignments from 10011 to 11111).
6. Implementation of FSM logic circuit is reduced to implementation of corre-
sponding circuits for systems (8.1) – (8.4) using given logic elements. We do not
discuss this step for the P
EC
Y Moore FSM S
25
.
The main drawback of P
EC
Y Moore FSM is the redundant number of feedback
variables, as it follows from (8.5). This number can be decreased using the prin-
ciple of code sharing [2],which can be explained as the following. Let GSA
Γ include G
E
different EOLC, and let each of them include M
g
components.
Let Q
E
= max(M
1
, . . . , M
G
E
). Obviously, it is enough R
EO
variables for EOLC
encoding:
R
EO
= log
2
G
E
|. (8.7)
These variables forma set τ. Next, it is enough R
CO
variables for encoding of EOLC
components:
R
CO
= log
2
Q
E
|. (8.8)
These variables form a set T. Let K(α
g
) and K(b
t
) be respectively a code of EOLC
α
g
∈C
E
and its component b
t
∈ B
1
. Then expression (1.33) determines an address
A(b
t
) of microinstruction corresponded to the vertex b
t
∈ B
1
.
Let microinstructions corresponded to components of each EOLC be addressed
using the principle of natural addressing. Let first components of each EOLC have
zero codes. In this case the GSA Γ can be interpreted by P
ES
Y Moore FSM having
the structural diagram shown in Fig. 8.4. The P
ES
Y Moore FSM operates in the
following manner.
Pulse ”Start” initiates loading of zero codes into both the register RG and
counter CT. Simultaneously, the flip-flop TF is set up and it allows generation of
8.1 Basic Models of FSM with Elementary Chains 199
Fig. 8.4 Structural diagram
of P
ES
Y Moore FSM
ͳ΁
΄ΥΒΣΥ
ʹΝΠΔΜ
Ή Ί
͜͢
Ί
͡
ͳΊ
΅
΃
΄
΅ͷ
΄ΥΒΣΥ
ͷΖΥΔΙ
ʹ΅
΃͸
Լ
͓͓͡
Ί
Ͷ
W
microinstructions by the block BY. If contents of RG and CT form an address of
microinstruction, which does not correspond to the output of some EOLC, then
pulse ”Clock” causes increment of CT. It corresponds to unconditional transitions
between adjacent components of the same EOLC. Otherwise, pulse ”Clock” causes
reset of CT, whereas the block BP loads into RG an input address of some other
EOLC. The following functions are used to form a microinstruction address:
ψ =ψ(τ, X). (8.9)
All other operation principles are the same for both P
ES
Y and P
EC
Y Moore FSM.
Procedures of their synthesis include the same steps, but sometimes there is some
difference in the execution of these steps. Let us discuss an example of logic syn-
thesis for the P
ES
Y Moore FSM S
25
represented by the GSAΓ
6
(Fig. 8.2).
Obviously, there are the same outcomes for such steps as GSA transformation
and EOLC construction for equivalent P
ES
Y and P
EC
Y Moore FSMs.
Natural microinstruction addressing is reduced to the natural addressing of
components of EOLC α
g
∈C
E
. In the discussed example, the following values and
sets can be found: R
EO
= 3, τ = ¦τ
1
, τ
2
, τ
3
¦, R
CO
= 2, and T = ¦T
1
, T
2
¦. Let us en-
code EOLC α
g
∈C
E
in a trivial way, namely: K(α
1
) = 000, . . ., K(α
8
) = 111. First
components of all EOLC have the code 00, second components of all EOLC have
the code 01, third components of all EOLChave the code 10, and fourth components
of all EOLC have the code 11. This procedure allows getting the microinstruction
addresses shown in Fig. 8.5.
T1T2
b
1
b
3
b
4
b
18
b
2
b
5
b
6
b
14
b
15
b
16
b
17
b
11
b
12
b
13
b
10
b
7
b
8
b
9
00
01
11
10
000 001 010 011
1 2 3
100 101 110 111
*
* * *
*
*
*
*
*
* *
*
*
*
Fig. 8.5 Microinstruction addresses for P
ES
Y Moore FSM S
25
200 8 FSM Synthesis with Elementary Chains
Construction of FSM structure table. This step is executed in two stages.
The first of them is construction of the system of generalized formulae of tran-
sitions. The GFT for our example is represented by system (8.6). The second
stage is construction of FSM structure table corresponding to this GFT. For the
P
ES
Y Moore FSM S
25
, it is Table 8.3. This table is the base to derive system
(8.8). For example, the following sum-of-products can be derived from Table 8.3:
D
1
= F
6
∨F
7
∨F
8
∨F
10
∨. . . ∨F
15
= ¯ τ
1
τ
2
¯ τ
3
x
2
¯ x
4
∨. . . ∨τ
1
τ
2
¯ τ
3
.
Specification of block BY. Obviously, this step is executed in the same manner
for both models of P
ES
Y and P
EC
Y Moore FSMs. Of course, the same microin-
structions have different addresses for equivalent P
ES
Y and P
EC
Y Moore FSMs. If
the logic circuit of block BY is implemented using embedded memory blocks, then
corresponding memory cells for both models have the same content. For example,
the cell with address A(b
5
) = 01001 includes the code corresponding to microoper-
ations y
0
y
2
y
5
(for the P
ES
Y Moore FSM S
25
), the same code is contained by the cell
with address A(b
5
) = 00100 (for the P
EC
Y Moore FSM S
25
).
Synthesis of FSM logic circuit is reduced to implementation of systems (8.2)
– (8.4) and (8.9) using some logic elements. The logic circuit of the P
ES
Y Moore
FSM S
25
is shown in Fig 8.6. This circuit includes a block generated pulses of
synchronization for the register and counter. The following functions are used to
control the synchronization:
C
1
= y
0
Clock; (8.10)
C
2
= ¯ y
0
Clock. (8.11)
The pulse C
1
is used to increment the counter for execution of unconditional jumps.
The pulse C
2
is used to clear the counter and to load a parallel code determined by
(8.9) into the register.
Analysis of P
ES
Y Moore FSM shows that there is no dependence between codes
of EOLC and codes of their components. It allows application for P
ES
Y Moore FSM
all known methods used for optimization of PY Moore FSM. Of course, these meth-
ods should be adapted to the peculiarities of P
ES
Y Moore FSM. Besides, application
of these models has sense only if the following condition takes place:
R
EO
+R
CO
= R
E
. (8.12)
If condition (8.12) is violated, then the total size of used blocks BRAM increases
drastically in comparison with its minimal value, determined as
V
min
= 2
R
E
(N+2). (8.13)
This formula assumes application of the hot-one encoding of microoperations. It
should be modified if the block BY is implemented using either maximal encoding
of collections of microoperations or encoding of the classes of compatible microop-
erations. The hardware amount in logic circuit of P
ES
Y Moore FSM can be reduced
using some optimization methods [3–7, 9]. Let us discuss these methods in details.
8.2 Optimization of Block of Input Memory Functions 201
Table 8.3 Structure table of P
ES
Y Moore FSM S
25
α
g
K(α
g
) I
j
m
A(I
j
m
) X
h
Ψ
h
h
α
1
000 I
2
00100 x
1
D
3
1
I
3
01000 ¯ x
1
x
2
D
2
2
I
4
01100 ¯ x
1
¯ x
2
D
2
D
3
3
α
2
001 I
3
01000 1 D
2
4
α
3
010 I
3
01000 x
2
x
4
D
2
5
I
5
10000 x
2
¯ x
4
D
1
6
I
6
10100 ¯ x
2
x
3
D
1
D
3
7
I
7
11000 ¯ x
2
¯ x
3
D
1
D
2
8
α
4
011 I
3
01000 x
2
x
4
D
2
9
I
5
10000 x
2
¯ x
4
D
1
10
I
6
10100 ¯ x
2
x
3
D
1
D
3
11
I
7
11000 ¯ x
2
¯ x
3
D
1
D
2
12
α
5
100 I
6
10100 1 D
1
D
3
13
α
6
101 I
8
11100 1 D
1
D
2
D
3
14
α
7
110 I
8
11100 1 D
1
D
2
D
3
15
Fig. 8.6 Logic circuit of
P
ES
Y Moore FSM S
25
΁ͽ͵
͢
͢
ͣ
ͤ
ͥ
ͦ
ͧ
ͨ
͢
ͣ
ͤ
ͣ
ͤ
ͥ
ͦ
ͤ͢
͵
͢
΃͸
͵
͢
͵
ͣ
͵
ͤ
΃
ʹ
͢
ͣ
ͤ
ͤ͢
ͥ͢
ͦ͢
͢͡
ͦ
ͧ
ͩ͢
ͨ
Ω
͢ ͢
Ω
ͣ ͣ
Ω
ͤ ͤ
ͥ͢
͵
ͣ
ͦ͢
͵
ͤ
ͧ
W
͢
W
ͣ
W
ͤ
ͥ
ͧ
ͨ
Ω
ͥ
ͦ
ͩ
ͪ
ͨ
ͨ
ͩ
ͪ
͢͡ ͪ
Ϊ
Ͷ
Ϊ
ͥ
Ϊ
ͦ
ͨ
͢
ͣ
ͤ
ͥ
ͦ
ʹ΄
͢
ͣ
ͤ
ͥ
ͦ
ͧ
ͨ
ͩ
Ϊ
͢
Ϊ
ͣ
Ϊ
ͤ
͢͡
͢͢
ͣ͢
W
͢
΄ΥΒΣΥ
ʹΝΠΔΜ
W
ͣ
΃ ΅
΄
ͷΖΥΔΙ ͪ
͢͡
ͩ͢
͗
͢
͗
ͧ͢
ͨ͢
ͩ
͢͢
͢͢
ʹ
͢
ʹ
ͣ
ͨ͢
ͩ
Ϊ
͡
ͪ͢
W
ͤ
Ϊ
͡
Ϊ
Ͷ
͓͓͡
ʹ΅
͵
͢
͵
ͣ
΃
ʹ
͢
ʹ
ͣ
͢
ͣ
ͣ͢
ͣ͢
͢͡
ͧ͢
ͣ͡
ͣ͢
ͩ͢
7
͢
7
ͣ
΁΃΀;
ͩ
Ϊ
͡
8.2 Optimization of Block of Input Memory Functions
All discussed methods are based on existence of pseudoequivalent elementary oper-
ational linear chains in a GSAΓ to be interpreted [2]. Elementary OLCs α
i
, α
j
∈C
E
are pseudoequivalent EOLCs, if their outputs are connected with the input of the
same vertex of GSA Γ. There are two optimization methods for the logic circuit of
block BP, namely:
1. The optimal encoding of EOLC leading to P
ES1
Y Moore FSM.
2. The code transformation of pseudoequivalent EOLC into the codes of their
classes leading to P
ES2
Y Moore FSM.
202 8 FSM Synthesis with Elementary Chains
For the GSA Γ
6
(Fig. 8.2), the partition Π
E
includes the following classes of
pseudoequivalent EOLC: B
1
= ¦α
1
¦, B
2
= ¦α
2
¦, B
3
= ¦α
3
, α
4
¦, B
4
= ¦α
5
¦, and
B
5
= ¦α
6
, α
7
¦.
Optimal EOLC encoding is executed in the way minimizing the number of
terms in system (8.14), represented in the following form:
B
i
=
G
E

g=1
C
gi
A
g
(i = 1, . . . , I
E
). (8.14)
In this system, the symbol C
gi
stands for a Boolean variable equal to 1 iff α
g
∈ Π
E
,
and I
E
= [Π
E
[. Let us point out that codes for EOLC whose outputs are connected
with the input of final GSA vertex are treated as ”don’t care” input assignments. It
is possible because the FSM structure table does not include transitions for these
outputs.
Structural models are the same for P
ES
Y and P
ES1
Y Moore FSMs. The only
difference in their design methods is an approach used for EOLC encoding. Let us
discuss an example of logic synthesis for the P
ES1
Y Moore FSM S
25
specified by
the GSA Γ
6
(Fig. 8.2). In comparison with previous example, some difference in
the outcomes of synthesis procedure steps appears only in generated addresses of
microinstructions.
Natural addressing of microinstructions. Component codes for EOLC α
g
∈C
E
are the same for both P
ES
Y and P
ES1
Y Moore FSMs S
25
. For the P
ES1
Y Moore FSM
S
25
, the system (8.14) is represented as the following one:
B
1
= A
1
; B
2
= A
2
; B
3
= A
3
∨A
4
; B
4
= A
5
; B
5
= A
6
∨A
7
. (8.15)
The algorithm ESPRESSO [8], can be used for optimal EOLC encoding. In the
discussed example, it generates the codes shown in Fig. 8.7.
Fig. 8.7 Optimal EOLC
codes of P
ES1
Y Moore FSM
S
25 1 2 3 6
8 5 4 7
0
1
00 01 11 10
Because the EOLC α
8
does not belong to set B
i
∈ Π
E
, then its code 100 is
treated as a ”don’t care” input assignment. Taking it into account, the following
conjunctions can be found for classes B
i
∈ Π
E
: B
1
= ¯ τ
2
¯ τ
3
; B
2
= ¯ τ
1
¯ τ
2
τ
3
; B
3

2
τ
3
;
B
4

1
¯ τ
2
; B
5

2
¯ τ
3
. Thus, the following codes correspond to the classes B
i
∈ Π
E
:
K(B
1
) = ∗00, K(B
2
) = 001, K(B
3
) = ∗11, K(B
4
) = 10∗, and K(B
5
) = ∗10.
The addresses of microinstructions shown in Fig. 8.8 are determined by concate-
nations of optimal EOLC codes from Fig. 8.7 and their components codes.
Construction of FSM transition table is executed in three stages. The first of
them is reduced to construction of the system of GTFs. In the discussed case it is
system (8.6). During the second stage, EOLC α
g
∈ B
i
from the left part of each
8.2 Optimization of Block of Input Memory Functions 203
T1T2
b
1
b
3
b
11
b
7
b
2
b
12
b
8
b
13
b
9
b
14
b
15
b
16
b
17
b
110
b
18
b
4
b
5
b
6
00
01
11
10
000 001 010 011
1 2 3
100 101 110 111
*
* * *
*
*
*
*
*
* *
*
*
*
Fig. 8.8 Microinstruction addresses for P
ES1
Y Moore FSM S
25
GTF are replaced by corresponding classes B
i
∈ Π
E
. If after such a replacement
the system includes equal formulae, then only one of them remains. For the P
ES1
Y
Moore FSM S
25
, the system of transformed GTF is the following one:
B
1
→ x
1
I
2
∨ ¯ x
1
x
2
I
3
∨ ¯ x
1
¯ x
2
I
4
;
B
2
→ I
3
;
B
3
→ x
2
x
4
I
3
∨x
2
¯ x
4
I
5
∨ ¯ x
2
x
3
I
6
∨ ¯ x
2
¯ x
3
I
7
;
B
4
→ I
6
;
B
5
→ I
8
. (8.16)
The third stage is connected with construction of the table having columns B
i
, K(B
i
),
I
g
, A(I
g
), X
h
, Ψ
h
, h (Table 8.4). Relationship of this table with system (8.16) is
evident.
This table is used to derive system (8.8). For example, the following sum-of-
products D
1
= F
3
∨ F
6
∨ F
8
∨ F
9
= ¯ τ
2
¯ τ
3
¯ x
1
¯ x
2
∨ τ
1
τ
2
x
2
¯ x
4
∨ τ
2
τ
3
¯ x
2
¯ x
3
∨ τ
2
¯ x
3
can be
derived from Table 8.4.
Specification of block BY is reduced to replacement of vertices b
t
by corre-
sponding collections Y(b
t
) and variables y
0
, y
E
.
Logic synthesis of FSM circuit is reduced to implementation of obtained func-
tions using some macrocells, whereas the block BY is implemented using embed-
ded memory blocks. Logic circuits for P
ES
Y and P
ES1
Y Moore FSMs are practi-
cally identical, but the block BY of P
ES1
Y Moore FSM S
25
includes only 10 terms
(Fig. 8.6), but it includes 15 terms in the case of P
ES
Y Moore FSM S
25
.
The number of inputs and terms of block BP can be decreased using the method of
transformation of EOLC codes into codes of the classes of pseudoequivalent EOLC.
In this case each class B
i
∈ Π
E
is identified by its binary code K(B
i
) having R
B
bits:
R
B
= log
2
I
E
|. (8.17)
Additional variables z
r
∈ Z, where [Z[ = R
B
, are used for EOLC encoding. Special
block of code transformer BTC is used for encoding of the classes B
i
∈ Π
E
. It turns
P
ES1
Y Moore FSM into P
ES2
Y Moore FSM (Fig. 8.9).
The principles of this FSM operation are clear. In this model, the blocks BTC
and BP generate functions
Z = Z(τ), (8.18)
204 8 FSM Synthesis with Elementary Chains
Table 8.4 Structure table of P
ES1
Y Moore FSM S
25
B
i
K(B
i
) I
g
A(I
g
) X
h
Ψ
h
h
B
1
∗00 I
2
00100 x
1
D
3
1
I
3
01100 ¯ x
1
x
2
D
2
D
3
2
I
4
11100 ¯ x
1
¯ x
2
D
1
D
2
D
3
3
B
2
001 I
3
01100 1 D
2
D
3
4
B
3
∗11 I
3
01100 x
2
x
4
D
2
D
3
5
I
5
10100 x
2
¯ x
4
D
1
D
3
6
I
6
01000 ¯ x
2
x
3
D
2
7
I
7
11000 ¯ x
2
¯ x
3
D
1
D
2
8
B
4
10∗ I
6
01000 1 D
2
9
B
5
∗10 I
8
10000 1 D
1
10
ͳ΁
΄ΥΒΣΥ
ʹΝΠΔΜ
Ή Ί
͜͢
Ί
͡
ͳΊ
΅
΃
΄
΅ͷ
΄ΥΒΣΥ
ͷΖΥΔΙ
ʹ΅
΃͸
Լ
͓͓͡
Ί
Ͷ
W
ͳ΅ʹ
΋
Fig. 8.9 Structural diagram of P
ES2
Y Moore FSM
Ψ = Ψ(Z, X). (8.19)
The synthesis method for P
ES2
Y Moore FSM includes two additional steps, namely
encoding of the classes B
i
∈Π
E
and construction of a table specified the block BTC.
Let us discuss an example of logic design for the P
ES2
Y Moore FSM S
26
specified
by the GSA Γ
7
(Fig. 8.10).
1. Construction of EOLC set results in the set C
E
= ¦α
1
, . . . , α
7
¦, where α
1
=
'b
1
, b
2
`, I
1
= b
1
, O
1
= b
2
, L
1
= 2; α
2
= 'b
3
, . . . , b
6
`, I
2
= b
3
, O
2
= b
6
, L
2
= 4;
α
3
= 'b
7
, b
8
`, I
3
= b
7
, O
3
= b
8
, L
3
= 2; α
4
= 'b
9
, . . . , b
12
`, I
4
= b
9
, O
4
= b
12
,
L
4
=4; α
5
='b
13
, b
14
, b
15
`, I
5
= b
13
, O
5
=b
15
, L
5
=3; α
6
='b
16
, b
17
`, I
6
=b
16
,
O
6
= b
17
, L
6
= 2; α
7
= 'b
18
, b
19
`, I
7
= b
18
, O
7
= b
19
, L
7
= 2. As it follows from
analysis of the GSAΓ
7
, there are two classes of pseudoequivalent EOLC, namely
Π
E
= ¦B
1
, B
2
¦, where B
1
= ¦α
1
¦, B
2
= ¦α
2
, . . . , α
6
¦.
2. Natural addressing of microinstructions. There are G
E
= 7 EOLC in the GSA
Γ
7
, they could be encoded using R
EO
= 3 elements from the set τ = ¦τ
1
, τ
2
, τ
3
¦.
The maximal number of components per EOLC is equal to four (Q
E
= 4), they
could be encoded using R
CO
= 2 elements from the set T = ¦T
1
, T
2
¦. If the logic
circuit of block BCT is implemented using some macrocells, then EOLC should
8.2 Optimization of Block of Input Memory Functions 205
ͶΟΕ
΄ΥΒΣΥ
Ω
͢
͢ ͡
Ϊ
ͤ
Γ
ͤ Ϊ
͢
Ϊ
ͣ
Ϊ
ͣ
Γ
ͨ
Γ
ͪ
Ϊ
ͤ
Ϊ
ͦ
Ϊ
ͤ
Ϊ
ͦ
Γ
ͩ
Γ
ͤ͢
Ϊ
ͥ
Γ
ͥ͢
Ϊ
͢
Ϊ
ͥ
Ϊ
ͦ
Ϊ
͢
Ϊ
ͣ
Γ
ͩ͢
Γ
ͦ͢
Ϊ
ͣ
Ϊ
Ͷ
Γ
ͪ͢
Ϊ
͢
Ϊ
ͣ
Ϊ
ͤ
Γ
͢
Γ
ͣ
Γ
͡
Ϊ
ͣ
Ϊ
ͥ
Γ
ͥ
Ϊ
͢
Ϊ
ͦ
Γ
ͦ
Ϊ
ͣ
Γ
ͧ
Ω
͢
͢ ͡
Ω
ͣ
͢ ͡
Γ
Ͷ
Ω
ͣ
͢ ͡
Ω
ͤ
͢ ͡
Ϊ
͢
Ϊ
ͥ
Γ
͢͡
Ϊ
ͣ
Ϊ
ͦ
Γ
͢͢
Ϊ
͢
Γ
ͣ͢
Ω
ͥ
͢ ͡
Γ
ͧ͢
Ϊ
͢
Ϊ
ͣ
Ϊ
ͤ
Γ
ͨ͢
Ϊ
ͤ
Ϊ
ͦ
Fig. 8.10 Transformed graph-scheme of algorithmΓ
7
206 8 FSM Synthesis with Elementary Chains
Fig. 8.11 Optimal EOLC
codes for Moore FSM S
26
1 2 3 4
5 6 7
0
1
00 01 11 10
*
T1T2
b
1
b
3
b
9
b
16
b
2
b
4
b
10
b
17
b
5
b
11
b
6
b
12
b
18
b
19
b
13
b
14
b
15
b
7
b
8
00
01
11
10
000 001 010 011
1 2 3
100 101 110 111
*
* * *
*
*
*
*
*
* *
*
*
Fig. 8.12 Microinstruction addresses for Moore FSM S
26
be encoded using the approach of optimal encoding. It minimizes the number of
terms in system (8.14). For the P
ES2
Y Moore FSM S
26
, the optimal EOLC codes
are shown in Fig. 8.11.
Encoding of EOLC components is executed in a trivial way. For the P
ES2
Y
Moore FSM S
26
, these codes are shown in Fig. 8.12.
3. Construction of FSM structure table is executed in the same manner as for
P
ES1
Y Moore FSM. But there is some additional stage connected with encoding
of the classes B
i
∈ Π
E
. In the discussed case, there are two classes (I
E
= 2) and
they can be encoded using the set Z = ¦z
1
¦. Let K(B
1
) = 0, K(B
2
) = 1. The
transformed system of GFT is the following one:
B
1
→ x
1
x
2
I
2
∨x
1
¯ x
2
I
3
∨ ¯ x
1
x
3
I
4
∨ ¯ x
1
¯ x
3
x
4
I
5
∨ ¯ x
1
¯ x
3
¯ x
4
I
6
;
B
3
→ x
1
I
2
∨ ¯ x
1
x
2
I
2
∨ ¯ x
1
¯ x
2
I
7
.
Table 8.5 Structure table of P
ES2
Y Moore FSM S
26
B
i
K(B
i
) I
g
A(I
g
) X
h
Ψ
h
h
B
1
0 I
2
00100 x
1
x
2
D
3
1
I
3
01100 x
1
¯ x
2
D
2
D
3
2
I
4
01000 ¯ x
1
x
3
D
2
3
I
5
10100 ¯ x
1
¯ x
3
x
4
D
1
D
3
4
I
6
11100 ¯ x
1
¯ x
3
¯ x
4
D
1
D
2
D
3
5
B
2
1 I
2
00100 x
1
D
3
6
I
2
00100 ¯ x
1
x
2
D
3
7
I
7
11000 ¯ x
1
¯ x
2
D
1
D
2
8
8.2 Optimization of Block of Input Memory Functions 207
This system is used to construct the structure table of P
ES2
Y Moore FSM S
26
(Table 8.5).
This table is used to derive system (8.19). For example, the following
SOP D
1
= F
4
∨F
5
∨F
8
= ¯ z
1
¯ x
1
¯ x
3
∨z
1
¯ x
1
¯ x
2
can be derived from Table 8.5 (after
minimization).
4. Specification of block BY is executed according with approaches discussed be-
fore. For example, the address 00101 corresponds to the vertex b
4
(Fig. 8.12),
then some memory cell having this address should contain the microoperations
y
2
and y
4
, as well as the additional variable y
0
.
5. Specification of block BTC is reduced to construction of the table with columns
α
g
, K(α
g
), B
i
, K(B
i
), Z
g
, g. In this table, the column Z
g
contains variables z
r
∈ Z
equal to 1 in the code K(B
i
), where α
g
∈ B
i
. For the P
ES2
Y Moore FSM S
26
, this
table has G
E
= 6 rows (Table 8.6).
If the logic circuit of block BTC is implemented using embedded memory
blocks BRAM, then the code K(α
g
) is treated as a memory address, whereas the
corresponding memory cell contains the code K(B
i
). If the logic circuit of block
BTC is implemented using some macrocells, then the table of block BTC is used
to derive system (8.18). The following minimized Boolean equation z
1
= τ
3

¯ τ
1
τ
2
can be derived fromTable 8.6. Obviously, in the second case classes B
i
∈Π
E
should be encoded in the way minimizing the number of terms in system (8.18).
If in our example classes B
i
∈Π
E
have the codes K(B
1
) =1 and K(B
2
) =0, then
the previous equation is simplified and represented as z
1
= ¯ τ
2
¯ τ
3
.
Table 8.6 Specification of block BTC for P
ES2
Y Moore FSM S
26
α
g
K(α
g
) B
i
K(B
i
) Z
g
g
α
1
000 B
1
0 – 1
α
2
001 B
2
1 Z
1
2
α
3
011 B
2
1 Z
1
3
α
4
010 B
2
1 Z
1
4
α
5
101 B
2
1 Z
1
5
α
6
111 B
2
1 Z
1
6
6. Implementation of FSM logic circuit is reduced to implementation of obtained
tables and functions using some macrocells and embedded memory blocks.
Let us point out that application of the block BTC guarantees reduction for
both numbers of ST rows and inputs of the block BP up to the corresponding
values of equivalent Mealy FSM. Fromthe other hand, this block consumes some
additional chip recourses. Therefore, the final choice between these two models
is determined by their hardware amounts. For the P
ES1
Y Moore FSM S
26
, the
system B(τ) is the following one: B
1
= ¯ τ
2
¯ τ
3
, B
2
= τ
3
∨ ¯ τ
1
τ
2
. Thus, the structure
table of P
ES1
Y Moore FSM S
26
includes 11 rows, whereas its block BP has three
inputs. Let us point out that the maximal number of rows in the structure table of
the Moore FSM S
26
is equal to 17.
208 8 FSM Synthesis with Elementary Chains
8.3 Optimization of Block of Microoperations
If condition (8.12) is violated, then required size of the block BY increases in m
K
times, where
m
K
= 2
R
EO
+R
CO
−R
E
. (8.20)
In this case, there is no sense in application of the code sharing method. From
the other hand, this method gives a potential possibility for the block BP hardware
amount decrease. To keep using this positive feature if condition (8.12) is violated,
it can be used transformation of the microinstruction address A(b
t
), represented as
(1.33), in an address having R
E
bits [2]. To execute such a transformation, a block
of address transformer BAT is introduced in P
ES
Y Moore FSM model. It results in
a model of P
ES
Y
T1
Moore FSM shown in Fig. 8.13.
ͳ΁
΄ΥΒΣΥ
ʹΝΠΔΜ
Ή Ί
͜͢
Ί
͡
ͳΊ
΅
΃
΄
΅ͷ
΄ΥΒΣΥ
ͷΖΥΔΙ
ʹ΅
΃͸
Լ
͓͓͡
Ί
Ͷ
W
ͳͲ΅
΋
΋
Fig. 8.13 Structural diagram of P
ES
Y
T1
Moore FSM
Let us discuss an example of logic synthesis for the P
ES
Y
T1
Moore FSM S
27
specified by an initial GSA Γ
8
(Fig. 8.14).
1. Construction of EOLC set. Applying the already known approaches to the GSA
Γ
8
, the following EOLCset C
E
=¦α
1
, . . . , α
8
¦ can be found, where α
1
='b
1
, b
2
`,
L
1
= 2; α
2
= 'b
3
`, L
2
= 1; α
3
= 'b
4
, b
5
`, L
3
= 2; α
4
= 'b
6
, b
7
`, L
4
= 2; α
5
=
'b
8
, b
9
`, L
5
= 2; α
6
= 'b
15
, . . . , b
19
`, L
6
= 5; α
7
= 'b
12
, b
13
, b
14
`, L
7
= 3; α
8
=
'b
15
, . . . , b
19
`, L
8
=5. Therefore, the GSAΓ
8
includes G
E
=8 elementary OLCs,
encoded using R
EO
= 3 elements. The maximal number of components for these
EOLC is equal to Q
E
= 5, thus it is enough R
CO
= 3 variables for component
codes. Besides, there are M
E
= 19 operator vertices in the GSAΓ
8
, thus there are
19 microinstructions and it is enough R
E
= 5 bits for their addressing. It can be
found that condition (8.12) is violated, because R
EO
+R
CO
= 6 > R
E
. Therefore,
there is sense in applying of the address transformer BAT.
2. Natural microinstruction addressing. Let us encode the EOLC α
g
∈C
E
in the
trivial way: K(α
1
) = 000, . . . , K(α
8
) = 111. The first component of any EOLC
has the address 000, the second has the address 001 and so on (Fig. 8.15).
3. Linear microinstruction addressing. It is enough R
E
= 5 variables to address
the microinstructions Y(b
t
). It determines the following set of address variables
8.3 Optimization of Block of Microoperations 209
ͶΟΕ
΄ΥΒΣΥ
Ω
͢
͢ ͡
Ϊ
͢
Ϊ
ͣ
Γ
ͤ
Ϊ
ͣ
Ϊ
ͤ
Ϊ
ͥ
Γ
ͧ
Ϊ
ͣ
Ϊ
ͦ
Γ
ͩ
Ϊ
ͣ
Ϊ
ͥ
Γ
ͪ
Ϊ
ͤ
Γ
ͦ͢
Ϊ
ͣ
Ϊ
ͤ
Ϊ
ͥ
Γ
ͧ͢
Ϊ
͢
Ϊ
ͣ
Ϊ
ͤ
Γ
͢
Γ
ͣ
Γ
͡
Ϊ
͢
Ϊ
ͥ
Γ
ͥ
Ϊ
ͣ
Ϊ
ͦ
Γ
ͦ
Ω
ͤ
͢ ͡
Ω
ͥ
͢ ͡
Γ
Ͷ
Ω
ͣ
͢ ͡
Ϊ
͢
Ϊ
ͣ
Γ
ͨ
Ω
ͤ
͢ ͡
Ω
ͦ
͢ ͡
Ϊ
ͣ
Ϊ
ͦ
Γ
ͨ͢
Ϊ
͢
Ϊ
ͥ
Γ
ͩ͢
Ϊ
ͣ
Ϊ
ͦ
Γ
ͪ͢
Ϊ
͢
Ϊ
ͣ
Γ
͢͡
Ϊ
ͣ
Ϊ
ͦ
Γ
͢͢
Ϊ
ͤ
Ϊ
ͧ
Γ
ͣ͢
Ϊ
ͣ
Ϊ
ͥ
Γ
ͤ͢
Ϊ
͢
Ϊ
ͣ
Γ
ͥ͢
Fig. 8.14 Initial graph-scheme of algorithmΓ
8
210 8 FSM Synthesis with Elementary Chains
T1T2T3
0
000 001 010 011 111 101 110 100
3 2 1
000
001
010
011
111
101
110
100
*
*
*
*
*
*
*
*
*
* *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* *
Fig. 8.15 Microinstruction addresses for P
ES
Y
T1
Moore FSM S
27
b
1
b
5
b
9
b
2
b
6
b
10
b
3
b
7
b
11
b
4
b
8
b
12
b
17
b
18
b
19
b
13
b
14
b
15
b
16
00
01
11
10
000 001 010 011
z
1
z
2
z
3
100 101 110 111
* *
* *
*
* * *
* * *
*
*
z
4
z
5
Fig. 8.16 Linear microinstruction addresses of P
ES
Y
T1
Moore FSM S
27
Z = ¦z
1
, . . . , z
5
¦. The microinstruction addresses of the P
ES
Y
T1
Moore FSM S
27
are shown in Fig. 8.16.
4. Construction of FSM structure table. This step is executed in the traditional
way. In the first place, the systemof GFT is constructed for EOLC, whose outputs
are not connected with the input of the final vertex b
E
. For the P
ES
Y
T1
Moore
FSM S
27
, the following system is constructed:
α
1
→ x
1
I
2
∨ ¯ x
1
x
2
I
4
∨ ¯ x
1
¯ x
2
x
3
I
5
∨ ¯ x
1
¯ x
2
¯ x
3
I
8
;
α
2
→ I
3
;
α
3
, α
4
, α
5
→ x
3
I
3
∨ ¯ x
3
x
4
x
5
I
7
∨ ¯ x
3
x
4
¯ x
5
I
6
∨ ¯ x
3
x
4
¯ x
5
I
1
5
∨ ¯ x
3
¯ x
4
I
8
;
α
6
→ I
7
.
(8.21)
Next, this systemis used to construct a table with columns α
g
, K(α
g
), α
m
, K(α
m
),
X
h
, Ψ
h
, h. For the P
ES
Y
T1
Moore FSM S
27
, the structure table includes H = 18
rows (Table 8.7).
8.3 Optimization of Block of Microoperations 211
Table 8.7 Structure table of P
ES
Y
T1
Moore FSM S
27
α
g
K(α
g
) α
m
K(α
m
) X
h
Ψ
h
h
α
1
000 α
2
001 x
1
D
3
1
α
4
011 ¯ x
1
x
2
D
2
D
3
2
α
5
100 ¯ x
1
¯ x
2
x
3
D
1
3
α
8
111 ¯ x
1
¯ x
2
¯ x
3
D
1
D
2
D
3
4
α
2
001 α
3
010 1 D
2
5
α
3
010 α
3
010 x
3
D
2
6
α
7
110 ¯ x
3
x
4
x
5
D
1
D
2
7
α
6
101 ¯ x
3
x
4
¯ x
5
D
1
D
3
8
α
8
111 ¯ x
3
¯ x
4
D
1
D
2
D
3
9
α
4
011 α
3
010 x
3
D
2
10
α
7
110 ¯ x
3
x
4
x
5
D
1
D
2
11
α
6
101 ¯ x
3
x
4
¯ x
5
D
1
D
3
12
α
8
111 ¯ x
3
¯ x
4
D
1
D
2
D
3
13
α
5
100 α
3
010 x
3
D
2
14
α
7
110 ¯ x
3
x
4
x
5
D
1
D
2
15
α
6
101 ¯ x
3
x
4
¯ x
5
D
1
D
3
16
α
8
111 ¯ x
3
¯ x
4
D
1
D
2
D
3
17
α
6
101 α
8
110 1 D
1
D
2
18
The structure table is used to derive system Ψ. For example, the following
SOP can be derived in our case: D
1
= F
3
∨F
4
∨F
7
∨F
8
∨F
9
∨F
11
∨F
12
∨F
13

∨F
15
∨. . . ∨F
18
= ¯ τ
1
¯ τ
2
¯ τ
3
¯ x
1
¯ x
2
x
3
∨. . . ∨τ
1
¯ τ
2
τ
3
.
5. Specification of address transformer is reduced to construction of the table
with columns b
q
, α
g
, K(α
g
), K(b
q
), A(b
q
), Z
q
, q, having M
E
rows. The column
Z
q
includes variables z
r
∈Z equal to 1 in the linear microinstruction address from
the row q of the table(q = 1, . . . , M
E
). For the P
ES
Y
T1
Moore FSM S
27
, this table
includes M
E
= 19 rows (Table 8.8).
Some of the bits for component codes are marked by the symbol ”∗” in
Table 8.8. This symbol points on the ”don’t care” variables z
r
∈ Z. The block
BAT generates functions
Z = Z(τ, T). (8.22)
For example, the following SOP z
1
= τ
1
τ
2
τ
3
T
2
∨τ
1
τ
2
τ
3
T
1
can be derived
from Table 8.8.
6. Specification of block BY. This step is reduced to replacement of vertices b
t
∈B
1
by corresponding contents. If some vertex is not an output of some EOLC, then
the variable y
0
is written in the corresponding cell. If the output of EOLC is
connected with the final vertex b
E
, then the variable y
E
is written in the corre-
sponding cell. In the discussed case, for example, the vertex b
5
corresponds to
address 00001, the cell with this address should contain y
2
, y
5
; the vertex b
19
corresponds to address 10001, the cell with this address should contain y
2
, y
5
,
y
E
, and so on.
212 8 FSM Synthesis with Elementary Chains
Table 8.8 Specification of block BAT for P
ES
Y
T1
Moore FSM S
27
b
q
α
g
K(α
g
) K(b
q
) A(b
q
) Z
q
q
b
1
α
1
000 ∗∗0 00000 – 1
b
2
α
1
000 ∗∗1 00001 z
5
2
b
3
α
2
001 ∗∗∗ 00010 z
4
3
b
4
α
3
010 ∗∗0 00011 z
4
z
5
4
b
5
α
3
010 ∗∗1 00100 z
3
5
b
6
α
4
011 ∗∗0 00101 z
3
z
5
6
b
7
α
4
011 ∗∗1 00110 z
3
z
4
7
b
8
α
5
100 ∗∗0 00111 z
3
z
4
z
5
8
b
9
α
5
100 ∗∗1 01000 z
2
9
b
10
α
6
101 ∗∗0 01001 z
2
z
5
10
b
11
α
6
101 ∗∗1 01010 z
2
z
4
11
b
12
α
7
110 ∗00 01011 z
2
z
4
z
5
12
b
13
α
7
110 ∗∗1 01100 z
2
z
3
13
b
14
α
7
110 ∗1∗ 01101 z
2
z
3
z
5
14
b
15
α
8
111 000 01110 z
2
z
3
z
4
15
b
16
α
8
111 ∗01 01111 z
2
z
3
z
4
z
5
16
b
17
α
8
111 ∗10 10000 z
1
17
b
18
α
8
111 ∗11 10001 z
1
z
5
18
b
19
α
8
111 1∗∗ 10010 z
1
z
4
19
7. Logic synthesis of FSM circuit is reduced to implementation of obtained sys-
tems and tables using some macrocells and embedded memory blocks. The logic
circuit of P
ES
Y
T1
Moore FSM S
27
is shown in Fig. 8.17.
As can be seen from Fig. 8.17, the data inputs of the counter are connected with
the wire 13 with logic ”0”. If y
0
= 0, then the pulse ”Clock” causes the pulse C
2
and
the counter is reset.
There are two approaches for reduction of the number of macrocells in the logic
circuit of block BP. The first approach is the optimal EOLC encoding leading to
P
ES1
Y
T1
Moore FSM. The second method assumes simultaneous application of the
blocks BAT and CCS resulted in P
ES2
Y
T1
Moore FSM. There are two approaches
for reduction of the number of embedded memory blocks in the logic circuit of
block BY. The addresses (1.33) can be transformed into the addresses of expanded
microinstructions (the first approach) or the addresses of collections of microopera-
tions (the second approach) [2].
An expanded microinstruction Y
E
(b
q
) is the set of microoperations y
n
∈ Y and
additional variables y
0
, y
E
, written into the vertex b
q
∈ B
1
. Let Y
E
(Γ) be a set of
expanded microinstructions of GSAΓand Q
E1
=[Y
E
(Γ)[. It is enough R
E1
variables
to encode the expanded microinstructions, where
R
E1
= log
2
Q
E1
|. (8.23)
8.3 Optimization of Block of Microoperations 213
Fig. 8.17 Logic circuit of
P
ES
Y
T1
Moore FSM S
27
΁ͽ͵
͢
͢
ͣ
ͤ
ͥ
ͦ
ͧ
ͨ
ͩ
͢
ͣ
ͤ
ͣ
ͤ
ͥ
ͦ
ͥ͢
͵
͢
΃͸
͵
͢
͵
ͣ
͵
ͤ
΃
ʹ
͢
ͣ
ͤ
ͥ͢
ͦ͢
ͧ͢
͢͢
ͧ
ͨ
ͪ͢
ͩ
Ω
͢ ͢
Ω
ͣ ͣ
Ω
ͤ ͤ
ͦ͢
͵
ͣ
ͧ͢
͵
ͤ
ͧ
W
͢
W
ͣ
W
ͤ
ͥ
ͧ
ͨ
Ω
ͥ
ͦ
ͩ
ͪ
ͨ
ͣͧ
ͣͨ
ͣͩ
ͣ͡
͢͡
Ϊ
Ͷ
Ϊ
ͥ
Ϊ
ͦ
ͣͥ
͢
ͣ
ͤ
ͥ
ͦ
ʹ΄
͢
ͣ
ͤ
ͥ
ͦ
ͧ
ͨ
ͩ
ͣͦ
Ϊ
͢
Ϊ
ͣ
Ϊ
ͤ
͢͡
͢͢
ͣ͢
W
͢
΄ΥΒΣΥ
ʹΝΠΔΜ
W
ͣ
΃ ΅
΄
ͷΖΥΔΙ ͪ
͢͡
ͩ͢
͗
͢
͗
ͧ͢
ͨ͢
ͩ
͢͢
͢͢
ʹ
͢
ʹ
ͣ
ͨ͢
ͩ
Ϊ
͡
ͪ͢
W
ͤ
Ϊ
͡
Ϊ
Ͷ
͓͓͡
ʹ΅
͵
͢
͵
ͣ
΃
ʹ
͢
ʹ
ͣ
͢
ͣ
ͣ͢
ͣ͢
͢͡
ͧ͢
ͣ͡
ͣ͢
ͩ͢
7
͢
7
ͣ
΁΃΀;
ͪ
Ϊ
͡
Ω
ͦ
ͤ͢
ͩ
Ϊ
ͧ
΁ͽ͵
ͧ
͢
ͣ
ͤ
ͥ
ͦ
ͧ
͢
ͣ
ͤ
ͥ
ͦ
ͨ
ͩ
ͣ͢
ͣͣ
ͣͥ
Ϋ
͢
ͣͦ
Ϋ
ͣ
ͣͧ
Ϋ
ͤ
ͣͤ
ͣͨ
Ϋ
ͥ
ͣͩ
Ϋ
ͦ
These variables form a set Z. Let the following condition take place
R
E1
< R
E
. (8.24)
In this case the size of block BY can be decreased in comparison with V
min
(8.13)
due to transformation of addresses A(b
q
) into addresses of expanded microinstruc-
tions. The block BAT is used for such a transformation. Its application results in
P
ES
Y
T2
, P
ES1
Y
T2
, and P
ES2
Y
T2
models of Moore FSM.
There are Q
E1
= 13 expanded microinstructions in the GSA Γ
8
, namely: Y
1
=
¦y
0
, y
1
, y
2
¦, Y
2
=¦y
1
, y
2
¦, Y
3
=¦y
1
, y
2
, y
E
¦, Y
4
=¦y
0
, y
3
¦, Y
5
=¦y
3
¦, Y
6
=¦y
0
, y
1
, y
4
¦,
Y
7
=¦y
0
, y
2
, y
5
¦, Y
8
=¦y
2
, y
5
¦, Y
9
=¦y
2
, y
5
, y
E
¦, Y
10
=¦y
0
, y
2
, y
3
, y
4
¦, Y
11
=¦y
2
, y
4
¦,
Y
12
=¦y
0
, y
2
, y
4
¦, Y
13
= ¦y
0
, y
3
, y
6
¦. It is enough R
E1
=4 variables for encoding mi-
croinstructions from the set Y
E

8
) = ¦Y
1
, . . . ,Y
13
¦. It means that condition (8.24)
takes place and the address transformation can be applied.
Let us discuss an example of logic synthesis for the P
ES
Y
T2
Moore FSM S
27
.
Its structural diagram is the same as the one for P
ES
Y
T1
Moore FSM shown in Fig.
8.13. It is necessary to execute the encoding of expanded microinstructions instead
of linear addressing of microinstructions. Let us encode expanded microinstructions
Y
t
⊆Y
E

8
) using the method of frequency encoding. In the discussed example, this
approach leads to the codes shown in Fig. 8.18.
The block BAT is specified by corresponding table, which is constructed in the
same way as for the P
ES
Y
T1
Moore FSM S
27
. But now its column A(b
q
) is replaced
by the column K(Y
q
), where Y
q
is an expanded microinstruction written in some
vertex b
q
∈ B
1
. This table is represented by Table 8.9. The table is used to derive
214 8 FSM Synthesis with Elementary Chains
Fig. 8.18 Expanded mi-
croinstruction codes for
P
ES
Y
T2
Moore FSM S
27
Y
1
Y
7
Y
9
Y
6
Y
10
Y
3
Y
11
Y
4
00
01
00 01 11 10
Y
5
Y
12
Y
2
Y
13
Y
8
11
10
*
*
z
1
z
2
z
3
z
4
*
system (8.22). If there are some insignificant input assignments for codes of EOLC
or their components, they are used for optimization of functions z
r
∈ Z.
The block BY can be specified by the Karnaugh map shown in Fig. 8.19.
Fig. 8.19 Specification of
block BY of P
ES
Y
T2
Moore
FSM S
27
y
0
y
1
y
2
y
0
y
2
y
5
y
0
y
1
y
4
y
2
y
5
y
E
y
0
y
2
y
3
y
1
y
2
y
E
y
0
y
3
y
2
y
4
00
01
00 01 11 10
y
1
y
2
y
0
y
3
y
6
y
2
y
5
y
3
y
0
y
2
y
4
11
10
*
*
z
1
z
2
z
3
z
4
*
This Karnaugh map can be used either to minimize functions y
0
, y
E
, and y
n
∈Y,
or to program embedded memory blocks BRAM. Let us point out that the structure
table of P
ES
Y
T2
Moore FSM S
27
is the same as Table 8.7.
The logic circuit of P
ES
Y
T2
Moore FSM S
27
is shown in Fig. 8.20. Comparison of
Fig. 8.17 and Fig. 8.20 shows that they are practically the same, but for the P
ES
Y
T2
Moore FSM S
27
the block BAT has fewer outputs, whereas the block BY has fewer
inputs than their counterparts of the P
ES
Y
T1
Moore FSM S
27
.
Let an initial GSA Γ include Q
E2
different collections of microoperations creat-
ing the set Y
N
(Γ). These collections can be encoded using
R
E2
= log
2
Q
E2
| (8.25)
variables, forming the set Z. If both condition (8.24) and condition
R
E2
< R
E1
(8.26)
take place, then the number of blocks BRAM in the FSM logic circuit can be de-
creased in comparison with equivalent P
ES
Y
T2
Moore FSM. But it is necessary to
use an additional block CCS to generate variables y
0
and y
E
. Such an approach
results in the model of P
ES
Y
T3
Moore FSM shown in Fig. 8.21.
8.3 Optimization of Block of Microoperations 215
Table 8.9 Specification of block BAT for P
ES
Y
T2
Moore FSM S
27
b
q
α
g
K(α
g
) K(b
q
) K(Y
q
) Z
q
q
b
1
α
1
000 ∗∗0 0000 – 1
b
2
α
1
000 ∗∗1 0010 z
3
2
b
3
α
2
001 ∗∗∗ 0000 – 3
b
4
α
3
010 ∗∗0 1100 z
1
z
2
4
b
5
α
3
010 ∗∗1 1111 z
1
z
2
z
3
z
4
5
b
6
α
4
011 ∗∗0 0001 z
4
6
b
7
α
4
011 ∗∗1 0011 z
3
z
4
7
b
8
α
5
100 ∗∗0 0100 z
2
8
b
9
α
5
100 ∗∗1 1001 z
1
z
4
9
b
10
α
6
101 ∗∗0 0000 – 10
b
11
α
6
101 ∗∗1 0100 z
2
11
b
12
α
7
110 ∗00 0111 z
2
z
3
z
4
12
b
13
α
7
110 ∗∗1 0110 z
2
z
3
13
b
14
α
7
110 ∗1∗ 0101 z
2
z
4
14
b
15
α
8
111 000 1101 z
1
z
2
z
4
15
b
16
α
8
111 ∗01 0001 z
4
16
b
17
α
8
111 ∗10 0100 z
2
17
b
18
α
8
111 ∗11 1100 z
1
z
2
18
b
19
α
8
111 1∗∗ 1000 z
1
19
Fig. 8.20 Logic circuit of
P
ES
Y
T2
Moore FSM S
27
΁ͽ͵
͢
͢
ͣ
ͤ
ͥ
ͦ
ͧ
ͨ
ͩ
͢
ͣ
ͤ
ͣ
ͤ
ͥ
ͦ
ͥ͢
͵
͢
΃͸
͵
͢
͵
ͣ
͵
ͤ
΃
ʹ
͢
ͣ
ͤ
ͥ͢
ͦ͢
ͧ͢
͢͢
ͧ
ͨ
ͪ͢
ͩ
Ω
͢ ͢
Ω
ͣ ͣ
Ω
ͤ ͤ
ͦ͢
͵
ͣ
ͧ͢
͵
ͤ
ͧ
W
͢
W
ͣ
W
ͤ
ͥ
ͧ
ͨ
Ω
ͥ
ͦ
ͩ
ͪ
ͨ
ͣͧ
ͣͨ
ͣ͡
͢͡
Ϊ
Ͷ
Ϊ
ͥ
Ϊ
ͦ
ͣͥ
͢
ͣ
ͤ
ͥ
ʹ΄
͢
ͣ
ͤ
ͥ
ͦ
ͧ
ͨ
ͩ
ͣͦ
Ϊ
͢
Ϊ
ͣ
Ϊ
ͤ
͢͡
͢͢
ͣ͢
W
͢
΄ΥΒΣΥ
ʹΝΠΔΜ
W
ͣ
΃ ΅
΄
ͷΖΥΔΙ ͢͡
͢͢
ͪ͢
͗
͢
͗
ͨ͢
ͩ͢
ͪ
ͣ͢
ͣ͢
ʹ
͢
ʹ
ͣ
ͩ͢
ͪ
Ϊ
͡
ͣ͡
W
ͤ
Ϊ
͡
Ϊ
Ͷ
͓͓͡
ʹ΅
͵
͢
͵
ͣ
͵
ͤ
΃
ʹ
͢
ʹ
ͣ
͢
ͣ
ͤ
ͤ͢
ͤ͢
ͥ͢
͢͢
ͣ͢
ͣͣ
ͨ͢
7
͢
7
ͣ
΁΃΀;
ͪ
Ϊ
͡
Ω
ͦ
ͤ͢
ͩ
Ϊ
ͧ
΁ͽ͵
ͧ
͢
ͣ
ͤ
ͥ
ͦ
ͧ
͢
ͣ
ͤ
ͥ
ͦ
ͨ
ͩ
ͣ͢
ͣͣ
ͣͥ
Ϋ
͢
ͣͦ
Ϋ
ͣ
ͣͧ
Ϋ
ͤ
ͣͤ
ͣͨ
Ϋ
ͥ
ͣͤ
7
ͤ
ͪ͢
216 8 FSM Synthesis with Elementary Chains
Fig. 8.21 Structural dia-
gram of P
ES
Y
T3
Moore
FSM
ͳ΁
΄ΥΒΣΥ
ʹΝΠΔΜ
Ή
Ί
Ͷ
͜͢
Ί
͡
ͳΊ
΅
ʹ΅
΃͸
Լ
͓͓͡
W
΋
ʹʹ΄
ͳͲ΅
Ί
In the discussed case, the set Y
N
(Γ) includes Q
E2
= 7 collections of micro-
operations, namely: Y
1
= ¦y
1
, y
2
¦, Y
2
= ¦y
3
¦, Y
3
= ¦y
1
, y
4
¦, Y
4
= ¦y
2
, y
5
¦, Y
5
=
¦y
2
, y
3
, y
4
¦, and Y
6
= ¦y
2
, y
4
¦, Y
7
= ¦y
3
, y
6
¦. It means that R
E2
= 3 and conditions
(8.24) and (8.26) take place. Thus, the application of address transformation allows
quadruple decrease for the block BY size in comparison with V
min
determined by
formula (8.13). To optimize the logic circuit of BAT, it is necessary to apply the
method of frequency encoding for collections of microoperations. Remind that such
an encoding is executed in the following manner: the more times some collection
appears in operator vertices of GSA, the more zeros its code contains. In the dis-
cussed case, there is the set of coding variables Z = ¦z
1
, z
2
, z
3
¦ and optimal codes
are shown in Fig. 8.22.
Fig. 8.22 Optimal codes for
collections of microopera-
tions
z
1
Y
1
Y
4
Y
5
Y
2
Y
3
Y
6
Y
7
0
1
00 01 11 10
z
2
z
3
*
The table of block BAT is built in the same manner as for previous examples. For
the P
ES
Y
T3
Moore FSM S
27
this table has M
E
= 19 rows (Table 8.10).
The logic circuit of block CCS is implemented using the Karnaugh map
(Fig. 8.23).
This map is filled in the following manner. For example, the cell 001001 of the
map corresponds to the vertex b
4
of GSAΓ
8
. This vertex should include the variable
y
0
. Therefore, the variable y
0
is written in the cell 001001. Next, the cell 000100
does not correspond to any vertex of the GSA Γ
8
. Therefore, this cell is marked by
the symbol "∗" (don’t care) and so on. The following equations can be derived from
this Karnaugh map:
y
0
=
¯
T
1
¯
T
3
∨τ
1
¯
T
1
∨ ¯ τ
1
¯ τ
2
τ
3
¯
T
2
;
y
E
= T
1
.
(8.27)
8.3 Optimization of Block of Microoperations 217
Table 8.10 Specification of block BAT for P
ES
Y
T3
Moore FSM S
27
b
q
α
g
K(α
g
) K(b
q
) K(Y
t
) z
q
q
b
1
α
1
000 ∗∗0 000 – 1
b
2
α
1
000 ∗∗1 010 z
2
2
b
3
α
2
001 ∗00 000 – 3
b
4
α
2
001 ∗∗1 100 z
1
4
b
5
α
2
001 ∗1∗ 001 z
3
5
b
6
α
3
010 ∗∗0 011 z
2
z
3
6
b
7
α
3
010 ∗∗1 000 – 7
b
8
α
4
011 ∗∗0 001 z
3
8
b
9
α
4
011 ∗∗1 101 z
1
z
3
9
b
10
α
5
100 000 000 – 10
b
11
α
5
100 ∗01 001 z
3
11
b
12
α
5
100 ∗10 110 z
1
z
2
12
b
13
α
5
100 ∗11 101 z
1
z
3
13
b
14
α
5
100 1∗∗ 000 – 14
b
15
α
6
101 000 010 z
2
15
b
16
α
6
101 ∗01 011 z
2
z
3
16
b
17
α
6
101 ∗10 001 z
3
17
b
18
α
6
101 ∗11 100 z
1
18
b
19
α
6
101 1∗∗ 001 z
3
19
T
1
T
2
T
3
y
0
y
0
y
0
y
0
0 y
0
0 y
0
0 y
0
y
0
y
0
y
0
y
0
y
0
y
0
0
000 001 011 010 110 111 101 100
y
E
y
E
000
001
011
010
110
111
101
100
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* *
*
*
*
*
*
*
*
*
*
*
1 2 3
Fig. 8.23 Specification of block CCS for P
ES
Y
T3
Moore FSM S
27
To find the content of embedded memory blocks BRAM, it is enough to replace
the symbols of collections of microoperations in a map similar to the one shown in
Fig. 8.22 by corresponding microoperations (Fig. 8.24 in our case).
Implementation of FSM logic circuit is reduced to implementation of obtained
tables and systems of functions using some logic elements. For the P
ES
Y
T3
Moore
218 8 FSM Synthesis with Elementary Chains
Fig. 8.24 Specification of
block BY for P
ES
Y
T3
Moore
FSM S
27
z
1
y
1
y
2
y
2
y
5
y
2
y
3
y
4
y
3
y
1
y
4
y
2
y
4
y
3
y
6
0
1
00 01 11 10
z
2
z
3
*
FSM S
27
, the logic circuit is similar to the one shown in Fig. 8.20, but there are two
alterations. Firstly, the block BAT generates only three functions (z
1
, z
2
, z
3
) served
as the block BRAM inputs. Secondly, the outputs y
0
, y
E
are generated by the block
CCS having only three inputs (T
1
, T
2
, T
3
), as follows from (8.27).
Logic circuits for models of P
ES1
Y
T2
and P
ES2
Y
T2
Moore FSM are implemented
in the same manner. It could be a good exercise for a reader.
8.4 Synthesis for Multilevel Models of FSM with Elementary
Chains
As it is for FSM with the register keeping state codes, the hardware amount for
FSM with the counter keeping microinstruction (or component) addresses can be
decreased using the methods of logical condition replacement and encoding of the
collections of microoperations. It results in multilevel models of P
EC
Y and P
ES
Y
Moore FSM (Table 8.11).
In this table, the symbol F (the level LC) stands for the block BAT, which can
generate either codes of collections of microoperations or codes of the classes of
compatible microoperations. In the last case, it is possible to use the verticalization
for initial GSA. The symbol P
EC
Y [1] stands for P
EC
Y Moore FSM with optimal
EOLC encoding, whereas the symbol P
EC
Y [2] stands for FSM with transforma-
tion of EOLC addresses into codes of the classes of pseudoequivalent EOLC. The
following numbers of different Moore FSM models can be found from Table 8.11:
1. NL
2
= 6 (It determines the basic models of the PY type).
2. NL
3
= 18G+6K+18 (The first member of the formula determines the number
of models with the logical condition replacement, whereas the rest determines
the number of models with the block BAT).
Table 8.11 Multilevel models of FSM with EOLC
LA LB LC LD
M
1
M
1
C M
1L
P
EC
P
EC1
P
EC3
Y Y
T1
Y
T2
Y
T3
.
.
. P
ES
P
ES1
P
ES2
F D
1
M
G
M
G
C M
G
L
.
.
.
D
K
8.4 Synthesis for Multilevel Models of FSM with Elementary Chains 219
3. NL
4
= 54G+18GK (It determines models using both logical condition replace-
ment and the block BAT).
As it can be found, Table 8.11 specifies 72G+6K +18GK +24 different models
of FSM with elementary operational linear chains. In the case of FSM with average
complexity [1], where G =K = 6, there are 1150 different models for interpretation
of the same GSA Γ. If values of both G and K increase up to 8, then the number of
models increases up to 1740.
As it has been already mentioned, logic synthesis method for a multilevel model
consists from some collection of synthesis methods for models with less number of
levels. Let us discuss an example of logic synthesis for the M
2
P
ES1
LFY
T1
Moore
FSM S
28
specified by the GSAΓ
9
(Fig. 8.25).
1. Construction of FSM structural diagram. According to the formula
M
2
P
ES1
LFY
T1
, its structural diagram includes the block BM with outputs p
1
and p
2
; the block BP, synthesized on the base of optimal EOLC encoding; the
block BAT used for transformation of microinstruction addresses form the code
sharing format into their linear format; the block CCS generating codes of log-
ical conditions for the block BM; and at last the block BY generating microop-
erations y
n
∈Y and additional variables y
0
, y
E
(Fig. 8.26).
2. Transformation of initial GSA. Because of the member M
2
in the FSM for-
mula M
2
P
ES1
LFY
T1
, the initial GSA Γ
9
should be transformed in such a way,
that transitions from each FSM state will depend on not more than two logical
conditions. In the discussed example, this transformation is reduced to intro-
duction of vertices b
19
(to eliminate the ambiguity for initial state code after
pulse ”Start”), b
20
and b
21
(to satisfy the condition G = 2). Besides, the vari-
able y
E
is inserted into the vertex b
13
. The transformed GSAΓ
9
is shown in Fig.
8.27.
3. Construction of EOLC set. The following set of EOLC C
E
= ¦α
1
, . . . , α
11
¦
can be found in our example. The characteristics of EOLC are shown in Table
8.12. Its first column contains the number of EOLC component, whereas its
first row includes inputs I
g
of corresponding EOLC. The following values can
be found fromthe table: G
E
=11, R
EO
=4, Q
E
=4, R
CO
=2, M
E
=21, R
E
=5,
and R
EO
+R
CO
= 6. It is more than R
E
, and therefore, there is necessity in the
block BAT.
4. Optimal EOLC encoding. Let us find the partition Π
E
for the EOLC set
¦α
1
, . . . , α
10
¦. This set does not include EOLCs whose outputs are connected
with the final vertex b
E
.
In the discussed example, there is the partition Π
E
= ¦B
1
, . . . , B
7
¦, where
B
1
= ¦α
1
¦, B
2
= ¦α
2
¦, B
3
= ¦α
3
¦, B
4
= ¦α
4
, α
5
, α
7
, α
10
¦, B
5
= ¦α
6
¦, B
6
=
¦α
8
¦, and B
7
= ¦α
9
¦. Thus, only EOLC α
g
∈ B
4
should be included in one
generalized interval of Boolean four-dimensional space, other EOLC can be
encoded in the arbitrary manner. The outcome for EOLC encoding for the
M
2
P
ES1
LFY
T1
Moore FSM S
28
is shown in Fig. 8.28.
The following codes K(B
i
) for classes B
i
∈ Π
E
can be found from the
Karnaugh map (Fig. 8.28): K(B
1
) = 0000, K(B
2
) = 001∗, K(B
3
) = ∗100,
220 8 FSM Synthesis with Elementary Chains
ͶΟΕ
΄ΥΒΣΥ
Ω
͢
͢ ͡
Ϊ
͢
Ϊ
ͣ
Γ
͢ Ϊ
ͣ
Ϊ
ͦ
Ϊ
ͧ
Γ
ͥ
Ϊ
ͨ
Ϊ
͢
Ϊ
͢͢
Γ
ͦ
Γ
ͩ
Ϊ
ͤ
Γ
ͪ
Γ
͡
Ϊ
ͤ
Γ
ͣ
Ϊ
ͥ
Ϊ
ͦ
Γ
ͤ
Γ
Ͷ
Ω
ͣ
͢ ͡
Ω
ͤ
͢ ͡
Ϊ
ͩ
Ϊ
ͪ
Γ
ͧ
Ϊ
ͣ
Ϊ
ͦ
Ϊ
͢͡
Γ
ͨ
Ω
ͤ
͢ ͡
Ω
ͥ
͢ ͡
Ω
͢
͢ ͡
Ϊ
ͥ
Ϊ
ͦ
Γ
͢͡
Ϊ
ͨ
Γ
͢͢
Ϊ
ͩ
Ϊ
ͪ
Γ
ͣ͢
Ϊ
͢
Ϊ
͢͢
Γ
ͤ͢
Ϊ
ͣ
Ϊ
ͪ
Ϊ
͢͡
Γ
ͥ͢
Ϊ
͢
Ϊ
ͣ
Γ
ͦ͢
Ϊ
͢
Ϊ
͢͢
Γ
ͧ͢
Ϊ
ͥ
Ϊ
ͦ
Γ
ͨ͢
Fig. 8.25 Initial graph-scheme of algorithmΓ
9
8.4 Synthesis for Multilevel Models of FSM with Elementary Chains 221
ͳ΁
΄ΥΒΣΥ
ʹΝΠΔΜ
Ή
΋
͜͢
Ί
͡
΅
ʹ΅
΃͸
Լ
͓͓͡
W
ͳͲ΅
ʹʹ΄
Ί
΃
΄
΅ͷ
΄ΥΒΣΥ
ͷΖΥΔΙ Ί
Ͷ
ͳ΅
Ή
ͳΊ
Fig. 8.26 Structural diagram of M
2
P
ES1
LFY
T1
Moore FSM
Table 8.12 Characteristics of EOLC for transformed GSAΓ
9
α
1
α
2
α
3
α
4
α
5
α
6
α
7
α
8
α
9
α
10
α
11
1 b
19
b
1
b
4
b
6
b
8
b
10
b
14
b
20
b
21
b
3
b
12
2 b
2
b
5
b
7
b
9
b
11
b
15
3 b
16
4 b
17
K(B
4
) = ∗ ∗ ∗1, K(B
5
) = ∗11∗, K(B
6
) = 1 ∗ 00, and K(B
7
) = 1 ∗ 1∗. Let us
point out that the code K(α
11
) is treated as insignificant input assignment.
5. Addressing of microinstructions based on code sharing. As usually, the first
EOLC components have code 00, the second 01, the third 10, and the fourth
11. These codes together with the codes K(α
g
) shown in Fig. 8.28 produce the
microinstruction addresses shown in Fig. 8.29.
6. Logical condition replacement. The following sets X(B
1
) =¦x
1
, x
2
¦, X(B
2
) =
/ 0, X(B
3
) = / 0, X(B
4
) = ¦x
3
, x
4
¦, X(B
5
) = / 0, X(B
6
) = ¦x
3
¦, X(B
7
) = ¦x
1
¦ can
be found in our example. The table of logical condition distribution is shown in
Table 8.13. There are no difficulties in this table construction.
Table 8.13 Distribution of logical conditions for M
2
P
ES1
LFY
T1
Moore FSM S
28
B
1
B
2
B
3
B
4
B
5
B
6
B
7
p
1
x
1
– – x
3
– x
3
x
1
p
2
x
2
– – x
4
– – –
The following sets X(p
1
) = ¦x
1
, x
3
¦, X(p
2
) = ¦x
2
, x
4
¦ can be extracted from
Table 8.13. Therefore, the logical conditions x
l
∈ X(p
1
) are encoded using the
variable z
1
, and the logical conditions x
l
∈X(p
2
) are encoded using the variable
z
2
. It determines the set Z
0
= ¦z
1
, z
2
¦. Let these logical conditions have the
following codes: K(x
1
) = K(x
2
) = 0, K(x
3
) = K(x
4
) = 1.
222 8 FSM Synthesis with Elementary Chains
ͶΟΕ
΄ΥΒΣΥ
Ω
͢
͢ ͡
Ϊ
͡
Ϊ
͢
Ϊ
ͣ
Γ
͢ Ϊ
͡
Ϊ
ͣ
Ϊ
ͦ
Ϊ
ͧ
Γ
ͥ
Ϊ
͡
Ϊ
ͨ
͞
Γ
ͦ
Γ
ͣ͡
Ϊ
͡
Ϊ
͢
Ϊ
͢͢
Γ
ͩ
Γ
͡
Ϊ
͡
Ϊ
ͤ
Γ
ͣ
Ϊ
ͥ
Ϊ
ͦ
Γ
ͤ
Γ
Ͷ
Ω
ͣ
͢ ͡
Ω
ͤ
͢ ͡
Ϊ
͡
Ϊ
ͩ
Ϊ
ͪ
Γ
ͧ
Ϊ
ͣ
Ϊ
ͦ
Ϊ
͢͡
Γ
ͨ
Ω
ͤ
͢ ͡
Ω
ͥ
͢ ͡
Ω
͢
͢ ͡
Ϊ
͡
Ϊ
ͥ
Ϊ
ͦ
Γ
͢͡
Ϊ
͡
Ϊ
ͨ
Γ
͢͢
Ϊ
͡
Ϊ
ͩ
Ϊ
ͪ
Γ
ͣ͢
Ϊ
͢
Ϊ
͢͢
Ϊ
Ͷ
Γ
ͤ͢
Ϊ
͡
Ϊ
ͣ
Ϊ
ͪ
Ϊ
͢͡
Γ
ͥ͢
Ϊ
͡
Ϊ
͢
Ϊ
ͣ
Γ
ͦ͢
Ϊ
͡
Ϊ
͢
Ϊ
͢͢
Γ
ͧ͢
Ϊ
ͥ
Ϊ
ͦ
Γ
ͨ͢
Ϊ
ͤ
Γ
ͪ
͞ Γ
ͣ͢
Fig. 8.27 Transformed GSAΓ
9
8.4 Synthesis for Multilevel Models of FSM with Elementary Chains 223
Fig. 8.28 Optimal codes of
EOLC for M
2
P
ES1
LFY
T1
Moore FSM S
28 1 4 2
3 5 6
00
01
00 01 11 10
7 11
8 10 9
11
10
*
*
1 2
*
3 4
*
*
b
1
b
5
b
9
b
12
b
6
b
10
b
13
b
14
b
15
b
16
b
17
b
21
b
17
b
13
b
19
b
6
b
1
b
3
b
7
b
2
b
20
b
10
b
11
b
8
b
9
b
4
b
5
00
01
11
10
0000
1 2 3 4
T
4
T
5
0001 0010 0101 0110 1000 1001 1010 1101 1110 0000
Fig. 8.29 Microinstruction addresses of M
2
P
ES1
LFY
T1
Moore FSM S
28
B
1
→ x
1
x
2
I
2
∨x
1
¯ x
2
I
3
∨ ¯ x
1
I
8
;
B
2
→ I
10
;
B
3
→ I
4
;
B
4
→ x
3
x
4
I
10
∨x
3
¯ x
4
I
11
∨ ¯ x
3
I
9
;
B
5
→ I
11
;
B
6
→ x
3
I
4
∨ ¯ x
3
I
5
;
B
7
→ x
1
I
6
∨ ¯ x
1
I
7
.
(8.28)
Next, the logical conditions in system of GFT are replaced by variables p
g
∈ P,
using the logical condition distribution shown in our example in Table 8.13:
B
1
→ p
1
p
2
I
2
∨ p
1
¯ p
2
I
3
∨ ¯ p
1
I
8
;
B
2
→ I
10
;
B
3
→ I
4
;
B
4
→ p
1
p
2
I
10
∨ p
1
¯ p
2
I
11
∨ ¯ p
1
I
9
;
B
5
→ I
11
;
B
6
→ p
1
I
4
∨ ¯ p
1
I
5
;
B
7
→ p
1
I
6
∨ ¯ p
1
I
7
.
(8.29)
This transformed system is used to construct the final transformed ST. For the
M
2
P
ES1
LFY
T1
Moore FSM S
28
, this table (Table 8.14) is constructed using sys-
tem (8.29) and EOLC codes from Fig. 8.28.
This table is used to derive the system of input memory functions
Ψ =Ψ(p
1
, p
1
, τ). (8.30)
For example, the following sum-of-products D
1
=F
3
∨F
4
∨F
5
∨. . . ∨F
9
∨F
13
=
¯ τ
1
¯ τ
2
¯ τ
3
¯ τ
4
¯ p
1
∨ ¯ τ
1
¯ τ
2
τ
3
∨τ
2
¯ τ
3
¯ τ
4
∨τ
4
∨ τ
2
τ
3
∨τ
1
τ
3
p
2
can be derived from Table
8.14. This formula is obtained after minimizing the initial expression derived
from the transformed ST.
224 8 FSM Synthesis with Elementary Chains
Table 8.14 Transformed structure table of M
2
P
ES1
LFY
T1
Moore FSM S
28
B
i
K(B
i
) α
g
K(α
g
) P
h
Ψ
h
h
B
1
0000 α
2
0010 p
2
D
3
1
α
3
0100 ¯ p
2
D
2
2
α
8
10100 ¯ p
1
D
1
3
B
2
001∗ α
10
1001 1 D
1
D
4
4
B
3
∗100 α
4
0001 1 D
4
5
B
4
∗∗∗1 α
10
1001 p
2
D
1
D
4
6
α
11
1110 ¯ p
2
D
1
D
2
D
3
7
α
9
1010 ¯ p
1
D
1
D
3
8
B
5
∗11∗ α
11
1110 1 D
1
D
2
D
3
9
1∗00 1∗00 α
4
0001 D
4
10
α
5
0101 ¯ p
1
D
2
D
4
11
B
7
1∗1∗ α
6
0110 D
2
D
3
12
α
7
1101 p
2
D
1
D
2
D
4
13
7. Specification of blocks BM and CCS. The following equations can be found
from the logical condition codes:
p
1
= ¯ z
1
x
1
∨z
1
x
3
;
p
2
= ¯ z
2
x
2
∨z
2
x
4
.
(8.31)
System (8.31) specifies the block BM, its analysis shows that z
1
= 1 for x
3
and z
2
= 1 for x
4
. It means that the following system can be derived from
Table 8.13:
z
1
= B
4
∨B
6

4
∨τ
1
¯ τ
2
¯ τ
3
;
z
2
= B
4

4
.
(8.32)
Analysis of system (8.32) shows that the equation z
2
is a part of the equation z
1
.
It means that it is enough only the variable z
1
to encode the logical conditions.
Thus, the block BM is represented by the following system.
p
1
= ¯ z
1
x
1
∨z
1
x
3
;
p
2
= ¯ z
1
x
2
∨z
1
x
4
,
(8.33)
In the same time, the block CCS is specified by the equation:
z
1

4
∨τ
1
¯ τ
2
¯ τ
3
. (8.34)
8. Linear microinstruction addressing is executed in a trivial way. In the dis-
cussed example, there are R
E
= 5, Z = ¦z
2
, . . . , z
6
¦. Let us address microin-
structions using maximal possible number of zeros in the addresses. One of the
addressing variants is shown in Fig. 8.30.
9. Specification of block BY. To specify the block BY, it is enough to replace
vertices b
q
∈B
1
by their contents, taking into account variables y
0
and y
E
. In the
8.4 Synthesis for Multilevel Models of FSM with Elementary Chains 225
b
1
b
2
b
3
b
14
b
9
b
10
b
11
b
5
b
18
b
19
b
13
b
8
b
17
b
7
b
16
b
4
b
12
b
20
b
6
b
15
b
12
00
01
11
10
000 001 010 011
z
4
z
5
z
6
100 101 110 111
*
*
* * *
* * *
z
2
z
3
* * *
Fig. 8.30 Linear microinstruction addresses of M
2
P
ES1
LFY
T1
Moore FSM S
28
discussed case, the initial specification is represented by Fig. 8.30. For example,
the cell with address A(b
2
) should contain the collection Y(b
2
) = ¦y
3
¦; the
cell with address A(b
8
) should contain the collection Y(b
8
) = ¦y
0
, y
1
, y
11
¦; the
cell with address A(b
13
) should contain the collection Y(b
13
) = ¦y
1
, y
11
, y
E
¦
and so on.
10. Specification of block BAT. This block is specified by the table with columns
b
q
, K(α
g
), K(b
q
), A(b
q
), Z
q
, q. In the discussed case, the address A(b
q
) is taken
Table 8.15 Specification of block BAT for M
2
P
ES1
LFY
T1
Moore FSM S
28
b
q
K(α
g
) K(b
q
) A(b
q
) Z
q
q
b
1
0010 ∗0 00000 – 1
b
2
0010 ∗1 00001 z
6
2
b
3
10∗1 ∗∗ 00010 z
5
3
b
4
∗100 ∗0 00100 4
b
5
∗100 ∗1 10000 z
2
5
b
6
00∗1 ∗0 00011 z
5
z
6
6
b
7
00∗1 ∗1 00101 z
6
7
b
8
01∗1 ∗0 00110 z
5
8
b
9
01∗1 ∗1 01000 z
3
9
b
10
011∗ ∗0 01001 z
3
z
6
10
b
11
011∗ ∗1 01010 z
3
z
5
11
b
12
111∗ ∗0 01100 z
3
12
b
13
111∗ ∗1 11000 z
2
z
3
13
b
14
110∗ 00 00111 z
5
z
6
14
b
15
110∗ 01 01011 z
3
z
5
z
6
15
b
16
110∗ 10 01101 z
3
z
6
16
b
17
110∗ 11 01110 z
3
z
5
17
b
18
– – – – 18
b
19
0000 10010 z
1
z
5
19
b
20
1∗00 ∗∗ 10100 z
1
20
b
21
101∗ ∗∗ 10011 ∗∗z
5
z
6
21
226 8 FSM Synthesis with Elementary Chains
ʹ΅
͵
͢
͵
ͣ
΃
ʹ
͢
ʹ
ͣ
͢
ͣ
ͦ
ͦ
ͧ
͢͡
ͣͣ
ͣͤ
ͣ͢
Ω
͢ ͢
Ω
ͣ ͣ
Ω
ͤ ͤ
7
͢
7
ͣ
ͥ
ͧ
ͨ
Ω
ͥ
ͦ
ͣͧ
ͣͨ
ͤ͢
͢͡
Ϊ
Ͷ
Ϊ
ͥ
Ϊ
ͦ
ͣͥ
͢
ͣ
ͤ
ͥ
ͦ
ʹ΄
͢
ͣ
ͤ
ͥ
ͦ
ͧ
ͨ
ͩ
ͪ
͢͡
͢͢
ͣ͢
ͤ͢
ͣͦ
Ϊ
͢
Ϊ
ͣ
Ϊ
ͤ
΄ΥΒΣΥ
ʹΝΠΔΜ
΃ ΅
΄
ͷΖΥΔΙ
ͧ
ͣ͢
͗
͢
͗
͢͡
͢͢
ͧ
ͧ
ʹ
͢
ʹ
ͣ
͢͢
Ϊ
͡
ͤ͢
͓͓͡
΃͸
͵
͢
͵
ͣ
͵
ͤ
͵
ͥ
΃
ʹ
͢
ͣ
ͤ
ͥ
ͩ͢
ͪ͢
ͣ͡
ͣ͢
ͥ͢
ͦ͢
ͧ
W
͢
W
ͣ
ͳ΃Ͳ;
ͪ
Ϊ
͡
Ϊ
ͧ
΁ͽ͵
ͥ͢
͢
ͣ
ͤ
ͥ
ͦ
ͧ
͢
ͣ
ͤ
ͥ
ͦ
ͦ͢
ͧ͢
ͨ͢
ͣͣ
ͣͥ
Ϋ
ͣ
ͣͦ
Ϋ
ͤ
ͣͧ
Ϋ
ͥ
ͣͤ
ͣͨ
Ϋ
ͦ
ͧ͢
W
ͤ
ͣ͢
ͨ͢
W
ͥ
Ϋ
ͧ ͣͩ
΁ͽ͵
ͩ
͢
ͣ
ͤ
ͥ
ͦ
ͧ
͢
ͣ
ͤ
ͥ
ͪ
ͩ͢
͵
͢
ͪ͢
͵
ͣ
ͣ͡
͵
ͤ
ͣ͢
͵
ͥ
΁ͽ͵
ͥ͢
͢
ͣ
ͤ
ͥ
͢
ͦ͢
ͧ͢
ͨ͢
ͣͪ
Ϋ
͢
Ϊ
͢͡
Ϊ
͢͢
Ϊ
ͨ
Ϊ
ͩ
Ϊ
ͪ
ͣͩ
͡ ;Ή
͢
͢
΁
ͣ
ͣͪ
ͪ
ͣ
ͥ
͡ ;Ή
͢
͢
΁
͢
ͣͪ
ͩ
͢
ͤ
Fig. 8.31 Logic circuit of M
2
P
ES1
LFY
T1
Moore FSM S
28
from Fig. 8.30; the column Z
q
contains variables z
r
∈ Z, equal to 1 in address
A(b
q
). Codes of components and EOLCs should be written taking into account
insignificant input assignments. The block BAT of M
2
P
ES1
LFY
T1
Moore FSM
S
28
is represented by Table 8.15.
This table is used to derive system
Z = Z(τ, T). (8.35)
For example, the following SOP z
1
= E
19
∨E
20
∨E
21
can be derived from Table
8.15, where the symbol E
q
stands for a conjunction of variables τ
r
∈ τ and T
r
∈ T
from the row q of the table (q = 1, . . . , M
E
). Taking into account the insignificant
input assignment, the final form z
1
= ¯ τ
2
¯ τ
3
¯ τ
4
∨τ
1
¯ τ
4
∨τ
3
τ
4
can be obtained.
Acting in the same manner, it is possible to design a logic circuit for any Moore
FSM represented by Table 8.11. The huge amount of possible solutions for the same
GSA shows necessity of an expert system using for a-priory choice of the best FSM
model on the base of preliminary analysis of characteristics for both a GSA to be
interpreted and logic elements to be used.
References 227
References
1. Baranov, S.I.: Logic Synthesis of Control Automata. Kluwer Academic Publishers,
Dordrecht (1994)
2. Barkalov, A., Titarenko, L.: Logic Synthesis for Compositional Microprogram Control
Units. Springer, Berlin (2008)
3. Barkalov, A., Titarenko, L., Kołopie´ nczyk, M.: Optimization of circuit of control unit with
code sharing. In: Proc. of IEEE East-West Design & Test Workshop - EWDTW 2006,
Sochi, Rosja, pp. 171–174. Kharkov National University of Radioelectronics, Kharkov
(2006)
4. Barkalov, A., Titarenko, L., Kołopie´ nczyk, M.: Optimization of control unit with
code sharing. In: Proc. of the 3rd IFAC Workshop: DESDES 2006, Rydzyna, Polska,
pp. 195–200. University of Zielona Góra Press, Zielona Góra (2006)
5. Barkalov, A., Wi´ sniewski, R.: Optimization of compositional microprogram control unit
with elementary operational linear chains. Upravlauscie Sistemy i Masiny (5), 25–29
(2004)
6. Barkalov, A., Wi´ sniewski, R.: Optimization of compositional microprogram control units
with sharing of codes. In: Proc. of the Fifth Inter. Conf. CADD’DD 2004, Minsk, Belorus,
vol. 1, pp. 16–22. United Institute of the Problems of Informatics, Minsk (2004)
7. Barkalov, A., Wi´ sniewski, R.: Design of compositional microprogram control units with
maximal encoding of inputs. Radioelektronika i Informatika (3), 79–81 (2004)
8. De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York
(1994)
9. Wi´ sniewski, R.: Synthesis of Compositional Microprogram Control Units for Pro-
grammable Devices. PhD thesis, University of Zielona Góra (2008)
Chapter 9
Conclusion
Now we are witnesses of the intensive development of design methods oriented on
field-programmable logic devices and ASICs. The complexity of digital system to
be designed increases drastically, as well as the complexity of FPLD chips used for
their design. These devices include billions of transistors and it is not a limit.
Development of digital systems with these complex logic elements is impossible
without application of hardware description languages, computer-aided design tools
and design libraries. But even application of all these tools does not guarantee that
some competitive product will be designed for appropriate time-to-market. To solve
this problem, a designer should know not only CAD tools, but the design and opti-
mization methods too. It is especially important in case of such irregular devices as
control units. Because of irregularity, their logic circuits are implemented without
using of the standard library cells; only macrocells of a particular FPLD chip can be
used in FSM logic circuit design. In this case, the knowledge and experience of a de-
signer become a crucial factor of the success. Many experiments conducted with use
of standard industrial packages showthat outcomes of their operation are, especially
in case of complex control units design, far fromoptimal. Thus, it is necessary to de-
velop own program tools oriented on FSM optimization and use them together with
industrial packages. This problemcannot be solved without fundamental knowledge
in the area of logic synthesis. Besides, to be able to develop his(her) own new design
and optimization methods, a designer should know the existed methods.
We think that FSM models and design methods proposed in our book will help
in solution of this very important problem. We hope that our book will be useful for
the designers of digital systems and scholars developing synthesis and optimization
methods oriented towards the control units and ever-changing field-programmable
logic devices used for FSM logic circuit implementation.
A. Barkalov and L. Titarenko: Logic Synthesis for FSM-Based Control Units, LNEE 53, pp. 229.
springerlink.com c Springer-Verlag Berlin Heidelberg 2009
Index
address decoder 53
addressing conflict 18
addressing of microinstructions
combined, 11
compulsory, 11, 15
linear, 213
natural, 11, 16
address transformer 208, 211
algorithm 1
application-specific integrated circuit
(ASIC) 25
automaton
control, 2
operational, 2
block of FSM 84
Boolean
equation, 98
function, 1
space, 9
system, 8
variable, 8
class
compatible microoperations, 87, 90
pseudoequivalent EOLC, 202
pseudoequivalent states, 9
code of
class of pseudoequivalent states, 9
code sharing 144, 198, 208
code transformer 46
combinational circuit 5
compatibility of microoperations 144
compatible microoperations 139
complex programmable logic de-
vice(CPLD) 60
compositional microprogram control
unit (CMCU) 23
computer aided design (CAD) system
ASYL, 9
ATOMIC, 70
DEMAIN, 70
MAX+PLUS II, 69
NOVA, 9
Quartus, 70
SIS, 70
ZUBR, 70
control memory 3, 10
control unit 10
data-path 2
decoding of collections of
microoperations 138
decomposition
functional, 53
structural, 67, 68, 138
design 10, 11
don’t care input assignments 10
embedded memory block 112, 113
encoding
collections of microoperations, 86
encoding of
classes of pseudoequivalent
elementary OLC, 202
states, 9
collections of microoperations, 38, 40
232 Index
fields of compatible microoperations,
87
logical conditions, 182
logical condtions, 187
rows of structure table, 92
states of FSM, 4, 5
ESPRESSO 9, 70
expanded microinstruction 212
expansion of
PLA terms, 57
PROM inputs, 54, 55
PROM outputs, 54, 55
field-programmable gate array (FPGA)
64
field-programmable logic device
(FPLD) 53
finite state-machine (FSM)
Mealy, 1
Moore, 1
flip-flop 4, 59, 62, 63
frequency encoding of
microoperations, 216
states, 141
function
ceil, 4
input memory, 106
irregular, 51
multiplexer, 51
regural, 51
generalized formula of transitions
(GFT) 197
generalized interval of Boolean space
9
generic array logic (GAL) 59
graph-schemes of algorithms
linear, 22
marked, 5, 7
transformed, 12
vertical, 139
hardware description language (HDL)
69
identification of
microoperations, 157
states, 162
identifier 157
input memory functions 197
input of EOLC 194
Karnaugh map 9
logical condition 1
look-up table (LUT) element 64
macrocell 59
matrix
AND, 29
OR, 29
matrix realization
of logical condition replacement, 35
of system of microoperations, 39
primitive, 29
microinstruction 1
control, 16
operational, 16
microinstruction address 11
microoperation 1
microprogram 1
microprogram control 1, 10
microprogram control unit 10
model of FSM 71
multiplexer 15, 51
one-hot encoding of microoperations
14
operational linear chain (OLC) 22
operational unit 2
optimal encoding of
elementary operational linear chains,
202
states, 9
output of OLC 23
partition on classes of
compatible microoperations, 87
pseudoequivalent elementary
operational linear chains, 202
pseudoequivalent states, 9
product term 9, 10
programmable array logic (PAL) 59
programmable logic 53
programmable logic array (PLA) 56
programmable logic device (PLD) 25
programmable logic sequencer (PLS)
58
Index 233
programmable read-only memory chips
(PROM) 53
pseudoequivalent
elementary operational linear chains,
201
states, 9
random-access memory (RAM) 9
read-only memory (ROM) 9
replacement of logical conditions 35
state
current, 4
initial, 4
internal, 4
next, 6
pseudoequivalent, 9
state assignment 5, 38
state code 4
state encoding
arbitrary, 45
combined, 45
frequency, 141
state variables 4
structural diagram 2
structure table of FSM 6
sum of products (SOP) 6
synchronization 61–63, 66, 140
synthesis 25, 41, 53
system of
Boolean functions, 29
generalized formulae of transitions,
200
table of
address transformer, 212
code transformer, 82, 83
transformation of
elementary OLC codes, 203
initial GSA, 12, 17
state codes, 29, 81, 104, 109
structure table, 91, 94
transformed
formula of transitions, 15
GSA, 12, 13
structure table, 10
vertex
conditional, 2
final, 2
initial, 2
operator, 2
verticalization of GSA 140

Lecture Notes Electrical Engineering Volume 53

Alexander Barkalov and Larysa Titarenko

Logic Synthesis for FSM-Based Control Units

ABC

Prof. Alexander Barkalov Institute of Informatics and Electronics University of Zielona Gora Podgorna Street 50 65-246 Zielona Gora Poland E-mail: a.barkalov@iie.uz.zgora.pl Dr. Larysa Titarenko Institute of Informatics and Electronics University of Zielona Gora Podgorna Street 50 65-246 Zielona Gora Poland E-mail: abar54@mail.ru

ISBN 978-3-642-04308-6 DOI 10.1007/978-3-642-04309-3

e-ISBN 978-3-642-04309-3

Library of Congress Control Number: 2009934355 c 2009 Springer-Verlag Berlin Heidelberg This work is subject to copyright. All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilm or in any other way, and storage in data banks. Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer. Violations are liable to prosecution under the German Copyright Law. The use of general descriptive names, registered names, trademarks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. Typeset & Coverdesign: Scientific Publishing Services Pvt. Ltd., Chennai, India. Printed in acid-free paper 987654321 springer.com

and final assembly of this book. His guidelines in making this book useful for students and practitioners were very helpful in the organization of this book. We also thank Professor Marian Adamski for his support and special attention to this work. Our PhD students Mr Jacek Bieganowski and Mr Slawomir Chmielewski worked with us on initial planning of this work.Acknowledgements Several people helped us with preparation of this manuscript. . distribution of tasks during the project.

. . . . . . .1 Principle of Microprogram Control . . . . . . . . . . 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Contents 1 Hardwired Interpretation of Control Algorithms . . .4 Design of Control Units with FPLD . . . . . . .2 Optimization of Mealy FSM Matrix Realization . . Evolution of Programmable Logic . . . . . . . . . . . . . . . . . . . . . . .2 Control Algorithm Interpretation with Finite State Machines . . . . . 2. . 1. . . . . . . . . . . . . . . . . . 1 1 4 10 22 25 29 29 35 42 52 53 53 60 64 67 71 77 77 86 92 2 3 4 . . . References . . . . . . . . . . . . . . . . . . 4. . . . . . . . . . . . . . . . . . . 1. . . . . . . . . . . . . . . . . . . . . 3. . . . . . . .1 Primitive Matrix Realization of FSM . . . . . . . . . . . . . . . . 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. . . . . . . . References . . . . . . . 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Programmable Devices Based on LUT Elements . . . . 3. . . . . .2 Programmable Logic Devices Based on Macrocells . . . . . . . . . . . . . . .1 Simple Field-Programmable Logic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. . . . . . . . . . . . . . . . . . . . . . . . .3 Optimization of Moore FSM Logic Circuit . .1 Synthesis of FSM with Replacement of Logical Conditions . . .3 Control Algorithm Interpretation with Microprogram Control Units . . . . . . . . . . . . . . .2 Synthesis of FSM with Encoding of Collections of Microoperations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . Optimization for Logic Circuit of Mealy FSM . . . . . . . . . . .3 Synthesis of FSM with Encoding of Rows of Structure Table . . . . . . Matrix Realization of Control Units . . . . . . . . . . . . . . . . . . . . . .4 Organization of Compositional Microprogram Control Units . . . . . . . . . . 4. . . . . . . . . . . . . . . . . . . 1. 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . FSM Synthesis with Elementary Chains . . . . . . . . 7. . . . . . . . . . . . . . . . 8. . . . . . . . . . . . . . . . . . . .4 Synthesis for Multilevel Models of FSM with Elementary Chains . . . . . 231 . .2 Optimization of Block of Input Memory Functions . . . . . . . . . . . . 8. . . . .2 Logic Synthesis for Mealy FSM with Object Code Transformation . . . . . .3 Optimization of Block of Microoperations . . . . . . . . . . . . . . . . . . . . References . . . . . . . . 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VIII Contents 4. . . . . 5. . . . . . . . . . . . . . . . . . . . . . . . 95 References . . . . . . . . . . . . . . . . . . . . . 5. . . . . . . . . 102 5 Optimization for Logic Circuit of Moore FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Synthesis of FSM Multilevel Logic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Optimization of Logical Condition Replacement Block . . . . . . . . . . . .1 Basic Models of FSM with Elementary Chains . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM Synthesis with Object Code Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . 7. . FSM Synthesis with Transformation of GSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Multilevel Models of FSM with Object Code Transformation . . . . . . . . . . . . . . .2 FSM Synthesis for CPLD with Embedded Memory Blocks . . . . . . 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. . . . 6. . . . . . . . . . . . . . . . . . . .1 Principle of Object Code Transformation . . . . 6. . . . . . . . . . . . . . 103 103 112 120 126 129 129 138 145 153 155 155 157 168 181 190 193 193 201 208 218 227 6 7 8 9 Conclusion . . . . . . . . . . . . . . . .2 Optimization for Block for Decoding of Microoperations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Synthesis of Multilevel FSM Models .1 Optimization for Two-Level FSM Model . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . .3 Logic Synthesis for Moore FSM with Object Code Transformation . . . . . 5. . . . . . . . . . 6. . . . . . . 7. . . . . . . . . 229 Index . . .3 Synthesis of Moore FSM with Logical Condition Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . .

. . . where |τ | = R0 and R0 = log2 I . . . . . . . where |P | = G. xL } Y = {y1 . . . . . ϕR } H ΠA = {B1 . . . . . yN } Yq ⊆ Y Γ b0 bE B1 B2 E = { bt . . . bq } am ∈ A K(am ) A = {a1 . . . TR } Am ∈ A Φ = {ϕ1 . .Symbols X = {x1 . .or OR-plane) area of matrix Mi set of FSM terms set of logical conditions determining transitions from the state am ∈ A additional variable used to replace logical conditions. bgFg Mi S(Mi ) F = {F1 . . . . . . |X(aM )|) set of logical conditions written in the column pg additional variable used to encode the microinstructions binary code of collection Yt set of variables used to code classes Bi ∈ Πa . . . . G = max(|X(a1 )|. . . aM } T = {T1 . . BI } K(Bi ) αg = bg1 . . FH } X(am ) pg ∈ P X(pg ) zr ∈ Z K(Yt ) τ set of logical conditions set of microoperations collection of microoperations (microinstruction) graph–scheme of algorithm start vertex of GSA end vertex of GSA set of GSA operator vertices set of GSA conditional vertices set of GSA arcs internal state of FSM code of internal state am ∈ A set of FSM internal states set of FSM state variables conjunction of state variables corresponding to the state code K(am ) set of FSM input memory variables (excitation functions) the number of structure table rows (lines) set of the classes of pseudoequivalent states code of class of pseudoequivalent states Bi ∈ ΠA operational linear chain matrix (AND.

. . . vRV } CE = {α1 . where RE = log2 ME the number of operator vertices in transformed GSA output of EOLC αg ∈ CE address of EOLC output Og input of EOLC αj ∈ CE address of EOLC input Ij the number of EOLC in GSA Γ the number of components in EOLC αj ∈ CE the maximal number of components in EOLC of GSA Γ . . αGE } RE ME Og A(Og ) Ij A(Ij ) GE Mg QE FSM block generating variables for logical condition replacement FSM block generating variables written in the rows of (transformed) structure table FSM block generating microoperations and implemented with embedded memory blocks FSM block generating microoperations and implemented with decoders FSM block generating variables corresponding to rows of (transformed) structure table multiplexer from block BM generating function pg ∈ P code of microoperation yn ∈ Y k from the class k of compatible microoperations the number of bits in the code K(yn ) additional variables used for encoding of microoperations yn ∈ Y k decoder from block BD generating microoperations from the class k of compatible microoperations binary code of row h of FSM structure table the number of bits in code K(Fg ) the number of terms for SOP of some function f the number of terms for PAL-based macrocell the number of macrocells having q terms. . .X Symbols BM BP BY BD BF M Xg K(yn ) Rk zr ∈ Z k DCk K(Fh ) RF H(f ) q n(f. . q) N Li V (Γ ) I K(Ik ) V = {v1 . necessary to implement the logic circuit for function f the number of FSM models having i levels graph-scheme of algorithm Γ after verticalization set of identifiers for FSM with object codes transformation binary code of identifier Ik ∈ I having RV = log2 K bits set of variables used for encoding of identifiers Ik ∈ I set of elementary operational linear chains the number of microinstruction address bits. .

Symbols XI REO RCO K(αg ) K(bt ) the number of variables for encoding of EOLC. where REO = log2 QE code of EOLC αg ∈ CE code of component bt ∈ B1 of EOLC αg ∈ CE . where REO = log2 GE the number of variables for encoding of EOLC.

Abbreviations ASIC BAT BTC BM BP BTC BY CA CAD CAMI CC CCS CFA CLB CM CMCU CMO CPLD EAB EPROM EEPROM EOLC FPLD FSM FPGA GFT GSA HDL LAB LE LUT application-specific integrated circuit block of address transformer block of code transformer block for logical condition replacement block forming input memory functions of FSM block for code transformation block forming microoperations of FSM control automaton computer-aided design counter of microinstruction address sequential circuit state code transformer circuit of address formation (sequencer) configurable logic block control memory compositional microprogram control unit circuit (block) of microoperation generation complex programmable logic devices embedded array block erasable programmable read-only memory electrically erasable programmable read-only memory elementary operational linear chain field-programmable logic devices finite state machine field-programmable gate arrays generalized formula of transition graph.scheme of algorithm hardware description language logic array block logic element look-up table .

XIV Abbreviations MCU MX OA OLC PAL PLD PLA PLS PROM RAM RAMI RG ROM SBF SOP SPLD ST TMS TSM VGSA VLSI microprogram control unit multiplexer operational automaton operational linear chain programmable array logic programmable logic device programmable logic array programmable logic sequencer programmable read-only memory random-access memory register of microinstruction address register read-only memory system of Boolean functions sums of products simple programmable logic devices structure table microoperation code transformer state code transformer vertical graph.scheme of algorithm very large scale integration circuit .

Up-to-day FPLD chips are so huge. Because of the extreme complexity of modern microchips. Logic schemes of data-path have regular structures. particularly the field programmable logic devices (FPLD). where there are no standard formal methods of their solution. that it is enough only one chip to implement a really complex digital system including a datapath and a control unit. such as VHDL and Verilog. such as performance. especially in the acceptable time-to-market. As a rule. It allows a researcher to pay more attention to some specific problems. any digital system can be represented as a composition of a datepath and a control unit. The development of digital systems with use of FPLD microchips is not possible without use of different hardware description languages (HDL). it is very important to develop effective design methods oriented on particular properties of logic elements. This problem solution is possible only if a researcher possesses fundamental knowledge of a design process and knows exactly the mode of operation of industrial CAD tools in use. depend to a large extent on characteristics of its control . multibit adders. decoders and so on) for their design. Actually. we observe a real technical boom connected with achievements in nanoelectronics.Introduction Tremendous achievements in the area of semiconductor electronics turn microelectronics into nanoelectronics. A control unit coordinates interplay of other system blocks producing a sequence of control signals that causes some operations in a data-path. It results in development of very complex integrated circuits. it allows use of standard library elements of CAD tools (such as counters. the problem of system design is reduced practically to the design of control units. multipliers. As it is known. the design process is now very similar to the process of program development. But application of all these achievements does not guarantee per se development of some competitive electronic product. In case of complex logic controllers. As majority of researches point out. Different computer-aided design tools (CAD) are wide used to develop digital system hardware. which makes process of their design very sophisticated. control units have irregular structures. power consumption and so on. Many important features of a digital system. multiplexers.

The book contains some original design and optimization methods based on the structural decomposition of FSM model. PLA. This choice is based on obvious fact that this specification provides simple explanation of methods proposed by authors. Such an approach results in multilevel models of FSM. In the same time. to design competitive digital systems with FPLD chips. the methods of transition from GSA to Mealy and Moore FSM graphs are shown. in which the following information is presented: Chapter 1 introduces such basic topics as principle of microprogram control and specification of control units by graph-scheme of algorithms. this book is devoted to solution of the problems of logic synthesis and reduction of hardware amount in control units. To help such a designer. this information should be transformed using data formats of particular industrial CAD systems. This step is beyond the scope of our book. In order to implement corresponding circuits. in case of complex control units design. such as finite state machines and microprogram control units. In our book. where regularity of the device increases in comparison with known single. or LUT macrocells) in comparison with logic circuits based on known models of FSM. Regular parts of these models can be implemented using such library elements as memory blocks. control algorithms are represented by graph-schemes of algorithms (GSA). interstate transitions. and FSM structure table are introduced. Last part of the chapter is devoted to organization principles of compositional microprogram control units. These control units are Moore . Next. next to program them and at last to combine them with standard packages to get a result with desired characteristics. which can be viewed as a composition of Mealy finite-state machine addressing microinstructions and microprogram control unit with natural microinstruction addressing. The methods of synthesis and design presented in the book are not oriented to any particular FPLD chips. FSM states. All FSM discussed in the book are specified either by GSA or by structure table of FSM. As our experience shows. These tables are used to find the systems of Boolean functions. a designer should have fundamental knowledge in the area of logic synthesis and optimization of logic circuits of control units. The FSM models of Mealy and Moore are introduced. but also the embedded memory blocks. It means that a designer may be forced to develop his own design methods. This approach is especially fruitful when a control unit is implemented using up-to-day FPLD chips which include not only combinational macrocells. Such conceptions as microoperations (FSM output signals). but to construction of tables describing the behaviour of FSM blocks. It permits to decrease the total number of logic elements (PAL. decoders and multiplexers. logical conditions (FSM input signals). some methods of control algorithms interpretation are discussed. an irregular part of the control units described by means of Boolean functions is reduced. when a control unit is represented using the model of finite state machine (FSM). far from optimal. Therefore. GAL. design methods used by standard industrial packages are. which can be used to implement logic circuits of particular FSM blocks.XVI Introduction unit.and double-level models.

or PLA. it is shown that the model of Moore FSM offers an additional possibility for its circuit optimization due to existence of the classes of pseudoequivalent states. the methods of structure table rows encoding are discussed. in which some particular elements are used. Next. These methods allow decrease for circuit redundancy due increase of the number of FSM model levels. they can be used for interpretation of linear GSA. It is reduced to direct interpretation of FSM structure table and is characterized by considerable redundancy. It increases FSM logic circuit regularity and leads to simplification of its design process. The methods of logical condition replacement are analyzed. Each such class corresponds to one state of the equivalent Mealy FSM. These methods are based on results of joint investigations conducted by the authors and their PhD students Cololo S. Each of these methods produces double-level circuit of Mealy FSM. whereas the encoding of collections of microoperations permits to use embedded memory blocks. PLA and PAL chips. connected with logic synthesis and optimization of FSM implemented with custom matrix integrated circuits. The analysis is accompanied by some examples for systems of Boolean functions implementation using PROM. PAL and GAL. Next. Chapter 3 discussed contemporary field-programmable logic devices and their evolution. starting from the simplest programmable logic devices such as PROM. (Poland).based macrocells are used for logic circuit . The primitive matrix implementation of FSM circuit is analyzed first. This analysis shows particular features of different logic elements and permits to optimize the FSM logic circuits.Introduction XVII FSMs using counter to represent their state codes. as well as on transformation of state codes into class codes. the methods of logical condition replacement and encoding of collections of microoperations are considered. Chapter 4 is devoted to the hardware amount reduction in the logic circuit of Mealy FSM. Standard decoders can be used in case of encoding of the classes of compatible microoperations. and finishing with very sophisticated chips such as CPLD and FPGA. as well as different methods of encoding of collections of microoperations (maximal encoding and encoding of the classes of compatible microoperations). Optimization methods are introduced based on different approaches for state encoding. (Ukraine) and Chmielewski S. the main advantage of whose is possibility of standard library cells use for implementation of logic circuits for some blocks of an FSM model. These methods deal with both homogenous and heterogeneous CPLD chips. The main part of the chapter is devoted to joint application of these methods. The last part of the chapter is devoted to optimization of the block generating microoperations. Chapter 5 is devoted to original synthesis and optimization methods oriented on Moore FSM logic circuit implemented with CPLD. the logical condition replacement allows application of multiplexers. Next. PLA. The principle of functional decomposition oriented on FPGA chips is analysed in the last part of the chapter. In the first case. For example. Chapter 2 discusses some problems. only PAL.

The methods assume joint minimization of Boolean expressions for input memory functions and microoperations of Moore FSM. where the register keeps EOLC codes. either microinstruction addresses or code of EOLC component. the multilevel models of FSM with object code transformation. the logic circuit is implemented using both PAL-based macrocells and embedded memory blocks. The second part of the chapter is devoted to hardware optimization for block of microoperations. This chapter is written together with employee of ”Nokia-Siemens Network” Alexander Barkalov (Ukraine). these methods permit to decrease the number of macrocells in the block generating input memory functions. At last. based on verticalization of an interpreted GSA. The methods of EOLC encoding and transformation are discussed. . The last part of the chapter is devoted to joint application of proposed methods and logical condition replacement. Chapter 7 is devoted to original optimization methods oriented on decrease of the number of outputs for FSM block generating input memory functions. The FSM objects are either states or collections of microoperations. Chapter 8 is devoted to original methods oriented on optimization of Moore FSM interpreting graph-schemes of algorithms with long sequences of operator vertices having only one input. Sometimes.XVIII Introduction implementation. These methods are based on the object code transformation. It permits to decrease the number of decoders (up to 1) and bit capacity of microinstruction word. In the beginning the Moore FSM models with code sharing are analysed. Chapter 6 is devoted to design methods based on transformation of an interpreted graph-scheme of algorithm. These FSM models include the counter keeping. Such optimization methods are discussed for both Mealy and Moore finite state machines. The second part of the chapter is devoted to reduction of the number of embedded memory blocks in the FSM block generating microoperations. but this optimization is connected with increase for the number of cycles required for a control algorithm interpretation. all FSM transitions depend on single logical condition. These methods are based on transformation of microinstruction address represented as concatenation of EOLC code and code of its component into either linear microinstruction address or code of collection of microoperations. In extreme case. some additional identifiers are needed for one-to-one representation of different objects. it allows use of embedded memory blocks for implementation of FSM input memory functions. The methods of decrease for the number of logical conditions per FSM state are discussed. In this case all FSM blocks are implemented using standard library cells (not just macrocells of a particular FPLD chip). the models based on joint application of these methods are discussed. These sequences are named elementary operational linear chains (EOLC). In the second case. The last part of the chapter discusses synthesis methods for multilevel FSM models with EOLC. At last. The hardware amount reduction is based on use of several sources (up to three) to represent the codes of classes of pseudoequivalent states. logical condition replacement and encoding of collections of microoperations are discussed.

. as well as for designers of modern digital devices.Introduction XIX We hope that our book will be interesting and useful for students and postgraduates in the area of Computer Science. We think that proposed FSM models enlarge the class of models applied for implementation of control units with modern CPLD and FPGA chips.

A digital A.1 Principle of Microprogram Control The principle of microprogram control was proposed by M. c Springer-Verlag Berlin Heidelberg 2009 springerlink. 69] and was developed by V. Last part of the chapter is devoted to the organization principles of compositional microprogram control units. Special logical conditions (status signals or flags) are used to control the order of execution of microoperations. Next. Glushkov [1]. pp. 1–28. The Mealy FSM is used in CMCU to address microinstructions. These control units provide efficient interpretation of the so-called linear GSA. 1. Their values are calculated as some Boolean functions depending on the values of operands. An algorithm of execution of some operation is represented in terms of microinstructions and logical conditions is named microprogram [22]. It permits to calculate the transition address during one cycle of control unit’s operation. It permits to use the counter to keep microinstruction addresses and to simplify the combinational part of control unit. The chapter introduces such basic topics. Barkalov and L. An ensemble of microoperations executed during one cycle of a digital system operation is named microinstruction.Chapter 1 Hardwired Interpretation of Control Algorithms Abstract. Microinstructions corresponding to the components of OLC are addressed using the principle of natural microinstruction addressing. Titarenko: Logic Synthesis for FSM-Based Control Units. which can be viewed as compositions of finite-state machine and microprogram control unit. any complex operation executed by a digital system is represented as a sequence of elementary operations of information processing. as compared with the classical Moore FSM. such as finite-state machines (FSM) and microprogram control units (MCU). are discussed. as principles of microprogram control and specification of the control unit behavior using the graph-scheme of algorithm. performance of the CMCU (proportional to the number of cycles needed to execute the control algorithm) is better than performance of the equivalent MCU with natural microinstruction addressing. Wilkes in 1951 [68. in which long sequences of operator vertices can be found. LNEE 53.com . These sequences are called operational linear chains (OLC). Due to this feature. some methods of control algorithm interpretation. These elementary operations are named microoperations. According to this principle.

Fig. 1. denoted here by the symbol b0 . It has two outputs. bq }. The vertices bt ∈ B are connected by arcs from a finite set E = { bt . Fig. GSA Γ is characterized by a finite set of vertices B = B1 ∪ B2 ∪ {b0 . .2 1 Hardwired Interpretation of Control Algorithms system with microprogram control is represented by an operational unit. . 1. xL }. denoted here by the symbol bE . which initialize operand processing and obtaining of intermediate and final results of operations. 8. yN } is a set of microoperations. where Y = {y1 .1 Structural diagram of operational unit Data F Data path X Control automation Y Results In the operational unit.1) [1. The operational unit is the composition of operational automaton (OA). bE }.2 Types of vertices of GSA a) Start Yq End 1 b) c) d) xl 0 The start vertex. where B2 is a set of conditional vertices of GSA Γ . which coordinates the interplay of all system blocks (Fig. corresponds to the end of control algorithm and has no output. characterized by a finite set of vertices. namely (Fig. 1. . and control automaton (CA). contains single element xl ∈ X. . . The end vertex. end (final) vertex. Thus.schemes of algorithm (GSA) which is very popular in design practice [8. executed by the data-path. . In this book we use the language of graph. bq ∈ B. where bt . The conditional vertex bt ∈ B2 . CA analyses the code of operation together with values of logical conditions from the set X = {x1 . The operator vertex bt ∈ B1 . Graph-scheme of algorithm Γ is the directed connected graph. 9]. contains a collection of microoperations Yq ⊆ Y which are executed in parallel. where B1 is a finite set of operator vertices of GSA Γ . 9]. operator and conditional vertices.2): start (initial) vertex. corresponds to the beginning of control algorithm to be interpreted and has no input. An algorithm of operational unit’s operation is represented using one of the formal methods [8]. which is a data-path of the system. first corresponding to value "1" and second to value "0" of the logical condition to be checked. Microinstructions Yq ⊆ Y are executed on the base of this analysis. . 1. . .

They could be found. These methods could be based either on a model of a finite state machine (automaton with hardwired logic) or on the principle of keeping the microprogram in a special control memory (automaton with programmed logic) [1]. for example. . the set of logical conditions X = {x1 .3 Graph-scheme of algorithm Γ1 Start b0 y1y2 b1 b2 1 x1 0 b4 y3 b3 1 x2 0 y2y3 b5 y1y4 b6 End bE A control algorithm can be implemented either as a program (program interpretation) or as a network of logic elements connected in a particular way (hardwired interpretation). . 8. . b1 . the GSA Γ1 (Fig. b6 . the set of microoperations Y = {y1 . b1 . . 35.3) is characterized by the following sets: • • • • the set of vertices B = {b0. . Fig. . b2 . Let us discuss the classical methods of control units design. . 1. 1. . In this book we discuss the methods of hardwired interpretation for control algorithms represented by GSAs. . in [1.1 Principle of Microprogram Control 3 For example. x2 }. . Methods of data-path design are not discussed in this book. 6. b1 . the set of arcs E = { b0 . . bE }. .1. y4 }. bE }. b6 . 47].

greater than or equal to A. 1. . . . . . especially if they contain cycles with unpredictable number of iterations.Y (t). output signal Y (t) at time t is determined by the following expression: Y (t) = f (X (0). Thus. . . This sequence is determined by input signals X (0). The code of current state is kept in register RG.4 Structural diagram of finite state machine X T CC Y RG Start Clock Presence of the register RG can be explained in the following way. . X (t − 1) for previous time intervals. which is the composition of sequential circuit CC and register RG (Fig. The FSM produces as its output information a time-distributed microinstruction sequence Y (0). . . which form the set Φ = {φ1 . . X (t)). 45]. 1. Fig. The internal states of FSM are used to represent the prehistory of its operation. . some information about prehistory of the system operation is needed. where A is the least integer. . . .4 1 Hardwired Interpretation of Control Algorithms 1. . . The states am ∈ A. . where t is the automaton time determined by synchronization pulse Clock. . The code of initial state a1 ∈ A is loaded into register using pulse ”Start”. Elements of the set of state variables T = {T1 .2 Control Algorithm Interpretation with Finite State Machines The finite state machine. TR } are used to encode the states of FSM. called in [9] as microprogram automaton.Y (1). are encoded by binary codes K(am ) having R = log2 M (1.4). X(t − 1). the register RG is implemented using D flip-flops [26. .2) bits. This function is known as a ceil function or ceiling [48]. which includes R flip-flops.1) Expressions of this kind are very complex and could not be easy realized in hardware. represents a control algorithm by a classical model. . the content of RG can be changed by pulse Clock on the base of input memory (excitation) functions. . As a rule. φR }. . aM } is a set of internal states. and common timing signal Clock is used for their synchronization. (1. where A = {a1 . . To produce such a sequence. . The initial instant t = 0 is determined by a single-shot pulse ”Start”.

5b). Let the states are encoded . H) corresponds to conjunction of some variables from the set X (or their complements).47. Input signal Xh (h = 1.37. Each arc is marked by a pair input signal. Output signal Yh ⊆ Y corresponds to some collection of microoperations yn ∈ Y . X). . Let us discuss some examples of FSM synthesis using GSA Γ1 to represent the control algorithm to be interpreted. Let us use a trivial encoding of states first.56. are marked by unique states a2 . Application of this procedure to GSA Γ1 leads to the marked GSA Γ1 (Fig. . . aM . 17. 1. .5) (1.42. (1.39. 25. output signal . In case of the Mealy FSM S1 .3) and the output functions Y. too).5a). There are many methods of state assignment [1. .44. 20. which belongs to the transition h of Mealy FSM (h = 1. 1. . written into an operator vertex. A = {a1 . connected with outputs of operator vertices. corresponding to the graph of Mealy FSM S1 (Fig. whereas its arcs correspond to the transitions among the states. Thus. x2 }. . .59. system Y is represented as Y = Y (T. using minimum possible amount of state variable to encode the states. encoding of the internal states (state assignment). . H). a2 . T2 }. Mealy FSM S1 is described by sets X = {x1 .46. 12. The vertices of this graph correspond to the states of Mealy FSM S1 . . . construction of the structure table of FSM. 28–34. a3 } and has H = 5 transitions among its states. R = 2. • inputs of vertices bt ∈ B. . we have M = 3.65–67. y4 }. X) (1.2 Control Algorithm Interpretation with Finite State Machines 5 The combinational circuit CC produces both input memory functions Φ = Φ (T. In case of the Mealy FSM. 23. These methods depend strongly on logic elements in use.53.1.36. Y = {y1 . In case of Mealy FSM. 21. 18. 7. implementation of FSM logic circuit using some logic elements. . targeted on optimization of hardware amount of the combinational circuit CC.4) The method of FSM synthesis on the base of GSA Γ includes the following steps [9]: • • • • • construction of marked GSA Γ . construction of systems Φ and Y on the base of the structure table.57. T = {T1 .54.61–63. 4. . which depend strongly on the FSM model in use [1]. • any input can be marked only once.51. .40. whereas in the case of Moore FSM these functions depend only on the states: Y = Y (T ).70]. 13. marked GSA is constructed in the following way [9]: • the output of the initial vertex b0 and the input of the final vertex bE are marked by an initial state a1 (it is a final state. .

as is the state of transition (next state of FSM). as . H). 1. This table includes a column Φh with input memory functions. Yh is the output signal produced during the transition am . term Am is the conjunction of state variables Tr ∈ T corresponding to the code of state am ∈ A from the line h of the structure table: . (1. Functions (1. K(a2 ) = 01 and K(a3 ) = 10. which are equal to 1 in order to change the states of particular FSM memory flip-flops. This table includes the following columns [9]: am is the current state of FSM.3) – (1. An FSM structure table (ST) can be viewed as the FSM graph represented by a list of interstate transitions. which are equal to 1 to change the register content from K(am ) into K(as ).5 Marked GSA Γ1 (a) and graph of Mealy FSM S1 (b) using the following codes:K(a1 ) = 00.6 1 Hardwired Interpretation of Control Algorithms a1 __ a2 _ a3 Fig. . Let us point out that the code K(a1 ) should include only zeros to simplify the circuit of setting FSM into the initial state a1 ∈ A.6) In this formula. as . .4) are derived from the FSM structure table as the sums of products (SOP) depending on the following product terms Fh = Am Xh (h = 1. Φh is the collection of input memory functions. Xh is the input signal determined the transition am . In case of Mealy FSM S1 this table contains H = 5 lines (Table 1.1). h = 1. K(as ) is the code of this state. . . K(am ) is the code of the state am ∈ A. H is the number of transition. Structure table is constructed in a trivial way using the automaton graph.

. if and only if (iff) the line of the ST includes the variable φr (yn ). lm (1. (1.1. • the operator vertices bt ∈ B1 are marked by unique states a2 . y4 = F4 . . . K(am ). ¯ ¯ For example. . from Table 1. The marked GSA of Moore FSM is constructed using the following procedure [9]: • the vertices b0 and bE are marked by the initial state a1 . the Moore FSM S2 is represented by the sets X = {x1 . variable lmr ∈ {0. . This table has the following columns: am . F4 = T1 T2 x1 x2 .2 Control Algorithm Interpretation with Finite State Machines Table 1. . . Thus. aM .6b). A = {a1 . F3 = T1 T2 x1 x2 . . . the structure table contains H = 7 lines (Table 1. . The vertices of Moore automaton graph are marked by output signals yn ∈ Y . corresponding to the automaton graph of Moore FSM S2 (Fig. as . . F5 = T1 T2 . K(as ). . . . F2 = ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ T1 T2 x1 . R. R). In case of the Moore FSM S2 . and ¯ Tr0 = Tr . 1. . because of it its arcs are marked only by input signals determining the transitions among the states. y3 = F2 ∨ F3 . . Systems (1. (n = 1. .2).(1. T2 . 1. . Application of this procedure to the GSA Γ1 leads to the marked GSA Γ1 (Fig. Crh (Cnh ) is a Boolean variable equal to 1. 1} is the value of bit r of the code K(am ). . Implementation of FSM circuit depends strongly on particular properties of logic elements in use.7) In this formula. . y2 = F1 ∨ F3 . . .9) In these expressions. m = 1. Information about output signals to be produced is placed into the column am [9].3) . D2 = F1 . . The structure table of Moore FSM is constructed using the automaton graph (or the marked GSA). we have R = 3. .1 we get the following equations: F1 = T1 T2 . .6a). . Tr1 = Tr (r = 1. y4 }. and it has H = 7 transitions. . a5 }. This step will be discussed a bit later.1 Structure table of Mealy FSM S1 am a1 a2 K(am ) 00 01 as a2 a3 a3 a1 a1 K(as ) 01 10 10 00 00 Xh 1 x1 x1 x2 ¯ x1 x2 ¯ ¯ 1 Yh y1 y2 y3 y2 y3 y1 D1 – 7 Φh D2 D1 D1 – – h 1 2 3 4 5 a3 10 Am = T1 lm1 · · · TR R .8) (1.. M). T = {T1 . D1 = F2 ∨ F3 . . . .4) are represented as the following SOPs: φr = ∨ Crh Fh yn = ∨ Cnh Fh h=1 h=1 H H (r = 1. Xh . Y = {y1 . T3 }. h. y1 = F1 ∨ F4 . N). K(a5 ) = 100. . In case of the Moore FSM S2 . . Φh . Let us encode its states in the following manner:K(a1) = 000. x2 }.

. . .8 1 Hardwired Interpretation of Control Algorithms a1 a2 a3 a5 a4 _ Fig.3) depends on terms (1. y 3 = A 3 ∨ A 4 .6) and its SOP is similar to system (1. .6 Marked GSA Γ1 (a) and automaton graph of Moore FSM S2 (b) Boolean systems (1.5) are represented in the form yn = ∨ Cnm Am m=1 M (n = 1. D1 = F5 ∨ F6 .10) where Cnm is a Boolean variable equal to 1 iff microoperations yn ∈ Y are executed. • system of output signals of Moore FSM has regular form. . (1. . . more states and transitions than the equivalent Mealy FSM. Comparison of automata S1 and S2 leads to the following conclusions satisfied for all equivalent Mealy and Moore automata: • Moore FSM has.8).5) are derived from the structure table. Functions (1. when FSM is in the state am ∈ A. ¯ ¯ ¯ ¯ ¯ ¯ For Moore FSM S2 . .2: F1 = T1 T2 T3 . 1. A1 = T1 T2 T3 . Automata S1 and S2 are equivalent in the sense that they interpret the same GSA Γ1 . A5 = T1 T2 T3 . F7 = ¯ ¯ ¯ ¯ ¯ ¯ ¯ T1 T2 T3 . y 4 = A 5 . . . let us point out that system (1. D3 = F1 ∨ F3 . . as a rule. . F1 = T1 T2 T3 x1 . . we get from Table 1. y 2 = A 2 ∨ A 4 . y1 = A 2 ∨ A 5 .3) and (1. D2 = F2 ∨ F3 . N). because it depends only on the states of FSM.

5) is regular. . The states am . . For example.2 Control Algorithm Interpretation with Finite State Machines Table 1. B4 }. where sign ”∗” T2T3 00 T1 0 a1 a5 01 a2 11 a3 10 a4 Fig. bt . Moreover. For example. 1. . B4 → K(B4 ) = 1 ∗ ∗. . the columns as − −Φh of structure table for the states a3 and a4 contain the same information. b j . the well-known algorithms NOVA. as ∈ A are called pseudoequivalent states of Moore FSM. 1. if there exist the arcs bi .2. where vertex bi ∈ B1 is marked by state am ∈ A and vertex b j ∈ B1 by state as ∈ A. ASYL or ESPRESSO [47] can be used for the state encoding mentioned above . system (1. They cannot be treated as equivalent states [9] because of different output signals generated for these states. . Thus.7. B2 = {a2 }. The number of terms in system Φ can be reduced due to optimal state encoding [14]. As follows from Table 1.7 Optimal state codes for Moore FSM S2 1 * * * . what means that it is specified for more than 50% of all possible input assignments. B3 = {a3 . This regularity makes possible implementation of this system using either read-only memory (ROM) chips or randomaccess memory (RAM) blocks [11]. with B1 = {a1 }. 1. a4 }. . bt ∈ E. the states a3 and a4 of the Moore FSM S2 are pseudoequivalent states.7).2 Structure table of Moore FSM S2 am a1 (–) a2 (y1 y2 ) a3 y3 ) a4 (y2 y3 ) a5 (y1 y4 ) K(am ) 000 001 as a2 a3 a4 a1 a5 a5 a1 K(as ) 001 010 011 000 100 100 000 Xh 1 x1 x1 x2 ¯ x1 x2 ¯ ¯ 1 1 1 9 Φh D3 D2 D2 D1 D1 - h 1 2 3 4 5 6 7 010 011 100 Let us point out that model of Moore FSM is used more often in practical design [48] because it offers more stable control than the control units based on the Mealy FSM model. Let ΠA = {B1 . the class B1 corresponds to the interval K(B1 ) = 000. when the codes of pseudoequivalent states from some class Bi ∈ ΠA belong to a single generalized interval of an R-dimensional Boolean space . . As follows from Fig. B2 → K(B2 ) = ∗01. BI } be a partition of set A into the classes of pseudoequivalent states .1. B3 → K(B3 ) = ∗1∗. in the case of Moore FSM S2 we have ΠA = {B1 . B4 = {a5 }. The number of product terms in the input memory functions system can be reduced due to existence of the pseudoequivalent states of Moore FSM [14]. The optimal state encoding for the Moore FSM S2 is shown in the Karnaugh map (Fig. .

.3 Control Algorithm Interpretation with Microprogram Control Units Microprogram control units are based on the operational . F6 = T1 . ¯2 T3 x1 x2 . . K(Bi ).address principle for presentation of control words (microinstructions) kept in a special control memory [1]. . R). r = 1.3 Transformed structure table of Moore FSM S2 Bi B1 B2 K(Bi ) 000 *01 as a2 a3 a4 a1 a5 a1 K(as ) 001 011 010 000 100 000 Xh 1 x1 x1 x2 ¯ x1 x2 ¯ ¯ 1 1 Φh D3 D2 D3 D2 – D1 – h 1 2 3 4 5 6 B3 B4 *1* 1** It was shown in [14] that optimal state encoding permits to compress the transformed structure table of Moore FSM up to corresponding size of the equivalent Mealy FSM structure table. As a rule. ¯ but now these terms include variables lmr ∈ {0.6). Tr∗ = 1(m = 1. M. which has only ¯ ¯ ¯ ¯ H0 terms. Let us construct a transformed structure table of Moore FSM with the following columns:Bi. • generation of microinstructions with given format. For example. . K(as ). The transformed structure table serves as the base to form product terms (1. F1 = T2 T3 x1 . h. ∗}. 1.8). The typical method of MCU design includes the following steps [1]: • transformation of initial graph-scheme of algorithm. in case of the Moore FSM S2 we have: F1 = T1 T2 T3 . the control unit can be implemented as a microprogram control unit (MCU).8). where Tr0 = Tr . F5 = T2 . . Tr1 = Tr . We find that terms F4 and F6 are ¯ ¯ ¯ F3 = T ¯ not the parts of SOP (1. Table 1. . models of FSM are used for implementation of fast operational units [1]. Thus. 1. . If system performance is not important for a project. Presence of "don’t care" input assignments makes possible to reduce the number of product terms in system (1. and the column K(am ) by the column K(Bi ). only one of them should find place in the final transformed table.3) contains H = 6 lines. F4 = T2 T3 x1 x2 . Φh . • microinstruction addressing.10 1 Hardwired Interpretation of Control Algorithms determines ”don’t care” value of state variable Tr ∈ T . . as . To do this we replace the column am by the column Bi . Xh . These intervals can be considered as the codes of classes Bi ∈ ΠA . the transformed structure table of Moore FSM S2 (Table 1. . If the structure table transformed in this way contains equal lines.

First line of expression 1. if [FX]t = 0.11) ⎩ [FA1 ]. or if xtl = 0. FA0 and FA1 . The field FA0 contains next microinstruction address At+1 (transition address).11).) using the following rules: ⎧ / ⎨ [FA0 ]t . • natural addressing of microinstructions.3 Control Algorithm Interpretation with Microprogram Control Units 11 • encoding of operational and address parts of microinstructions. As a rule. 1. contains information about microoperations yn ∈ Y (t = 0. . . Three particular addressing modes are used most often nowadays: • compulsory addressing of microinstructions . . if xtl = 0. . . . block of microoperation generation CMO.9) includes the following blocks [13]: • • • • • sequencer CFA. register of microinstruction address RAMI. 1. which is checked at time t(t = 0. • combined addressing of microinstructions.3). calculating transition address from (1.1. The field FX contains information about logical condition xtl ∈ X . The field FY . FX. [FA0 ]t and [FA1 ]t (t = 0. . . keeping address At . FA0 andFA1 form the address part of microinstruction. • synthesis of logic circuit of MCU using given logic elements. 1. either in case of unconditional transition (go to type). • construction of control memory content. The mode of microinstruction addressing affected tremendously the method of MCU synthesis [2. The fields FX. keeping microinstructions. whereas the second and third lines determine this address for the conditional jump. . control memory CM. The microinstruction format is shown in Fig. microinstruction formats include the following fields:FY . (1.11 determines the address of transition in case of unconditional jump. The field FA1 contains next microinstruction address for the case when xtl = 1. At+1 = [FA0 ].). 1.8 Format of microinstructions with compulsory addressing FY FX FA0 FA1 The address of next microinstruction At+1 is determined by contents of the fields [FX]t . . Structural diagram of MCU with compulsory microinstruction addressing (Fig. operational part of the microinstruction.8. 1. Consider an example of MCU design with compulsory microinstruction addressing S3 interpreting GSA Γ1 (Fig. 1. if xtl = 1. . fetch flip-flop TF used to organize the stop mode of the MCU. which are executed in cycle t of control unit operation.). Fig. 1. 5].. 3.

Let some address At be located in the register RAMI at time t (t = 0. the variable yE is assigned to the vertex bq . It causes termination of microinstruction fetching from memory CM. the transformation of GSA for MCU with compulsory addressing of microinstructions is necessary to organize the ending mode of the MCU. At the same time the flip-flop TF is set up. such that bq ∈ B2 . 1. whereas its field FY contains the set of microoperations Yq and field FA0 contains the microinstruction address. All possible vertices pair configurations are shown in Fig. bE . which means the end of MCU operation. This address is loaded into RAMI by synchronization pulse "Clock". and the arc bq . Corresponding microinstruction is then fetched from the memory CM.).11 There are four possible configurations: • bq . The analysis should be continued for the vertex . then special signal yE is generated to clear the flip-flop TF. 1. transformation of the GSA Γ1 is reduced to inserting the variable yE into the vertex b6 ∈ B1 and adding the vertex b7 . 1. . . 1. corresponding to vertex bt ∈ B1 . signal Fetch=1 initiates reading of a microinstruction from the control memory. bt ∈ B1 (Fig. bt ∈ E. The pulse "Start" is used to load the address of first microinstruction to be executed (start address) into RAMI.11a). If the end of microprogram is reached. The operational part of this microinstruction is next transformed by the block CMO into microoperations yn ∈ Y . . bE ∈ E. bE is replaced by arcs bq . Generation of microinstructions with compulsory addressing is reduced to successive analysis of pairs of vertices bq. 1. • if there is an arc bq . bE ∈ E.9 Structural diagram of MCU with compulsory addressing X 1 Hardwired Interpretation of Control Algorithms FA1 At CFA RAMI CM FA0 FX FY Start Clock S R TF CMO Fetch yE Y The control unit S3 operates as follows. which form a transition address At+1 sent into register RAMI. The transformation of initial GSA Γ is executed using the following rules [10]: • if there is an arc bq .10. such that bq ∈ B1 . Therefore. In this case the vertex bq ∈ B corresponds to microinstruction with empty fields FX and FA1 . Thus. The transformed GSA Γ1 (S3 ) thus obtained is shown in Fig. The sequencer CFA processes both the microinstruction address part and logical conditions X to produce the functions Φ . which are directed to a system data-path. an additional operator vertex bQ+1 (Q = |B| − 2) with the variable yE is inserted into GSA Γ .12 Fig. bQ+1 and bQ+1 .

Let A2 = 001. 1. bt ∈ B2 (Fig. • bq . Fig. A6 = 101. now the following microinstructions can be generated using the transformed GSA Γ1 (S2 ): O1 = b1 . second vertex is the final vertex of GSA (bt = bE ). . In this case. . If. M). the pair of vertices corresponds to one microinstruction with all fields containing useful information. FA0 and FA1 . it is clear that A1 = 000. and therefore the start address belongs to the microinstruction O1 . corresponding to the pair with vertex b1 ∈ B1 . 0 . bq ∈ E. . Let us denote microinstructions by symbols Om (m = 1. 0 . bt ∈ B1 (Fig. 1. b2 . • bq ∈ B1 . thus R = 3. • bq ∈ B2 . in such a pair. b1 ∈ E (Fig. 1.10).3 Control Algorithm Interpretation with Microprogram Control Units 13 bt ∈ B1 . M). In this case the analysis should be continued for the both vertices of the pair. / / / / / Addresses of microinstructions with compulsory addressing can be appointed in the following manner. . 1. and the analysis should be continued for the vertex b q ∈ B2 . O2 = b3 . .11d). . . then the vertex bq corresponds to microinstruction with empty fields FX. All other microinstructions are addressed in arbitrary manner. .. O3 = 0. 1. O6 = b7 . .11c). In this case the vertex bt ∈ B2 corresponds to microinstruction with empty field FY . 0 . b4 . Each microinstruction Om corresponds (one-to-one) to a binary code Am with R = log2 M bits (m = 1. O5 = b6 . O4 = b5 . A microinstruction with start address is determined by the arc b0 . The microprogram of MCU S3 (Γ1 ) includes M = 6 microinstructions. bt ∈ B2 (Fig. In the case under consideration there is the arc b0 .10 Transformed GSA Γ1 (S3 ) Start b0 y1y2 b1 b2 1 x1 0 b4 y3 b3 1 x2 0 y2y3 b5 yE b7 y1y4yE b6 End bE .11b). . 0 .1. .

K(x2 ) = 10.12) For MCU S3 (Γ1 ) this formula gives the value n1 = 5.4. whereas the codes of microinstructions are represented by variables a) b) c) bq d) bq 1 0 xI 0 bt yq bq yq bq 1 xI bt yt bt 1 xI 0 1 xI 0 yt bt Fig.14 1 Hardwired Interpretation of Control Algorithms Because the control memory can keep only some bit strings.13) in order to take into account the code for unconditional jump.11 Possible configurations for pairs of GSA vertices . / Let K(0) = 00. the encoding of operational and address parts of microinstructions is necessary to load microinstructions into the control memory. For MCU S3 (Γ1 ) this formula gives the value n2 = 2.13) The value 1 is added into (1. In case of one-hot encoding the length (bit capacity) n1 of the field FY is determined by the following formula: n1 = N + 1. Control memory of MCU S3 keeps M microinstructions with n3 = n1 + n2 + 2R (1. In this table. Addressing of microinstructions gives information. microinstruction addresses are represented by variables from the set A = {a1. Let us encode logical conditions xl ∈ X using binary codes with minimum length (called sometimes minimal-length codes) n2 = log2 (L + 1) . (1.14) bits. (1. a3 }. / Construction of the control memory content results in construction of a table with lines keeping microinstruction addresses and binary codes of particular microinstructions.There are many methods to encode operational part of microinstructions [11]. which should be written into the fields FA0 and FA1 . where S3 (Γ1 ) means that the GSA Γ1 is interpreted by MCU with compulsory addressing of microinstructions. when [FX] = 0. The control memory content for MCU S3 (Γ1 ) is shown in Table 1. In case of MCU S3 (Γ1 ) this formula gives the value n3 = 13. 1. K(x1 ) = 01. Let us choose the one-hot encoding of microoperations to design the control memory of MCU S3 (Γ1 ). a2 .

.11) can be represented as At+1 = z1 [FA0 ] ∨ z1 [FA1 ]. . where bt ∈ B1 . which are direct analogues of the formulae of transitions for operators of GSA [9].15) The variable z1 = 1. (1. The last column of the table contains formula of transitions for microinstructions. . otherwise (if z1 = 0) RAMI is loaded from the field FA0 of current microinstruction.15) is represented as a1 = z1 v8 ∨ z1 v11 . / It results in the inefficient use of control memory volume. . Analysis of this table shows the main drawbacks of MCU with compulsory addressing of microinstructions.3 Control Algorithm Interpretation with Microprogram Control Units Table 1. 0 .17) . expression (1. . it means that z1 = ∨ Vl xl . . Let us point out that some logic elements should be used to implement the block CMO [1]. v13 }. but a positive feature of compulsory addressing is the minimum number of microinstructions for the particular GSA. corresponding to the pairs 0. ¯ ¯ a2 = z1 v9 ∨ z1 v12 . such as: • an empty field FY for microinstructions. where |A| = R. such as PROM or RAM chips [1]. ¯ (1. Synthesis of the logic circuit of MCU S3 is reduced to the implementation of block CFA using standard multiplexers and control memory using standard memory blocks. Assume that content of the field FA1 is loaded into register RAMI if z1 = 1. where / bt ∈ B2 . bt . |V | = n3 . In case of the MCU S3 (Γ1 ) expression (1. L). .16) where Vl is a conjunction of variables vr ∈ V . • empty fields FX and FA1 for microinstructions. in comparison with MCU with other modes of microinstruction addressing [1]. . l=1 L (1.1.4 Control memory content for MCU S3 (Γ1 ) Address a1 a2 a3 000 001 010 011 100 101 FY v1 v2 v3 v4 v5 11000 00100 00000 01100 10011 00001 FX v6 v7 01 00 10 00 00 00 FA0 v8 v9 v10 010 100 101 100 000 000 FA1 v11 v12 v13 001 000 011 000 000 000 Formula of transition O1 → x1 O3 ∨ x3 O2 ¯ O2 → O 5 O3 → x2 O6 ∨ x2 O4 ¯ O4 → O 5 O5 → End O6 → End 15 from the set V = {v1 . corresponding to the pairs bt . Thus. corresponding to the code K(xl ) (l = 1. if a logical condition to be checked is equal to 1.

12 Logic circuit of CFA of MCU S3 (Γ1 ) D1 "0" x1 x2 v6 v7 0 1 2 3 1 2 MX z1 v8 v11 0 MX1 1 1 . 0 MX3 1 1 v10 v13 D3 There are two microinstruction formats in case of natural microinstruction addressing [1. variables ar from (1. when a logical condition to be checked is equal to 1. . Symbol "0" represents the fact that logic 1 should be connected with informational input of the multiplexer corresponding to code 00. used to recognize the type of microinstruction. R). 12]: operational microinstructions corresponding to operator vertices of GSA Γ and control microinstructions corresponding to conditional vertices of GSA Γ (Fig. . . Expressions (1.19) . Fig.16 1 Hardwired Interpretation of Control Algorithms a3 = z1 v10 ∨ z1 v13 .18) This formula specifies standard multiplexer with two control inputs and three data inputs in use. 1. The first term of expression (1.13 Microinstruction formats for MCU with natural addressing of microinstructions 0 1 FX FY F A0 First bit of each format represents field FA.18) determine the logic circuit of sequencer CFA of the MCU S3 (Γ1 ). 1. Fig. ¯ and expression (1. In both cases mentioned above current address At is used to calculate next address: At+1 = At + 1. The same is true for the case.17) coincide with variables Dr (r = 1. . Operation of this circuit can be easily deduced from Fig.13). 1. ¯ ¯ ¯ ¯ (1. .13. .16) has now the form z1 = v1 v2 0 ∨ v1 v2 x1 ∨ v1 v2 x2 . (1.17) – (1. 1. Let FA = 0 correspond to operational microinstruction and FA = 1 to control microinstruction. next address is not included into operational microinstructions.12.18) corresponds to unconditional jump. 1. shown in Fig. 1.12. As follows from Fig.

Nature of addressing conflicts is the consequence of implicit transition addresses. . Let us point out that in case of MCU S4 operational microinstructions correspond to operator vertices bq ∈ B1 and control microinstructions correspond to conditional vertices bq ∈ B2 .19). The pulse "Start" initiates loading of start address into CAMI. Fig. t+1 A = ⎪ [FA0]t . bq ∈ E. and the sequencer produces either signal z0 (corresponding to an address loaded from the field FA0 ). . 1. ⎪ ⎩ [FA0]t .20) Analysis of (1.14 Structural diagram of MCU with natural addressing of microinstructions FA0 FA FX X +1 Start Clock S R TF CMO Fetch FY yE CFA z0 z1 At CAM I CM FA Y This MCU operates in the following manner. If variable yE is generated by CMO. then the flip-flop TF is cleared and operation of MCU terminated. At the same time flip-flop TF is set up. . Let indexes of vertices. 1. 1. if (xtl ) ∧ ([FA]t = 1). .15a). microoperations are not generated. b j ∈ B1 (Fig. if ([FX]t = 0) ∧ ([FA]t = 1).12] are eliminated during the second step. if [FA]t = 0. the block CMO generates microoperations yn ∈ Y .14. First step involves the same transformations as in case of MCU S3 . Let some GSA include two arcs bi . Addressing conflicts between microinstructions [1. Corresponding structure is shown in Fig. According to (1. The transformation of initial GSA is executed in two consecutive steps.20) shows that MCU with natural addressing of microinstructions should include a counter CAMI. Now we use an example of MCU S4 (Γ1 ) to discuss some particular problems of such a design. If this address determines an operational microinstruction. bq .1. corresponding microinstructions and microinstruction addresses be the same and take Ai = 100. Let symbol S4 stand for this kind of MCU. b j . where bi . 1. The content of counter CAMI can be changed by pulse "Clock".3 Control Algorithm Interpretation with Microprogram Control Units 17 Hence the following rule is used for next address calculation: ⎧ t ⎪ A + 1. Let an address At be located in CAMI at time t (t = 0. or signal z1 (it corresponds to adding 1 to the content of CAMI). as expressed by (1. ). and the sequencer CFA produces signal z1 . If this address determines a control microinstruction.19) we find that . ⎪ t ⎨ A + 1. / (1. if (xtl = 0) ∧ ([FA]t = 1).

17). to eliminate addressing conflict between microinstructions corresponding to vertices b3 and b5 . 1. We call this situation addressing conflict. . Addressing conflict is possible also between control microinstructions (Fig. if Ai = 100.18 1 Hardwired Interpretation of Control Algorithms Aq = 101. and the field FA0 of microinstruction Ot contains address Aq = 101.16a). 1. 1. The transformed GSA Γ1 (S4 ) contains M = 8 vertices (Fig. variable yE is inserted into vertex b6 .16b).16 Elimination of addressing conflicts Now.15b). when FX = 0 (Fig. 1. can have arbitrary number of vertices.15. 1. and vertex b8 is also added. microinstructions Oi and O j should have the same address. vertex b7 with yE is added. which means that the address A j should be equal to 100. we have Aq = 101. As the result of transformation. 1. and its elimination requires inserting of some additional vertex (Fig.15 Addressing conflicts in MCU S4 a) yi bi yj bt x0 1 bq 1 xI 0 0 bj b) bi 1 xi 0 xj 1 bj 0 bt x0 1 0 yq bq Fig. / a) yi bi yj bj 1 xi 0 bq 1 xI 0 yq bq b) bi xj 1 bj 0 Fig. This condition corresponds to the unconditional jump. Let us point out that GSA subgraphs. Some conditional vertex bt with logical condition x0 should be inserted in the initial GSA to eliminate this conflict. Addressing conflicts can arise also among operational microinstructions and control microinstructions [11]. 1. Thus. similar to ones shown in Fig.

O5 . α3 = O7 . elements of which are inputs of the sequences. Let us take the case of MCU S4 (Γ1 ). Vertex bq ∈ B1 ∪ B2 is the input of a sequence. O2 . when R = 3. O8 . These sequences are created as follows. Generation of special microinstruction sequences is needed in case of natural addressing of microinstructions. In case of the MCU S4 (Γ1 ). Encoding of operational and address parts of microinstructions is executed in the same manner as in case of MCU S3 . the set I(Γ ) = {b1. or conditional vertex with x0 . and so on. where b0 . Let αg denote a microinstruction sequence. For example.5. bt ∈ E. The address of current sequence input is calculated by adding 1 to the address of last microinstruction from previous sequence. α2 = O4 . Application of this procedure to the case of MCU S4 (Γ1 ). Addresses of next microinstructions belonging to this sequence are calculated according to (1. 1. and . End points of these sequences are microinstructions corresponding to vertices connected with final vertex bE . results in the microinstruction addresses shown in Table 1. b4 .1. each operator vertex corresponds to an operational microinstruction and each conditional vertex corresponds to a control microinstruction. namely α1 = O1 . Let us build a set I(Γ ). There are three such sequences in case of MCU S4 (Γ1 ). O6 . It means that microinstructions are generated in a very simple way. the microprogram of MCU S4 (Γ1 ) includes M = 8 microinstructions. O3 . marked as "0".17 Transformed GSA Γ1 (S4 ) 19 Start b0 y1y2 b1 b2 1 x1 0 b4 1 x2 0 y3 b3 b8 1 x0 0 y2y3 b5 yE b7 y1y4yE b6 End bE As it was mentioned above.19). if the input of this vertex is connected either with the output of vertex b0 or with the output of conditional vertex. b7 } and microinstruction sequences are started by corresponding microinstructions. The zero address is assigned to the microinstruction corresponding to vertex bt .3 Control Algorithm Interpretation with Microprogram Control Units Fig.

The control memory of MCU S4 contains M microinstructions with n4 = max(n1 + 1.16): z1 = ( ∨ Vl xl ) ∨ v1 . The corresponding Boolean expressions for C1 andC2 have the form: . the logical expression for calculation of z1 can be obtained by the following transformation of expression (1.6 Microinstruction addresses of MCU S4 (Γ1 ) Address a1 a2 a3 000 001 010 011 100 101 110 111 FA v1 0 1 0 1 1 0 0 0 FX FA0 FY v2 v3 v4 v5 v6 11000 01100 00100 00110 10111 01100 10011 00001 Formula of transitions O 1 → O2 O2 → x1 O4 ∨ x1 O3 ¯ O 3 → O8 O8 → x0 O6 ∨ x0 O6 ¯ O4 → x2 O7 ∨ x2 O5 ¯ O 5 → O6 O6 → End O7 → End Let us discuss now the design of sequencer CFA for MCU S4 .22) ¯ where v1 = 0 corresponds to FA=0. Table 1. n2 + R + 1) (1. Let the counter CAMI have input C1 . It is clear that z0 = z1 . as well as minimal-length codes for logical conditions (n2 = 2). Let corresponding codes for both MCU S3 (Γ1 ) and S4 (Γ1 ) be the same. for example.21) bits. used to increment the counter content and input C2 to load the input parallel code into the counter under the influence of pulse "Clock".20 1 Hardwired Interpretation of Control Algorithms Table 1.6. for MCU S4 (Γ1 ) it can be found that n4 = 6. ¯ l=1 L (1. Thus. The variable z1 = 1 should be generated either if xtl = 1 or when an operational microinstruction is executed at time t. Construction of the control memory content is executed due to the fact that the usage of microinstruction bits depends on microinstruction type.5 Microinstruction addresses of MCU S4 (Γ1 ) Om O1 O2 Am 000 001 Om O3 O8 Am 010 011 Om O4 O5 Am 100 101 Om O6 O7 Am 110 111 use one-hot codes for microoperations (n1 = 5). The control memory content of MCU S4 (Γ1 ) is shown in Table 1.

52. 17n4.19. ⎩ [FA1 ]t . ¯ (1.12.13. if |FX|t = 0. 55. It corresponds to a control microinstruction. 43.24. can be found in [1.27. but they have one serious disadvantage. Thus. that addressing conflicts are possible only between microinstructions with [FX] = 0. t+1 A = [FA0 ]t . 1. As a rule.23) serve to design the logic circuit of sequencer CFA for MCU S4 (Γ1 ) shown in Fig.18. 60. The comparative analysis of Tables 1. 1.24) It follows from (1.18 Implementation of the block CFA for MCU S4 (Γ1 ) "0" x1 x2 v2 v3 v1 0 MX 1 2 3 1 2 CS z1 1 Clock _ v1 1 z0 & C2 & C1 In this circuit multiplexer MX is active if v1 = 1 is applied to the "enable" input CS of the chip. than the equivalent MCU S3 . than in case of the equivalent MCU S3 . which can be used for MCU with com/ bined microinstruction addressing.24). 11].19 Microinstruction format with combined addressing FY FX F A0 In this case. A positive feature of MCU S4 is smaller microinstruction length. The methods of control memory implementation will be discussed later.4 and 1. 41. 64].23) Expressions (1. Fig. In case of MCU S4 .16. of bit capacity and of control algorithm execution time. transition address is described by the expression: ⎧ / ⎨ [FA0 ]. if xtl = 0.6 shows that MCU S4 is characterized by longer microprogram.22) and (1. 58. only single logical condition is checked during one cycle of MCU operation. C2 = z1 ·Clock. Microprogram control units were very popular in the past [1. 38. In case of our example we find that n3 = 2. multidirectional transitions depending on k > 1 logical conditions need k > 1 cycles .19) represent a compromise settlement with average number of microinstructions. (1.3 Control Algorithm Interpretation with Microprogram Control Units 21 C1 = z1 ·Clock. 1. 1. A design method.1. Remaining elements of this circuit follow directly from expressions (1. control algorithm execution requires more time. namely inferior performance in comparison with the equivalent finite state machines. Microprogram control units with combined microinstruction addressing (Fig. if xtl = 1.23). Fig.

An operator vertex bq ∈ Dg is called an input of OLC αg . such that bt ∈ Dg . when its resources are not in use. if the number of its operator vertices exceeds 75% of the total number of vertices.1. Microinstruction format includes the operational part only. where i is the component number of vector αg . . These units have several particularities. which can be viewed as a composition of the finite state machine and microprogram control unit [15]. An operational linear chain (OLC) of GSA Γ is a finite vector of operator vertices αg = bg1 . 49] is used to keep state codes. which include operator vertices only.4 Organization of Compositional Microprogram Control Units The properties of the interpreted control algorithm have great influence on the hardware amount of corresponding control unit [11]. Multidirectional transitions are executed in one cycle of CMCU operation. Let us introduce some definitions helping to understand the features of CMCU. .22 1 Hardwired Interpretation of Control Algorithms for its execution. which are components of OLC αg . any change in the control algorithm leads to the redesign of corresponding FSM. Definition 1. As a rule. and the controlled data-path will have k − 1 idle cycles. It permits to minimize the control word bit capacity. 1. Let Dg be a set of operator vertices. One of the approaches for linear GSA interpretation is the use of compositional microprogram control units (CMCU). Existence of operational linear chains allows simplification of input memory functions and reduction of hardware amount in the logic circuit of control unit. One of such properties is the existence of operational linear chains corresponding to the paths of GSA. because MCU are Moore FSM [1]. bgFg . Let us call a GSA Γ the linear GSA (LGSA). Thus control words kept in control memory have minimum possible length in comparison with all organizations of MCU mentioned above. the sequencer CFA is very simple and can be implemented using standard multiplexers. It provides minimum time of control algorithm interpretation. 2. . / . distinguishing them from other control units: 1. . Positive feature of MCU is the use of regular control memory to implement the microinstruction system. bq ∈ E. bgi+1 ∈ E corresponds to each pair of adjacent vertices bgi . Microprograms have minimum possible length (the number of microinstructions). as compared with the equivalent FSM. such control units have similar performance. if there is an arc bt . such that an arc bgi . In this case either shift register [50] or up counter [4. Thus. Definition 1. 3. because the CMCU control memory is free from control microinstructions. bgi+1 . but only small modifications of the control memory content in the equivalent MCU are needed. Besides.2.

αG }. . / It follows from the basic properties of GSA [9] that each OLC αg corresponding to definitions given above should have at least one input and exactly one output.4. A set of inputs I(Γ ) of the operational linear chains of GSA Γ : I(Γ ) = G g=1 (1. . 1.20 Structural diagram of compositional microprogram control unit with basic structure . A set of OLC C = {α1 . . .28) symbol A(bgi ) stands for the address of microinstruction corresponding to component i of vector αg ∈ C. . . Let us denote it as unit U1 . Definition 1. (1.27) Let the natural microinstruction addressing be executed for microinstructions corresponding to the adjacent components of each OLC αg ∈ C: A(bgi+1 ) = A(bgi ) + 1 (i = 1. . An input bq ∈ Dg is called a main input of OLC αg . (1. |Di ∩ D j | = 0 (i = j. For GSA Γ we have the following sets: 1. ∪ D G = B 1 . if GSA Γ does not include an arc bt . where i = 1. . . 1. . +1 X CC Start Clock CT CM yE R Start RG S TF Fetch y0 Y Fig.26) 3. In this case GSA Γ can be interpreted by compositional microprogram control unit with basic structure of Fig. if there is an arc bq .4 Organization of Compositional Microprogram Control Units 23 Definition 1.1. bt ∈ E. Let inputs of OLC αg form a set I(αg ). . . OG }. i. A set of outputs O(Γ ) of the operational linear chains of GSA Γ : O(Γ ) = {O1 .28) In expression (1. (1. . . Fg − 1). Fg − 1. . G}).25) I(αg ). . . G → min . satisfying the following condition D1 ∪ .20 [15]. . j ∈ {1. . .3. An operator vertex bq ∈ Dg is called an output of OLC αg . . bq ∈ E such that bt ∈ B1 . where bt ∈ Dg . 2. Let Igj stand for input j of OLC αg and Og for its output. .

It corresponds to a transition between adjacent components of OLC αg ∈ C. (1.31) where M1 = |A1 |. The unit U1 operates in the following manner. The pulse ”Start” initializes following actions: the zero code of FSM S1 initial state is loaded into register RG. the content of register RG is unchangeable and 1 is added to the content of counter CT. used to organize transitions between microinstructions corresponding to adjacent components of OLC αg ∈ C. As follows from (1.24 1 Hardwired Interpretation of Control Algorithms In the unit U1 .) the code of state am ∈ A1 . the flip-flop TF is cleared. Content of both CT and RG is changed by the pulse ”Clock”. In this case circuit CC generates Boolean functions: Φ = Φ (τ . The minimum number of these variables is determined as R1 = log2 M1 . This set includes R2 = log2 M2 (1. be loaded into the register RG and address A(Igj ) of the input j of OLC αg ∈ C be loaded into the counter CT. Current microinstruction is read out of CM and its microoperations yn ∈ Y initialize some actions of the datapath. because changes in the interpreted . Outputs of the CT. .30) where τ = {τ1 . where A1 is a set of FSM S1 states. If Fetch=1. . . If there is a transition from output Og to some input under influence of some values of logical conditions. At the same time MCU S2 implements addressing rule (1.29) (1. control memory CM should only keep microoperations yn ∈ Y and additional variables y0 . where M2 = |B2 |. If y0 = 1. additional variable y0 = 1 is generated by MCU S2 . . If yE = 1.29) determine the address of this j input Ii ∈ I(Γ ) which is to be loaded into the counter. Ψ = Ψ (τ . TR2 } determine next microinstruction address. . start address of microprogram is loaded into counter CT. some additional variable yE = 1 is generated. . X). yE . Therefore. If this input is not the output of current OLC αg ∈ C (Igj = Og ). microinstructions can be fetched out of the control memory. .29). Functions (1. FSM S1 of unit U1 implements any multidirectional microprogram transition between output Og ∈ O(Γ ) and input Iij ∈ I(Γ ) in one cycle of CMCU operation. bE ∈ E. T = {T1 . 1. then y0 = 0. .30) calculate the code of next state as ∈ A1 to be loaded into RG.28).32) variables. In other words. If the output Og is reached. . X). Counter CT. combinational circuit CC and register RG form a finite state machine S1 . Let at time t (t = 0. . Thus Fetch=0 and microinstruction fetching from the control memory is terminated. If CT contains the address of microinstruction corresponding to vertex bq ∈ B1 such that bq . τR1 } is a set of state variables encoding states am ∈ A1 . functions (1. (1. . an address part is absent in the microinstruction format in case of CMCU U1 . flip-flop TF is set up (Fetch=1). which will be called microinstruction addressing unit or FSM S1 . control memory CM and flip-flop TF form microprogram control unit S2 with natural microinstruction addressing. The main disadvantage of CMCU U1 is the loss of universality. 2.

Baitinger. Devidas. TUT Press. Adamski. C. Das. T.. Tallinn (2008) 9. Barkalov. K(αg ) is a code of OLC. Symp. including the vertex bt . we should analyze main features of ASIC and PLD. L. S. R. Bacchetta. The counter CT is used to represent both address of microinstruction and code of OLC. Kluwer Academic Publishers. University of Zielona Góra Press. F. as a component of OLC. S.: Microprogram optimization: A survey. L. A. U.: Architectural and Sequential Synthesis of Digital Devices. Asahar. It results in CMCU with common memory [11]. It leads to CMCU with code sharing [11].: Logic Synthesis for Compositional Microprogram Control Units. Newton. the methods of synthesis are discussed. P. S. UNITECH.. Berlin (2008) 12. References 1. 962–973 (1976) 3. There are two main methods used to decrease the number of outputs of the block CC of CMCU U1 [11]: 1. K(bt ) is a code of the vertex bt ∈ B1 . Addison-Wesley.: Low-power state assignment techniques for finite state machines. pp. K. Barkalov. A. Because of it.: Logic and System Design of Digital Systems. vol.: Foundations of Microprogramming.: Synthesis of Operational and Control Automata. 153–170 (1989) 5. Starodubov. Donetsk (2009) . control automata and FSM as synonyms. Titarenko. 2. A.: Optimization of mealy automaton logic using programmable logic arrays. 2. In our book. Silvano. 789–793 (1991) 11. A.: Optimal state chains and states codes in finite state machines.. Titarenko. Microinstruction address can be represented as concatenation: A(bt ) = K(αg ) ∗ K(bt ). Zielona Góra (2006) 2. Rauscher. Workingham (1986) 6.: The Architecture of Microprocessors.. In our book we use the terms control unit.I. Salomatin. current achievements in semiconductor technology permit to eliminate this drawback. which target on applicationspecific integrated circuits (ASIC) and standard programmable logic devices (PLD). Baranov. Dordrecht (1994) 10..: Sequential Logic Synthesis. L.. A. Academic Press. Anceau. Daldos. Cybernetics and system analysis 27(5).. as it will be shown below. (1. 641–644 (2000) 8. Springer. Sciuto. Agerwala. Baranov. Fortunately. Barkalov. New York (1976) 4.. Amann.References 25 microprogram lead to the redesign of circuit CC. D. Barkalov. on Circuits and Systems (ISCAS 2000). of the IEEE Inter. Kluwer Academic Publishers. IEEE Transactions of Computers (10).. In: Proc.: Logic Synthesis of Control Automata. P. A.. IEEE Transactions on Computer-Aided Design 8(2). Boston (1992) 7.33) where A(bt ) is an address of microinstruction corresponding to the vertex bt ∈ B1 .. K. Agrawala. T.. V. M. These methods depend strongly on logic elements in use..

Debnath. S. S. Du. Sasao. 463–473 (1997) 20. ACM Computing Survey (24). In: Proc. Newton. S. A. Chattopadhyay. Automatics and computer technique (4). Los Alamitos (1998) 22..: The Principles of Computer Hardware.W.. B. S. 1290–1300 (1988) 32.. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10(1). Ciesielski. and four-level boolean minimization. 28–38 (1991) . Newton. Englewood Cliffs (1972) 23..: Easily testable PLA-based finite state machines. Ma. IEEE Transactions on Computer-Aided Design 7(12). Kluwer Academic Publishers. In: Proceedings of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems (DDECS 1998). K.26 1 Hardwired Interpretation of Control Algorithms 13. Dasgupta. Kania. 127–134 (2005) 27.: Design of Control Units With Programmable Logic.: Principles of optimization of logic circuit of Moore FSM. R. IEEE Transactions on Computer-Aided Design 6. In: Proc. R.level logic optimization system. Wang. Webb.: Logic Minimization Algorithms for VLSI Synthesis. of Programmable Devices and Systems. A. Lin. Barkalov. Czerwinski. Brayton. G. IEEE Computer Society. New York (2000) 25. IEEE Transactions on Computer-Aided Design 11(8) (1992) 24.: Genetic algorithm based approach for integrated state assignment and flipflop selection in finite state machines synthesis. 604–611 (1990) 31. Chu.: Doutput phase optimization for and-or-exor plas with decoders and its application to design of adders. M. Barkalov. S. Kania.: Computer Organization and Microprogramming. Y. R. Czerwinski. D. 101–176 (1979) 28. IBM Journal of research and Development 41(4/5). of the IEEE Inter. 443–450 (2005) 21. pp. R. In: Proc.: MUSE: a multilevel symbolic encoding algorithm for state assignment. P. W˛ grzyn...: MIS: a multi.. 216–221 (2004) 26. X. Devadas.: Exact algorithms for output encoding. on Digital System Design. D.A. 1062–1081 (1987) 19. Barkalov. H. D. A. Prentice Hall. T. 1492–1500 (2005) 29. Devadas. The Computer Journal 48(4). M. A. Newton. Sangiovanni-Vincentelli. H. Cybernetics and System Analysis (1).. of 8th Euromicro Sym. S.: Implementation of microprogrammed control in FPGAs.. Hachtel. Inc.: The organization of microprogram stores. Univere sity of Zielona Góra Press (2006) 14. Oxford University Press.: Microprogram control unit as composition of automate with programmable and hardwired logic. pp.: State assignment method for high speed FSM. Chaudhuri.A.: Area conscious state assignment with flip-flop and output polarity selection for finite state machines synthesis – a genetic algorithm... A. 415–422 (2002) 17. B. Bomar.... pp. S.. Boston (1984) 18. 47–53 (1998) 30..: MUSTANG: State assignment of finite state machines targeting multilevel logic implementation. J. C.: PLADE: A two-stage PLA decomposition. Chattopadhyay. 522–527. G. state assignment. IFICE Transactions on Information and Systems E88-D (7). on VLSI Design... Liptay.: An efficient algorithm of perfect state encoding for CPLD based systems. Sangiovanni-Vincentelli. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 9(6).. Conf. Clements. IEEE Transactions on Computer-Aided Design 10(1). S. Sapiecha. A. Sangiovanni-Vincentelli. Rudell.. Ma. pp. A. 65–72 (1998) (in Russian) 15. C. 143–154 (1991) 33. A.. 36–41 (1983) (in Russian) 16. IEEE Transactions on Industrial Electronics 49(2).. Jang. R.C. A. A. McMullen. Devadas. Deniziak. Brayton. A.: State assignment for PAL-based CPLDs.: A high-frequency custom cmos s/390 microprocessor.. Hatchel.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and System 12(8).References 27 34. H. New York (2005) 45.: Principles of Digital Design. New York (1994) 48. Gambhir. E. pp. Narayanan. H. Morgan Kaufmann. R. Conf. B..: Computer Organization and Design: The Hardware/Software Interface. Inc. D. Gupta.. Somenzi.and multilevel logic implementations. P. of the Asia and South Pacific– DAC. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17(12).: ALTO: An iterative area/performance algorithms for LUTbased FPGA technology mapping. Automation and Test in Europe Conf.: Synthesis and Optimization of Digital Circuits. pp. 1281–1291 (1998) 54. In: Software Frameworks and Embedded Control Systems. S. 1123–1131 (1993) 55. 727–731 (1971) 44.: Symbolic design of combinational and sequential logic implemented by two–level macros. 392–400 (2000) 41. In: Proc. Iranli. Yang.. 597–616 (1986) 47.: FSM-based digital design using Verilog HDL.. Despain..: Microprogramming: An introduction and a viewpoint.: Exact and heuristic algorithms for the minimization of incompletely specified state machines.: A microsequencer architecture with firmware support for modular microprogramming. Electronic Letters 36(18).. on ASIC. of 5th Inter. 2. Pugh. R. and Exhibition (DATE 2002). vol. Escherman. John Wiley and Sons.: A heuristic state assignment algorithm targeting area. Jou. Jacoby.. S. De Micheli. Desai. Maxfield.. D. 248–254 (2002) 37.. New York (1997) 36. Chichester (2008) 49. J.. Gajski. In: Proc. Habib.: Microprogramming: Principles and Practices. G. McGraw-Hill. 3–15 (1981) 50.: STOIC: state assignment based on output/input functions. C. Minns. Hatchel. Patterson. Husson. Goren. F. C. IEEE Transactions on VLSI Systems 18(4). Papachristou. C. ACM Computing Surveys 25(4).: Finie State Machine Implementation in FPGAs.: Microprogramming and Firmware Engineering Methods. Orlando (2004) 46. Park. Prentice Hall.F. J. Rezvani.J. IEEE Transactions on Computer-Aided Design 5(9).: A state assignment scheme targeting performance and area. S. Prentice Hall. Springer. Elliot... R. G.. L. M. Rho. vol. Conf. Papachristou. B.: Low power synthesis of finite state machines with mixed D and T flip-flops. S.. Kubatova. I.. A. H. Cho. of 12th Inter. 1. C. Bian. IEEE transactions on Computers C–20(7).: State assignment for hardwired vlsi control units. pp. Flynn..: Hardware microcontrol schemes using PLAs. H. W. pp. In: Proc.. IEEE Transactions on ComputerAided Design 13(2). Rosin. J. Ferguson.... Xue.: Optimal state assignment technique for partial scan designs. Academic Press. pp. J. Henessy.: IBM’s 360 and Early 370 Systems. 415–436 (1993) 35. S. 378–383 (1999) 38. M. Shen. 167–177 (1994) . MIT Press. J.: CHESMIN: a heuristic for state reduction of incompletely specified finite state machines. New York (1988) 39. P. S... S. 177–187.: The Design Warrior’s Guide to FPGAs. In: Proceeding of 14th Microprogramming Workshop. Englewood Cliffs (1970) 42.. F. De Micheli. 1527–1529 (2000) 52. Hu. 803–808 (2003) 43. pp. Pomerancz. Cheng. Johnson. on VLSI Design. M. 93–96 (2003) 40. of the Design. In: Proc. J. Pedram. ACM SIGMICRO Newsletters 13(4) (1982) 51. Pedram. Palmer. Cambridge (1991) 56. John Wiley and Sons. A. San Moteo (1998) 53. Huang. K.: Low-power state assignment targeting two. I.

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the methods of logical condition replacement and encoding of collections of microoperations are considered. 29–52. this conception can be explained as the following one.1). two-level circuits of the FSM type are often realized in a form of custom matrices [2. This system can be implemented as a two-level matrix circuit (Fig. 2. connected with logic synthesis and optimization of FSM implemented with custom matrix integrated circuits. and a matrix M2 . which includes H AND gates (AND-plane). The primitive matrix implementation of FSM circuit is analyzed first.1) is characterized by the following parameters: the number of inputs L = 3. The chapter discusses some problems. It is reduced to direct interpretation of FSM structure table and is characterized by considerable redundancy. which includes N OR gates (ORplane). 2. Titarenko: Logic Synthesis for FSM-Based Control Units. These methods allow decrease for circuit redundancy due increase of the number of FSM model levels. The last part of the chapter is devoted to optimization of the block generating microoperations. 2.Chapter 2 Matrix Realization of Control Units Abstract. The logic circuit shown in Fig. 3].1 Primitive Matrix Realization of FSM In case of ASIC. Optimization methods are introduced based on different approaches for state encoding.com .1) System (2. the number of functions N = 2. Next. c Springer-Verlag Berlin Heidelberg 2009 springerlink. the number of product terms (conjunctions of arguments) H = 4.1 can be viewed as a matrix M1 . The conception of distributed logic [10] is used in custom matrices. Each such class corresponds to one state of the equivalent Mealy FSM. it is shown that the model of Moore FSM offers an additional possibility for its circuit optimization due to existence of the classes of pseudoequivalent states. ¯ c ∨ abc = F2 ∨ F4 y2 = a b ¯ ¯ (2. Barkalov and L. as well as on transformation of state codes into class codes. Next. Consider implementation of the following system of Boolean functions: ¯¯ ¯ ¯ y1 = abc ∨ abc ∨ abc = F1 ∨ F2 ∨ F3 . LNEE 53. Each element of the matrix M1 has up to L inputs (the number of inputs A. pp.

and OR-planes (matrices M1 and M2 ). Let us consider the matrix implementation of Mealy FSM represented by systems (1.30 Fig. then it should require up to 64 000 gates in the ANDplane. For the sake of simplification.1) 2 Matrix Realization of Control Units a b c & & 1 & y1 & y2 1 can be less than L. A matrix M2 has H inputs and implements N + R functions. which are members of functions Y and Φ . depended on terms (1.2 are used for interconnections of rows and columns of AND. The distributed NOR gate implementing the minterm F1 is shown by the circuit in Fig.3). 2.2 Distributed implementation of terms and functions b) F1 F2 F1 F3 F4 y1 a) a a b b c c CMOS transistors shown in Fig.1 Matrix implementation of system (2. 2. Fig. We should add that technological aspects of logic circuits implementation are out the scope of this book. The complexity of matrix . 2. each input could be connected with each gate of the matrix M1 (up to 64000 connections).9). To eliminate these drawbacks. . A matrix M1 has 2(L + R) inputs and implements H conjunctive terms Fh ∈ F = {F1 . then both matrices M1 and M2 are implemented using NAND or NOR gates [10]. 2. FH }. Practical hardware implementation of such a circuit is very difficult because of problems with routing wires and building of multi input gates.6). whereas each gate of OR-plane should have up to 64K inputs. if a circuit has L = 16 inputs. which are derived from FSM structure table (Fig. the gates are distributed along the rows and columns of the matrices [10]. . Because realization of AND and OR gates in modern technologies generally uses more transistors (and hence more delays and chip area). 2. if an implemented Boolean system can be minimized).2b depicts the distributed implementation of the function y1 from system (2. . Moreover. Each element of the matrix M2 has up to H inputs.8) – (1. Such an implementation is very space and time consuming because of large gates and long lines of connections among them. whereas Fig.2a. . 2. For example.1). let symbol AND stand for M1 and OR for M2 . Let us point out that all ASIC are implemented using CMOS transistors [11].

2.1 Primitive Matrix Realization of FSM Fig. 2.3 Primitive matrix realization of Mealy FSM
X & M1 1 M2 Y Start Clock RG

31

F

T

realization can be estimated as a total area of matrices M1 and M2 [3]. Let S(M1 ), S(M2 ) and S(MT ) denote respectively the areas of matrices M1 , M2 and total area of the circuit shown in Fig. 2.3. These areas can be determined in the following way: S(M1 ) = 2(L + R)H; S(M2 ) = H(R + N); S(MT )1 = (3R + 2L + N)H. (2.2) (2.3) (2.4)

Assessments (2.2) – (2.4) are rather theoretical, because they do not include technological coefficients to give real sizes of transistors, wires and spaces among these components of the circuit. Let us analyze the parameters of matrix implementation for the Mealy FSM S5 , represented by its structure table (Table 2.1). ¯ ¯ In this case there is the set of terms F = {F1 , . . . , F8 }, where F1 = T1 T2 , F2 = ¯1 T2 x1 , . . . , F8 = T1 T2 x4 . For the Mealy FSM S5 , functions yn ∈ Y and φr ∈ Φ are ¯ T represented as the following equations: y1 y2 y3 y4 y5 = = = = = F1 ∨ F4 ∨ F5 ∨ F8 ; F1 ∨ F3 ∨ F5 ; F2 ∨ F4 ∨ F8 ; F3 ∨ F6 ; F4 ∨ F7 ∨ F8 ; D1 = F2 ∨ F3 ∨ F4 ∨ F6 ∨ F8 ; D2 = F1 ∨ F4 ∨ F8 . (2.5)

The primitive matrix realization of FSM S5 is shown in Fig. 2.4, where CMOS transistors are replaced by the sign ”•”. The following values can be found for FSM S5 : S(M1 ) = 2(4+2)8 = 96, S(M2 ) = 8(5 + 2) = 56 and S(MT ) = 152. The circuit shown in Fig. 2.4 includes two levels of matrices on the path from inputs X to outputs Y. Let tM and tRG stand for propagation delay of a combinational circuit and a register respectively, then the cycle time of such a circuit is determined as t(T ) = 2tM + tRG . (2.6)

In expression (2.6), the symbol T stands for the primitive matrix realization of FSM circuit.

32 Table 2.1 Structure table of Mealy FSM S5 am a1 a2 K(am ) 00 01 as a2 a3 a3 a4 a1 a3 a1 a4 K(as ) 01 10 10 11 00 10 00 11 Xh 1 x1 x1 x2 ¯ x1 x2 ¯ ¯ x3 x¯3 x4 x4 ¯

2 Matrix Realization of Control Units

Yh y1 y2 y3 y2 D1 y1 y3 y5 y1 y2 D1 y5 y1 y3 y5

Φh
D2 D1 D1 D1 D2 – D1 – D1 D2

h 1 2 3 4 5 6 7 8

a3 a4

10 11

x1 x2

x3

x4

T1 T 2 F1 F2 F3 F4 F5 F6 F7 F8 y 1 y 2 y 3 y 4 y5 Start Clock D1 D2 R C RG

T1 T2

Fig. 2.4 Primitive matrix realization of FSM S5

The primitive realization leads to logic circuits with maximal possible performance (minimal cycle time) among all possible matrix implementations of Mealy FSM. But such an approach leads to very redundant logic circuits. For example, an FSM with average complexity is characterized by the following values of parameters [3]:H ≈ 2000, R ≈ 8, N ≈ 5, L ≈ 30. It follows from (2.4), that such an FSM has S(MT ) = 268000. This parameter determines the number of possible interconnections in both matrices M1 and M2 . Obviously, only some part of possible interconnections is used for a particular FSM. Let a term Fh include Lh letters from the input alphabet X , and let Nh microoperations and Rh input memory functions be produced for each FSM transition. It means that the number of interconnections for matrix Mi are determined as S(Mi )R , where i = 1, 2, T : S(M1 )R = (Lh + R)H; S(M2 )R = (Nh + Rh)H; S(MT )R = (Lh + Nh + Rh + R)H. (2.7)

2.1 Primitive Matrix Realization of FSM

33

Let the symbol ET stand for efficiency of use of matrix areas for matrices M1 and M2 in the case of FSM primitive realization. For Mealy FSM, it is determined as: ET = S(MT )R /S(MT ). (2.8)

Let an FSM of average complexity be characterized by the values Lh = Nh = 6 and Rh = 4, then ET = 16/134 ≈ 0, 12. It means that near 88% of matrix area is wasted in case of the primitive realization. If a designer does not strive for ultimate performance, then the primitive Mealy FSM matrix realization is not used. Outputs of Moore FSM depend only on its states am ∈ A, as follows from (1.10). Thus, functions yn ∈ Y are independent on terms Fh , represented as (1.6). The terms Am ∈ A0 , corresponding to states am ∈ A, are used as the minterms of output functions yn ∈ Y . Therefore, the primitive matrix realization of Moore FSM can be represented as it is shown in Fig. 2.5.
Fig. 2.5 Primitive matrix realization of Moore FSM
X & M3 F A0 Y Start Clock RG T 1 M4

A conjunctive matrix M3 has 2(L + R) inputs; it implements H terms Fh ∈ F from system Φ , and M terms Am ∈ A0 from system Y . A disjunctive matrix M4 has H + M inputs and implements N + R functions. Let us find the areas of matrices M3 , M4 and the total area occupied by the FSM circuit. By analogy with (2.2) – (2.4), these areas can be found as the following: S(M3 ) = 2(L + R)(H + M); S(M4 ) = (H + M)(R + N); S(MT )2 = (3R + 2L + N)(H + M). (2.9) (2.10) (2.11)

Consider an example of the primitive matrix realization for the Moore FSM S6 , represented by its structure table (Table 2.2). For the FSM S6 , we have L = 4, R = 3, H = 15, M = 5, N = 6, therefore, S(M3 ) = 280, S(M4 ) = 180, S(MT )2 = 460. In the case of FSM S6 , as for any Moore FSM, there are two sets of terms, namely the set F = {F1 , . . . , F15 }, where, ¯ ¯ ¯ ¯ ¯ for example, F3 = T1 T2 T3 x1 x2 , and the set A0 = {A1 , . . . , A8 }, where, for example, ¯1 T2 T3 . The Boolean expressions for functions yn ∈ Y and φr ∈ Φ are derived ¯ A3 = T from Table 2.2.

34 Table 2.2 Structure table of Moore FSM S6 am a1 (–) K(am ) 000 as a2 a3 a4 a2 a1 a5 a2 a1 a5 a1 a4 a4 a1 a4 a4

2 Matrix Realization of Control Units

K(as ) 001 010 011 001 000 100 001 000 100 000 011 011 000 011 011

Xh x1 x1 x2 ¯ x1 x2 ¯ ¯ x1 x3 x1 x3 ¯ x1 ¯ x1 x3 x1 x3 ¯ x1 ¯ x3 x4 x3 x4 ¯ x3 ¯ x3 x4 x3 x4 ¯ x3 ¯

Φh
D3 D2 D2 D3 D3 – D1 D3 – D1 – D2 D3 D2 D3 – D2 D3 D2 D3

h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

a2 (y1 y3 D1 y5 y6 )

001

a3 (y1 y2 D1 y5 )

010

a4 (y2 y6 )

011

a5 (y1 y3 D1 y6 )

100

In the case of FSM S6 , the matrix M4 implements the following systems of Boolean functions y1 = A2 ∨ A3 ∨ A5 , . . . , y6 = A2 ∨ A4 ∨ A5 , D1 = F6 ∨ F9 , . . . , D3 = F1 ∨ F3 ∨ F4 ∨ F7 ∨ F11 ∨ F12 ∨ F14 ∨ F15 . The primitive matrix realization of FSM S6 is shown in Fig. 2.6.
Fig. 2.6 Primitive matrix realization of Moore FSM S6
X & M3 F A0 Y Start Clock RG T 1 M4

As follows from analysis of Fig. 2.6, both matrices M3 and M4 are used very ineffectively. There are 280 possible interconnections for the matrix M3 , but only 85 of them are in use (less than 30%). As well, only 31 from 180 interconnections are used in the matrix M4 , it gives us near 17% of all possible interconnections. Thus, in whole only 116 from 460 possible interconnections are used, it means that 75% of mutual area of matrices M3 and M4 is free. So, the primitive matrix realization results in very redundant logic circuits of Moore FSM. The real number of needed interconnections can be found from analysis of Fig. 2.6, namely:

2.2 Optimization of Mealy FSM Matrix Realization

35

S(M3 )R = (Lh + R)H + RM; S(M4 )R = Nm M + Rh H; S(MT )R = (Lh + Rh + R)H + (R + Nm)M,

(2.12)

where Nm is an average number of microoperations executed in one state of Moore FSM. Using both expression (2.8) and parameters of an FSM with average complexity, it could be found that ET ≈ 0.13 (if H = 2000, L = 30, N = 50, Lh = 6, Rh = Nm = 4, M = 200, R = 8). Thus, approximately 87% of a chip area occupied by logic circuit of Moore FSM is not used. Thus, primitive matrix realizations of Moore and Mealy FSMs are redundant considering use of a chip area. In both cases, only 12–13% is used to implement the really needed interconnections. The value of parameter ET can be increased due to the multilevel realization of FSM logic circuits [3].

2.2

Optimization of Mealy FSM Matrix Realization

Let X (am ) be a set of logical conditions determining transitions from the state am ∈ A, and let G = max(|X (a1 )|, . . . , |X(aM )|). (2.13) If condition G L (2.14) takes place, then the method of logical condition replacement [3] can be used to improve the quality of the FSM matrix realization. The main idea of the method is reduced to construction of some additional variables pg ∈ P used for replacement of logical conditions xl ∈ X , where |P| = G. From analysis of Table 2.1, we can find for the Mealy FSM S5 the following sets: X (a1 ) = 0, X (a2 ) = {x1 , x2 }, X (a3 ) = {x3 }, X(a4 ) = {x4 }; it means that G = 2. / Therefore, the set X can be replaced by a set P = {p1 , p2 }. Let us construct the table of logical condition replacement, having G columns marked by variables pg ∈ P, and M rows marked by states am ∈ A. If a variable pg replaces in a state am a logical condition xl , then the symbol xl is written on the intersection of the row am and column pg of the table. To minimize the hardware amount of logic circuit used for the logical condition replacement, the distribution of logical conditions is executed in such a manner that each variable xl ∈ X is always placed in the same column of the table for all states of FSM. In the case of Mealy FSM S5 , above mentioned distribution of logical conditions is shown in Table 2.3. There are formal methods for execution of required distribution in cases of very complex FSM which can be found in [3]. The following system of Boolean functions should be constructed to replace the logical conditions: P = P(X, T ). (2.15) In our particular case, this system is the following one: p1 = A2 x1 ∨ A3 x3 , p2 = A2 x2 ∨ A4 x4 . Generally, system (2.16) is represented as:

16) where Cml is a Boolean variable. G). 2. .3 Logical condition replacement for Mealy FSM S5 am a1 a2 a3 a4 p1 – x1 x3 – p2 – x2 – x4 pg = ∨ Cml Am xl m=1 M (g = 1. a matrix M5 implements terms of the system (2. After these transformations. iff the variable pg replaces the logical condition xl for the state am . (2.7 Matrix realization of logical condition replacement for Mealy FSM S5 M5 x1 x2 x3 x4 T1 T2 F1 F2 F3 F4 F5 y1 y2 M6 In this circuit. . which is equal to 1. .16) can be implemented as a two-level matrix circuit shown in Fig. system (2.8 Matrix realization of Mealy FSM with logical condition replacement Start Clock RG T . X & M5 1 M6 P & M7 F 1 M8 Y V Fig. making a set of terms V = {v1 . whereas a matrix M6 implements functions pg ∈ P as some disjunctions from terms vi ∈ V .7. 2.36 2 Matrix Realization of Control Units Table 2. 2.8). . For the FSM S5 . vI }. . .16). 2. . . Fig. the matrix realization of Mealy FSM includes four matrices (Fig.

The transformed structure table of Mealy MP FSM S5 (Table 2.17) is derived from Table. replaced the corresponding conjunctions of logical conditions xl ∈ X . V2 = T1 T2 x2 . its minimal value is equal . Table 2.3. IG.4 Transformed structure table of MP Mealy FSM S5 am a1 a2 K(am ) 00 01 as a2 a3 a3 a4 a1 a3 a1 a4 K(as ) 01 10 10 11 00 10 00 11 Ph 1 p1 p1 p2 ¯ p1 p2 ¯ ¯ p1 p1 ¯ p2 p2 ¯ Yh y1 y2 y3 y2 D1 y1 y3 y5 y1 y2 D1 y5 y1 y3 y5 Φh D2 D1 D1 D1 D2 – D1 – D1 D2 h 1 2 3 4 5 6 7 8 a3 a4 10 11 ¯ ¯ ¯ System (2. Obviously. 2(G + R)H. a matrix M7 implements terms from the system F = F(P.2. the initial structure table of Mealy FSM should be transformed in such a way that its column Xh is replaced by a column Ph . a block BM.4. To construct the system (2. T ) (2. .8. p 2 = v2 ∨ v4 . F8 = T1 T2 p2 . V3 = T1 T2 x3 . The matrix M6 implements equations from the system (2. The system of terms ¯ V = V (X. (2. is represented by matrices M5 and M6 . H(N + R).1 and Table 2. The column Ph contains conjunctions of variables pg ∈ P.8.19) shows that decrease for areas of both matrices M5 and M6 can be reached due to decrease of the value I. Mealy FSM shown in Fig. Complexity of MP Mealy FSM can be estimated adding the matrix areas: S(M5 ) S(M6 ) S(M7 ) S(M8 ) = = = = (L + 2R)I.16). 2.19) Analysis of system (2. .17) used to form functions Y and Φ . T ).2 Optimization of Mealy FSM Matrix Realization 37 In Fig. (2. and the term MP FSM is used to denote Mealy FSM shown in Fig.17). F2 = T1 T2 p1 . For our example. 2. F1 = T1 T2 . used to replace the logical conditions. 2. p1 = v1 ∨ v3 .3 are named P FSM. V4 = T1 T2 x4 . . this system is derived from ¯ ¯ ¯ Table 2.3 as the following one: V1 = T1 T2 x1 .18) is implemented by the matrix M5 . As a rule [1]. namely. 2. In case of MP FSM. .4) is constructed using both Table 2. for example.

3] is used to decrease the area of matrix M2 (Fig. the logical conditions should be distributed among the table columns in such a manner. In common case. 2.3). corresponding to states am ∈ A(xl ). in this case sets A(xl ) are used as restrictions of the algorithm [12. let the following solution of the first problem be obtained for some FSM S: p1 = (A2 ∨ A12 ∨ A13 )x1 ∨ (A1 ∨ A8 )x4 ∨ (A7 ∨ A9 ∨ A10 )x5 . Obviously.38 2 Matrix Realization of Control Units to the number of logical conditions. Let X(pg ) be a set of logical conditions written in the column pg of replacement table. this problem is solved using two approaches from [3].3). The method of encoding of collections of microoperations [1. Let the structure table . For the FSM S. that the following condition takes place: X (pi ) ∩ X (p j ) = 0 / (i = j. First. the appropriate state assignment allows three times decrease for the number of terms in system (2. which is replaced by matrices M5 . j ∈ {1.. . For example. that each disjunction Bl is represented by a single conjunctive term. the next system can be ¯ ¯ ¯ ¯ derived from the Karnaugh map (Fig.20) Let Bl be a disjunction of terms Am . p2 = (A4 ∨ A5 ∨ A6 ∨ A7 )x2 ∨ (A3 ∨ A4 ∨ A5 )x3 ∨ (A6 ∨ A11 ∨ A12 )x6 ∨ (A5 ∨ A8 ∨ A13 )x7 . because there is no another variant of the logical condition replacement. . The logical condition replacement targets in reducing of the area occupied by the matrix M1 (Fig. The well-known algorithm ESPRESSO [9] can be used for such an encoding. In the considered example. there are M = 13 states.18). (2.8). L. and it is enough R = 4 state variables Tr ∈ T for their encoding.9 Codes for Mealy FSM S T3T4 T1T 2 00 01 11 10 00 01 11 10 Taking into account the ”don’t care” input assignments. from 21 (it is determined by the number of terms for logical condition replacement) to L = 7. in this case value of parameter I can be any. 2. M7 (Fig. i. 2. Thus.9. Fig. The second task is reduced to such a state assignment for states am ∈ A.9): p1 = T3 T4 x1 ∨ T1 T3 T4 x4 ∨ T1 T2 x5 . One of the possible encoding variants is shown in Fig. p2 = ¯ ¯ ¯ T3 T4 x2 ∨ T1 T4 x3 ∨ T1 T2 x6 ∨ T1 T2 x7 . .17) for logical condition xl ∈ X . 13]. M6 . 2. this minimum was reached automatically. for this variant we can find the following values: I = L = 7. 2. Let A(xl ) be a set of states which can be extracted from terms (2. 2. it leads to PY Mealy FSM [7]. G).

Now. To get system (2. .25) Values of variables R3 and N are determined by initial GSA to be interpreted.2 Optimization of Mealy FSM Matrix Realization 39 of Mealy FSM include T0 different collections of microoperations Yt ⊆ Y . Y3 = {y2 .. and a matrix M10 implements functions yn ∈ Y as some disjunctions of the terms W j ( j = 1.5). whereas parameter J can be changed from T0 to N (the value N corresponds to such a situation when each microoperation is represented as a single term).21) bits. Y5 = {y6 }.24) (2. where |Z| = R3 . the initial structure table of Mealy FSM should be transformed by the replacement of the column Yh by the column Zh (Table 2. K(Y6 ) = 101. 3]. . (2.23) The matrix realization used for implementation of system (2. . a matrix M9 implements terms w j from a set of terms W. z2 . . y4 }. Therefore. because the structure fable (Table 2.10). 2. corresponding to the code K(Yt ). It can be derived from the column Yh (Table 2. X ) is transformed into the following systems: Z = Z(T. Encode each collection Yt by a binary code K(Yt ) having R3 = log2 To (2. .22). Y = Y (Z). namely: K(Y1 ) = 000. (2. y2 }.4) that: y1 = Y1 ∨ Y4 . 2. 2. . for such an encoding. and C(Yt ) be a conjunction of variables zr ∈ Z. Fig. we have T0 = 6.10 is determined as result of summation for areas of matrices M9 and M10 : S(M9 ) = 2R3 J. Y4 = {y1 . J). y4 = Y3 ∨ Y5 . y3 = Y2 ∨ Y4 . For the FSM S5 . y3 . R3 = 3 and Z = {z1 . X ). S(M10 ) = JN. Y6 = {y5 }.2.10). . y5 = Y4 ∨ Y6 . Let B(yn ) be a set of collections of microoperations containing the microoperation yn ∈ Y . Let us use variables zr ∈ Z. system Y = Y (T. 2. y5 }. y2 = Y1 ∨ Y3 . Let us point out that the matrix M10 is disappeared if J = N [2.10 Matrix realization of system of microoperations for PY Mealy FSM In the circuit (Fig. The complexity of matrix realization shown in Fig. Encode the collections Yt in a trivial way. .22) (2. z3 }.23) includes matrices M9 and M10 (Fig.4) includes the following collections of microoperations: Y1 = {y1 . Y2 = {y3 }.

For the FSM S5 . The matrix realization of PY Mealy FSM is shown in Fig.23) is represented by SOP with the minimal possible number of terms. The wellknown algorithm ESPRESSO [9] can be applied to solve this problem. 2.12 Optimal codes of collections of microoperations for PY Mealy FSM S5 .12. 3] should be solved. 2. Fig. optimal codes of collections of microoperations are represented by the Karnaugh map shown in Fig. 2. the problem of optimal encoding of collections of microoperations [2. then the column Zh should contain variables zr ∈ Z.40 2 Matrix Realization of Control Units Table 2.11.11 Matrix realization of PY Mealy FSM To minimize the areas of matrices M9 and M10 . Fig.5 Transformed structure table of PY Mealy FSM S5 am a1 a2 K(am ) 00 01 as a2 a3 a3 ¯ a4 x4 a1 a3 a1 a4 K(as ) 01 10 10 11 00 10 00 11 Xh 1 x1 x1 x2 ¯ x1 x2 ¯ ¯ x3 x3 ¯ x4 Zh – z3 z2 z2 z3 – z1 z1 z3 z2 z3 Φh D2 D1 D1 D1 D2 – D1 – D1 D2 h 1 2 3 4 5 6 7 8 a3 a4 10 11 An approach for filling of the column Zh is the following one: if the row h of initial ST contains a collection Yt . when each expression (2. 2. corresponding to 1 in the code K(Yt ).

2.2 Optimization of Mealy FSM Matrix Realization

41

Taking these codes into account, the system (2.23) is represented as the following one for FSM S5 : y1 = z1 z2 , y2 = z1 z3 , y3 = z1 z3 , y4 = z2 z3 , y5 = z2 z3 . This system is ¯ ¯ ¯ ¯ ¯ ¯ ¯ implemented by the matrix circuit shown in Fig. 2.13.
Fig. 2.13 Matrix realization of microoperations for PY Mealy FSM S5

In the circuit from Fig. 2.13, the wire z1 is not used, because of it the matrix area can be calculated as 5 × 5 = 25. Let us point out that the initial values obtained from (2.24) and (2.25) are equal to S(M9 ) = 2 · 3 · 6 = 36 and S(M10 ) = 6 · 5 = 30. It gives the total area equal to 66. Thus, the application of optimal encoding results in the block BY having 2.6 times less hardware, than in case of a straightforward implementation of microoperations. The joint application of logical condition replacement and encoding of collections of microoperations leads to MPY Mealy FSM (Fig. 2.14).
Fig. 2.14 Matrix realization of MPY Mealy FSM

Functions of all matrices from this matrix realization are clear from preceding information as well as formulae for their areas. The synthesis method of MPY Mealy FSM includes the following steps:

42

2 Matrix Realization of Control Units

1. 2. 3. 4. 5. 6. 7. 8.

Construction of marked GSA. Construction of transition table of Mealy FSM. Construction of table of logical condition replacement. State assignment targeted in reduction of hardware for the block BP. Optimal encoding of collections of microoperations. Construction of transformed structure table of Mealy FSM. Construction of systems for realization of matrices M1 – M6 . Design of FSM logic circuit using functions obtained in step 7.

The transformed structure table of MPY Mealy FSM S5 (Table 2.6) is constructed taking into account the codes of collections of microoperations from Fig. 2.12.
Table 2.6 Transformed structure table of MPY Mealy FSM S5 am a1 a2 K(am ) 00 01 as a2 a3 a3 a4 a1 a3 a1 a4 K(as ) 01 10 10 11 00 10 00 11 Ph 1 p1 p1 p2 ¯ p1 p2 ¯ ¯ p1 p1 ¯ p2 p2 ¯ Zh z3 z2 z2 z3 – z3 z1 z2 z3 z1 –

Φh
D2 D1 D1 D 1 D2 – D1 – D 1 D2

h 1 2 3 4 5 6 7 8

a3 a4

10 11

It is really easy to design the logic circuit (matrix realization) of MPY Mealy FSM S5 , because all its components were already designed. Obviously, the discussed method can be adapted to design either Mealy MP– or PY FSM. The results of many researches show that application of the logical condition replacement and optimal encoding of collections of microoperations results in significant hardware amount reducing, especially for complex FSM having more than 2000 transitions. This approach has one serious drawback, namely decrease in FSM performance in comparison with the primitive matrix realization of Mealy FSM. It is an effect of the cycle time increase due to increase for the number of levels in the resulting FSM realization (in comparison with the primitive matrix realization of Mealy FSM).

2.3

Optimization of Moore FSM Logic Circuit

Analysis of systems (1.8) and (1.10) shows that the combinational part of Moore FSM matrix realization (it is shown in Fig. 2.5) can be divided by two blocks. By analogy with Mealy FSM, let us denote as P Moore FSM the device whose structure is shown in Fig. 2.5 and let the denotation PY Moore FSM stand for the device from Fig. 2.15. In Fig. 2.15, a matrix M1 implements terms Fh ∈ F, corresponding to rows of Moore FSM structure table, while a matrix M2 implements system (1.8). Matrices

2.3 Optimization of Moore FSM Logic Circuit Fig. 2.15 Matrix realization of PY Moore FSM

43

M3 andM4 form a block BY. In this block, the matrix M3 implements terms Am ∈ A0 from system (1.10), while the matrix M4 implements microoperations yn ∈ Y . Complexity of PY Moore FSM matrix realization is determined as a total area for matrices M1 – M4 , namely: S(M1 ) = 2(L + R)H; S(M2 ) = HR; S(M3 ) = 2RMS(M4 ) = MN; S(MPY ) = (2L + 3R)H + (2R + N)M. (2.26)

For an FSM with average complexity (L = 30, H = 2000, R = 8, L = 30, L = 30), we can find that S(MPY ) = 181200. In case of P Moore FSM, interpretation of such kind GSA gives control units with the total area S(MT )2 = 294800. Therefore, the replacement of P Moore FSM by PY Moore FSM results in considerable area decreasing (in 1.63 times). It means that the efficiency of chip area usage increases too. If device shown in Fig. 2.6 is divided by blocks BP and BY, then it could be found that only 70 from 210 possible interconnections are used in the matrix M1 , 16 interconnections from 45 are used in the matrix M2 ,and 15 interconnections from 30 are used in both matrices M3 and M4 . It gives the value EPY = (70 + 16 + 15 + 15)/(210 + 45 + 30 + 30) = 0.37, that is 12% more, than for the primitive matrix realization for Moore FSM S6 . A chip area for matrices M1 and M2 can be decreased due to decrease of parameter H. It can be obtained if states of Moore FSM are encoded using the method from Section 1.2. Remind, this approach is named as an optimal state encoding. Let us discus application of this approach for the Moore FSM S6 . As follows from Table 2.2, the Moore FSM S6 includes I = 3 classes of the pseudoequivalent states, namely: B1 = {a1 }, B2 = {a2 , a3 }, B3 = {a4 , a5 }. Let us encode the states am ∈ A by the optimal codes (Fig. 2.16).
Fig. 2.16 Optimal state codes for Moore FSM S6
T2T3
T1

00

01

11

10

0 1

44

2 Matrix Realization of Control Units

As follows from Fig. 2.16, the class B1 corresponds to the generalized interval ∗, 0, 0 of three-dimensional Boolean space, the class B2 to ∗, ∗, 1 , and the class B3 to ∗, 1, ∗ . Thus, the class B1 is determined by the code ∗00, the class B2 by the code ∗ ∗ 1, and the class B3 by the code ∗1∗. The transformed structure table of Moore FSM S6 (Table 2.7) includes H0 = 9 rows, where the symbol H0 stands for the number of structure table rows for an equivalent Mealy FSM [1].

Table 2.7 Transformed structure table of Moore FSM S6 Bi B1 K(Bi ) ∗00 ∗∗1 ∗1∗ as a2 a3 a4 a2 a1 a5 a1 a4 a4 K(as ) 001 101 010 001 000 110 000 010 010 Xh x1 x1 x2 ¯ x1 x2 ¯ ¯ x1 x2 x1 x3 ¯ x1 ¯ x3 x4 x3 x4 ¯ x3 ¯

Φh
D3 D1 D3 D2 D3 – D1 D2 – D2 D2

h 1 2 3 4 5 6 7 8 9

B2

B3

From Table 2.7, for example, the following Boolean function D1 = F2 ∨ F6 = ¯ ¯ ¯ ¯ T2 T3 x1 x2 ∨T3 x1 can be derived. The matrix circuit of Moore FSM S6 is characterized by the following areas of matrices: S(M1 ) = (4 + 8) · 9 = 108, S(M2 ) = 9 · 3 = 27, S(M3 ) = 6 · 5 = 30, and S(M4 ) = 5 · 6 = 30. Therefore, the application of the optimal state encoding results in considerable decrease of the total area in comparison with PY Moore FSM. In considered example, the total area decreases from 315 to 195, that is near 1.6 times less. The total area for matrices M3 and M4 (Fig. 2.15) can be decreased using the state encoding targeted in decrease for the number of terms in system Y. Let us name this approach as a refined state encoding. For the FSM S6 , one of the possible variants for the refined state encoding is shown in Fig. 2.17.
Fig. 2.17 Refined state codes for Moore FSM S6
T2T3
T1

00

01

11

10

0 1

As follows from Table 2.2, the system of microoperations for Moore FSM S6 is the following one: y1 = y4 = A2 ∨ A3 ∨ A5 , y2 = A3 ∨ A4 , y3 = A2 ∨ A5 , y5 = A2 ∨ A3 , y6 = A2 ∨ A4 ∨ A5 . Taking into account the codes from Fig. 2.17, the system ¯ ¯ of microoperations can be represented as: y1 = y4 = T3 , y2 = T1 T2 , y3 = T1 T3 ,

For the FSM S6 . Obviously.27) is more than once shown in our book. y2 .28) are represented as Bi = ∨ Cim Am m=1 M (i = 1. . y6 = T1 T3 ∨ T1 T3 = y3 ∨ T1 T3 . y3 = A2 ∨ A5 = T y6 = A2 ∨ A4 ∨ A6 = y3 ∨ T3 . . This method can be explained as the following. Let us point out that microoperations y1 . y1 = y4 = ¯1 T3 . It means that the matrix M3 has 5 inputs (the input T2 is absent) and realizes 4 terms.27) (2. Obviously. and only 3 outputs (y3 . that is 2. (2. T1 . we have S(M3 )+ S(M4 ) = 60.28) can be derived from the partition ΠA as the following one: B1 = A1 . T3 ). . B3 = T2 . thus S(M1 ) + S(M2 ) = 135.18). B3 = A4 ∨A5 . y2 = A3 ∨ A4 = T1 . ¯ ¯ ¯ From Fig. the aim of the optimal state encoding differs from the aim of the refined state encoding.73 more than the area of these matrices for the refined state encoding. y5 = A2 ∨ A3 = T2 T3 .19.29) where Cim is a Boolean variable equal to 1. but only two of them are used by the matrix M4 . y5 . while the elements of system (2. (2. B2 = A2 ∨A3 . T2 . B = B(A). Simultaneous decrease for areas of matrices M1 . ¯ A2 ∨ A3 ∨ A5 = T3 . This problem can be solved using. it can be found that: B1 = T2 T3 .3 Optimization of Moore FSM Logic Circuit 45 ¯ ¯ ¯ ¯ y5 = T2 T3 . the areas of matrices M1 and M2 are the same for both combined and optimal state encoding. . One of the possible variants for combined state encoding is shown in Fig. 2. y4 are produced without additional transistors.27) and (2.2.27) be determined by expression (1. ¯ ¯ The matrix M3 has 4 inputs (T1 . whereas system (2. 2. that the total number of terms is minimal for systems (2. 2. This system is implemented using two matrices (Fig. In case of the arbitrary state encoding.M4 can be achieved by application of a combined state encoding [5. B2 = T2 T3 . the algorithm ESPRESSO [9].28). 2. Fig. The combined state encoding is executed in such a manner. .28) Let system (2. I).19. Let us construct the following systems of functions: Y = Y (A). T3 ). system (2. implemented only the microoperation y6 . for example. iff am ∈ Bi . 6].10).18 Matrix realization for microoperations of FSM S6 The total area of this matrix circuit can be calculated as S(M3 )+S(M4 ) = 5·4+2· 1 = 22.

ΠA = {B1 . used to generate the microoperation y6 . 2. The following values and sets can be derived from Table 2. this value corresponds to the number of rows in the structure table of equivalent Mealy FSM. I = 4.8). Remind. there is no such a state encoding variant which gives the transformed structure table with H0 = 9 rows. B3 = {a5 . y2 = A5 ∨ A6 . It results in PCYMoore FSM shown in Fig. a4 }. B3 . 8]. a3 .19 Combined state codes for Moore FSM S6 2 Matrix Realization of Control Units T2T3 T1 00 01 11 10 0 1 The matrix M4 has 2 inputs (y3 and T3 ). A code transformer BTC generates codes of classes Bi ∈ ΠA on the base of codes for states am ∈ Bi . we can construct the functions: y1 = A2 ∨ A3 . B4 = {a8 }. B2 = {a2 . a7 }. X). Therefore. where B1 = {a1 }. . y3 = A2 ∨ A4 ∨ A7 .M4 is equal to 149 in the case of FSM S6 . total area of matrix realization is decreased from 315 (in the case of arbitrary state encoding) to 149. R = 3. and the total area for matrices M1 . B2 . where the FSM is set up by its transition table (Table 2. Obviously. y4 = A3 ∨ A6 . For the Moore FSM S7 . Let us point out that the combined state encoding could produce results. In this case the total area can be decreased using a transformer of state codes into codes of the classes of pseudoequivalent states [4. The total area for these matrices can be found as S(M3 ) + S(M4 ) = 4 · 3 + 2 · 1 = 14. B4 }. 1. so the block BTC implements the Boolean system τ = τ (T ). a6 . 2.20 Structure of PCYMoore FSM In PCYMoore FSM. which are far from optimal for one or both parts of the matrix realization of PY Moore FSM. a block BP implements functions Φ = Φ (τ . that is more than 2 times. (2.46 Fig.8: M = 8. The method of synthesis includes the following steps.30) where τ is a set of variables used to code classes Bi ∈ ΠA .31) Consider an example of the PCYMoore FSM S7 design. 2. Construction of systems Y and B. (2. Fig.20.

3 Optimization of Moore FSM Logic Circuit Table 2.21 Refined state codes for Moore FSM S7 T2T3 T1 00 01 11 10 0 1 3.8 Transition table of Moore FSM S7 am a1 (–) a2 (y1 y3 y5 y7 ) a3 (y1 D1 y7 ) a4 (y3 ) a5 (y2 ) as a2 a3 a4 a5 a4 a5 a4 a5 a7 a6 a8 a7 a6 a8 a6 a7 a8 a3 a1 Xh x1 x1 ¯ x2 x2 ¯ x2 x2 ¯ x2 x2 ¯ x3 x3 x4 ¯ x3 x4 ¯ ¯ x3 x3 x4 ¯ x3 x4 ¯ ¯ x3 x3 x4 ¯ x3 x4 ¯ ¯ x5 x5 ¯ h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 47 a6 (y2 D1 y7 ) a7 (y3 y5 y7 ) a8 (y6 ) y5 = A 2 ∨ A 7 . 2. y7 = T3 = Δ7 . Thus. y7 = A 2 ∨ A 3 ∨ A 6 ∨ A 7 . 2. For PCYMoore FSM. y6 = T1 T2 = Δ6 . the state encoding targets in hardware decrease for block of microoperations. B4 = A8 . The outcome of this step is shown in Fig.2. ¯ T2 T3 = Δ5 . Construction of functions describing the block BY.21 permit to get the following system: y1 y2 y3 y4 = = = = ¯ T1 T3 = Δ1 . The codes represented by Fig. 2.32) The terms Δk from the system (2. y5 = Δ 4 . (2. the refined state encoding should be done. Fig. B3 = A5 ∨ A6 ∨ A7 . . y6 = A 7 ∨ A 8 .32) form a set F(Y ). ¯ T1 T2 = Δ2 . State assignment. 2. B 2 = A 2 ∨ A 3 ∨ A 4 .21. ¯ T1 T2 ∨ T2 T3 = Δ3 ∨ Δ4 . B 1 = A 1 .

τ2 = Δ1 ∨ Δ3 ∨ Δ9 . (2. Construction of functions describing the block BTC. Obviously. It is necessary 6 matrices to implement the logic circuit of PCYMoore FSM (Fig. K(B4 ) = 11. D2 = F1 ∨ F3 ∨ F5 ∨ F7 . the blocks BTC and BY have the same inputs and. The following form of system (2.35) The terms from the system (2. S(M4 ) = 2 · 1 = 2. Xh .30) are determined as the following conjunctions: l Fh = ∧ τrhr Xh r=1 R0 (2. It gives the following system to represent the system (2.48 2 Matrix Realization of Control Units 4. H0 ). 1} is equal to the value of bit r for code K(Bi ). For the FSM S7 . 2. whereas matrices M3 and M4 implement the block BY. S(M2 ) = 8 · 3 = 24. D3 = F1 ∨ F2 ∨ F5 ∨ F6 ∨ F8 .22). F2 = τ1 τ2 x3 x4 and so on. we can found that: S(M1 ) = 10 · 8 = 80. 2.15 is equal to 361. S(M5 ) = 6 · 5 = 30. K(Bi ). . . . The terms of system (2. Φh . Let us point out that this table includes H0 = 9 rows. . 6. In the matrix realization of PCYMoore FSM. . For the Moore FSM S7 .. Besides.37). the block BP is implemented by matrices M1 and M2 . a variable lhr ∈ {0.21 permit to get the following system: ¯ ¯ ¯ B1 = T1 T2 T3 = Δ8 . it can ¯ ¯ ¯ ¯ be found that: F= τ1 τ2 x1 . namely: K(B1 ) = 00. Classes Bi ∈ ΠA can be coded using R0 = log2 I (2. ¯ B4 = T1 T2 T3 = Δ9 .21. it is the absolute minimum for the Moore FSM S7 . therefore. K(as ). For the PCYMoore FSM S7 .37) In (2.31): τ1 = Δ2 ∨ Δ9 ∨ Δ10 . as .34) ¯ B3 = T1 T2 ∨ T1 T3 = Δ2 ∨ Δ10 .9: D1 = F4 ∨ F5 ∨ F6 ∨ F7 . Now we can find that τ1 = B3 ∨ B4 . the total area of matrices from Fig.9. 2. . Encode the classes Bi ∈ ΠA in a trivial way. This table includes the columns Bi .36) (h = 1. S(M6 ) = 5 · 2 = 10. . From Table 2. Let us construct the transformed structure table of the Moore FSM S7 .30) is derived from Table 2. which is written in the row h of the table. h.33) variables τr ∈ τ . . S(M3 ) = 6 · 6 = 36. thus. 5. (2. 2. Matrix realization of FSM circuit. they can be combined in a single block consisting from two matrices. τ2 = B2 ∨ B4 . where |τ | = R0 . ¯ ¯ B2 = T1 T3 ∨ T1 T2 = Δ1 ∨ Δ3 .35) make up a set F(TC). the codes K(Bi ) can be derived from Fig. the codes represented by Fig. Construction of transformed structure table. for example. (2. in the same time the block BTC is implemented by matrices M5 and M6 .

3 Optimization of Moore FSM Logic Circuit Table 2. we have G = 2. The total area occupied by matrices M1 and M2 can be decreased using the approach of logical condition replacement. . These calculations show that the total area is decreased near two times due to replacement of the model PY by the model PCY(in the case of FSM S7 ). For the FSM S7 .22 Matrix realization of PCYMoore FSM the total area is equal to 182.10).10 Replacement of logical conditions for PCYMoore FSM S7 am a1 a2 a3 a4 p1 x1 – – – p2 – x2 x2 x2 am a5 a6 a7 a8 p1 x3 x3 x3 x5 p2 x4 x4 x4 – . x5 can be replaced by the additional variables p1 . 2. . Table 2.2. p2 (Table 2.9 Transformed structure table for PCYMoore FSM S7 Bi B1 B2 B3 K(Bi ) 00 01 10 as a2 a3 a4 a5 a7 a6 a8 a3 a1 K(as ) 011 001 010 100 111 101 110 001 000 Xh x1 x1 ¯ x2 x2 ¯ x3 x3 x4 ¯ x3 x4 ¯ ¯ x5 x5 ¯ 49 Φh D2 D3 D3 D2 D1 D1 D2 D3 D1 D3 D1 D2 D3 – h 1 2 3 4 5 6 7 8 9 B4 11 Fig. . . thus the logical conditions x1 .

11). p2 = (B1 ∨ B2 ∨ B6 )x3 ∨ (B3 ∨ B4 )x4 .38) depend on variables τr ∈ τ . The number of terms in system (2. Let the following system be found for some Moore FSM S8 : p1 = (B1 ∨ B2 )x1 ∨ (B3 ∨ B4 ∨ B5 )x2 .38) In contrast to system (2.38). 2. (2. 2. where states am ∈ Bi are replaced by corresponding classes Bi ∈ ΠA (Table 2. (2.38) can be decreased due to an optimal class encoding approach. forming for MPY Moore FSM. application of the optimal state encoding permits decrease for the number of terms in system P = P(X. But now the matrices M1 and M2 implement the system P = P(τ .23).9.11 Transformed table of logical condition replacement for Moore FSM S7 Bi B1 B2 p1 x1 p2 x2 Bi B3 B4 p1 x3 x3 p2 x4 – Using codes K(Bi ) from table 2. 2. X). the following system (2.50 2 Matrix Realization of Control Units Analysis of this table shows that content of columns p1 and p2 is the same for each state am ∈ Bi .23 are clear from previous reading. Fig. Thus. T ). The logical condition replacement turns PCYMoore FSM into MPC YMoore FSM (Fig. p2 = τ1 τ2 x2 ∨ τ1 τ2 x4 .15).38) can be built for ¯ ¯ ¯ ¯ ¯ our example:p1 = τ1 τ2 x1 ∨ τ1 τ2 x3 ∨ τ1 τ2 x5 . the functions of system (2. Table 2. To form the system (2.39) .23 Matrix realization of MPC YMoore FSM Functions of all matrices shown in Fig. it should be constructed the table of logical condition replacement.

than their total possible number. τ1 . structure tables for FSM with average complexity include H ≈ 2000 rows.24.40) For implementation of system (2. 2. Only direct (or only complement) values of logical conditions are used. Thus. the block BM. ¯ ¯ p2 = τ1 x3 ∨ τ1 τ2 x4 . Let us name these circuits and corresponding systems of functions as regular circuits and regular functions respectively.39). such as states. (2. the matrix M1 has 2R0 + L = 10 inputs and 10 outputs. It means that the arbitrary class encoding for MPC YMoore FSM S8 leads to the block BM with the area equal to 10 · 10 + 10 · 2 = 120.40) ¯ ¯ depends on variables τ1 . As a rule. Using the codes from Fig. 2. τ2 .39) and get the following system of equations: ¯ ¯ p1 = τ1 τ2 x1 ∨ τ1 x2 . The methods of optimization discussed in this Chapter can be used for optimization of matrix FSM circuits. while there are 2L+R ≈ 238 possible terms. The number of implemented terms is considerably less. multilevel models of FSM include three different types of circuits (blocks): 1. we can transform the system (2. Let us name these circuits and corresponding systems of functions as multiplexer circuits and multiplexer functions respectively. blocks BY and BTC. whereas the encoding belongs to algorithmic methods. as well as FSM circuits implemented with standard VLSI .24 Optimal codes for classes of Moore FSM S8 2 3 1 51 00 01 11 10 0 1 having 10 terms. 2.2. or collections of microoperations. Let us name these circuits and corresponding systems of functions as irregular circuits and irregular functions respectively. whereas the matrix M2 has 10 inputs and 2 outputs. The matrix M2 has 4 inputs and 3 outputs.3 Optimization of Moore FSM Logic Circuit Fig. Let the first approach be named as a structural decomposition. This class of circuits includes.24. 2. 3.3 times. This class of circuits includes. the total area of FSM matrix realization can be decreased due to increase for the number of levels and coding of some objects. The system (2. Thus. for example. The number of implemented terms is near 50% from their total possible number. for example. For example. Let us encode the classes Bi ∈ ΠA by analogy with the optimal state encoding of Moore FSM. whereas the optimal encoding for classes Bi ∈ ΠA leads to the same block with the area 7 · 4 + 4 · 2 = 36. classes of pseudoequivalent states. it means that now the matrix M1 has 7 inputs and 4 outputs. This encoding outcome is shown in Fig. applying of the optimal encoding permits to decrease the total area of the block BM by 3.

Brayton. In: Proc. Barkalov. Los Alamitos (1998) 12. Barkalov. Saldachna. G. Sangiovanni-Vincentelli. Pozna´ . L. Zielona Góra (2006) 8.I. Lviv Polytechnic National University. Navabi. Kluwer Academic Publishers. Baranov...52 2 Matrix Realization of Control Units chips. Kluwer Academic Publishers. M. Boston (1998) 13. Lviv-Slavsko (2008) 7. T. Kam.: Logic and System Design of Digital Systems.. W˛ grzyn. IEEE Computer Society Press. Brayton. Chmielewski. Publishing House of Lviv Polytechnic. Ministry of Education and Science of Ukraine.: Optimization of moore fsm on systemon-chip using pal technology. A. Poland.: Design of Control Units With Programmable Logic. Chmielewski.: The anatomy of a High-performance Microprocessor: A Systems Perspective.. A. In: Proc.. Baranov.: Embedded Core Design with FPGAs. Conf.. T. Titarenko. Sangiovanni-Vincentelli. Cybernetics and System Analysis (1). R. S.. De Micheli. References 1. Dordrecht (1994) 4. 417–420. New York (1994) 10. Adamski. L. S.: Architectural and Sequential Synthesis of Digital Devices. z s 750–752 (2008) 5..: A Synthesis of Finie State Machines: Logic Optimization. Chmielewski. R.. McGraw-Hill.: Symbolic two-level minimization.: Principles of optimization of logic circuit of Moore FSM.. Tallinn (2008) 3. TUT Press. MIXDES 2008. Przegl´ d Telekomunikacyjny i Wiadomo´ci Telokomunikacyjne (6).: Optimization of moore control unit with refined state encoding. 65–72 (1998) (in Russian) 9. Obviously. B. A. Shriver.: Synthesis and Optimization of Digital Circuits. T. of the 15th Inter. S. Villa. of the International Conference TCSET 2008.. Villa. A.: Logic Synthesis of Control Automata. T. Barkalov. Smith. University of Zielona Góra Press. New York (2007) 11.. A. Titarenko. McGraw-Hill.. Let us discuss these features more thoroughly. pp. Zielona Góra (2006) 2.: Decrease of hardware amount in logic circuit of moore FSM. B. A. IEEE Transactions on Computer-Aided Design 16(7).A. S. Departament of Microeletronics and Computer Science.. Lviv. Z.. A. 314–317. n pp. S. Titarenko. 692–708 (1997) . Barkalov. A. Technical University of Łódz (2008) 6. peculiarities of specific types of VLSI circuits significantly affect the methods of FSM optimization. Barkalov. M. Barkalov. Univere sity of Zielona Góra Press. L.

In a PROM. . Such devices are named field-programmable logic devices (FPLD) [61. PAL and GAL. . This architecture perfectly fits for implementation of a system of Boolean functions Y = {y1 . Such emphasis of our book is explained by domination of FPLD for design of modern digital devices.1 Simple Field-Programmable Logic Devices This book deals mostly with synthesis methods oriented on logic devices. c Springer-Verlag Berlin Heidelberg 2009 springerlink.1 shows a programmable connection. 3. . 3. having S inputs and q = 2S outputs. PLA. PLA and PAL chips. 3. This analysis shows particular features of different logic elements and permits to optimize the FSM logic circuits. The analysis is accompanied by some examples for systems of Boolean functions implementation using PROM. A FPLD is a general purpose chip whose hardware can be configured by the end user to implement a particular project. xL }. The content of OR-array is programmable and the sign ”X” in Fig. which are programmed by the end user. but mostly FPLD are marked out as a separate class of digital devices [61]. which were produced by Harris Semiconductor in 1970 [61] They include a fixed array of AND gates (AND-array) followed by a programmable array of OR gates (OR-array) as it shown in Fig. the AND-array implements an address decoder DC. where each output corresponds to an unique address of a memory cell. pp. and finishing with very sophisticated chips such as CPLD and FPGA. which run programs but posses a fixed hardware. 53–75. yN } on Boolean variables X = {x1 . . which is represented A.62]. Titarenko: Logic Synthesis for FSM-Based Control Units. The chapter discussed contemporary field-programmable logic devices and their evolution. The programmability of FPLD is intended at the hardware level contrary to microprocessors. starting from the simplest programmable logic devices such as PROM.Chapter 3 Evolution of Programmable Logic Abstract. . .1. Some researches treat FPLD as representatives of Application Specific Integrated Circuits [81]. . The principle of functional decomposition oriented on FPGA chips is analysed in the last part of the chapter.com . Barkalov and L. in which some particular elements are used. . LNEE 53. The first representatives of FPLD are programmable read-only memory chips (PROM).

where PROM(S. . Fig. yN 1 PROM . . then the approach of expansion of inputs of PROM [13] is used and n2 = 2L /2S = H/q (3.54 Fig. N .3) chips of PROM is necessary to implement a system Y (L. . 3. S 1 .t). N lead to the following implementations of SBF.3). and each chip generates up to t output functions yn ∈ Y (Fig. The implementation is shown in Fig. Such an approach sometimes is named as ”an expansion of outputs of PROM” [13.t ≥ N. N) and discuss its implementation with PROM(S. . In case when S ≥ L. . . 2S OR . . N) (Fig. .2) chips of PROM(S. . . L. In case when S ≥ L. 3.t < N it is necessary n1 = N t (3. . xL y1 .1) rows. . t. The value of parameter i for Fig. DC AND 1 t by a truth table [61]. and functions Y are appeared on the outputs of PROM.2. 27]. 3. L .1 Architecture of PROM 3 Evolution of Programmable Logic 1 S 1 . If S < L. Address inputs of all chips are connected with logical variables xl ∈ X. Combinations of parameters S. . 3. Let us denote this system of Boolean functions (SBF) as Y (L. .t) to implement a system Y (L. t 2. N). 1.4). In this case the system to be implemented can be viewed as a table with H = 2L (3.t). 3. where logical variables X are connected with address inputs of PROM.2 Trivial implementation of SBF with PROM x1 . where each row includes L input columns and N output columns. N) can be implemented in a trivial way using only one chip of PROM(S. 3.3 can be calculated as i = t(n1 − 1) + 1. . 3.t) means that a PROM chip has S inputs and t outputs. .t ≥ N a system Y (L..

Outputs of the decoder are connected with enable inputs of corresponding PROMs. it leads to PROM. because this level of the circuit could be implemented using three-stable outputs of PROM chips [61]. 2.4) chips of PROM is necessary for implementation of a SBF. ORgates are used to produce the final values of functions yn ∈ Y . Programming on the base of mask. The memory devices used this type of programming are named read-only memories (ROM). 3. 55 y1 yt Fig. PROM n2 Yn 2 OR Y In this circuit the L − S leftmost bits of input assignment x1 .. 4. . . Programming is executed using a mask in a manufacturing process. . but the following ones are used mostly: 1.4 Implementation of SBF with expansion of PROM inputs X1 DC 1 n2 X2 X2 PROM 1 Y1 .1 Simple Field-Programmable Logic Devices Fig. address inputs of all chips are connected with S rightmost bits of input assignment and these variables form a set X 2 . 3. . . There are many ways for programming of FPLD [66]. If S < L. . This information cannot be altered or erased.3 Implementation of SBF with expansion of PROM outputs X PROM 1 . which targets on a mass production. In this case both methods of expansions of outputs and inputs are used together. then n3 = n1 · n2 (3.4. In this case programming is executed using a high voltage. 3.. One-time programming. .3. . Such an approach is rather a theoretical one. . The partial functions Y i are generated as outputs of i-th microchip and these functions correspond to subtables of the truth table with rows from q(i − 1) till qi . y1 .. As it can be seen from Fig. xL form a set of variables X 1 . which are connected with inputs of a decoder DC having n2 outputs. Such an approach is used in case of ASIC. This ”program” cannot be changed.t < N. . yt PROM n1 .

An EEPROM can be reprogrammed from 10 to 20 000 times. Besides. In this case initial information can be completely erased and PROM can be reprogrammed. To do it.56 3 Evolution of Programmable Logic 3. Previous content is deleted by EPROM exposing to ultra-violet light (for several minutes). . AND . such that at least one of the functions yn ∈ Y is equal to 1. 3. . because of it such chips are named EEPROM (Electrically Erasable PROM). chips of PROM find a wide application for implementation of tabular functions. Writing information into an EPROM is about a 1000 times slower than reading from a device. 1 . 3. . In this case PROM can be electrically erased. Thanks to regularity of their structure. . PROMs cannot be used for implementation of SBF satisfying to condition H1 H.5) where H1 is the number of input assignments. Such PLDs are divided into smaller fixed-size blocks that can be reprogrammed independently (erased and programmed). Programmable logic arrays (PLA) were introduced in the mid 1970s by Signetics [61] and they were oriented on implementation of SBF.5) takes place. Such an approach is possible due to usage of floating-gate transistors. 5. In case of PROM such devices are named as Erasable PROM (EPROM). An EEPROM can be erased and reprogrammed without removing from a printed board (as it was necessary for all previous cases). Fig. 4. . These devices are named Flash Memory. As a rule.. q . when condition (3. The main drawback of PROM is doubling of their capacity if the number of inputs is incremented by 1. Reprogramming with erasing of information. that determines greater flexibility than in case of PROM. S OR 1 2 . Because both EPROMs and EEPROMs save their internal data while not powered.. Partial reprogramming.5 Architecture of PLA 1 t .and OR-arrays (Fig. Reprogramming with electrical erasing. they belong to the class of non-volatile memories. (3. the time of erasing should be taking into account. This feature is very useful for reconfiguring a design on-fly. a device should be taking out from a printing board. . Writing information into an EEPROM is about a 500 times slower than reading from a device.5). they are used to keep either a system configuration (if they are internal devices) or to keep some temporary data (if they are external devices). The peculiarity of PLA is programmability of both AND. To get a real value for reprogramming time.

t. but decoder DC is absent. because inputs of all microchips are connected with the same logical conditions X . Let PLA with S inputs. 1. q < H1 . 2. shown in Fig.6) chips of PLA(S. then both abovementioned methods of expansion should be applied simultaneously. q < H1 . 3.6 Implementation of SBF with expansion of PLA terms PLA 1 Y1 OR Y X . More complex synthesis methods are used to implement a SBF Y .4. t outputs and q terms be denoted as PLA(S. where value n1 is determined by (3. q ≥ H1 .t < N. 3.. The structure of resulting circuit is similar to the structure shown in Fig. If S ≥ L. then a logic circuit is implemented with n1 PLA chips. (3.t < N. then the approach of ”expansion of PLA terms” should be used [13.7) In this case a synthesis method depends on condition . If S ≥ L. PLA can be applied to implement SBF represented as minimal sum-of-products [1.t ≥ N. and the structure of this circuit is similar to the structure from Fig. q) and let us discuss how they can be used for implementation of SBF Y (L. 2. and a circuit can be implemented using n4 = H1 q (3. which are listed below. But programmability of AND-array leads to increase of a chip area and decrease of the both resulting circuit speed and value of parameter q in comparison with PROM-implementations [61].t. Implementation of logic circuit in this case (Fig.3. If S ≥ L. then SBF Y is implemented in a trivial way using one PLA chip. 3. 3. Minimization of hardware amount can be made with application of sophisticated design methods [27]. 3. q ≥ H1 .63].t ≥ N. There are the following combinations of SBF and PLA parameters.3. when the following condition holds: S < L. based on the search of some partitions on the set of SBF terms. where PLA should be used instead of PROM. If S ≥ L.1 Simple Field-Programmable Logic Devices 57 Thanks to programmability of both arrays. q). Fig. N.2.2)..6) is similar to one. PLA n4 Yn 4 4. H1 ). 27].

U → min . which is shown in Fig.. . . Let X (Eu ) be a set of logical conditions.58 3 Evolution of Programmable Logic Fmax ≤ L. EU }. and Y (Eu ) be a set of functions depending on the terms Eu ∈ ΠF . (3. which form in the terms from a set Eu ∈ ΠF = {E1 . This disadvantage was eliminated with including of flipflops at each output of PLA inside the chip. X(EU) PLA U Y(E1) OR Y Y(EU) To design the logic circuit. . 3. X Fig. and it is connected with decrease of a resulted digital system performance. |Y (Eu )| ≤ t. The partition ΠF should satisfy to the following condition: |X (Eu )| ≤ S. 3.8) is violated. that practical digital devices are specified by SBF with limited number of terms.8) where Fmax is the maximal number of literals [1] in the terms of SBF Y . If this condition takes place. it should be found a partition ΠF of a set of terms F.U) |Eu | ≤ q. . oriented on solution of the problem (3.9) Many different approaches are known. If a sequential circuit should be implemented. with the minimum number of blocks U [27]. (u = 1. then an initial SBF can be implemented by a single-level circuit. . that PLA allows only the implementation of combinational circuits. (3.7 Single-level implementation of SBF with PLA 1 X(E1) PLA . where condition (3.10) holds. where |F| = H1 . It is known. If condition (3. where |H(yn )| ≤ 16.7. then outputs of PLA should be connected with an external register. that an FSM corresponding to each subgraph can be implemented using only one chip of PLS [27].10) . then an SBF Y is implemented as a multilevel circuit [1].. .9) with minimizing of value U [27]. . Such chips are named registered PLA or programmable logic sequencers (PLS) [61]. (3. Design methods targeted on PLS use a decomposition of initial GSA by subgraphs in such a manner. It is clear. .

3. The peculiarity of PAL is existence of programmable AND-arrays and t fixed ORarrays (Fig. 3. 43. To increase the area of such chips application. which were rather different from designed methods with PLA chips [7. Let us point out.. etc. were oriented on implementation of SBF. which are used as products of SOP of a Boolean function yn ∈ Y . Programmable array logic (PAL) chips. Appearance of EECMOS (Electrically Erasable CMOS) technology permitted very simple reprogramming. .1 Simple Field-Programmable Logic Devices 59 Here H(yn ) is a set of terms. An analysis of this condition shows that PLA have redundancy of connections. . the tristable outputs permit usage of either direct or complement Boolean functions. 56. . Besides. because any term of PLA can be connected with any output of a chip. The growth of the number of PAL inputs results in drastic performance decrease and. that chips of GAL are still manufactured in a standalone packages by Lattice. A typical example of GAL device is the GAL16V8 chip. 55.q .8 Architecture of PAL 1 . 8 outputs and 20 pins. Feedbacks in PAL chip permit to implement the functions with parenthesis [5. Appearance of PAL stimulated development of FSM design methods [1]. some additional elements were added to each output of PAL.8 includes t macrocells. Atmel. This device has 8 input pins and 8 bidirectional input/output pins. which were introduced by Lattice in 1985 [61]. 83].8). 58. 11. . Combining structure of PAL and EECMOS technology results in generic array logic (GAL) chips. 6]. 1 . For example. The connections inside a macrocell were programmable too and it increases flexibility of PAL. .q ORt OR1 . logic gates and multiplexers. it means that these pins can be used either as inputs or as outputs. TI. . enabling FSM implementation without external memory registers. 82. 44. Macrocells have tristate outputs and there is a possibility to use the chip pins as bidirectional input-outputs. S 1 . . the chip shown in Fig. Fig. The macrocell has a feedback path from the output of the cell to the AND-array. The macrocell is a part of a chip connected with a single PAL output. . determining the number of AND-arrays connected with single OR-array [51–55. 74–77]. .10). hence.3. such as flip-flops. which has 16 inputs. 1 t One of the new conceptions connected with PAL was the conception of a macrocell. Macrocells include a programmable embedded flip-flop. satisfying (3. 3. which were introduced by Monolithic Memories in 1978 [61]. in limitations for their usage in practical designs [61]. 9. It results in increase for the number of inputs and outputs of PAL in comparison with a PLA chip of the same size. . Design methods for PAL are oriented on minimizing of the value |H(yn )| up to the some fixed value q.

3. Atmel. PAL. Development of semiconductor technology allowed quite different solution of this problem. it is interesting that different manufactures use different terminology to name the same things. GAL belong to the class of Simple Programmable Logic Devices (SPLD). 1 S .. they have not more than 40 inputs/outputs and they are equivalent not more than 500 NAND-gates with two inputs [69]. the simplified structure of a typical CPLD is shown in Fig. .2 Programmable Logic Devices Based on Macrocells To implement complex logic controllers. For different CPLD vendors. Let us discuss as a typical example a family MAX of Altera [2]. . CPLD EPM5032 includes only single LAB. where acronym MAX stands for Multiple Array Matrix. . Xilinx.. . which can interplay using programmable connections from PIA (Programmable Interconnect Array). Cypress.60 3 Evolution of Programmable Logic Such chips as PLA. like JTAG support and interface to other logic standards. based on EPROM technology. PALI I/OI In this CPLD each macrocell PALi (i = 1. such chips are notable for very big propagation time and very small coefficient of chip area usage [66]. . Lattice manufacture CPLDs [61]. as well as with very large number of macrocells. named LAB (Logic Array Block). Modern CPLDs contain some additional features. . it is necessary to have PAL chips with large number of terms per a macrocell.. Fig. I) is connected with S fixed inputs of a chip and with programmable input/outputs IOi . Now several companies such as Altera. As example of a typical CPLD we can mention the Xilinx XC9500.. 3.9. The block outputs can be used as input information for a switch matrix SM. PLS. The first CPLD were devices MegaPAL of MMI [61]. 3. For example. Such chips belong to the class of CPLD (Complex Programmable Logic Devices). named as system gates [61].9 Simplified architecture of CPLD SM 1 S . This chip includes a term expander ES to share terms among . where PLD resembling a 36V18 GAL device are used. when a single chip includes a collection of simple PAL macrocells connected using programmable connections. Unfortunately. Macrocells of this family are combined in blocks. macrocells have different configurations [61]. Let us choose a family MAX5000. PAL1 I/ O1 .

3.. a matrix of macrocells MCA. and a block of internal interconnections BII... the number of bidirectional input-outputs t from 4 to 16. The first of them is used to connect the macrocell output either with the combination output of PAL or registered output of TT flip-flop. t Link outputs Depending on a chip. and the number of blocks LAB from 1to 12. connected with OR gate.2 Programmable Logic Devices Based on Macrocells 61 different macrocells. and outputs of input-output block I/O.10. The synchronization mode can be either common for all macrocells (Global Clock).10 Architecture of MAX5000 family members 1 . The second multiplexer together with additional AND gate is used to control a synchronization mode of the flip-flop. borrowed from [61]. as well as the AND gate to control both flip-flop TT and macrocell output (Output Enable).11 Architecture of CPLD MAX5000 macrocell S PIA ES I/O Global Clock Output Enable I/O PAL R S D C TT MX Array Clock MX In Fig. outputs of matrix PIA. Fig. The macrocell has the following structure (Fig. the block PAL includes three programmable AND gates. the input number S varies from 8 to 20. 3. Additionally. or local for the given block (Array Clock). an input-output block I/O.11. outputs of block ES. The number of logic blocks LAB is increased with growth of chip complexity. each macrocell includes two multiplexers. 3. This tendency is shown in Fig. . Fig. 3. Internal expanders are used to increase the number of terms implemented by a macrocell..3. S LAB A 1 MCA BII PIA ES Block I/O . There are four types of macrocell inputs: fixed chip inputs (up to S inputs). 3.11).

as well as states of their outputs. the chips of MAX7000S family are based on EEPROM technology and they can replace from 600 to 5000 system gates. some outputs of PTA are used for special purposes. Fig. Each logic block has 36 inputs from ZIA. whereas the number of inputs connected with a block of input-output logic (I/O Logic) can be different for different logic blocks from the same chip. General overview of XPLA3 chip is shown in Fig. having 8 LAB blocks. t = 16 outputs. With development of semiconductor technology. . For MAX5000 family. One of the serious restrictions of CPLD based on PAL macrocells is the limited number of implemented product terms per macrocell. whereas outputs PT[8–15] can be used to organize feedback as outputs of NAND gates. Blocks interconnect through block ZIA (Zero-power Interconnect Array). It restrains application of CPLD in such areas as mobile phones. . Architecture of the logic block is shown in Fig.13.1MHz. . Thus. Logic complexity of a chip is about 2500 system gates. 16). . which can be distributed among 16 OR gates. or the disjunction of any terms from the set PT[0–47] using blocks ORi and V FMi (i = 1. 16). 3. and each block contains 16 macrocells.12. Terms PT[32–47] can be used for synchronization of macrocell flip-flops. The terms of a logic block are generated by a matrix PTA (product term array). For example. having S = 36 inputs. The outputs of OR gates are connected with multiplexers VFM (Variable Function Multiplexer). computer games. the Cool Runner XPLA3 family was introduced by Xilinx. 772 flip-flops. 216 input-outputs. The logic block generates 8 control terms PT[0–7] to asynchronous controlling flip-flops of macrocells MCi (i = 1. having 36 inputs (outputs of ZIA) and 48 terms. their inputs are connected with fixed chip inputs.62 3 Evolution of Programmable Logic The expander block is used for increasing the numbers of terms implemented by the block PAL. . all parameters of CPLD (such as the number of pins. this block includes from 32 to 64 multi input AND gates. For example. Each logic block can be viewed as a PLA block. 3. the number of macrocells and so on) are increased. EMP9560 chip includes 560 macrocells. It is equal to 12000 system gates and operates with maximum frequency up to 118MHz. This family is based on macrocells of PLA type [89]. The CPLD of MAX9000 family are even more complex. where each LAB includes 16 macrocells. .3 V. and personal digital assistances. 3. and outputs of blocks PIA and BII. To overcome this drawback. Inputs of macrocells MCi are connected either with the term PTi + 15.12 Architecture of CPLD XPLA3 family I/O 16 Logic Block I/O Logic PLA Logic Interconnect Array ZIA Logic Block PLA Logic I/O Logic 16 I/O Different CPLD XPLA3 chips include up to 24 logic blocks. . the maximum frequency of its operation is 147. . each logic block is equivalent to a PLA. and q = 48 product terms. The chip can operate with 5 V or 3. The typical representative of this family is CPLD EMP7128S. .

or registered. The bidirectional macrocell input-output is connected with the block ZIA too.3. then macrocell output is set up in the third state using a special control term. fmax is a maximal frequency of operation. The macrocell output can be either combinational. but they are not suitable enough for implementing regular functions. the symbol I stands for the number of macrocells (the number of blocks is obtained automatically. . In this case the combinational output cannot be used as feedback for the block ZIA. The truth table is the best way for presentation of regular functions (and their systems). t p is a propagation time. Table 3. The flip-flop synchronization has 8 modes. which are not used as inputs of ZIA. dividing the number of macrocells by 16). which is used as a feedback signal for the ZIA. The input-output logic allows disconnection of pins. 3. Macrocells based on both PAL and PLA architectures are very efficient in implementing irregular and multiplexer functions.1. G is the number of system (equivalent) gates.5 127 In this table. it means that the best way for implementing .5 127 512 12800 7.5 140 384 9600 7.2 Programmable Logic Devices Based on Macrocells Fig. measured in nanoseconds. The PLAbased macrocells are used in CPLD chips of Cool Runner II family by Xilinx [89].13 Architecture of logic block for XPLA3 family PTA ZIA 36 63 PT[0-7] Control Terms MC1 PT16 PT[0-47] . If this pin is used as an input. or as a latch. . measured in megahertz. this table is based on [89]. including the global clock (system synchronization).1 Characteristics of CoolRunner XPLA3 family Chip XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL I G tp fmax 32 800 5 200 64 1600 6 145 128 3200 6 145 256 6400 7. Important features of the representatives of CoolRunner XPLA3 family are listed in Table 3. PT31 PT[32-47] PT[32-47] PT[8-15] VFM16 VFM1 OR1 MC16 Clock Feedback NAND OR16 Macrocells of CoolRunner XPLA3 family include a memory element configured either as D FF or T FF.

namely for implementation of regular. 40]. was only 20$. LUT elements make a Configurable Logic Block (CLB). Single LUT can implement an arbitrary Boolean function depended on S ≤ 4 input variables and represented as a truth table. the signal ”Select” uses a multiplexer MX and chooses either combinational or register mode of PLB output. based on PAL architecture. Spartan-3. operating in both synchronous or asynchronous modes and having the following characteristics: 8K × 1. They were introduced by designers of Xilinx in 1985 [89]. the LUT-element implements an arbitrary Boolean function y = y(x1 . 3072 macrocells. LUT can be used as a 16-bit shift register.64 3 Evolution of Programmable Logic regular functions is usage of memory blocks (PROM. Besides. each cluster includes an additional block of channel memory with 4K bits. chips of Delta 39K(TM) family include 350000 gates. Typical representatives of FPGA produced by Xilinx are the chips from the Spartan family.14. each LUT element represents a RAM or PROM memory. and 480Kb of RAM.3 Programmable Devices Based on LUT Elements Technology of field-programmable gate arrays (FPGA) is developed simultaneously with technology of CPLD [31. In 2003. . xS ). Together with reconfigurable flip-flops. 2K × 4. These chips are powered by 1. All 10 cluster blocks interplay through a matrix of programmable interconnections PIM (Programmable Interconnect Matrix). Architecture of Delta 39K family includes a collection of clusters. Each logic block includes 16 macrocells.2V and they use the 90-nanometre technology. Taking it into account. the Delta 39K200 chip includes 200000 system gates. named Cluster RAM Blocks (CRB). A simplified architecture of CLB is shown in Fig. these memory blocks can be . Each CRB has 8 Kbit of memory and can be configured as a memory block. having in average 4 inputs. Then. which are based on look-up table (LUT) elements. 4. 4K × 2. Obviously. where each cluster includes 8 logic blocks and 2 blocks of a cluster memory. and 8. irregular.62]. 3. allowing interplay of different clusters. These chips can replace millions 2NAND gates. for example. the number of its outputs can be different. As a rule. 3. they have a propagation time around 7 nanoseconds. each logic block of FPGA is equivalent from 10 to 20 system gates [66].61. namely. it can be equal to 1. the price for chip with 17000 CLBs.and RAM-based macrocells in their Delta 39K family [39. Contrariwise. On the one hand. There is a system of global interconnections. Separate registers can be combined together forming a long shift register chain. and multiplexer functions. 2. This family is characterized by impressive values of parameters. LUT elements are based on RAM. . Consider some representatives of FPGA family produced by Xilinx. and operate with maximum frequency 233MHz. 1K × 8. these chips have effective tools for implementing all kind of Boolean functions. the pulse ”Clock” is used for timing of the flip-flop TT. RAM).59. . which is equivalent to 1000000 system gates. . designers from Cypress use both PAL. In such a circuit. For example.

XCR3000XL (having up to 512 macrocells). They support 23 different input-output standards. Moreover. the symbol I determines the number of macrocells per chip. and Spartan-3 (having up to 5000000 system gates). Spartan. For example.and multimedia systems. Table 3. XC9500XL. and each EAB includes 2048 bits. Some characteristics of Spartan-3 family are shown in Table 3. There are many FPGA families produced by Xilinx [89]: XC9500.3. . the symbol DRAM determines the number of bits when LUT elements are treated as a distributed memory. the chip includes an additional column with 9 embedded memory blocks EAB (Embedded Array Block). . as well as for video. Totally. Virtex E. . The frequency of operation for these chips can be variable (from 25 MHz till 325 MHz).3 Programmable Devices Based on LUT Elements Fig. The second large-scale producer of FPGA chips is Altera [2]. with 18Kb for each of them. these chips include up to 1. Thus. there are 468 blocks LAB arranged as a matrix having 52 columns and 9 rows.2. 3. Virtex. this specific feature enables application of Spartan-3 chips in different fields of digital automatics.2 Characteristics of Spartan-3family Device XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 I G BRAM DRAM 1728 50K 72K 12K 4320 20K 216K 30K 8064 40K 288K 56K 17280 1000K 432K 120K 29952 1500K 576K 208K 46080 2000K 720K 320K 62208 4000K 1728K 432K 74880 5000K 1872K 520K In this table. the symbol G determines the number of system gates per chip. Each LAB block consists from 8 logic elements LE.87Mb in their embedded blocks of RAM (BRAM). Spartan XL. the chip EPF10K70 of FLEX family is equal to 70000 system gates (taking into account embedded blocks BRAM). XC9500XV. The chips of Spartan-3 family include up to 104 memory blocks. Logic of a project is implemented using blocks LAB. the chip possesses up to 18432 bits of RAM. LUT y MX 65 Select Clock D C TT f combined together to create a memory block with an arbitrary configuration.14 Architecture of programmable logic block 1 S . that is the chip 3744 LEs. Typical representatives of its FPGA are chips FLEX10K. the symbol BRAM determines the number of embedded memory blocks. where acronym FLEX stands for Flexible Logic Element MatriX. and Virtex II Pro (having up to 4000000 system gates and up to 4 PowerPC microprocessors). These devices can be reconfigured in 320 milliseconds. Virtex II.

It permits to increase the system performance if calculation of complex combinatorial functions is in need. JK. 1024x2. which includes the global clear signal. The output OLE is connected with the matrix of local interconnect. The register RG can be programmed for D. 3. T. These blocks can be used for implementing parallel multipliers. blocks EAB can be configured as 2048x1. or together with others blocks. sequential circuits (such as FSM). Carry In Cascade In d1 d2 d3 d4 LUT Carry chain Cascade chain OLE MX MX RG Carry Out Logic of RG Cascade Out V1 3 2 V2 Logic of RG Fig. an internal logic represented by inputs d1 and d3 is used. A special block of Clock logic is used to generate synchronization pulses. Technological progress leads to decrease of transistor sizes and. To control the RG (such as clear. and so on. 3. FPGA chips of Cyclone family produced by Altera include up to 20060 logic elements and 288K bits of RAM. blocks EAB can be used for implementing systems of regular Boolean functions. the LAB of Altera corresponds to the CLB of Xilinx). Each block can be used either separately. Elements of the set V2 including global and local synchronization signals are used for synchronizing. For combinatorial functions. These blocks EAB can be viewed as an additional large LUT element. Different representatives of the Cyclone family have from 2910 to 20060 logic elements. 512x4.66 3 Evolution of Programmable Logic Obviously. which can be adjusted to the global chip synchronization.15 Simplified architecture of logic element from FLEX10K family Three variables are connected with an output OLE of the logic element. namely: an input d4 of the LE. Blocks EAB can be used as synchronous blocks RAM. a combinational output of the LUT. or synchronization). where each EAB of FLEX10K family replaces up to 600 system gates. or 256x8 devices. or RS operation. and some additional logic used for organizing adders (carry logic or carry chain) and cascading of functions (cascade chain). Eight logic elements LE and a local interconnect form single block LAB (obviously. to increase of their number in a chip. a programmable flip-flop. the RG is bypassed. . As for Delta 39K.15. or it is controlled by elements of a set V1 . represents up to 100 system gates. each LAB includes 10 logic elements. In these devices. as it is shown in Fig. therefore. Each LE includes one LUT element. or a registered output of a programmable flip-flop RG. having 4 inputs. Each LAB. as well as different devices for signal processing. For example. preset.

Altera.4 Design of Control Units with FPLD 67 The embedded memory is represented by so called M4K RAM blocks. . 3. 12.4 Design of Control Units with FPLD The main problem in design of control units is irregularity of their logic circuits. or decoders. It is necessary to perform the mutual minimization of the system of Boolean functions to be implemented. that is to partitioning an initial logic circuit by subcircuits implemented using one PLA macrocell. Table 3. in contrary to design of operational automata (data-path) having regular structures [5]. CPLD based on PLA macrocells. The subsystems with limited amount of product terms should be found. 40. 67. 4. Appearance of the chips CoolRunner family should renew an interest for development of these design methods. To keep pace with technical progress. but due to rapid technological advance such information is going out of date very quickly. 68]. Let us discuss some of these features. multiplexers.3 Characteristics of Cyclone family Device Number of LE Number of blocks RAM (128x36 bits) Total capacity of RAM. 30. Reduction of combinational part could be reached due to usage of a counter instead of a register to interpret the linear parts of a control algorithm [8. Lattice. 89]. it is important to use models of control units having regular parts. it is necessary to visit the web sites of such FPLD producers as Xilinx. Optimization methods should take into account peculiarities of both logic elements in use and a control algorithm to be implemented. The second problem is lack of universal methods for minimizing the hardware amount in logic circuits of control units. a reader now has some preliminary knowledge about both CPLD and FPGA.27. These blocks are reconfigurable and their outputs can include up to 36 bits (each word has 32 bytes and 4 bytes are used for parity control). Design methods are reduced to modularization an initial logic circuit. the structural decomposition was used.3. Atmel.45].3. Memory blocks operate with frequency up to 250 MHz. In our opinion. It does not permit usage of large library cells. To decrease the hardware amount. bits Number of pins for a user EP1C3 2910 13 59904 104 EP1C4 4000 17 78336 301 EP1C6 5980 20 92160 185 EP1C12 12060 52 239616 249 EP1C20 20060 64 294912 301 Examples of different representatives of FPGA family can be continued. Cypress [2.31. In this case some part of a logic circuit can be implemented using such library cells as memory blocks. each of them includes 4K bits of memory. 59. it allows usage of multiplexers and PROM chips jointly with PLA modules [27]. Thus. 1. Design methods target in PLA can be found in [1. Some characteristics of Cyclone family are shown in Table 3. 9.

(3. 58. 37. Fig. 49. I) gives an initial set X . Let us point out that the decomposition is executed in such a manner that each from the functions Gi (i = 0. 61. . 3. Some methods targeted on structural decomposition leading to combined use of PAL chips together with PROM chips [14–21. Otherwise. . . could be implemented by a single LUT element. 72. It is desirable that the number of terms in the SOP of a Boolean function does not exceed the number of product terms per a macrocell. Finally. Also.16.11) In (3. 86]. The design methods have been developing starting from the first announcement about appearance of PAL chips [3. . or logic expanders should be used. some methods are developed. 48. there are coding functions Gi and a base function F. either the macrocell cascading should be executed. GI XI H F In such a representation. 51–56. 41. . EMBs and counters for interpretation of linear parts of control algorithms [10. unification of the sets Xi (i = 0. a group of methods deal with LUT elements. 37. It is based on representation of a Boolean function F = F(X) in the following form: F(X ) = H(X0 . 29. 82–84].78]. . . . G1 (X1 ). 72–74].. 28]. Design methods are developed permanently taking into account features of particular FPGA families (a practical approach). 31. Design methods are reduced to the separate minimization of functions representing a logic circuit of a control unit. I). 42. 3. Now such methods can be used in designs connected with CPLD Delta 39K family by Cypress. 60. as well as the abstract conception of FPGA (a theoretical approach) [31. 13. 31. . as it is shown in Fig. CPLD based on PAL macrocells.16 Illustration of the principle of functional decomposition X X0 X1 G1 . The principle of functional decomposition is the base for designing logic circuits with FPGA [33.11).. 22–26.72. Consider the method of functional decomposition in more details. as well as the function H.73. . . 86–88].70. FPLD based on LUT elements. Both approaches lead to slowdown of a resulted design. It is shown in [56] that optimization methods targeted on FPGA . GI (XI )). the functional decomposition can be used under the design of control units with CPLD [48]. 32. Besides. 3. which are targeted on the joint use of LUT elements and embedded memory blocks [33.68 3 Evolution of Programmable Logic 2. . Methods of digital devices design with FPGA significantly distinguish from their counterparts targeted on CPLD.

then previous steps of design process should be repeated to get some new results. Both VHDL and Verilog are the most popular HDLs [35. where the actual values of delays among the physical elements of the chip are used. This step is named a mapping. 91]. A design entry can be executed using the schematic editor (a design is represented by some circuit). Project verification. Chip programming. Obviously. such steps as placement and routing are executed. 3. The library cells from system and user libraries are used during this step. 66. Now the Netlist is translated into an internal format of CAD system and such physical objects as CLBs and chip pins are assigned for initial logic elements. 38. It allows finding out the real values of propagation times for an FPGA chip selected for implementation of a project with the control unit. Logic synthesis. then the previous steps should be repeated. The exceptional complexity of both CPLD and FPGA chips requires use of computer-aided design (CAD) tools for designing control units [49. as in case of FPGAbased designs. The final outcome of this step is some data used to program a chip named as BitStream. 50. Implementation of control units with CPLDs is as difficult. Implementation of logic circuit. For example. Thus. It assumes development of formal methods for synthesis and verification of control units [5. After such a verification. If outcome of this step is negative (actual performance of control unit is less than it is needed).86] show that decrease for amount of terms in SBF of control units yields in reduction of the number of LUT elements in logic circuits of these control units. or the state editor (a design is represented by a state diagram). 36. 31.3. the package FPGA Express executes synthesis and optimization of a control unit logic circuit. 6. 71]. 61]. The file can be represented using either EDIF or XNF formats. An initial specification should be verified using procedures of syntax and semantic analysis. 46.4 Design of Control Units with FPLD 69 can decrease hardware amount in logic circuits with CPLD. The step of simulation is executed without taking into account real propagation times in a chip. or some program written on a hardware description language (HDL). As an outcome. The functional correctness of a control unit is checked during this step. for example. 47. Results of the investigations described in [37. the initial specification can be corrected and this step should be repeated. Each producer of FPGA and CPLD chips has its own CAD to support the design process. that step is connected with writing a final bit stream into the chip. a design process for FPLD from Xilinx includes the following steps: 1. Simulation. 64. Next. The most known packages are. it is reasonable to develop optimization methods targeted on some particular logic elements and then to check their usability for different types of FPLD chips. Specification of a project. . 2. Now there are physical elements and connections among them. 4. The final simulation is performed. 5. MAX+PLUS. 85. During this step. If an outcome of simulation is negative. an FPGA Netlist file is generated with a list of chains for a control unit to be implemented.

WebPack. As a rule. In our book. there are CAD tools of some producers specialized only on synthesis and verification. the highest performance belongs to a single-level model (Fig. Let us denote it as a P FSM. Leonardo Spectrum. 6] or structure tables are used for specification of control units.or PLA-based macrocells (if a circuit is implemented using CPLDs). Łuba. But the P FSM is the single-level model because it includes only single block of .70 3 Evolution of Programmable Logic MAX+PLUSII. where can be found various methods for design and optimization of control units. A design system DEMAIN [60. The well-known system MIS [34] is a base for development of the SIS. A special algorithm STAMINA is used for minimizing the number of states. 77]. because of it we use only the symbol PLD (Programmable Logic Device) in logic circuits for discussed examples. or for a group of PAL. QuartusII. such as ASYL [76. targeting in designs of compositional microprogram control units with FPGA [86]. A block BP of P FSM can include more than one layer of logic elements. which can be used to derive the systems of Boolean functions specified some parts of logic circuit of a control unit. executed minimization of logic functions by appropriate state assignment. Among all known models of control units. Synopsis FPGA Compiler II and so on. all presented methods are accompanied by examples. This symbol can stand either for a group of LUT elements (if FPGAs are used to implement a circuit).17). represented in the KISSII format. 3. To compare design outcomes for different CAD. or ZUBR. there is a lot of different academic CAD tools. As a rule. Some other academic systems are known. it depends on both complexity of a control algorithm to be interpreted and parameters of logic elements in use. Information about these tools can be found on the sites of corresponding producers. Some of them are free of charge and can be obtained through Internet. some intermediate software should be developed to connect academic and industrial tools. whereas the second form is very close to the KISSII format. such as Symplicity Amplify Physical Synthesis Support. then the state assignment is executed by an algorithm JEDI. The system generates some preliminary data used by the MAX+PLUSII of Altera. We escape from particular types of microchips. 73] is developed in Poland (Politechnika Warczawska) by Professor T. The set contains practical examples of sequential circuits. For example. The intermediate software allows entering either Boolean systems describing some parts of control units or VHDL-models of these parts. the system SIS from Berkeley. Besides. as well as ATOMIC. If control units are implemented with FPGA. The language is an entry to the program ESPRESSO. The base of the system is a set of algorithms target on decomposition of a system of Boolean functions describing a combinational part of a control unit. USA [79. a standard set of tests (benchmarks) [90] is used. either graph-schemes of algorithms [5. This system deals with FPGA-based designs. targeting in designs with PLA and ROM. Besides. The examples are completed by some tables. 80] has tools for singlelevel and multi-level design of digital devices. We do not discuss the particular problems of logic circuit implementation using some specific chips. targeting in designs with CPLD [82]. This system uses a special language KISS to specify a control unit. Its counterpart for PLA case is an algorithm NOVA. The first form gives clearness of presentation.

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as well as different methods of encoding of collections of microoperations (maximal encoding and encoding of the classes of compatible microoperations). Fig. 2. the main advantage of whose is possibility of standard library cells use for implementation of logic circuits for some blocks of an FSM model. The main part of the chapter is devoted to joint application of these methods. it replaces logical conditions xl ∈ X by additional variables pg ∈ P. The chapter is devoted to the hardware amount reduction in the logic circuit of Mealy FSM.8) and implements the following systems: A. For example. c Springer-Verlag Berlin Heidelberg 2009 springerlink.1). 4. Standard decoders can be used in case of encoding of the classes of compatible microoperations.com .Chapter 4 Optimization for Logic Circuit of Mealy FSM Abstract. pp. Titarenko: Logic Synthesis for FSM-Based Control Units. A block BP replaces the matrices M7 and M8 (Fig. 77–102. Next. 4. Each of these methods produces double-level circuit of Mealy FSM. 2.1 Structure diagram of MP Mealy FSM X BM P BP RG Start Clock T Y In MP Mealy FSM. whereas the encoding of collections of microoperations permits to use embedded memory blocks. The methods of logical condition replacement are analyzed. 4. It increases FSM logic circuit regularity and leads to simplification of its design process. the logical condition replacement allows application of multiplexers. LNEE 53.1 Synthesis of FSM with Replacement of Logical Conditions Usage of the logical condition replacement transforms P Mealy FSM shown in Fig.8. 3. a block BM replaces the matrices M5 and M6 shown in Fig.17 into MP Mealy FSM (Fig. the methods of structure table rows encoding are discussed. Barkalov and L.

3) generated by the block BM. For example.2) (4.16). Thus. This table is the base for deriving of system (4. (4. Implementation of systems (4. Construction of transformed structure table for MP Mealy FSM.3).3). The synthesis method for MP Mealy FSM includes the following steps [2]: 1. in the case of FSM S9 this system is the following one: p1 = (A2 ∨ A7 )x1 ∨ (A5 ∨ A6 ∨ A8 )x5 ∨ A10 x9 . it is enough G = 3 variables pg ∈ P to replace the logical conditions xl ∈ X . L = 9 logical conditions. The transitions for states am ∈ A depend on logical conditions forming the following subsets of the initial set of logical conditions X: subsets X(a1 ) = X (a4 ) = X(a9 ) = 0 (unconditional jumps).1) – (4. (4. some subtable of transformed structure table for the state a5 of the Mealy FSM S9 is shown in Table 4.2) are irregular and they are implemented using basic PLD cells. X (a8 ) = {x5 x8 }. T ). the table for logical condition replacement includes G = 3 columns and 10 rows (Table 4. Construction of table for replacement of logical conditions. In this case the column Xh of initial structure table is replaced by the column Ph .1) (4.2).1).1. and N = 8 microoperations. The principle of logical condition replacement was discussed in Chapter 2.3. p3 = (A2 ∨ A6 ∨ A10 )x3 ∨ A3 x5 ∨ A7 x7 ∨ A8 x8 . 2. X (a7 ) = {x1 x7 }.4) As it was mentioned a bit earlier. Analysis of system (4.3) using PLD cells. the transformed structure table of MP Mealy FSM is constructed from its initial structure table. shows that system (4. functions (4. functions pg ∈ P belong to the class of multiplexer functions and multiplexers can be used for their implementation.1) – (4. Let us discuss application of this method for optimization of the Mealy FSM S9 represented by its structure table (Table 4.5) . 3. T ). T ). depended on terms Fh = Am Ph . The functions of these systems depend on variables P = P(X. X(a6 ) = {x3 x5 x6 }. For our example. X (a1 0) = {x3 x9 } (conditional jumps).1) and (4. p2 = (A2 ∨ A5 )x2 ∨ A3 x4 ∨ A6 x6 .3) uses only direct values of logical conditions. X (a5 ) = {x2 x5 }. As follows from Table 4. Φ = Φ (P.2). (4. Let us point out that multiplexers are standard library cells implemented from basic cells of PLD in use and their usage accelerates the design process for the logic circuit of a control unit. represented as (2.78 4 Optimization for Logic Circuit of Mealy FSM Y = Y (P. the Mealy FSM S9 has M = 10 states. Therefore. The transformed structure table is used for deriving systems (4. and X (a2 ) = / {x1 x2 x3 }. Obviously.

2 Table for logical condition replacement of FSM S9 am a1 a2 a3 a4 a5 p1 – x1 – – x5 p2 – x2 x4 – x2 p3 – x3 x5 – am a6 a7 a8 a9 a10 p1 x5 x1 x5 – x9 p2 x6 – – – – p3 x3 x7 x8 – x3 Table 4.1 Structure table of Mealy FSM S9 am a1 a2 K(am ) 0000 0001 as a2 a3 a4 a3 a5 a2 a3 a5 a6 a3 a5 a6 a2 a5 a7 a8 a8 a9 a10 a3 a9 a1 a10 a1 a2 a6 K(as ) 0001 0010 0011 0010 0100 0001 0011 0100 0101 0010 0100 0101 0001 0100 0110 0111 0111 1000 1001 0010 1000 0000 1001 0000 0001 0101 Xh 1 x1 x2 ¯ x1 x2 x1 x3 ¯ x1 x3 ¯ ¯ x4 x4 x3 ¯ x4 x3 ¯ ¯ 1 x2 x2 x5 ¯ x2 x5 ¯ ¯ x3 x6 x3 x6 ¯ x3 x5 ¯ x3 x5 ¯ ¯ x1 x7 x1 x7 ¯ x1 ¯ x5 x5 x8 ¯ x5 x8 ¯ ¯ 1 x9 x9 x3 ¯ x9 x3 ¯ ¯ Yh y1 y2 D1 y2 y3 y5 y6 y3 y1 y9 y5 D1 y1 y3 y5 y1 y6 D1 y2 y3 y7 y1 y8 y2 D1 y3 y1 y2 – y2 D1 y6 y1 y8 y5 y1 y3 y6 79 Φh D4 D3 D3 D4 D3 D2 D4 D2 D4 D2 D2 D4 D3 D2 D2 D4 D4 D2 D2 D3 D2 D3 D4 D2 D3 D4 D1 D1 D4 D3 D1 – D1 D4 – D4 D2 D4 h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a3 0010 a4 a5 0011 0100 a6 0101 a7 0110 a8 0111 a9 a10 1000 1001 Table 4.1 Synthesis of FSM with Replacement of Logical Conditions Table 4.3 Fragment of transformed structure table for MP Mealy FSM S9 am a5 K(am ) 0100 as a3 a5 a6 K(as ) 0010 0100 0101 Ph p2 p2 p1 ¯ p2 p1 ¯ ¯ Yh y1 y3 y5 y1 y6 Φh D3 D2 D2 D4 h 10 11 12 .4.

To design the logic circuit of the block BM. having R control inputs and 2R data inputs. 4. For all multiplexers. 4. 2. If a variable pg ∈ P replaces a logical condition xl ∈ X for a state am ∈ A. 4.80 4 Optimization for Logic Circuit of Mealy FSM In our example. Using these terms. the table of replacement corresponds to G tables. it is enough to replace states am ∈ A by their codes in the table of logical condition replacement.2. then this logical condition is connected with data input of multiplexer MXg . Each function pg ∈ P corresponds to one multiplexer MXg . and only 6 for MX3 .2. 3. whereas only 4 for MX2 . and F12 = A5 p2 p1 . the block BM includes three multiplexers (Fig. As follows from Fig. y5 = F11 . where each table determines one of the multiplexers MXg .2) and Table 4. activated by the state code K(am ). only 6 from available 16 data inputs of the multiplexer MX1 are used (they are connected with logical conditions). x1 T1 T2 T3 T4 1 2 3 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MX1 P1 x2 x4 T1 T2 T3 T4 1 2 3 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MX2 P2 x3 x4 T1 T2 T3 T4 1 2 3 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MX3 T P3 x3 x7 x8 x9 x2 x6 x5 x5 x1 x5 x9 Fig. Thus.3: y1 = F10 ∨ F11 . only 37% from potentials of both multiplexers MX1 and . D2 = F11 ∨ F12 . control inputs are connected with state variables Tr ∈ T of Mealy FSM. F11 = A5 p2 p1 .2). y6 = D4 = F12 . The following approach can be used to implement the block BM: 1. After such a changing. 4.2 Circuit of block BM for MP Mealy FSM S9 There is obvious correspondence between the block BM (Fig. ¯ ¯ ¯ ¯ ¯ ¯ where A5 = T1 T2 T3 T4 . the following parts of SOP can be derived from Table 4. y3 = D3 = F10 . there are the terms F10 = A5 p2 . For the MP Mealy FSM S9 .

3). . Binary codes of states am ∈ AC should correspond to decimal equivalents from zero (for the state a1 ) till MC − 1. 2. Encode states am ∈ A as it shown in the Karnaugh map (Fig. that sets X (am ) = 0 for states / am ∈ AC . whereas only 25% is used for MX2 . 67% out of all data inputs is used. In this case. Multiplexer state encoding. Remained codes are used for states am ∈ AU . whereas X (am ) = 0 for states am ∈ AU .4. 4]: 1. In average. 4 out of 8 inputs). 4.1 Synthesis of FSM with Replacement of Logical Conditions 81 MX3 are used.4. 3. Let us split the set of states A on classes AC and AU in such a manner. only 33% of available data inputs are used. which belong to the methods of object code transformation indextransformation of!object codes.5) should be used. State code transformation into multiplexer state codes. now it is used 6 from 8 data inputs of both MX1 and MX3 (75% of data inputs). To increase the rate of data inputs’ usage. a5 . The following methods can be used to solve this problem [2.3 Multiplexer state codes for MP Mealy FSM S9 T3T4 00 T1T2 00 01 11 10 01 11 10 Now the states am ∈ AC correspond to the part of Karnaugh map with T4 = 0. As it follows from Fig. For the FSM S9 . It means that all multiplexers of the block BM for FSM S9 have three control and eight data inputs per a multiplexer. a3 . If a method of state encoding in use targets on the hardware decrease for the block BP. State code transformation into codes of logical conditions. 4. In both models of FSM. and they can be coded in an arbitrary order. a2 . a10 } and AU = {a4. Let the model of Mealy FSM with transformation of state codes into multiplexer state codes be denoted as MPC Mealy FSM. Thus. the sets AC = {a1 . where MC = |AC |. 4. . The value of parameter MC gives the number of data inputs for multiplexers of the block BM. a8 . that gives MC = 8. It generates some additional variables zr ∈ Z used as control inputs of multiplexers of the block BM. whereas the symbol MPL denotes FSM with transformation of state codes into codes of logical conditions. the initial state a1 always / belongs to the set AC . Let us discuss the main idea of the multiplexer state coding. whereas only 50% out of data inputs is used for MX2 (that is. states am ∈ A are encoded to solve some other problems distinguished from . it is necessary to decrease the number of control inputs per a multiplexer. a special state code transformer CCS (Fig. 4. it is reasonable to use the methods from second group. Besides. . . that is a very poor outcome. Fig. therefore these states are determined by variables T1 – T3 . a9 } can be found.

there are MC = 7. 4. RC = 3. the initial state a1 ∈ A is included into the set AC if and only if (iff ) X (a1 ) = 0. z2 .5 Structural diagram of Mealy FSM with state code transformer X BM P BP Y RG Start Clock T ccs Z the hardware optimization for the block BM. Coding of states am ∈ AC by multiplexer binary codes C(am ) with RC bits. Implementation of the block CCS using given logic elements. . where RC = log2 MC .4 Block of logical condition replacement for MP Mealy FSM S9 with multiplexer state coding 4 Optimization for Logic Circuit of Mealy FSM x1 T1 T2 T3 1 2 3 0 1 2 3 4 5 6 7 MX1 P1 x2 x4 x2 x6 T1 T2 T3 1 2 3 0 1 2 3 4 5 6 7 MX2 P2 x3 x 5 T1 T2 T3 1 2 3 0 1 2 3 4 5 6 7 MX3 T P3 x3 x7 x8 x3 x5 x1 x5 x9 Fig. . . such that the multiplexer MXg (g = 1. 2. Let A(MXg ) be a set of states. 4. Coding can be executed in an arbitrary order.82 Fig. z3 }.6) . Construction of a table for code transformer CCS. It means that states are encoded using the variables from the set Z = {z1 . though its outcome can decrease the number of control inputs for some multiplexers. 3. In the discussed case. . / The synthesis method for MPC Mealy FSM includes the following additional steps: 1. G) (4. In both cases.

If a PROM-based implementation is not possible due to absence of free resources of a chip in use. z3 . For the FSM S9 . the following set A(MX2 ) = {a2. C(am ). C(a8 ) = 101. and C(a10 ) = 110. . a5 .1 Synthesis of FSM with Replacement of Logical Conditions 83 transforms logical conditions determining transitions from these states.4. 4. Fig. while both MX1 and MX3 only 75%. then this table is used to derive the following SOP represented the system Z = Z(T ): zr = ∨ Cmr Am m=1 M (r = 1.6 Block BM for MPC Mealy FSM S9 x1 Z1 Z2 Z3 1 2 3 0 1 2 3 4 5 6 7 MX1 P1 x2 x4 x2 x6 Z2 Z3 1 2 0 1 2 3 MX2 P2 x 3 x5 Z1 Z2 Z3 1 2 3 0 1 2 3 4 5 6 7 MX3 Z P3 x3 x7 x8 x3 x5 x1 x5 x9 In this circuit. 4. The table of code transformer CCS includes columns am .7) . a6 } can be found. The column Zm includes variables zr ∈ Z. C(a7 ) = 100. (4. the multiplexer MX2 uses 100% of its data inputs. . average use of data inputs is increased up to 83%. a3 . C(a3 ) = 001. . RC ). Therefore.6). Obviously. In this table. Zm . this table (Table 4. the code K(am ) is used as an input of the block CCS. In the discussed case. equal to 1 in the code C(am ).4) includes M = 10 rows. . the best way for implementation of this table is use of a PROM chip having R inputs and RC outputs. C(a6 ) = 011. Now the states am ∈ A(MX2 ) are determined by the variables z2 . whereas the code C(am ) is its output. m. it is connected with introduction of the code transformer CCS consuming some area of a chip. Of course. Let us encode the states of FSM S9 using the following multiplexer codes:C(a2 ) = 000. it yields in the following circuit for the logical condition replacement (Fig. such that it is enough two variables for its components encoding. C(a5 ) = 010. K(am ).

84 4 Optimization for Logic Circuit of Mealy FSM Table 4.4 Table of code transformer CCS for FSM S9 am a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 K(am ) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 C(am ) 000 001 010 – 011 100 101 110 – 111 Zm – z3 z2 – z2 z3 z1 z1 z3 z1 z2 – z1 z2 z3 m 1 2 3 4 5 6 7 8 9 10 In (4. We do not discuss the problems of logic circuits’ physical realization. 4.7) can be minimized. Obviously. . all examples discussed here are ended by construction of some tables describing blocks of FSM and corresponding systems of Boolean functions. The first approach is applied if PLA -based macrocells are used. G). Depending on logic elements in use.8. . . . such an approach is applied for any system of Boolean functions. either joint or separate minimization should be carried out for the system. let us point out that Cmr = 1. let us just remember about it. the symbol MX shows that multiplexer functions are implemented. 4. the variable Cmr ∈ {01}. Remind. the following form can be derived from the Karnaugh map shown in Fig. Let X (Pg ) be a set of logical conditions from the column Pg (g = 1. the symbol PLD corresponds to implementation of irregular functions. where Lg = |X(Pg )|. it is enough . It is quite enough to start using of commercial CAD. . in reality only LUT elements (or PAL macrocells) are used to implement logic circuits for multiplexer and irregular functions.7) . . . Obviously. system (4. In this circuit.7 Karnaugh map for function z1 T3T4 00 T1T2 00 01 11 10 0 01 0 11 0 10 0 The logic circuit of MPC Mealy FSM S9 is shown in Fig. For example.7: z1 = T2 T4 ∨ T2 T3 ∨ T1 T4 . RC ). . iff the bit r of the code C(am ) is equal to 1 (r = 1. 4. whereas the symbol PROM informs about implementation of regular functions. Fig. Obviously. Obviously. whereas the second one targets on PALimplementation.

1 Synthesis of FSM with Replacement of Logical Conditions Fig.4. L2 = 3. we can get the following sets: X (p1 ) = {x1 x5 x9 }. x7 . . Additionally. X(p2 ) = {x2 x4 x6 }. It gives R1 = R2 = R3 = 2 and RL = 6.9) variables. forming a set Z. z6 }.8) variables to encode the logical conditions xl ∈ X (Pg). . . Structural diagrams are the same for both MPL and MPC models of Mealy FSM. X (p3 ) = {x3 . For the FSM S9 . . The method of state code transformation into the codes of logical conditions is based on replacement of state variables Tr ∈ T by variables zr ∈ Z. . . L3 = 4. x5 . the design method for MPC Mealy FSM includes the step of encoding of logical conditions by some binary codes Kg (xl ). . Let us denote such an FSM as MPL Mealy FSM. To encode the logical conditions xl ∈ X it is enough RL = R1 + . + R G (4. L1 = 3.5. Let us encode the logical conditions for FSM S9 as shown in Table 4. x8 }. Z = {z1 .8 Logic circuit of MPC Mealy FSM S9 19 20 12 21 22 23 24 25 y1 y2 y3 y4 y5 y6 y7 y8 D1 D2 D3 D4 85 x1 x2 x3 x4 x5 x6 x7 x8 x9 0 1 1 1 2 2 5 3 3 5 4 4 1 5 5 5 6 9 7 6 14 1 7 15 2 16 8 3 MX1 P1 1 2 3 4 5 6 7 PLD 0 1 2 3 4 5 6 z1 14 7 z2 15 14 1 z3 16 15 2 16 3 Start 17 Clock 18 0 3 1 3 2 3 3 4 7 5 8 6 3 7 14 1 15 2 16 3 9 T1 10 2 T2 11 4 2 T3 12 6 T4 13 1 2 3 4 5 6 7 8 9 10 11 12 22 23 24 25 10 11 12 13 MX2 22 P2 20 23 D1 D2 24 D3 25 D4 17 R 18 C 10 11 12 13 D1 D2 D3 D4 RG T 1 1 2 T2 3 T3 4 T4 PROM z 1 1 2 z2 3 z3 14 15 16 MX3 P3 21 Rg = log2 Lg (4. where |Z| = RL . 4.

9 Logic circuit of block BM for MPL Mealy FSM S9 x1 x5 x9 Z1 Z2 1 2 0 1 2 3 MX1 P1 x2 x4 x6 Z3 Z4 1 2 0 1 2 3 MX2 P2 x3 x5 x7 x8 Z5 Z6 1 2 0 1 2 3 MX3 Z P3 To implement the logic circuit for the block CCS. . For the MPL Mealy FSM S9 . K1 (xl ). namely: .9). 4. 4. KG (xl ).6. . 4.86 4 Optimization for Logic Circuit of Mealy FSM Table 4. K(am ). Zm . it is necessary to construct a corresponding table with columns am . m. this block is specified by Table 4. . Fig. . Logic circuit of MPL Mealy FSM can be implemented in the same way as it is done for MPC Mealy FSM.2 Synthesis of FSM with Encoding of Collections of Microoperations Two different approaches are possible under encoding of collections of microoperations.5 Codes of logical conditions for MPL Mealy FSM S9 X(p1 ) x1 x5 x9 – z1 0 0 1 1 z2 0 1 0 1 X(p2 ) x2 x4 x6 – z3 0 0 1 1 z4 0 1 0 1 X(p3 ) x3 x5 x7 x8 z5 0 0 1 1 z6 0 1 0 1 The logic circuit of block BM for the MPL Mealy FSM S9 is implemented using three multiplexers (Fig.

4.3) and (2. A block BY replaces matrices M9 and M10 (Fig. the logic circuit of block BY can be implemented using either PROM or RAM chips. Due to regularity of system (2. (4.6 Specification of block CCS for MPL Mealy FSM S9 am a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 K(am ) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 K1 (xl ) – 00 – – 01 01 00 01 – 10 K2 (xl ) – 00 01 – 00 10 – – – – K3 (xl ) – 00 01 – – 00 10 11 – 00 Zm – – z4 z6 – z2 z2 z3 z5 z2 z5 z6 – z1 m 1 2 3 4 5 6 7 8 9 10 87 1.22) respectively. where Rk = log2 (Nk + 1) . . Collections Yt ⊆ Y are encoded by binary codes K(Yt ) having minimal bit capacity R3 . then microoperations yn ∈ Y k are encoded by binary codes K(yn ) having Rk bits.11). a block BP corresponds to matrices M11 and M12 (Fig. y j ∈ Y are compatible.17 into PY Mealy FSM (Fig. microoperations yi . determined by (2.11) . it generates data-path microoperations represented as (2. it generates functions Φ and Z determined by expressions (1. Fig. The set of microoperations Y is divided by the classes of compatible microoperations [2] and represented as Y = Y 1 ∪ . iff they do not written in the same operator vertex of an interpreted GSA [3]. ∪Y K . 2.2 Synthesis of FSM with Encoding of Collections of Microoperations Table 4. Let Nk = |Y k |. 2.10 Structural diagram of PY Mealy FSM X BP T Z BY Y RG Start Clock For PY Mealy FSM.23).21). This approach turns P Mealy FSM shown in Fig.10). 2.10) Remind.4. .23). 3. (4. 4.11).

11. K). y8 }. where Y1 = {y1 . It turns P Mealy FSM into PD Mealy FSM [2] with the structural diagram shown in Fig. .11). To encode the microoperations. (4. K).13) After encoding. . H). . . it is enough R3 = 3 variables zr ∈ Z for encoding of these collections. . . replacing the column Yh from the initial structure table. . . j ∈ {1. there are T0 = 8 collections of microoperations. the transformed structure table includes the column Zh . y9 }. The variables zr ∈ Z k are used for encoding of microoperations yn ∈ Y k . . 1. Y K = Y (Z K ). K(Y8 ) = 111. Y7 = {y7 . . The column Zh contains variables zr ∈ Z.7. represented by its structure table (Table 4. 4. . Let us encode collections Yt ⊆ Y in a trivial way: K(Y1 ) = 000. Encoding of collections of microoperations. 4. ∪ Z K . it is enough RD = R1 + . . . Y5 = {y2 . Y6 = {y7 }.14) .21).88 4 Optimization for Logic Circuit of Mealy FSM If interpreted GSA includes some collections of microoperations without representatives of the class k.11 Structural diagram of PD Mealy FSM X BP T Z BD Y RG Start Clock Let us discuss an example of synthesis for the PY Mealy FSM S10 . Y8 = 0. . + R K (4. i. As / follows from (2. Y3 = {y4 . y2 }. As it can be found from Table 4. equal to 1 for the code K(Yt ) from the row h of the initial structure table (h = 1. having Rk inputs and Nk outputs (k = 1. / (4. then 1 is added to Nk in (4. . y5 }. Y2 = {y3 }.7). Fig. 2. the system Y can be represented as the following collection of systems: Y 1 = Y (Z 1 ). Microoperations yn ∈ Y k are generated by a decoder DCk . . . . Construction of transformed structure table. . Y4 = {y6 . let us point out that Z i ∩ Z j = 0 (i = j. . The totality of these decoders forms a block BD. As it was mentioned in Chapter 2. y7 }. .12) variables forming a set Z = Z 1 ∪ . . .

which can be represented as the following one: .4.8.22) is constructed.8 Transformed structure table of PY Mealy FSM S10 am a1 K(am ) 000 as a2 a3 a4 a3 a5 a6 a2 a1 a6 a2 a3 a1 a5 a1 K(as ) 001 010 011 010 100 101 001 000 101 001 010 000 100 000 Xh x1 x1 x2 ¯ x1 x2 ¯ ¯ x3 x3 ¯ 1 x2 x2 x3 ¯ x2 x3 ¯ ¯ x1 x2 x1 x2 ¯ x1 x3 ¯ x1 x3 ¯ ¯ 1 Zh – z3 z2 – z3 z2 z3 z1 – z1 z3 z2 z1 z2 z1 z2 z3 z3 – Φh D3 D2 D2 D3 D2 D1 D1 D3 D3 – D1 D3 D3 D2 – D1 – h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a2 a3 a4 001 010 011 a5 100 a6 101 Using the transformed structure table. the transformed structure table is represented by Table 4. Table 4. system (2.7 Structure table for Mealy FSM S10 am a1 K(am ) 000 as a2 a3 a4 a3 a5 a6 a2 a1 a6 a2 a3 a1 a5 a1 K(as ) 001 010 011 010 100 101 001 000 101 001 010 000 100 000 Xh x1 x1 x2 ¯ x1 x2 ¯ ¯ x3 x3 ¯ 1 x2 x2 x3 ¯ x2 x3 ¯ ¯ x1 x2 x1 x2 ¯ x1 x3 ¯ x1 x3 ¯ ¯ 1 Yh y1 y2 y3 D1 y5 y1 y2 y3 y6 y7 y2 y8 y1 y2 y7 D1 y5 y7 y9 – y3 y1 y2 89 Φh D3 D2 D2 D3 D2 D1 D1 D3 D3 – D1 D3 D3 D2 – D1 – h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a2 a3 a4 001 010 011 a5 100 a6 101 For the FSM S10 . Obviously. the number of rows for both tables is the same.2 Synthesis of FSM with Encoding of Collections of Microoperations Table 4. only contents of some columns are different.

the following SOP y2 = Z1 ∨ Z5 = z2 z3 can be derived from Table 4. . the following equation can be derived from Table 4. 4.15) In expression (4. This block is represented by a table reflected the dependence of microoperations from variables zr ∈ Z. The logic circuit of PY Mealy FSM S10 is shown in Fig. R3 ). there are the following values and sets: R1 = 2.9 Specification of block BY PY Mealy FSM S10 z1 0 0 0 0 1 1 1 1 z2 0 0 1 1 0 0 1 1 z3 0 1 0 1 0 1 0 1 y1 1 0 0 0 0 0 0 0 y2 1 0 0 0 1 0 0 0 y3 0 1 1 0 0 0 0 0 y4 0 0 1 0 0 0 0 0 y5 0 0 1 0 0 0 0 0 y6 0 0 0 1 0 0 0 0 y7 0 0 0 1 0 1 1 0 y8 0 0 0 0 1 0 0 0 y9 0 0 0 0 0 0 1 0 If the logic circuit of block BY is implemented using some macrocells.9) and can be used for programming of PROM. y8 }. y7 }. H). . iff yn ∈ Yt . . R2 = 2. . . y4 . z6 }. R3 = 2. . y6 . the Boolean variableCnt = 1. let us discuss the example of logic synthesis for PD Mealy FSM S11 .90 H 4 Optimization for Logic Circuit of Mealy FSM zr = ∨ Crh Am Xh h=1 (r = 1. Z 2 = {z3 . For example. then system Y (Z) is represented as the following SOP: yn = ∨ Cnt Zt t=o T0 (r = 1.9 (after minimization). R3 ). Y 3 = {y3 . . So. . iff the variable zr presents in the row h of transformed ST(h = 1. represented by its structure table (Table 4. which are programmed for some CAD systems. z6 }. . For example.16). Specification of block BY. This step is executed using rather complex combinatorial algorithms [1]. This table is constructed in a trivial way (Table 4. z4 }. ¯ ¯ Logic circuit of PY Mealy FSM is implemented on the base of these tables (and derived systems of minimized Boolean functions). For example. (4.15). . the following SOP z1 = F7 ∨ F8 ∨ F11 ∨ F12 can be derived from Table 4. a Boolean variable Crh = 1.8. and Z = {z1 . . Partitioning of the set of microoperations by classes of compatible microoperations. Now. z2 }. (4.16) In (4. Table 4. . Z 1 = {z1 . . For FSM S11 .3) is used for designing the block BP too. . it is easy to get three following classes: Y 1 = {y1 .10). 3. Y 2 = {y2 . y5 }. . System (1.8: D1 = F5 ∨ F6 ∨ F9 ∨ F13 . 1.12. Z 3 = {z5 . . . RD = 6.

12 can be formed. Transformation of initial structure table. the column K(Y 1 ) contains codes K(yn ) of microoperations yn ∈ 1 and so on. . . Encoding of compatible microoperations. For the discussed example. This step is executed in the same manner. because codes of microoperations have no influence on the hardware amount in the logic circuit. T0 ). Obviously. It is true.4. 3. as it was done for PY Mealy FSM. . the outcome of trivial encoding is shown in Table 4. then compatible microoperations can be encoded in a trivial way.12 Logic circuit of PY Mealy FSM S10 1 1 2 2 3 4 3 5 4 6 5 6 D1 D2 D3 z1 z2 z3 9 12 PROM 1 10 13 1 2 11 14 2 3 12 3 4 13 5 14 6 7 8 9 9 10 11 8 7 D1 D2 D3 R C RG 91 y1 y2 y3 y4 y5 y6 y7 y8 y9 x1 x2 x3 T1 T2 T3 1 2 3 4 5 6 PLD 1 2 3 4 5 6 Start 7 Clock 8 T 1 1 4 2 T2 5 3 T3 6 Table 4. In this table. For the FSM S11 .11. . If standard decoders are used for implementing the logic circuit of block BD. the logic circuit for block BD has the same hardware amount for any codes of compatible microoperations.2 Synthesis of FSM with Encoding of Collections of Microoperations Fig. . Table 4. The symbol ”0” corresponds to lack of microoperations of the Y / given class in some collection of microoperations Yt (t = 1.10 Structure table of Mealy FSM S11 am a1 a2 K(am ) 000 001 as a2 a3 a3 a4 a2 a5 a3 a5 a6 a2 a1 a1 K(as ) 001 010 010 011 001 100 010 100 101 001 000 000 Xh x1 x1 ¯ x2 x2 x3 ¯ ¯ x2 x3 ¯ ¯ 1 x2 x2 x4 ¯ x2 x4 ¯ ¯ x5 x5 ¯ 1 Yh y1 y2 y3 y1 y6 y3 D1 y6 D1 y8 y5 y7 y1 y5 y8 y3 D1 y7 y8 y1 y6 – y5 y7 Φh D3 D2 D2 D2 D3 D3 D1 D2 D1 D1 D2 D3 – – h 1 2 3 4 5 6 7 8 9 10 11 12 a3 a4 010 011 a5 a6 100 101 2. 4.

For example. which can be derived from them. the decoder DC2 for yn ∈ Y 2 .11 Codes of compatible microoperations for PD Mealy FSM S11 Y1 0 / y1 y4 y7 K(Y 1 ) z1 z2 00 01 10 11 Y2 0 / y2 y6 y8 K(Y 2 ) z3 z4 00 01 10 11 Y3 0 / y3 y5 K(Y 3 ) z5 z6 00 01 10 Table 4.13 is implemented using either obtained tables or systems of Boolean functions. y5 = z5 ).12. because each from the microoperations of the third class depends only on one variable (y3 = z6 . the following SOP z1 = F3 ∨ F4 ∨ F5 ∨ F8 ∨ F9 can be derived from Table 4. Because decoders are the standard library cells.13. It leads to decrease for the number . The logic circuit of PD Mealy FSM (in our case this circuit is shown in Fig.92 4 Optimization for Logic Circuit of Mealy FSM Table 4. whereas the decoder DC3 is absent.15) is derived from this table. As follows from Fig. their application yields in simplification and acceleration of a design process. 4. 4.12 Transformed structure table of PD Mealy FSM S11 am a1 a2 K(am ) 000 001 as a2 a3 a3 a4 a2 a5 a3 a5 a6 a2 a1 a1 K(as ) 001 010 010 011 001 100 010 100 101 001 000 000 Xh x1 x1 ¯ x2 x2 x3 ¯ ¯ x2 x3 ¯ ¯ 1 x2 x2 x4 ¯ x2 x4 ¯ ¯ x5 x5 ¯ 1 Zh z2 z4 z6 z2 z3 z1 z3 z6 z1 z3 z4 z1 z2 z5 z2 z5 z3 z4 z1 z6 z1 z2 z3 z4 z2 z3 – z1 z2 z5 Φh D3 D2 D2 D2 D3 D3 D1 D2 D1 D1 D2 D3 – – h 1 2 3 4 5 6 7 8 9 10 11 12 a3 a4 010 011 a5 a6 100 101 System (4.3 Synthesis of FSM with Encoding of Rows of Structure Table The main outcome of encoding of collections of microoperations is decrease for the number of the block BP outputs from R + N (P Mealy FSM) till R + R3 (PY Mealy FSM) or R + RD (PD Mealy FSM). 4. having RD functions. the decoder DC1 is used for implementation of microoperations yn ∈ Y 1 .

Let us encode the row h of ST by a binary code K(Fh ) having RF bits.20) . Fig. . where RF = log2 H .18) (4. .4. .14 Structure diagram of PF Mealy FSM X BP P BF Y RG Start Clock T In PF Mealy FSM. . r r=1 RF (4.3 Synthesis of FSM with Encoding of Rows of Structure Table Fig. .19) φr = ∨ Crh Zh In systems (4.13 Logic circuit of PD Mealy FSM S11 D1 D2 D3 z1 z2 z3 z4 z5 z6 11 12 13 14 15 16 17 18 19 93 x1 x2 x3 x4 x5 T1 T2 T3 1 1 1 2 2 2 3 3 3 4 4 4 5 5 6 6 5 7 7 6 8 8 7 PLD 1 2 3 4 5 6 7 8 9 14 1 15 2 DC1 1 2 3 4 1 2 3 4 y1 y4 y7 16 1 17 2 y5 y3 DC2 y2 y6 y8 8 11 D1 Start 9 12 D2 13 D Clock 10 9 3 R 10 C RG 18 T 1 1 6 19 T2 7 2 3 T3 8 of macrocells. 4. for such an encoding.19) the symbol Zh stands for a conjunction of variables zr ∈ Z. 4. It results in the model of BF Mealy FSM. corresponded to the code K(Fh ): Zh = ∧ zlrh . . The method of encoding of structure table rows [3] targets on solution of this problem too. 4. A block PF implements systems Y and Φ . (r = 1.17) Let us use variables zr ∈ Z. where |Z| = RF .18)–(4. . N).14. . (4. used to implement irregular functions. the block BP implements system (4.15). which includes RF functions. represented as: yn = ∨ Cnh Zh H h=1 H h=1 (h = 1. (4. shown in Fig. R).

1.15. 4. . h (Table 4. . represented by Table 4. 1} stands for value of the bit r of the code K(Fh ) corresponded to the row h of ST. . Synthesis of FSM logic circuit is executed using the obtained tables and systems of Boolean functions. the ST includes H = 14 rows and. the symbol lrh ∈ {0. .13 Transformed structure table of PF Mealy FSM S10 am a1 K(am ) 000 K(Fh ) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Xh x1 x1 x2 ¯ x1 x2 ¯ ¯ x3 x3 ¯ 1 x2 x1 x4 ¯ x2 x3 ¯ ¯ x1 x2 x1 x2 ¯ x1 x3 ¯ x1 x3 ¯ ¯ 1 Zh – z4 z3 z3 z4 z2 z2 z4 z2 z3 z2 z3 z4 z1 z1 z4 z2 z3 z1 z3 z4 z1 z2 z1 z2 z4 h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a2 a3 a4 001 010 011 a5 100 a6 101 This table is the base for deriving the system Z. . .13 (after minimization). This block can be specified by a table with the columns K(Fh ). . the simplest way for implementation of the logic circuit of the block BF is usage either of PROM or RAM chips with inputs zr ∈ Z. Let us encode the rows in a trivial way: K(F1 ) = 0000.7. . z4 }. and z0 = zr . For example. The transformation is reduced to moving away the columns as – Φh of initial ST and replacement them by the columns K(Fh ) and Zh . Specification of block BF. . the following SOP ¯ ¯ z1 = T1 T2 T3 x2 x3 ∨ T1 T2 can be derived from Table 4. For the PF Mealy FSM S10 . . Obviously.7. . This table in constructed in a trivial way. therefore. Construction of transformed structure table. D1 .94 4 Optimization for Logic Circuit of Mealy FSM In (4. . Encoding of structure table rows. As follows from Table 4. . The transformed ST of PF Mealy FSM S10 is represented by Table 4. y1 . . . . . DR . and Z = {z1 .20). 4. RF = 4. the logic circuit is shown in Fig. ¯ ¯ 3. RF ). . Table 4. z1 = zr (r = 1.13. yN . ¯ r r Let us discuss an example of PF Mealy FSM synthesis for the FSM S10 . K(F14 ) = 1101. . . 2.14 for FSM S10 ). .

Table 4.4.15 Logic circuit of PF Mealy FSM S10 x1 x2 x3 T1 T2 T3 1 1 1 2 2 2 3 3 4 4 3 5 5 4 6 6 PLD 5 13 D1 6 14 D2 15 D Start 7 3 8 Clock 8 7 R C RG z1 9 9 1 1 z2 10 10 2 PROM 1 2 2 z3 11 11 3 3 3 z4 12 12 4 4 4 5 6 7 T1 4 1 8 T2 5 2 9 3 T3 6 10 D1 11 D2 12 D3 y1 y2 y3 y4 y5 y6 y7 y8 y9 13 14 15 4. 4.4 Synthesis of FSM Multilevel Logic Circuits Combined application of methods discussed in this Chapter allows obtaining threeand four-levels models of Mealy FSM [2].14 Table of block BF for PF Mealy FSM S10 K(Fh ) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 y1 1 0 0 1 0 0 0 1 0 0 0 0 0 1 y2 1 0 0 1 0 0 1 1 0 0 0 0 0 1 y3 1 1 1 0 1 0 0 0 0 0 0 0 1 0 y4 0 0 1 0 0 0 0 0 0 1 0 0 0 0 y5 0 0 0 0 0 0 0 0 0 1 0 0 0 0 y6 0 0 0 0 0 1 0 0 0 0 0 0 0 0 y7 0 0 0 0 1 1 0 0 1 0 1 0 0 0 y8 0 1 1 1 0 0 1 0 0 0 0 0 0 0 y9 1 0 1 0 0 0 0 0 0 0 1 0 0 0 D1 0 0 0 0 1 1 0 0 1 0 0 0 1 0 D2 0 1 1 1 0 0 0 0 0 0 1 0 0 0 D3 1 0 1 0 0 1 1 0 1 1 0 0 0 0 h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 95 Fig.15 Multilevel models of Mealy FSM LA M MC ML LB P LC F DY LD DY .15.4 Synthesis of FSM Multilevel Logic Circuits Table 4. All possible multilevel models are represented by Table 4.

which implements functions (4.21) Functions (4. Table 4.16: X (a1 ) = {x1 }. (4. the model of MPD Mealy FSM should include the blocks BM. where the level LA is a prefix of the word. the level LB as its base. and BY). and the level LD as its ending (for some particular cases of PF Mealy FSM). X (a2 ) = {x2 . the following sets are derived from Table 4.16). X (a3 ) = X (a6 ) = 0.14). Logical condition replacement.96 4 Optimization for Logic Circuit of Mealy FSM The process of generation of three-level Mealy FSM logic circuit structures can be interpreted as a word-formation process. / . synthesis methods for multilevel models can be viewed as combining of corresponding methods for two-level model synthesis. x3 }. BD. encoding of structure table rows.or MLPD Mealy FSM. they always include all four levels. BP. Obviously. Four-level models are based on encoding of ST rows.16 Structure table of Mealy FSM S12 am a1 a2 K(am ) 000 001 as a2 a3 a2 a3 a4 a5 a5 a1 a7 a6 a7 a1 a2 a5 a3 K(as ) 001 010 001 010 011 100 100 000 110 101 110 000 001 100 010 Xh x1 x1 ¯ x2 x3 x2 x3 ¯ x2 ¯ 1 x3 x4 ¯ x3 x4 x3 ¯ x5 x5 ¯ 1 x5 x6 x5 x6 ¯ x5 ¯ Yh y1 y2 y3 y1 y6 y3 D1 y6 D1 y8 y5 y7 y1 y5 y8 y3 D1 y6 D1 y8 y1 y6 – y5 y7 y1 y6 y8 y1 y5 Φh D3 D2 D3 D2 D2 D3 D1 D1 – D1 D2 D1 D3 D 1 D2 – D3 D1 D2 h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a3 a4 010 011 a5 a6 a7 100 101 110 Obviously. T ). the level LC either as its suffix (for the block BF) or ending (for blocks BF. For the FSM S12 .16). For example.3). the word LA*LB*LC*LD determines MPFD Mealy FSM. 4. as well as functions Z = Z(P. For example. and BD (Fig. The following procedure can be used to synthesize the logic circuit of MPD Mealy FSM. Let the Mealy FSM S12 be specified by its structure table (Table 4. the word LA*LB*LC can stand for either MPY. and encoding of the classes of compatible microoperations. It means that synthesis method includes the methods of logical condition replacement. Let us discuss some examples.21) control the block BD.2). The block BM implements logical condition replacement and generates functions (4. 1. The block BP generates functions (4. Let us discuss an example of synthesis for the MPD Mealy FSM S12 .

17.17. Table 4. Encoding of the classes of compatible microoperations. while the second for PD Mealy FSM (Table 4. Y 2 = {y2 . namely: Y 1 = {y1 . whereas only two control inputs are enough for the multiplexer MX2 . Transformation of FSM structure table. The outcome of such a recoding is shown in Fig. The table of logical condition replacement for FSM S12 (Table 4. Fig. y6 .4.19). It is enough RD = 6 variables zr ∈ Z for encoding of microoperations. To transform an initial structure table.16 Structural diagram of MPD Mealy FSM Z BM P BD BP RG Start Clock 97 Y X T X (a4 ) = {x3 . y8 }. . 3. the multiplexer MX1 has three control inputs. y5 }. y7 }. x6 }. x4 }. 4. 4. the codes of states am ∈ A should be recoded using the method of multiplexer encoding.17 Multiplexer codes for Mealy FSM S12 T2T3 00 T1 0 1 a1 a3 01 a2 a5 11 a7 10 a4 a6 * 2. It means that G = 2 and determines the set P = {p1 . the column Xh is replaced by the column Ph . X (a5 ) = {x5 }. Thus. y4 . Y 3 = {y3 . 4.17 Table of logical condition replacement for MPD Mealy FSM S12 am p1 p2 a1 x1 – a2 x2 x3 a3 – – a4 x4 x3 a5 x5 – a6 – – a7 x5 x6 As it follows from Table 4. The first replacement is executed in the manner used for MP Mealy FSM. let us point out that microoperations yn ∈ Y 3 are encoded using one-hot codes. and the column Yh by the column Zh . p2 }. and X(a7 ) = {x5 . the set Y can be divided by three classes of compatible microoperations.18. The final codes are represented by Table 4.4 Synthesis of FSM Multilevel Logic Circuits Fig. For the FSM S12 .17) is constructed using all rules discussed in previous Sections.

18. In this circuit. The structural diagram of MPFY Mealy FSM is shown in Fig.19). In this model. the block BP includes two multiplexers and is implemented using information from Table 4. represented by its structure table (Table 4. ¯ The logic circuit of MPD Mealy FSM S12 is shown in Fig. the block BD includes two decoders and is implemented using Table 4. the block BF generates variables zr ∈ ZF used for encoding of collections of microoperations. Let us discuss an example of design for the MPFY Mealy FSM S12 . as well as input memory functions φr ∈ Φ .16).98 4 Optimization for Logic Circuit of Mealy FSM Table 4. The block BP is designed on the base of transformed ST (Table 4. The block BY implements the system Y depended on variables zr ∈ ZF . The . For example.18. 4. 4. the block BM replaces logical conditions and generates functions P(X .18 Codes of microoperations for MPD Mealy FSM S12 Y1 0 / y1 y4 y7 K(Y 1 ) z1 z2 00 01 10 11 Y2 0 / y2 y6 y8 K(Y 2 ) z3 z4 00 01 10 11 Y3 0 / y3 y5 K(Y 3 ) z5 z6 00 01 10 Table 4.19. the block BP generates variables zr ∈ ZP used for encoding of rows of transformed structure table.16. Dr ∈ Φ .17. T ).19. D1 = F2 ∨ F4 ∨ F6 ∨ F7 ∨ F10 ∨ F14 ∨ F15 can be derived from Table 4. the following Boolean equations for functions z1 = F3 ∨ F4 ∨ F5 ∨ F8 ∨ F9 ∨ F12 = A2 ∨ A3 p2 p1 ∨ A3 p2 ∨ A6 . 4. as well as codes shown in Fig.19 Transformed structure table of MP Mealy FSM S12 am a1 a2 K(am ) 000 001 as a2 a3 a2 a3 a4 a5 a5 a1 a7 a6 a7 a1 a2 a5 a3 K(as ) 001 010 001 100 010 101 101 000 011 110 011 000 001 101 100 Ph p1 p1 ¯ p1 p2 p1 p2 ¯ p1 ¯ 1 p2 p1 ¯ p2 p1 p2 ¯ p1 p1 ¯ 1 p1 p2 p1 p2 ¯ p1 ¯ Zh z2 z4 z6 z2 z3 z1 z3 z6 z1 z3 z4 z1 z2 z5 z2 z5 z3 z4 z1 z6 z1 z2 z3 z4 z2 z3 – z1 z2 z5 z2 z3 z3 z4 z2 z5 Φh D3 D1 D3 D1 D2 D1 D3 D1 D3 – D2 D3 D1 D2 D2 D3 – D3 D1 D3 D1 h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a3 a4 100 010 a5 a6 a7 101 110 011 The table is used to derive functions zr ∈ Z.

the outcome for this step does not depend on the model in use. As in previous case. it is determined by the initial structure table. T ).24) (4. 4. Y = Y (ZF ). (4. ZP = ZP (P.18 Logic circuit of MPD Mealy FSM S12 z1 z2 z3 z4 z5 z6 D1 D2 D3 99 14 15 16 17 18 19 20 21 22 x1 x2 x3 x4 x5 x6 T1 T2 1 1 2 5 3 5 4 1 5 5 9 6 14 7 15 16 8 0 1 2 3 4 5 6 7 1 2 3 MX1 P1 12 12 13 7 8 9 1 2 3 4 5 6 PLD 1 2 3 4 5 6 7 8 9 T3 9 0 Start 10 3 1 3 2 Clock 11 6 8 3 9 1 2 20 21 22 23 24 D1 D2 D3 R C MX2 P2 13 14 1 15 2 DC1 1 2 3 4 1 2 3 4 y1 y4 y7 RG T 1 1 7 2 T2 8 3 T3 9 16 1 17 2 18 19 y5 y3 DC2 y2 y6 y8 Fig. states codes are shown in Fig. This table determines system (4.22). Obviously.17. ZF = ZF (ZP ). 4.25) (4. instead.23) (4.22) (4. 4.4 Synthesis of FSM Multilevel Logic Circuits Fig.26) Φ = Φ (ZP ).19 Structural diagram of MPFY Mealy FSM X BM P BP ZP BF ZF Y BY RG Start Clock T following systems of Boolean functions should be found to design the logic circuit of MPFY Mealy FSM: P = P(X . . T ).4. This step has been discussed for the MPD Mealy FSM S12 . Logical condition replacement.17 shows the outcome of logical condition replacement. 1. whereas Table 4.

can be derived from Table 4. 6.Φh are replaced by the column Zh (as it is for PF Mealy FSM). BP. the following SOP y1 = Z2 ∨ Z3 ∨ Z7 = z5 z6 z7 ∨ z6 z7 . For the Mealy FSM S12 . Logic circuits for blocks BM. Y4 = / {y3 . The logic circuit for block BM is implemented using both Table 4.100 4 Optimization for Logic Circuit of Mealy FSM 2. Joining these circuits into the final logic circuit is easy enough. we do not discuss this step. .20. Obviously. y4 . ZF (outputs of memory blocks). To construct such a table. 3. ¯ ¯ 4. Let us encode the structure table rows in a trivial way: K(F1 ) = 0000. we have the set ZP = {z1 . Y2 = {y1 . and columns as . Specification of block BF. for example. we have the set ZF = {z5 . . y5 }. 4. Thus. K(F15 ) = 1110. y2 .Φ . In this case. . the structure table includes H = 15 rows. as it is shown for the system (4. . the following ¯ ¯ ¯ Boolean function for the block BP z1 = F9 ∨ . Logic circuit implementation.. Y3 = {y1 . This table can be used for deriving SOP functions yn ∈ Y . In the discussed example.17 and state codes shown in Fig.24) and (4. these systems can be represented as SOPs. . y3 }. Transformation of initial structure table.26). corresponding to the code K(Yt ). Y5 = {y4 .21. these circuits are combined together to form a final logic circuit.16. . Y7 = {y1 . Let the symbol Zt stand for a conjunction of variables zr ∈ ZF . In the discussed case. ∨ F15 = T1 T2 T3 p2 ∨ A5 ∨ A6 ∨ ¯ ¯ ¯ ∨A7 = T1 T2 T3 p2 ∨ T1 T3 ∨ T1 T2 ∨ T2 T3 can be derived from Table 4. The logic circuit for block BF is implemented using Table 4. This table is used for deriving systems (4. Encoding of collections of microoperations.21.20 Table of block BY for MPFY Mealy FSM S12 z5 0 0 0 0 z6 0 0 1 1 z7 0 1 0 1 Y (ZF ) – x1 y2 y3 x1 y6 y3 y4 y6 t 1 2 3 4 z5 1 1 1 1 z6 0 0 1 1 z7 0 1 0 1 Y (ZF ) y4 y8 y5 y7 x1 y5 y8 t 5 6 7 8 The simplest way for implementation of the block BY is use of PROM (or RAM) chips with address inputs z5 – z7 . It is enough R3 = 3 variables for such an encoding.21). z7 }.22. . For the FSM S12 .25).23). therefore. Y6 = {y5 . the outcome of transformation is shown in Table 4. y6 }. 5. Y8 = {y8 }. BF. The block BF is represented by the table with columns K(Fh ) (inputs of memory blocks). y6 }. y7 }. Table 4. . and BY are implemented during this step. Encoding of structure table rows. y8 }.22). the block BY is represented by Table 4. The FSM S12 includes T0 = 8 collections of microoperations: Y1 = 0. z4 }. . The logic circuit for block BY is implemented using Table 4. This table is used for deriving system (4. it is enough RF = 4 variables for encoding of its rows.20. The logic circuit for block BP is implemented using the transformed structure table (Table 4. the column Xh should be replaced by the column Ph (as it is for MP Mealy FSM).20. For example. this table includes H = 15 rows (Table 4. z6 . Next. . therefore.

4.22 Specification of block BF for MPFY Mealy FSM S12 K(Fh ) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Φ D3 D1 D3 D1 D2 D1 D 3 D1 D 3 – D2 D 3 D1 D 3 D1 D2 – D3 D1 D3 D1 ZF z7 z6 z6 z7 z5 z5 z7 z5 z6 z5 z6 z7 z6 z7 z5 z6 – z5 z7 z6 z5 z6 z7 z5 z6 h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 .4 Synthesis of FSM Multilevel Logic Circuits Table 4.21 Transformed structure table of MPFY Mealy FSM S12 am a1 a2 K(am ) 000 001 Ph p1 p1 ¯ p1 p2 ¯ p1 p2 p1 ¯ 1 p2 p1 p2 p1 ¯ p2 ¯ p1 p1 ¯ 1 p1 p2 p1 p2 ¯ p1 ¯ Zh – z4 z3 z3 z4 z2 z2 z4 z2 z3 z2 z3 z4 z1 z1 z4 z1 z3 z1 z3 z4 z1 z2 z1 z2 z4 z1 z2 z3 h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 101 a3 a4 100 010 a5 a6 a7 101 110 011 Table 4.

A. e University of Zielona Góra Press.15 can be designed using the same approach. University of Zielona Góra Press.: Design of Control Units