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®

X5043, X5045
4K, 512 x 8 Bit
Data Sheet March 16, 2006 FN8126.2

CPU Supervisor with 4K SPI EEPROM
These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as 512 x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.

Features
• Low VCC Detection and Reset Assertion - Four standard reset threshold voltages 4.63V, 4.38V, 2.93V, 2.63V - Re-program low VCC reset threshold voltage using special programming sequence. - Reset signal valid to VCC = 1V • Selectable Time Out Watchdog Timer • Long Battery Life with Low Power Consumption - <50µA max standby current, watchdog on - <10µA max standby current, watchdog off • 4Kbits of EEPROM–1M Write Cycle Endurance • Save Critical Data with Block Lock™ Memory - Protect 1/4, 1/2, all or none of EEPROM array • Built-in Inadvertent Write Protection - Write enable latch - Write protect pin • SPI Interface - 3.3MHz Clock Rate • Minimize Programming Time - 16-byte page write mode - 5ms write cycle time (typical) • Available Packages - 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP - 14 Ld TSSOP • Pb-Free Plus Anneal Available (RoHS Compliant)

Applications
• Communications Equipment - Routers, Hubs, Switches - Set Top Boxes • Industrial Systems - Process Control - Intelligent Instrumentation • Computer Systems - Desktop Computers - Network Servers • Battery Powered Equipment

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

X5043, X5045 Typical Application

2.7-5.0V
VCC

VCC
uC

X5043
RESET CS SCK SI SO WP VSS

10K
RESET SPI

VSS

Block Diagram
POR and Low Voltage Reset Generation Reset & Watchdog Timebase Watchdog Timer Reset RESET (X5043) RESET (X5045)

VCC
VTRIP

+

X5043, X5045 STANDARD VTRIP LEVEL Watchdog Transition Detector 4.63V (+/-2.5%) 4.38V (+/-2.5%) 2.93V (+/-2.5%) 2.63V (+/-2.5%) SUFFIX -4.5A -4.5 -2.7A -2.7

CS/WDI
SI SO SCK WP Command Decode & Control Logic Protect Logic

Status Register EEPROM Array 4Kbits

See “Ordering Information” on page 3. for more details For Custom Settings, call Intersil.

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FN8126.2 March 16, 2006

25-4.5-4.5-5.5A* (Note) X5045M8-4.5V VTRIP RANGE 4. X5045 Ordering Information PART NUMBER RESET (ACTIVE LOW) X5043P-4.5A X5045S8Z-4.75 TEMP RANGE (°C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free) X5043P Z AL X5045PZ-4.5A* (Note) X5043M8-4.5A X5045PI-4.5A X5043M8Z-4.5A (Note) X5045M8I-4.5A (Note) X5043V14I-4.5A (Note) X5045V14I-4.5A X5045S8-4.5A (Note) X5043P X5043P Z X5043P I X5043P Z I X5043 X5043 Z X5043 I X5043 Z I AEO DBN AEP DBJ X5043V I X5043V Z I X5045P X5045PZ (Note) X5045PI X5045PIZ (Note) X5045S8* X5045S8Z* (Note) X5045S8I* X5045S8IZ* (Note) X5045M8 X5045M8Z (Note) X5045M8I X5045M8IZ (Note) X5045V14I X5045V14IZ (Note) 3 FN8126. 2006 .5A X5045M8Z-4.5A X5043S8-4.5A (Note) X5045P Z AM X5043S8Z-4.5A (Note) X5045P Z AL X5043PIZ-4.5A X5045M8IZ-4.5A PART MARKING X5043P AL X5043P AM X5043 AL PART NUMBER RESET (ACTIVE HIGH) X5045P-4.5A X5043PZ-4.5 VCC RANGE 4.2 March 16.5A PART MARKING X5045P AL X5045P AM X5045 AL X5045 Z AL X5045 AM X5045 Z AM AEV DCB AEW DBX X5045V AM X5045V Z AM X5045P X5045P Z X5045P I X5045P Z I X5045 X5045 Z X5045 I X5045 Z I AEX DBY AEY DBT X5045V I X5045V Z I 4.5A X5043M8IZ-4.5A* X5045S8IZ-4.5A* X5043S8IZ-4.5A (Note) X5043P X5043PZ (Note) X5043PI X5043PIZ (Note) X5043S8* X5043S8Z* (Note) X5043S8I* X5043S8IZ* (Note) X5043M8 X5043M8Z (Note) X5043M8I X5043M8IZ (Note) X5043V14I X5043V14IZ (Note) X5043 AM X5043 Z AM AEM DBS AEN DBM X5043V AM X5043V Z AM X5045V14IZ-4.5A (Note) X5043P Z AM X5045PIZ-4.5A (Note) X5043M8I-4.5A (Note) X5043 Z AL X5043S8I-4.5A (Note) X5045S8I-4.5A (Note) X5043PI-4.X5043.5A X5043V14IZ-4.

7A X5043PZ-2. which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations.7* X5043M8IZ-2.2 March 16.7A (Note) X5043P-2.7* (Note) X5043V14I-2.7* PART MARKING X5043P AN X5043P AP X5043 AN X5043 Z AN X5043 AP X5043 Z AP AEQ DBR AER DBL X5043V AP PART NUMBER RESET (ACTIVE HIGH) X5045P-2.7A (Note) X5043PI-2. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets.7 X5043M8Z-2.7A (Note) X5043M8I-2.7A X5045PI-2.7A PART MARKING X5045P AN X5045P AP X5045 AN X5045 Z AN X5045 AP X5045 Z AP AEZ DCA AFA DBW X5045V AP X5045V Z AP X5045P F X5045P Z F X5045P G X5045P Z G X5045 F X5045 G X5045 Z G AFB AFC 2.7A (Note) X5043P F X5043P Z F X5043P G X5043P Z G X5043 F X5043 G X5045P-2.7 X5043PZ-2.0 TEMP RANGE (°C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free) X5043P Z AN X5045PZ-2. 4 FN8126.7 (Note) X5045V G X5045V Z G *Add "-T1" suffix for tape and reel.7* X5043S8I-2.7A* (Note) X5043S8I-2.7 (Note) X5043M8I-2.7A* (Note) X5043V14I-2.7* (Note) X5043 Z F X5043S8IZ-2. molding compounds/die attach materials and 100% matte tin plate termination finish.7* (Note) X5043 Z G X5043M8-2.7A (Note) X5045P Z AN X5043PIZ-2.7 X5043PIZ-2.7* (Note) X5045M8-2.7A (Note) X5045V14I-2.X5043.85-3. X5045 Ordering Information (Continued) PART NUMBER RESET (ACTIVE LOW) X5043P-2.7A (Note) X5045M8I-2.7A (Note) X5045P Z AP X5043V Z AP X5045V14IZ-2.7* X5045S8I-2.7 (Note) X5045PI-2.7A X5045S8Z-2.7A* X5043S8IZ-2.7A* X5043S8Z-2.7 X5043V14IZ-2.7A X5045M8Z-2.7 X5043S8Z-2.7A X5045S8IZ-2.7A X5043S8-2.7A X5045M8IZ-2.7 (Note) X5043S8-2.7A (Note) X5045S8I-2.7 (Note) X5045S8-2.7 X5045V14IZ-2.7 (Note) X5043PI-2.7 VCC RANGE 2.7 (Note) AES DBP AET DBK X5043V G X5043V Z G X5045S8Z-2. 2006 .7 X5045PZ-2. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.7* (Note) X5045 Z F X5045M8Z-2.7 (Note) DBZ X5045M8IZ-2.7-5.7A* (Note) X5043M8-2.7 (Note) DBU X5045V14I-2.7* X5045S8IZ-2.7A (Note) X5045M8-2.7A X5045S8-2.7A* X5043M8IZ-2.7 X5045M8I-2.7A (Note) X5043P Z AP X5045PIZ-2.55-2.7 X5045PIZ-2.7A* X5043M8Z-2.5V VTRIP RANGE 2.7A X5043V14IZ-2.

Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. X5045 are disabled. The RESET/RESET signal remains active until the voltage drops below 1V. unless an internal write operation is underway. but the part otherwise functions normally. WP going low while CS is still low will interrupt a write to the X5043. the X5043. During a read cycle. X5045 6 5 VCC RESET/RESET SCK SI cycle has already been initiated. and data to be written to the memory are input on this pin. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET/RESET. Chip Select (CS/WDI) When CS is high. RESET/RESET is an active low/HIGH.2 March 16. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. X5045. If the internal write 5 . X5045 activate a Poweron Reset Circuit. X5045 11 10 9 8 VCC RESET/RESET NC NC NC SCK SI Pin Names SYMBOL CS/WDI SO SI SCK WP DESCRIPTION Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage Reset Output Pin Descriptions Serial Output (SO) SO is a push/pull serial data output pin. A falling edge of CS will reset the watchdog timer. Data is clocked out by the falling edge of the serial clock. With FN8126. X5045. Data is latched by the rising edge of the serial clock. the X5043. data is shifted out on this pin. RESET/RESET prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. X5045 Pin Configuration 8 Ld SOIC/PDIP/MSOP CS/WDI SO WP VSS 1 2 3 4 8 7 X5043. Low Voltage Monitoring During operation. Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. Reset (RESET. nonvolatile writes to the X5043. X5045.X5043. while data on the SO pin changes after the falling edge of the clock input. Opcodes. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. or data present on the SI pin is latched on the rising edge of the clock input. The microprocessor must toggle the CS/WDI pin periodically to prevent an active RESET/RESET signal. RESET) X5043. WP going low will have no affect on a write. 14 Ld TSSOP CS SO NC NC NC WP VSS 1 2 3 4 5 6 7 14 13 12 X5043. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. open drain output which goes active whenever VCC falls below the minimum VCC sense level. the X5043. Serial Input (SI) SI is the serial data input pin. The microprocessor can change these watchdog bits. all functions. X5045 are deselected and the SO output pin is at high impedance and. X5045 monitor the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. It also remains active until VCC returns and exceeds VTRIP for 200ms. CS low enables the X5043. It will remain active until VCC rises above the minimum VCC sense level for 200ms. placing it in the active power mode. byte addresses. When WP is held high. addresses. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. X5045 will be in the standby power mode. VSS VCC RESET/RESET Principles of Operation Power-on Reset Application of power to the X5043. This circuit pulls the RESET/RESET pin active. All opcodes. 2006 Write Protect (WP) When WP is low. It should be noted that after power-up. allowing the processor to begin executing code. including non volatile writes operate normally. a high to low transition on CS is required prior to the start of any operation.

if the current VTRIP is 4. apply at least 3V to the VCC pin and tie the WP pin to the programming voltage VP. VCC Threshold Reset Procedure The X5043. When VTRIP is reset. apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. 2006 . X5045 are shipped with a standard VCC threshold (VTRIP) voltage. CS going HIGH on the write operation initiates the VTRIP programming sequence. Note: This operation also writes 00h to array address 03h. this procedure will directly make the change.0V. Then send a WREN command. even during total power failure.7V. Note: This operation also writes 00h to array address 01h.4V and the new VTRIP must be 4. the new VTRIP is something less than 1. For example. To set the new VTRIP voltage. X5045 threshold may be adjusted. Then send a WREN command. SET VTRIP LEVEL SEQUENCE (VCC = DESIRED VTRIP VALUE. This procedure must be used to set the voltage to a lower value.2 March 16. CS going HIGH on the write operation initiates the VTRIP programming sequence.4V and the new VTRIP is 4. the X5043. the watchdog timer control bits remain unchanged. or if higher precision is needed in the VTRIP value. Resetting the VTRIP Voltage This procedure is used to set the VTRIP to a “native” voltage level. followed by a write of Data 00h to address 01h. then the VTRIP must be reset. address 03h.) 6 FN8126. The procedure is described below. Bring WP LOW to complete the operation. if the current VTRIP is 4. This value will not change over normal operating and storage conditions. However. For example. in applications where the standard VTRIP is not exactly right. Bring WP LOW to complete the operation. then it is necessary to reset the trip point before setting the new value. If the new setting is to be lower than the current setting.6V. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher voltage value.X5043. followed by a write of Data 00h to WP VP = 15-18V CS 0 1 2 3 4 5 6 7 SCK 8 Bits SI 06h WREN 02h Write 01h Address 00h Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FIGURE 1. X5045 no microprocessor action. and uses the application of a high voltage control signal. To reset the VTRIP voltage.

X5043. RESET VTRIP LEVEL SEQUENCE (VCC > 3V. X5045 WP VP = 15-18V CS 0 1 2 3 4 5 6 7 SCK 8 Bits SI 06h WREN 02h Write 03h Address 00h Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FIGURE 2. WP = 15–18V) 4.2 March 16. 1 2 3 4 X5043 X5045 8 7 6 5 RESET µC SCK SI SO CS Run FIGURE 3.7K VP Adjust VTRIP Adj. 2006 . SAMPLE VTRIP RESET CIRCUIT 7 FN8126.

providing a minimum endurance of 1. All instruction. X5045 SPI Serial Memory VTRIP Programming Execute Reset VTRIP Sequence The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. Data is output on the SO line by the falling edge of SCK. 8 FN8126.000. addresses and data are transferred MSB first.2 March 16. address and data bits are clocked by the SCK input. The array is internally organized as 512 x 8 bits. Instructions are transferred MSB first. The instruction code is written to the device via the SI input. Error ≤ -Emax Error ≥ Emax -Emax < Error < Emax DONE Emax = Maximum Desired Error FIGURE 4. All instructions (Table 1). The remainder of the operations require an instruction byte. The device utilizes Intersil’s proprietary Direct Write™ cell. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.Error Execute Set VTRIP Sequence Apply 5V to VCC The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. then data bytes. There are two read operations that use the instruction byte to initiate the output of data. Execute Reset VTRIP Sequence Decrement VCC (VCC = VCC–10mV) NO RESET pin goes active? YES Measured VTRIP -Desired VTRIP Clock and Data Timing Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW.000 cycles and a minimum data retention of 100 years. The device contains an 8-bit instruction register that controls the operation of the device. CS must be LOW during the entire operation.X5043. allowing the user to stop the clock and then start it again to resume operations where left off. New VCC Applied = Old VCC Applied . INSTRUCTION SET INSTRUCTION NAME WREN WRDI RSDR WRSR READ WRITE Note: INSTRUCTION FORMAT* 0000 0110 0000 0100 0000 0101 0000 0001 0000 A8011 0000 A8010 OPERATION Set the Write Enable Latch (Enable Write Operations) Reset the Write Enable Latch (Disable Write Operations) Read Status Register Write Status Register (Watchdog and Block Lock) Read Data from Memory Array Beginning at Selected Address Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes) *Instructions are shown MSB in leftmost position. VTRIP PROGRAMMING SEQUENCE TABLE 1.Error Set VCC = VCC Applied = Desired VTRIP New VCC Applied = Old VCC Applied . There are two write operations that requires only the instruction byte. 2006 . SCK is static. an 8-bit address.

it is not necessary to send a byte address or data. Refer to the Read Status Register Sequence (Figure 6). The Status Register may be read at any time. even during a Write Cycle. The WEL bit is a volatile. WRITE ENABLE/DISABLE LATCH SEQUENCE (WREN/WRDI INSTRUCTION) Read Status Register To read the Status Register. X5045 None $180–$1FF $100–$1FF $000–$1FF 0 SCK 1 2 3 4 5 6 7 The Watchdog Timer bits. STATUS REGISTER BITS WD1 WD0 0 1 0 1 WATCHDOG TIME OUT (TYPICAL) 1. WD0 and WD1. If CS does not go HIGH between WREN and WRSR. clocked by CLK. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory. Status Register The Status Register contains four nonvolatile control bits and two volatile status bits. The Status Register is formatted as shown in “Status Register”. This latch must be SET before a Write Operation is initiated. STATUS REG BITS BL1 0 0 1 1 CS BL0 0 1 0 1 ARRAY ADDRESSES PROTECTED X5043. This latch is automatically reset upon a power-up condition and after the completion of a valid byte. When set to a “1”. the “Write Enable” Latch (WEL) must be set by issuing the WREN instruction (Figure 5). Status Register: (Default = 30H) 7 0 6 0 5 WD1 4 WD0 3 BL1 2 BL0 1 WEL 0 WIP The Write-In-Progress (WIP) bit is a volatile. set the level of block lock protection. no write is in progress. When issuing a WREN. the array that is block lock protected can be read but not written. The WIP bit is read using the RDSR instruction. the WRSR instruction is ignored. Any portion of 9 FN8126. pull CS low to select the device. The WREN instruction sets the WEL bit and the WRDS instruction resets the WEL bit.2 March 16. Then bring CS LOW again and enter the WRSR instruction followed by 8 bits of data. or status register write cycle. BL0 and BL1. The block lock bits. 2006 . These nonvolatile bits are programmed with the WRSR instruction. The latch is also reset if WP is brought LOW. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter.4 seconds 600 milliseconds 200 milliseconds disabled (factory default) SI High Impedance 0 0 SO 1 1 FIGURE 5. When set to a “0”. X5045 Write Enable Latch The device contains a Write Enable Latch. First pull CS LOW. When WEL = 1. The control bits set the operation of the watchdog timer and the memory block lock protection. The operation ends with CS going HIGH. read only bit and indicates whether the device is busy with an internal nonvolatile write operation. These 8 bits of data correspond to the contents of the status register. the latch is set and when WEL = 0 the latch is reset. Then the contents of the Status Register are shifted out on the SO line. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 5). select the Watchdog Time-out Period. a nonvolatile write operation is in progress. Write Status Register Prior to any attempt to write data into the status register. WRDI or RDSR commands. read only bit. all or none of the EEPROM array. then clock the WREN instruction into the device and pull CS HIGH. one half. page. then send the 8-bit RDSR instruction.X5043. The Write Enable Latch (WEL) bit indicates the status of the “write enable” latch.

WD1) Protected Protected Writable CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Instruction SI SO High Impedance Data Out 7 MSB 6 5 4 3 2 1 0 FIGURE 6.X5043. X5045 TABLE 2. DEVICE PROTECT MATRIX WREN CMD (WEL) 0 x 1 MEMORY BLOCK DEVICE PIN (WP) x 0 1 PROTECTED AREA Protected Protected Protected UNPROTECTED AREA Protected Protected Writable STATUS REGISTER (BL0. BL1. 2006 . WD0.2 March 16. READ STATUS REGISTER SEQUENCE CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Instruction SI 7 6 5 Data Byte 4 3 2 1 0 SO High Impedance FIGURE 7. WRITE STATUS REGISTER SEQUENCE 10 FN8126.

followed by the 8-bit address. If the byte address reaches the last byte on the page and the clock continues. WIP is HIGH while the nonvolatile write is in progress. then clock the WREN instruction into the device and pull CS HIGH. the Status Register may be read to check the WIP bit. When the highest address is reached. The WRITE operation requires at least 16 clocks.X5043. The 8-bit READ instruction is transmitted to the device. CS must go low and remain low for the duration of the operation. Refer to the Read EEPROM Array Sequence (Figure 8). the write operation will not be completed (Figure 9). CS is first pulled low to select the device. If it is brought HIGH at any other time. First pull CS LOW. After the READ opcode and address are sent. Then bring CS LOW again and enter the WRITE instruction followed by the 8-bit address and then the data to be written. the “Write Enable” Latch (WEL) must be set by issuing the WREN instruction (Figure 5). which selects the upper or lower half of the array. Bit 3 of the READ instruction selects the upper or lower half of the device. While the write is in progress following a status register or memory array write sequence. The only restriction is that the 16 bytes must reside within the same page. For the write operation (byte or page write) to be completed. the counter will roll back to the first address of the page and overwrite any data that has been previously written. CS 0 SCK 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 Instruction SI 8 7 6 8 Bit Address 5 3 2 1 0 9th Bit of Address High Impedance SO 7 MSB FIGURE 8. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the WRITE instruction is ignored. The address is automatically incremented to the next higher address after each byte of data is shifted out. Bit 3 of the WRITE instruction contains address bit A8. CS must be brought HIGH after bit 0 of the last complete data byte to be written is clocked in. A page address begins with address [x xxxx 0000] and ends with [x xxxx 1111].2 March 16. the data stored in the memory at the selected address is shifted out on the SO line. READ EEPROM ARRAY SEQUENCE 6 5 4 Data Out 3 2 1 0 11 FN8126. X5045 Read Memory Array When reading from the EEPROM memory array. The host may continue to write up to 16 bytes of data. The read operation is terminated by taking CS high. the address counter rolls over to address 000h allowing the read cycle to be continued indefinitely. If CS does not go HIGH between WREN and WRITE. 2006 . Write Memory Array Prior to any attempt to write data into the memory array.

12 FN8126. SO pin is high impedance. The device is in the low power standby state. • Block Protect bits provide additional level of write protection for the memory array. WRITE MEMORY SEQUENCE Operational Notes The device powers-up in the following state: 1. 2. • CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle.X5043. The Flag Bit is reset. A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. 6.2 March 16. Data Protection The following circuitry has been included to prevent inadvertent writes: • A WREN instruction must be issued to set the Write Enable Latch. 5. 2006 . Reset Signal is active for tPURST. 4. The Write Enable Latch is reset. • The WP pin LOW blocks nonvolatile write operations. X5045 CS 0 SCK Instruction SI 8 7 6 8 Bit Address 5 3 2 Data Byte 1 4 3 2 1 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 1 0 7 6 5 0 9th Bit of Address CS 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK Data Byte 2 5 4 3 2 Data Byte 3 5 4 3 2 Data Byte N 4 3 2 1 SI 7 6 1 0 7 6 1 0 6 5 0 FIGURE 9. 3.

. . . . . . 10 seconds) . . . . . . . . .4 V Capacitance SYMBOL COUT CIN NOTES: (2) TA = +25°C. .25mA IOL = 1mA VCC . . DC Electrical Specifications SYMBOL ICC1 ICC2 ISB1 ISB2 ILI ILO VIL (1) (1) (Over the recommended operating conditions unless otherwise specified. .) LIMITS PARAMETER VCC Write Current (Active) VCC Read Current (Active) TEST CONDITIONS/COMMENTS SCK = 3. RESET. . . . . . . . . RESET = Open SCK = 3. .8 VCC . . .5V Blank. . . . . . WP.5V SCK. . SO. . . . functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. RESET. RESET = VSS to VCC SCK. . SI. . . . . . . SI = VSS. . . . . . . This is a stress rating only. . . . . . . .5 VCC x 0. . . . 2006 . . . . .7 0. and VIH max. .0. . . Exposure to absolute maximum rating conditions for extended periods may affect device reliability. . .2 -0. . 2.-65°C to +150°C Voltage on any pin with respect to VSS . . . . . . . . . . . . . . SCK. 3. . . . . . . . .5V to 5. RESET) Input Capacitance (SCK. IOH = –0. . . . .4mA VCC ≤ 2V. . . . f = 1MHz. . This parameter is periodically sampled and not 100% tested. . . . . . . .1/VCC x 0. . are for reference only and are not tested. RESET. . . .-40°C to +85°C Supply Voltage: -2. . . . . . VCC = 5. . . . . . . SI. . 5mA Lead temperature (soldering. . . . .1 0.5 0.3MHz(3). . . SCK. .7V to 5. . . . . .7. SI = VSS.3V. . .4 VIH VOL VOH1 VOH2 VOH3 VOLRS 0.5V CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. SI = VSS. .0mA 2V < VCC ≤ 3. . . . . output current. . . . . . . .3MHz(3). . X5045 Absolute Maximum Ratings Temperature under bias . . CS SCK. -1.0. 0°C to +70°C Industrial . . -2. . . CS. . . . . . . . .7V IOL = 0. RESET = Open MIN TYP(2) MAX 3 2 10 50 UNIT mA mA µA µA µA µA V V V V V V VCC Standby Current WDT = OFF CS = VCC.1 10 10 VCC x 0. .5V VCC Standby Current WDT = ON Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage (SO) Output HIGH Voltage (SO) Output HIGH Voltage (SO) Output HIGH Voltage (SO) Output LOW Voltage (RESET. . VCC = 5V TEST CONDITIONS VOUT = 0V VIN = 0V MAX 8 6 UNIT pF pF Output Capacitance (SO. . . . . . . . .C. . 4. . . WP. . . . . . .5A .3 VCC + 0. . . . .4 VCC . . . SCK frequency measured from VCC x 0. . . . RESET.5mA @ VCC = 1. VIL min. . . . WP = VSS to VCC SO. . . . .X5043. . . . . . . . . . -4.9 13 FN8126. . . . .0. . . . . . 300°C Recommended Operating Conditions Temperature: Commercial. . . . . . . SI. . WP) (2) 1. . IOH = –1. . . . . . .2 March 16. . . 2. VCC = 5. . . . . . . .3V.8V VCC > 3. IOH = –0. . RESET) CS = VCC. . . .0V to +7V D. SI. .7A . . . . .-65°C to +135°C Storage temperature . CS IOL = 2mA @ VCC = 2. . . .

7V–5.X5043.1 to VCC x 0. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.3 150 120 UNIT MHz ns ns ns 0 50 50 ns ns (4) NOTES: 4.5V PARAMETER MIN MAX UNIT 0 300 150 150 130 130 30 30 3.5 1. Load Circuit at 5V VCC 5V 5V 4.2 March 16. unless otherwise specified) 2.C.6kΩ A. X5045 Equivalent A.9 10ns VCC x 0.64kΩ 30pF RESET/RESET 30pF AC Electrical Specifications SYMBOL DATA INPUT TIMING fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(4) tFI(4) tCS tWC(5) Clock Frequency Cycle Time CS Lead Time CS Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Input Rise Time Input Fall Time CS Deselect Time Write Cycle Time (Over recommended operating conditions.3 MHz ns ns ns ns ns ns ns 2 2 100 10 µs µs ns ms Data Output Timing 2.7–5. Test Conditions Input pulse levels Input rise and fall times Input and output timing level VCC x 0. 14 FN8126. 5.64kΩ Output 1.C.5V SYMBOL fSCK tDIS tV tHO tRO tFO (4) PARAMETER Clock Frequency Output Disable Time Output Valid from Clock Low Output Hold Time Output Rise Time Output Fall Time MIN 0 MAX 3. 2006 . This parameter is periodically sampled and not 100% tested.

X5043.2 March 16. X5045 Serial Output Timing CS tCYC SCK tV SO MSB Out MSB–1 Out tHO tWL LSB Out tDIS tWH tLAG SI ADDR LSB IN Serial Input Timing tCS CS tLEAD SCK tSU SI MSB In tH tRI tFI tLAG LSB In High Impedance SO Symbol Table WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance 15 FN8126. 2006 .

92 2.62 200 MAX 4.4 MAX UNIT 100 450 1 400 100 300 800 2 ms ms sec ns tCST tRST 200 400 ms 16 FN8126. CS/WDI vs. RESET/RESET Timing CS/WDI tCST RESET (5043) tWDO RESET (5045) tRST tWDO tRST RESET/RESET Output Timing SYMBOL tWDO PARAMETER Watchdog Time Out Period. WD0 = 1 (default) WD1 = 1.62 4.1 1 MIN 4.5A) Reset Trip Point Voltage.5 4.0 2. WD0 = 1 WD1 = 0.X5043.5 3. WD0 = 0 CS Pulse Width to Reset the Watchdog Reset Time Out MIN TYP OFF 200 600 1.38 2.25 2. This parameter is periodically sampled and not 100% tested.7) Power-up Reset Time Out VCC Detect to Reset/Output VCC Fall Time VCC Rise Time Reset Valid VCC 10 0. WD0 = 0 WD1 = 0.7A) Reset Trip Point Voltage.2 March 16. 2006 .75 4.85 2. (-2. (-4. (-2. (Blank) Reset Trip Point Voltage. WD1 = 1.55 100 TYP 4. X5045 Power-Up and Power-Down Timing VCC VTRIP 0 Volts tR RESET (X5043) tPURST tPURST tF tRPD VTRIP RESET (X5045) RESET Output Timing SYMBOL VTRIP PARAMETER Reset Trip Point Voltage.7 400 500 UNIT V tPURST tRPD tF (6) ms ns µs ns V (6) (6) tR VRVALID NOTE: 6.

(Programmed at 25°C.2 March 16. 2006 .75 +25 MIN 1 1 1 1 10 10 MAX UNIT µs µs µs µs ms ms µs ms V V mV VTRIP programming parameters are periodically sampled and are not 100% tested. 17 FN8126.) 0 10 15 1.X5043. X5045 VTRIP Programming Timing Diagram VCC (VTRIP) VTRIP tTSU VP tTHD WP tVPS tVPH tVPO tPCS CS tRP SCK SI 06h 02h 01h or 03h VTRIP Programming Parameters PARAMETER tVPS tVPH tPCS tTSU tTHD tWC tVPO tRP VP VTRAN Vtv DESCRIPTION VTRIP Program Enable Voltage Setup time VTRIP Program Enable Voltage Hold time VTRIP Programming CS inactive time VTRIP Setup time VTRIP Hold (stable) time VTRIP Write Cycle Time VTRIP Program Enable Voltage Off time (Between successive adjustments) VTRIP Program Recovery Period (Between successive adjustments) Programming Voltage VTRIP Programmed Voltage Range VTRIP Program variation after programming (0-75°C).7 -25 18 4.

030 (0.00 ± 0.002 (0.81) 7° Typ.91) 0. R 0.2 March 16.05) 0.05) 0.008 (0.007 (0.30 + 0.118 ± 0.004 (0.005 (0.36) 0.002 (3.036 (0.220" FOOTPRINT 0.X5043.012 + 0.55) 0. 2006 .65) Typ.118 ± 0.014 (0.0216 (0.150 (3.81) Ref.00 ± 0. 0.0256" Typical 0.76) 0.032 (0.02 ± 0.002 (3.18) 0.90) Ref.13) 0.0256 (0.193 (4.20) 0.05) 0.006 / -0. X5045 Packaging Information 8-Lead Miniature Small Outline Gull Wing Package Type M 0.025" Typical 0. ALL DIMENSIONS IN INCHES AND (MILLIMETERS) 18 FN8126.040 ± 0.15 / -0.020" Typical 8 Places NOTE: 1. 0.10) 0. 0.05) 0.002 (1.

10) Pin 1 Index Pin 1 0. 0.62) Ref.090 (2.52) 0.430 (10.25) 0° 15° NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2.81) 0.045 (1.68) 0.25) 0.14) 0.38) 0.92) 0.065 (1.125 (3.020 (0. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 19 FN8126.325 (8.150 (3.14) 0.62) Typ.060 (1.010 (0.020 (0.025 (0.X5043.015 (0. 0.128 (3.073 (1.260 (6.51) 0.18) 0.2 March 16. 0.300 (7. 2006 .51) Half Shoulder Width On All End Pins Optional Seating Plane 0.360 (9.64) 0.65) 0.79) 0.29) .300 (7.25) 0.60) 0.145 (3. X5045 Packaging Information 8-Lead Plastic Dual In-Line Package Type P 0.016 (0.84) Max.41) 0.240 (6.110 (2.

244 (6.037 (0.25) 0.010 (0.75) 0.2 March 16.49) 0.197 (5.19) 0.00) 0.250" 0.030" Typical 8 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20 FN8126.25) X 45° 0.00) (4X) 7° 0.8° 0.010 (0.228 (5.35) 0.X5043.19) 0.004 (0.150 (3. 2006 .069 (1.25) 0.27) 0.050 (1.78) 0.50) 0.20) Pin 1 Index Pin 1 0.019 (0.016 (0.188 (4.158 (4.014 (0.0075 (0.937) 0.010 (0. X5045 Packaging Information 8-Lead Plastic Small Outline Gull Wing Package Type S 0.053 (1.050" Typical FOOTPRINT 0.35) 0.80) 0.050"Typical 0° .80) 0.410) 0.020 (0.

see www.S.80) .5) . Package Type V .50) .047 (1.010 (.15) . Accordingly.041 (1. software and/or specifications at any time without notice. nor for any infringements of patents or other rights of third parties which may result from its use. Intersil Corporation reserves the right to make changes in circuit design.252 (6.1) .019 (. X5045 Packaging Information 14-Lead Plastic.65) BSC .0118 (.intersil.031 (.3) .169 (4.193 (4.4) BSC .75) Detail A (20X) Seating Plane . TSSOP. Information furnished by Intersil is believed to be accurate and reliable. 2006 . However.002 (.177 (4.30) .19) . no responsibility is assumed by Intersil or its subsidiaries for its use.05) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) All Intersil U.X5043.006 (.com/design/quality Intersil products are sold by description only.20) .05) . products are manufactured.25) Gage Plane 0° .9) .com 21 FN8126. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products.0075 (.8° . Intersil Corporation’s quality certifications can be viewed at www.2 March 16.intersil. assembled and tested utilizing ISO9000 quality systems.029 (.200 (5.025 (. the reader is cautioned to verify that data sheets are current before placing orders.