G. H.

RAISONI COLLEGE OF ENGINEERING, NAGPUR Department of Electronics & Communication Engineering Branch:-4thSemester[Electronics And Telecommunication] Subject: - Digital Circuits List of Experiment
Sr. No. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. Name Of Experiment To study and verify the Pin configuration of the ICs: 7400, 7402 , 7404, 7408, 7432, 7486, 7496. To study and verify the Truth Table of the Basic Logic Gates. 7400, 7402 , 7404, 7408, 7432, 7486, 7496. NAND and NOR as universal gates. To study and verify the Multiplexer 8:1, Multiplexer16:1 (IC-74150). Simulate using micro-cap. To study and verify the De-Multiplexer 1:16.(IC-74154). Simulate using micro-cap To study and verify the DECODER (IC-74138). Simulate using micro-cap To study and verify the Priority ENCODER (IC-74147). Simulate using micro-cap To study and verify the BCD to Seven Segments DECODER.(IC-7447). Simulate using micro-cap. To study and verify the Decimal to BCD Encoder. (IC-74147). Simulate using micro-cap. To study and verify the Truth Tables of S-R Flip/Flop-(IC-7474), J-K Flip/Flop IC-7476), T- Flip/Flop, D- Flip/Flop. Simulate using micro-cap. To study and Simulate The Conversion of the J-K Flip/Flop to S-R Flip/Flop. Simulate using micro-cap. To study the conversion of SR Flip/Flop to D Flip/Flop. Simulate using micro-cap. To study and verify the 4 Bit shift Register.(IC-74195). Simulate using micro-cap. To study and verify the Half Adder And Full Adder.(IC-7483). Simulate using micro-cap. To study and verify the Half Subtractor and Full Subtractor. (IC-7483). Simulate using micro-cap. To study and verify the 4 Bit Adder. (IC-7483). Simulate using micro-cap. To study and verify the 4 Bit comparator. (IC-7485). Simulate using micro-cap. To study and verify the Carry Loop Ahead adder. Simulate using micro-cap.

19. 20. 21.

To study and verify the Decade Counter.(IC-7490). Simulate using micro-cap. To study and verify the Synchronous And Asynchronous Counter.(IC-7490). Simulate using micro-cap. To study and verify the UP Down Counter. (IC-7490). Simulate using micro-cap.

Experiment no: -1 Aim: - To study and verify the Pin configuration of the ICs:
7400,7402, 7404,7408,7432, 7486, 7496.

board, Wires etc.

Apparatus: - ICs 7400, 7402, 7404, 7408, 7432, 7486, 7496, power supply, bread Theory: -

Digital circuits are different from analog circuits. Almost all digital circuits are designed for two state operations. This means using only two non-adjacent points on the load line, typically saturation and cutoff. As a result the output voltage has only two states, either low or high. Thus, the digital electronics deals with binary numbers, which has only two values 1 & 0 .Logic gates are the digital circuits with one or more voltage but only one output voltage. The most basic gates are called the NOT gate, the OR gate, the AND gate. By connecting these gates in different ways, we can build circuit that performs arithmetic and other function. The symbol and truth table of various gates are given below. 1) NOT gate (IC 7404) NOT is a one input and one output logic gate. The output is given as Q = A. Truth table is shown in table. IC 7404 is an NOT gate IC contains total 6 NOT gates.

Input A 0 1

Output Q=A 1 0

2) AND gate (IC 7408) This gate has two input (A, B) and one output Q. The output is related with input as Q = A.B. Truth table is shown in table. IC 7408 is a two input AND gate IC.

Input A B 0 0 0 1 1 0 1 1

Output Q=AB 0 0 0 1

3) AND gate (IC 7411) IC 7411 is a 3 input AND gate with three inputs (A, B, C,) and only one output Q. The output is related with 3 input as Q = A.B.C. Truth table is shown in table. This IC contains 3 AND gates. Input 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Output 0 0 0 0 0 0 0 1

A B C Q = A.B.C.

4) OR gate (IC 7432) An OR gate have two inputs (A&B) and only one output Q. The output can be related with two inputs as Q = A+B. Truth table is shown in table 4. IC 7432 is a two input OR gate IC. This IC contains total 4 OR gates.

Input A 0 0 1 1 B 0 1 0 1

Output Q = A+B 0 1 1 1

5) OR gate: Table 5 A 0 0 0 0 1 1 1 1 Input B 0 0 1 1 0 0 1 1 Output Q = A+B+C 0 1 1 1 1 1 1 1

C 0 1 0 1 0 1 0 1

There is no such IC in the logic gate family which is 3 input OR gate. Although it can be constructed using 3 input NOR gate. If a NOT gate is connected to the output of NOR gate then the output are converted into OR gate. A 3 input NOR gate is obtained from IC 7427. It contains 3 NOR gates in it. A symbol of 3 input OR gate and its truth table is shown in fig. 5 and table 5 respectively. 6) NAND gate (IC 7400) Input A 0 0 1 1 Output Q = AB 1 1 1 0

B 0 1 0 1

The construction and input and output system is same as IC 7404 (given in Sr. No.2) except that output is related to the input by the equation. Q = AB Symbol and the truth table for 2 input NAND gate is shown in fig. 6 and table 6 respectively. 7) NAND gate (IC 7410) Table 7 A 0 0 0 0 1 1 1 1 Input B 0 0 1 1 0 0 1 1 Output Q = ABC 1 1 1 1 1 1 1 0

C 0 1 0 1 0 1 0 1

Theory of IC 7410 is same as IC 7411 (as given in Sir. No. 3) except that the output is related as follows. Q = ABC. The symbol of 3 input NAND gate is shown in fig. 7 where as the truth table is shown in table 7. 8) NOR gate (IC 7402) Input A 0 0 1 1 Table 8 The explanation of this IC is same as IC 7432 (given in Sr. No. 4). The output of two input NOR gate is given as Q = A+B A symbol of two input NOR gate and truth table is given in fig. 8 and table 8. B 0 1 0 1 Output Q = A+B 1 0 0 0

9) NOR gate (IC 7427) Table 9 A 0 0 0 0 1 1 1 1 Input B C 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Output Q= A+B+C 1 0 0 0 0 0 0 0

IC 7427 is a 3 input NOR gate with three input terminals A, B & C and one output terminal Q. The output is related to the three inputs as follows. Q = A+B+C This IC contains only 3 NOR gates. The truth table is shown in table 9.Using above logic gates we can solve different types of Boolean expression. NOT gate is the gate which is used to make reverse of output i.e. if input is one then it will give 0 as output and vice versa. The logical expression for NOT gate is Y= A. 10) The Exclusive-OR gate The last six gate types are all fairly direct variations on three basic functions: AND, OR, and NOT. The Exclusive-OR gate, however, is something quite different. Exclusive-OR gates output a "high" (1) logic level if the inputs are at different logic levels, either 0 and 1 or 1 and 0. Conversely, they output a "low" (0) logic level if the inputs are at the same logic levels. The Exclusive-OR (sometimes called XOR) gate has both a symbol and a truth table pattern that is unique:

There are equivalent circuits for an Exclusive-OR gate made up of AND, OR, and NOT gates, just as there were for NAND, NOR, and the negative-input gates. A rather direct approach to simulating an Exclusive-OR gate is to start with a regular OR gate, then add additional gates to inhibit the output from going "high" (1) when both inputs are "high" (1)

In this circuit, the final AND gate acts as a buffer for the output of the OR gate whenever the NAND gate' output is high, which it is for the first three input state combinations s (00, 01, and 10). However, when both inputs are "high" (1), the NAND gate outputs a "low" (0) logic level, which forces the final AND gate to produce a "low" (0) output. Another equivalent circuit for the Exclusive-OR gate uses a strategy of two AND gates with inverters, set up to generate "high" (1) outputs for input conditions 01 and 10. A final OR gate then allows either of the AND gates' "high" outputs to create a final "high" output: Exclusive-OR gates are very useful for circuits where two or more binary numbers are to be compared bit-for-bit, and also for error detection (parity check) and code conversion (binary to Grey and visa-versa).

11) The Exclusive-NOR gate Finally, our last gate for analysis is the Exclusive-NOR gate, otherwise known as the XNOR gate. It is equivalent to an Exclusive-OR gate with an inverted output. The truth table for this gate is exactly opposite as for the Exclusive-OR gate:

As indicated by the truth table, the purpose of an Exclusive-NOR gate is to output a "high" (1) logic level whenever both inputs are at the same logic levels (either 00 or 11).

Procedure: 1) 2) 3) 4) Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table.

Result: - Pin configuration of the ICs: 7400,7402, 7404,7408,7432, 7486 & 7496 are studied & verified Viva Questions: 1. What is the D Morgans law? 2. What is the Assertive Law?

Experiment no: - 2 Aim: - To study and verify the Truth Table of the Basic Logic Gates 7400, 7402, 7404,7408,7432, 7486, 7496. Apparatus: ICs 7400, 7402, 7404,7408,7432, 7486, 7496, power supply, breadboard, Wires etc.

Circuit Diagram:-

Theory:Digital circuits are different from analog circuits. Almost all digital circuits are designed for two state operations. This means using only two non-adjacent points on the load line, typically saturation and cutoff. As a result the output voltage has only two states, either low or high. Thus, the digital electronics deals with binary numbers, which has only two values 1 & 0.Logic gates are the digital circuits with one or more voltage but only one output voltage. The most basic gates are called the NOT gate, the OR gate, the AND gate. By connecting these gates in different ways, we can build circuit that performs arithmetic and other function. The symbol and truth table of various gates are given below.

1) Not gate (IC 7404) Input A 0 1 Output Q=A 1 0

NOT is a one input and one output logic gate. The output is given as Q = A. Truth table is shown in table. IC 7404 is an NOT gate IC contains total 6 NOT gates. 2) AND gate (IC 7408) Input A B 0 0 0 1 1 0 1 1 Output Q=AB 0 0 0 1

This gate has two input (A, B) and one output Q. The output is related with input as Q = A.B. Truth table is shown in table. IC 7408 is a two input AND gate IC. 3) AND gate (IC 7411) Input 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Output 0 0 0 0 0 0 0 1 A B C Q = A.B.C.

IC 7411 is a 3 input AND gate with three inputs (A, B, C,) and only one output Q. The output is related with 3 input as Q = A.B.C. Truth table is shown in table. This IC contains 3 AND gates.

4) OR gate (IC 7432) Input A 0 0 1 1 B 0 1 0 1 Output Q = A+B 0 1 1 1

An OR gate have two inputs (A&B) and only one output Q. The output can be related with two inputs as Q = A+B. Truth table is shown in table 4. IC 7432 is a two input OR gate IC. This IC contains total 4 OR gates. 5) OR gate: Input B 0 0 1 1 0 0 1 1 Table 5 C 0 1 0 1 0 1 0 1 Output Q = A+B+C 0 1 1 1 1 1 1 1

A 0 0 0 0 1 1 1 1

There is no such IC in the logic gate family which is 3 input OR gate. Although it can be constructed using 3 input NOR gate. If a NOT gate is connected to the output of NOR gate then the output are converted into OR gate. A 3 input NOR gate is obtained from IC 7427. It contains 3 NOR gates in it. A symbol of 3 input OR gate and its truth table is shown in fig. 5 and table 5 respectively. 6) NAND gate (IC 7400) A 0 0 1 1 Input Table 6 B 0 1 0 1

Output Q = AB 1 1 1 0

The construction and input and output system is same as IC 7404 (given in Sr. No.2) except that output is related to the input by the equation. Q = AB Symbol and the truth table for 2 input NAND gate is shown in fig. 6 and table 6 respectively. 7) NAND gate (IC 7410) Input B 0 0 1 1 0 0 1 1 Table 7 C 0 1 0 1 0 1 0 1 Output Q = ABC 1 1 1 1 1 1 1 0

A 0 0 0 0 1 1 1 1

Theory of IC 7410 is same as IC 7411 (as given in Sir. No. 3) except that the output is related as follows. Q = ABC The symbol of 3 input NAND gate is shown in fig. 7 where as the truth table is shown in table 7. 8) NOR gate (IC 7402) Input A 0 0 1 1 Table 8 B 0 1 0 1 Output 1 0 0 0

Q = A+B

The explanation of this IC is same as IC 7432 (given in Sr. No. 4). The output of two input NOR gate is given as Q = A+B A symbol of two input NOR gate and truth table is given in fig. 8 and table 8. 9) NOR gate (IC 7427) Table 9 A 0 0 0 0 1 1 1 1 Input B C 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Output Q= A+B+C 1 0 0 0 0 0 0 0

IC 7427 is a 3 input NOR gate with three input terminals A, B& C and one output terminal Q. The output is related to the three inputs as follows. Q = A+B+C This IC contains only 3 NOR gates. The truth table is shown in table 9. Using above logic gates we can solve different types of Boolean expression. NOT gate is the gate which is used to make reverse of output i.e. if input is one then it will give 0 as output and vice versa. The logical expression for NOT gate is Y= A

Procedure: 1. 2. 3. 4. Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table.

Simulation: -

Result:Truth Table of all the gates are verified.

Viva Questions:1. 2. What is the Logic Gate? What are the different Types of the Logic Gate?

Experiment no:- 3 Aim:- To study and verify the NAND And NOR as a Universal Gates (7400, 7402). Apparatus: - IC 7400, 7402, power supply, breadboard, wires etc. Circuit Diagram:-

Theory: NAND gate and NOR gate are called as universal gates because every basic gate can be constructed using these gates 1. NAND gate: - Logic Equation Y = A. This gate gives an output of 1 if all of its inputs are 0 or any one of them is 0. In fact it a NOT of AND gate. It is constructed by connecting a NOT gate at the output of AND gate. A] NAND as NOT gate: - NOT gate can be constructed using NAND gate by connecting both its inputs together.

Y = A.A = A B] NAND as AND gate: - AND gate is constructed by connecting NAND as NOT gate at the output of NAND gate. Y = A.A = A C] NAND as OR gate: - Y = A. B = A+B ____ NOR gate: - Logic Equation Y= A+B This gate gives an output of 1 if all of its inputs are 0.If any of the input is 1 then o/p will be 0. A] NOR as NOT gate:-It is constructed by connecting both its input together. Y = A+A = A B] NOR as OR gate: - It is constructed by connecting a NOR as NOT gate at the output of a NOR gate. Y = A+B =A+B C] NOR as AND gate: - Y = A + B = A.B = A.B A) NOT Gate: A NOT gate is a gate with only one I/p and one o/p. It is also called an Inverter because the o/p is always opposite to the I/p i.e. when the I/p voltage is high (logic 1), the o/p is low (logic 0). On the other hand when the I/p voltage is low (logic 0) the o/p is high (, logic 1).The relation between I/p state & o/p state of a NOT gate are shown in following truth table. Fig (1) shows the symbol of NOT gate. I/P 0 1 A O/P 1 0 Y=A

2.

B) OR Gate: An OR gate has two or more I/p and only one o/p. It is called an OR gate because the o/p voltage is high (logic 1) if any or all of the I/p are high (logic 1) and the o/p becomes low (logic 0) only when all the I/p are low

(logic 0).

Fig (2) shows the symbol and truth table for 2 I/p OR gate is given in table (2).

TRUTH TABLE I/P O/P A B Y=A+B 0 0 0 0 1 1 1 0 1 1 1 1 C) AND Gate: AND gate has two or more i/ps and only one o/p. The o/p is high (logic 1) only when all i/ps are high (logic 1) and o/p becomes low (logic 0) when booth or any one I/p are low (logic 0).Fig (3) shows the symbol and table of two I/p AND gate. TRUTH TABLE I/P A 0 0 1 1 D) NAND GATE:TRUTH TABLE I/P O/P A B Y=A+B 0 0 1 0 1 0 1 0 0 1 1 0 E) NOR GATE:TRUTH TABLE I/P O/P A B ____ Y=A+B B 0 1 0 1 O/P Y=A.B 0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

Simulation:-

Result:The basic logic gates are successfully constructed using NAND and NOR gates this verifies that they are universal gates.

Viva Questions:1. What is the Demultiplexer? 2. What is the code converter?

Experiment no: - 4 Aim: - To study and verify the multiplexer 8:1, Multiplexer16: 1 (IC-74150).
Simulate using micro-cap.

Apparatus: - 16:1 MUX IC 74150, 8:1 MUX IC 74152, DC Supply Voltage (+5v). Circuit Diagram:-

Theory:A multiplexer is a circuit with many inputs but only one output. i.e. Multiplex means many into one. By applying control signals, we can select any into to the output figure (1) illustrates the general idea. The circuit has n input signals m control signals & Only One Output signal..A3A2A1A0 =0000, then complement of data I/P D0 is transmitted at the output

Control signal

n input Signal
Multiplexer

O/P Signal

Fig 1: - Block Diagram of Multiplexer The 16:1 multiplexer has 16 input bits, 4 control bits and 1 output bit. IC 74150 is a 16:1 TTL multiplexer with the pin diagram shown in fig.2. This is a 24 pin IC. It has 16 Data Input D0 D15, Four Control (Select) A3 A2, A1 A0 I/P signal and one O/P (Y), which is Compliment of Selected Data, with pins Diagram Shown in Figure(2). The pin 9 is active Low Enable/Strobe I/P. A low enable/strobe enables the Multiplexer. But a high strobe disable O/P becomes high If strobe/Enable is low, then o/p Y equals the complement of the Data I/P depending upon the control Signal A3A2A1A0, Data I/P D0 D15 is Transmitted at the O/P which is compliment of this Data as shown in the Truth Table Y = Dn Where n is the decimal equivalent of A3A2A1A0 Control Signals. A3A2A1A0 =0000, then complement of data I/P D0 is transmitted at the output Y = D0 If D0 is low, Y will be high If D0 is high, Y will be low Similarly If A3A2A1A0 = 1111 then Y = D15

D15 is high/low then O/P Y becomes low / high respectively.

IC 74150 D7 D6 D5 D4 D3 D2 D1 D0 EN Y A3 1 2 3 4 5 6 7 8 9 10 11 12 16:1 MUX IC 74150 24 23 22 21 20 19 18 17 16 15 14 13 +V D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2

GND

Fig 2: Pin out diagram of IC 74150

Procedure: 1. Study the circuit diagram. 2. Connect the circuit as shown in fig. by using connecting wires. 3. Switch ON the power supply. 4. Apply the corresponding inputs and verify the truth table.

Observation Table:Enable/ Strobe I/P 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Truth Table Control Signal A3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 O/P Y

Simulation:-

Result: The Multiplexer 16:1 and 8:1 is studied and truth table is verified.

Viva Questions: 1. What is the Combinational Logic Design? 2. What is the difference between the Sequential & the combinational Logic circuit?

Experiment no:- 5 Aim:- To study and verify the De-Multiplexer 1:16.(IC-74154).

Simulate using micro-cap

Apparatus: - IC-74154, breadboard, wires etc. Circuit Diagram:A0 A1 A2 74LS138 DEMUX o ENABLE o
O

D0 D1 D2 D3 D4 D5 D6 D7

Theory: The demultiplexer performs the reverse operation of a multiplexer. It accepts single input and distributes it over several outputs. Fig shows the diagram of demultiplexer. The select input code determines to which output the data input will be transmitted the number of output lines is n and the number of select lines is m where n=2m. The data bit is transmitted to the data bit of the output lines and this depends on the value of ABCD, the control input. When ABCD=0000, the upper AND gates is enabled while all other gats are disabled. Therefore, data bit is transmitted only to the Y0 output, giving Y0=0. If D is low Y0 is low. If D is high, Y0 is high. If the control ABCD is changed to ABCD =1111, all the gates are disabled except the bottom AND gate. The D is transmitted only to the Y15 output and gives y15=Din this way the output depends on the value of D. The demux circuits are used in binary to decimal decoder. The multiplexer with gates are used to realize the Boolean expression in standard SOP form. The IC 74LS138 can be used as DEMUX.

Procedure:1. 2. 3. 4. Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table.

Observation Table:Enable 1 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 D0 D1 D2 D3 D4 D5 D6 D7

Result:The De-Multiplexer 1:16.(IC-74154) is studied and simulated using microcap. Viva Questions:1. How the Karnaugh map is importance in the Digital Circuit? 2. How the Sum of the product is implementing in the Karnaugh map?

Experiment no: - 6 Aim: - To study and verify the DECODER (IC-74138). Simulate using micro-cap Apparatus:- Bread board, connecting wires, power supply, IC 74138. Circuit Diagram:A0 A1 A2 74LS138 DECODER o o
O

D0 D1 D2 D3 D4 D5 D6 D7

ENABLE

Theory:A decoder is a logic circuit an n-bit binary input code into M output lines such that only one is output is activated at a time for possible combinations of inputs. Consider the decoder on which three inputs and eight outputs are present. For active HIGH circuit AND gate is used. For active low circuit the NAND gate is used. The decoder is called as 3 to 8 line decoder because it has three input lines and eight output lines. Some decoders have one or more ENABLE inputs that are used to control the operation of the decoder .

Procedure:1. 2. 3. 4. Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table.

Observation Table: E3 0 1 1 1 1 1 1 1 1 E2 1 0 0 0 0 0 0 0 0 E1 1 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 D0 D1 D2 D3 D4 D5 D6 D7

Result: - The DECODER (IC-74138). Is studied & verified Viva Questions:1. What is the Different Application of the Combinational Logic circuit? 2. What is the SSI circuit?

Experiment no:- 7 Aim :- To study & verify the Priority ENCODER (IC-74147). Simulate using micro-cap Apparatus:- IC 74147, Bread board, connecting wires, power supply etc. Circuit Diagram:_____ +VCC ___ D0 ___ Q3 _____ D3 ____ D2 ___ D1 ___ D9 ___ Q0

16

15

14

13 IC 74147

12

11

10

___

___

__

___

___

___

___

___

D4

D5

D6

D7

D8

Q2

Q1

GND

Theory:The encoder is a device whose inputs are decimal digits and outputs are the coded representation. The encoder has 10 inputs and 4 out puts corresponding to BCD code. A basic 10 line to 4 line encoder shown above. It performs the operation reverse of the decoder. The encoder has number of input lines and one of which is activated at a given time and produces an N bit out put code depending on which input is activated. In a simple encoder it is assumed that only one input line is equal to 1 at any given time. If a situation arises whether more than one i/p is high then the encoder will not function properly. To tackle such a situation a priority encoder is used. These encoders establish an input priority to insure that only the highest priority input line is Encoded. Thus if a priority is given to an input with a higher subscript number over the one with a lower subscript number. Then if both D2 and D5 at logic1 simultaneously, the output will be 101 because D5 has higher priority over D2. IC 74147 is a active low IC .Therefore when logic 0 is applied to any input that input will be active and corresponding output is obtained which is compliment of usual output.

Procedure:1. 2. 3. 4. Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table.

Observation Table:Dec 0 0 1 2 3 4 5 6 7 8 9 D0 1 0 x x x x x x x x x D1 1 1 0 x x x x x x x x D2 1 1 1 0 x x x x x x x D3 1 1 1 1 0 x x x x x x D4 1 1 1 1 1 0 x x x x x D5 1 1 1 1 1 1 0 x x x x D6 1 1 1 1 1 1 1 0 x x x D7 1 1 1 1 1 1 1 1 0 x x D8 1 1 1 1 1 1 1 1 1 0 x D9 1 1 1 1 1 1 1 1 1 1 0 Q3 Q2 Q1 Q0

Result:The Priority ENCODER (IC-74147) is studied and verified

Viva Questions:1. What is encoder? 2. Who will set the priority?

Experiment no:- 8 Aim:- To study and verify the BCD to Seven Segments DECODER.(IC-7447).
Simulate using micro-cap.

Apparatus:-

IC 7447, segment display, power supply, bread board , IC 74147, wires

Circuit Diagram:-

Theory:7 1 2 6 3 5 4 A B C D OA OB OC OD OE
O

o o o o o o

13 12 11 10 9 15 14

LT o OF o RBI OG o BI/RBO 7447N

Seven Segment Display consists of 7 LEDs in form of segments that are physically arranged like decimal 8. There is one circular LED connected either in common cathode configuration or in common anode configuration by giving logic 1/0 to anode configuration by giving logic 0/1 to cathode LED can be made ON/OFF respectively. When 4 bit BCD number is applied to input of decoder, then decoder will be corresponding 7 bit output Ya to Yg. If these 7 bits are applied to 7 LEDs of seven

segment display and if this seven segment display is connected in common cathode configuration, then to make LED ON/OFF decoder will give 1/0 to anode of LED.

Procedure:1) Connect the circuit diagram as per the circuit diagram. 2) Vary the input with 4 switches from 0 to 9 (valid BCD number). 3) The corresponding number of BCD number will be displayed.

Observation Table:A 0 0 0 0 0 0 0 0 1 1 Inputs B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 D 0 1 0 1 0 1 0 1 0 1 a b c Outputs d e f g

Simulation:-

Result:BCD to Seven Segment Decoder is studied.

Viva Questions:1. List the various char. of the Display devices? 2. List the Standard Configuration of the gate as SSI/MSI/VLSI circuit

Experiment no:- 9 Aim:- To study and verify the Decimal to BCD Encoder.(IC-74147).
Simulate using micro-cap.

Apparatus:- Power supply, bread board , IC 74147, wires etc Circuit Diagram:-

Theory:An encoder performs a function which is inverse to the function performed by a decoder. An encoder has 2n input lines and n output lines. The output lines generate the binary code for the 2 n input variables .In an encoder it is assumed that only one input line can be equal to at any time.

Priority Encoder: In a simple encoder it is assumed that only one input line is equal to 1 at any given time. If a situation arises whether more than one i/p is high then the encoder will not function properly. To tackle such a situation a priority encoder is used. These encoders establish an input priority to insure that only the highest priority input line is encoded. Thus if a priority is given to an input with a higher subscript number over the one with a lower subscript number. Then if both D2 and D5 at logic1 simultaneously, the output will be 101 because D5 has higher priority over D2. IC 74147 is a active low IC .Therefore when logic 0 is applied to any input that input will be active and corresponding output is obtained which is compliment of usual output.

Truth Table :dec 0 0 1 2 3 4 5 6 7 8 9 D0 1 0 x x x x x x x x x D1 1 1 0 x x x x x x x x

D2 1 1 1 0 x x x x x x x

D3 1 1 1 1 0 x x x x x x

D4 1 1 1 1 1 0 x x x x x

D5 1 1 1 1 1 1 0 x x x x

D6 1 1 1 1 1 1 1 0 x x x

D7 1 1 1 1 1 1 1 1 0 x x

D8 1 1 1 1 1 1 1 1 1 0 x

D9 1 1 1 1 1 1 1 1 1 1 0

Q3 1 1 1 1 1 1 1 1 1 0 0

Q2 1 1 1 1 1 0 0 0 0 1 1

Q1 1 1 1 0 0 1 1 0 0 1 1

Q0 1 1 0 1 0 1 0 1 0 1 0

_____ +VCC

___ D0

___ Q3

_____ D3

____ D2

___ D1

___ D9

___ Q0

16

15

14

13 IC 74147

12

11

10

___

___

__

___

___

___

___

___

D4

D5

D6

D7

D8

Q2

Q1

GND

Procedure:1 ) Connect the input lines D0,D1,----------,D9 to the power supply (0 or 1). 2) Now apply logic 0 to all input lines one by one and observe the output _ _ _ _ Q3 Q2 Q1 Q0. 3) The output is compliment of usual output.

Observation Table:dec 0 0 1 2 3 4 5 6 7 8 9 D0 1 0 x x x x x x x x x D1 1 1 0 x x x x x x x x D2 1 1 1 0 x x x x x x x D3 1 1 1 1 0 x x x x x x D4 1 1 1 1 1 0 x x x x x D5 1 1 1 1 1 1 0 x x x x D6 1 1 1 1 1 1 1 0 x x x D7 1 1 1 1 1 1 1 1 0 x x D8 1 1 1 1 1 1 1 1 1 0 x D9 1 1 1 1 1 1 1 1 1 1 0 Q3 Q2 Q1 Q0

Simulation:-

Result:-

The decimal to BCD encoder is studied.

Viva Questions:-

1. Differentiate between decoder and encoder. 2. Give any two application of each.

Experiment no: - 10 Aim: - To study and verify the Truth Tables of S-R Flip/Flop (IC-7474), J-K Flip/Flop.
IC-7476), T- Flip/Flop, D- Flip/Flop. Simulate using micro-cap.

Apparatus:- Digital Multimeter, Patch Chords, IC 7400 NAND gate IC, IC 7402
NOR gate IC, IC 7404 NOT gate IC, LED.

Circuit Diagram:-

Theory: A flip-flop is a bistable electronic circuit that has two stable states i.e. its output is either 0 or +5Vdc. The main difference between the analog and digital circuit is that, the digital circuits are designed for two state operations. That means the O/p of the digital circuit has only two states (values), either low or high. In other words the O/p of the digital circuit changes when the I/p changes. However, there are requirements for a digital device or circuit. Whose O/P will remain unchanged, once set, even if there is a change in input. A flip-flop is one such circuit, whose O/p will remain unchanged once set. There are basic three types of Flip-Flops 1. SR Flip-Flop 2. D Flip-Flop 3. JK Flip-Flop A flip-flop is a bistable electronic circuit that has two stable states i.e. its output is either 0 or +5Vdc. One of the easiest methods to construct a flip-flop is to connect two inverters in series. But basic flip-flop can be improved by replacing two inverters with either NAND or NOR gate. The additional input of these gates provides a conventional means for application of input signals to switch the flip-flop from one stable state to another.

Two input NAND gate are connected to from flip-flop circuit. These two inputs are R& S. The flip-flop has two outputs terms as Q and Q. If flip-flop is put into one state it will remain in that state as long as power is applied or until tit is changed. In digital circuit, flip-flops are used in variety of storage, counting, sequencing and timing application. 1. R- S Flip-Flop:The R-S flip-flop is the simplest. It has two inputs, S & R input; it will put the latch into one state or the other. When a flip-flop is set by S input, it is said to be storing binary 1. (O/P = high). When reset by R input, it is said to be storing binary 0 ( O/P = low). An RS flip-flop constructed by cross- coupling two NAND gates as shown in fig. Fig shows the symbol of the R-S flip-flop. Both Q& Q output goes high, when both R-S inputs are binary 0. This condition is not allowed in normal use of flip-flop, as the Q represents the complement output of Q. The truth table for RS flip-flop is given in table. Truth Table:Input R 0 0 1 1 S 0 1 0 1 Q Q 0 0 0 1 1 0 Not determinant Output

2. Study D Flip-Flop: The R S Flip flop has two data inputs R & S. Generation of two signals to drive a flipflop is a disadvantage in much application. Furthermore, the forbidden condition of both R and S high may occur inadvertently. This has lid to the D Flip Flop a circuit that needs only a single data input. Fig shows the simple diagram of D Flip- Flop using NOR Gate. Truth Table:Input D 0 1 Output Q 0 1

In this circuit the D input is just transferred to the output e.g. If D =0 then output Q is also & If D = 1 output is also 1, as shown in the truth table.

3. Study of T Flip Flop: The basic digital memory circuit is known as flip flop. It two stable states which are known as the 1 state 0 state. It can be obtained by using NAND or NOR gates. Generally there are two inputs to the flip flops (R, S or J K) and two outputs Q and Q. The outputs Q and Q are always complementary. The circuit has two stable state Q=1 which is referred to as the 1 state( or set state ) whereas in the other stable state Q=0 which is referred to as the 0 sate ( or reset state ) If the circuit is in 1 state. It continues to remain in this state and similarly if it is in 0 state, it continues to remain in this state. This property of the circuit is referred to as memory, that is it can store 1 bit of digital information. In a JK flip flop, if J=K the resulting flip flop is referred to as a T Flip Flop, as shown in fig. it has only input, referred to as T input. Its truth table is given in table 1. If T=1 it acts as a toggle witch for every clock pulse the output Q changes. Truth Table: Input Output T 0 1 4. J-K Flip-flop:JK Flip-Flop is the most versatile binary strange element. It can perform all the functions of SR and D flip-flop. The uncertainty in the State of SR Flip- Flop when S = R = 1 can be eliminated by using JK Flip-Flop Truth Table Input J 0 0 1 1 K 0 1 0 1 Output Q Qn 0 0 Qn Q 1 0

Procedure: 1. 2. 3. 4. 5. 6. Study the circuit diagram. Connect the circuit as shown in fig i.e. JK Flip Flop by using connecting wires. Switch ON the power supply. Apply proper I/P to J & K I/Ps of Flip-Flop from Logic I/P Check the O/P on Logic O/P Section. Change the I/P & Verify the Truth Table.

Observation Table: Input S 0 0 1 1 1 R 0 1 0 1 1 Output Q Input D 0 1 Output Q

Input J 0 0 1 1

K 0 1 0 1

Output Q

Input Output T Q 0 1

Result:Thus R-S Flip-Flop without clock is studied and Truth table is verified. Thus D Flip-Flop without clock is studied and Truth table is verified. Thus Clocked T Flip-Flop is studied and truth table is verified. The JK Flip-Flop using NAND gate is studied and the Truth Table is verified

Viva Questions:1. What is the Latch? 2. What is the Race around condition in the Flip Flop?

Experiment no: - 11 Aim:- To study and Simulate The Conversion of the S-R Flip/Flop to JK Flip/Flop. Simulate using micro-cap. Apparatus:- Bread board, connecting wires, power supply, IC 7400. Circuit Diagram: -

Theory: The R-S flip-flop is the simplest. It has two inputs, S & R input; it will put the latch into one state or the other. When a flip-flop is set by S input, it is said to be storing binary 1. (O/P = high). When reset by R input, it is said to be storing binary 0 (O/P = low). An R-S flip-flop constructed by cross- coupling two NAND gates as shown in fig . Fig shows the symbol of the R-S flip-flop. Both Q& Q output goes high, when both R-S inputs are binary 0. This condition is not allowed in normal use of flip-flop, as the Q represents the complement output of Q. The truth table for RS flip-flop is given in table. Design is possible from one flip flop to another flip-flop. . Truth Table: Input R 0 0 1 1 S 0 1 0 1 Q Q 0 0 0 1 1 0 Not determinant Output

J-K Flip-flop: JK Flip-Flop is the most versatile binary strange element. It can perform all the functions of SR and D flip-flop. The uncertainty in the State of SR Flip- Flop when S = R = 1 can be eliminated by using JK Flip-Flop Truth Table Input J 0 0 1 1 K 0 1 0 1 Output Q Qn 0 0 Qn

Procedure: 1. 2. 3. 4. Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table.

Observation Table:Table for JK using SR Input Output J K Q 0 0 0 1 1 0 1 1

Result:- Conversion of SR flip into JK flip is studied. Viva Questions:1. What is the difference between the Delay &Toggle Flip flop? 2. Explain the concept of the clock in the Digital circuit?

Experiment no: - 12 Aim: - To study conversion of SR Flip/Flop to D Flip/Flop. Simulate using micro-cap. Apparatus:- SR flip flop, power supply, patch cords, IC 7400. Circuit Diagram:-

Theory: There are basic three types of Flip-Flops 1. SR Flip-Flop 2. D Flip-Flop 3. JK Flip-Flop A flip-flop is a bistable electronic circuit that has two stable states i.e. its output is either 0 or +5Vdc. One of the easiest methods to construct a flip-flop is to connect two inverters in series. But basic flip-flop can be improved by replacing two inverters with either NAND or NOR gate. The additional input of these gates provides a conventional means for application of input signals to switch the flip-flop from one stable state to another. Two input NAND gate are connected to from flip-flop circuit. These two inputs are R& S. The flip-flop has two outputs terms as Q and Q. If flip-flop is put into one state it will remain in that state as long as power is applied or until tit is changed. In digital circuit, flip-flops are used in variety of storage, counting, sequencing and timing application. 1. R- S Flip-Flop:The R-S flip-flop is the simplest. It has two inputs, S & R input; it will put the latch into one state or the other. When a flip-flop is set by S input, it is said to be storing binary 1. (O/P = high). When reset by R input, it is said to be storing binary 0 ( O/P = low). An RS flip-flop constructed by cross- coupling two NAND gates as shown in fig .

Fig shows the symbol of the R-S flip-flop. Both Q& Q output goes high, when both R-S inputs are binary 0. This condition is not allowed in normal use of flip-flop, as the Q represents the complement output of Q. The truth table for RS flip-flop is given in table. Truth Table: Input R 0 0 1 1 S 0 1 0 1 Q Q 0 0 0 1 1 0 Not determinant Output

2. Study D Flip-Flop:The R S Flip Flop has two data inputs R & S. Generation of two signals to drive a flipflop is a disadvantage in many application. Furthermore, the forbidden condition of both R and S high may occur inadvertently. This has lid to the D Flip Flop a circuit that needs only a single data input. Fig shows the simple diagram of D Flip- Flop using NOR Gate. Truth Table: Input D 0 1 Output Q 0 1

In this circuit the D input is just transferred to the output e.g. If D =0 then output Q is also & If D = 1 output is also 1, as shown in the truth table.

Procedure: 1. 2. 3. 4. Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table.

Observation Table:Input S=R= D 0 1 Output Q

Result: The conversion of SR to D flip flop is studied.

Viva Questions: 1. Explain the Memories organization in the Digital circuit? 2. What is the Memory?

Experiment no:- 13 Aim:- To study and verify the 4 Bit shift Register,IC-7495)
Simulate using micro-cap.

Apparatus: - Bread board, connecting wires, power supply, IC 7495, LEDs,

resistor.

Circuit Diagram: -

Theory: A register is a device, which is used to store information in the form of binary bits. A register in which stored data can be shifted from one flip flop to another is called as shift register .A register in which data is shifted left is known as left shift register and vice versa for the shift right register. The one I which data is shifted in both directions is known as bi-Directional shift register. If the data is stored into the flip flop bit by bit then it is called as serial in & if all the input bits are applied t the same time then it is called as parallel in If data is required bit by bit then it is called as serial out & if all the bits are used together then it is called as parallel out. The applications of shift registers are: 1) To store the data 2) Shifting the data 3) Transmitting from one line to parallel line & vice versa.

There are basically 4 shift registers: Serial in serial out Serial in parallel out Parallel in parallel out Parallel in serial out

Procedure: Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table. When switches are adjusted at high or low the LED glows towards right or towards left. 6. Direction of glowing of LEDs shows the right shifting operation. 1. 2. 3. 4. 5.

Result: - The operation of Shift register is studied. Viva Questions: 1.What is the EPROM memory? 2.What is the EEPROM memory?

Experiment no:- 14 Aim: - To study and verify the Half Adder & Full Adder. Simulate using micro-cap. Apparatus: - Power supply, bread board, IC 7404, IC 7408, IC 7486, IC 7432, wires Circuit Diagram: -

Theory: Half & Full Adder By combining logic gate in the right way we can built circuits that can add and subtract binary bits. In binary system, any number can be represented with the combination of any digits 0 and 1 as own up binary addition table. 0+0=0 1+0=1 0+0=1 1+1=0, carry=1 Half Adder: Fig shows, a block symbol of half adder. Outputs A (sum) Half B Adder Co (carry out)

Inputs

Fig (1) Block symbol of half adder

Truth Table:A 0 0 1 1 Inputs B 0 1 0 1 Output Co Sum 0 0 1 0 1 0 0 1

The output of the X-Or gate is called the () sum O/P while the O/P of the AND gate is the Carry (Co) The AND gate produce a high O/P only when both I/Ps are high (logic 1). The X-OR gate produces a high O/P if, either of I/P is high. A & B=0. _ _ Output sum = A.B + A.B = 0.0 + 0.0 = 1.0 + 0.1 =0+0 Sum = 0 Output carry = A .B Co = 0. 0 Co =0 Hence For A =0, B=0, sum= 0 & Co = 0. If A=0, B=1 Output carry = A.B

= 0.1 =0

Hence If A =0 & B=1, l then sum = 1 & carry = 0 Similarly if A = 1, B = 0 then Output sum = 1 Output carry = 0 If A & B =1 then. Output sum = 0 & Output carry =1 (to next MSB)

For Full Adder:Half adder circuit is used to add two bits at a time. A full adder circuit is used for addition of three at a time giving sum and carry out. Following fig. 1 & 2 shows the Block schematic and logical diagram of Full Adder. C in I/Ps A B Truth Table:Cin 0 0 0 0 1 1 1 1 Full Adder Cin + A+ B Sum = A B Cin O/Ps Co = carry = A.B + Cin.(A B)

Inputs A 0 0 1 1 0 0 1 1

B 0 1 0 1 0 1 0 1

Output 0 1 1 0 1 0 0 1

Co 0 0 0 1 0 1 1 1

Consider any case of input combination. e.g. Cin = 1, B =0, A = 1 Now refer fig (2). _ _ Output of P gate, Y 1 = A.B + A.B. = 1.1 + 0.0 =1 Q gate, Y2 = A.B = 1. 0 =0 F S gate, Y3 = Cin. Y1 = 1.1 =1 Sum =Cin. Y1 = Y1.Cin =1.0 = 0.1 = 0+0 =0 Carry out Co. = Y3 +Y2 =1+0 =1 For cin =1,B =0 & A =1, then Sum O/P = 0 and carry O/P=1.

Procedure: 1) 2) 3) 4) Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table.

Observation Table: For Half Adder: Inputs B 0 1 0 1 Output Co Sum

A 0 0 1 1

For Full Adder: Cin 0 0 0 0 1 1 1 1 Inputs A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 Output Sum Co

Simulation: -

Result:The circuit for half adder and full adder is studied and the truth table is verified.

Viva Questions: 1) How the multiplexer is used as the Function Generator? 2) What is Flip Flop?

Experiment no: - 15 Aim: - To study and verify the Half Subtractor and Full Subtractor.
Simulate using micro-cap.

Apparatus: -Bread board, connecting wires, power supply, ICS 7400,7402,7404,7408,

7486.

Circuit Diagram: -

Theory: By combining logic gate in the right way we can built circuits that can add and subtract binary bits. Binary systems there are only are only two numbers, 0 & 1. There are four basic cases of binary Subtraction. Half Substractor Half subtract or is a logic circuit that performs the subtraction of one Binary bit only. It Subtracts B (Subtracted) from A (minuend) and generates the difference (D) and borrow (Bo). Following figure shows the block systematic of half substractor A Input B Half Subtractor D (Difference) B (Borrow)

Fig 1:- Symbols for Half Substractor _ _

Difference (D) = AB + AB Barrow (Bo) = AB A 0 0 1 1 Input Output Bo 0 1 0 0

B 0 1 0 1

D 0 1 1 0

The output of the Ex-OR gate called differences while the o/p of AND gate is the barrow. Consider 1st Condition _ _ O/P Difference =AB + AB = 1.0 + 0.1 =0 O/P of Borrow = A.B. = 1.0 =0 = A=0, B=1 _ _ I/P Differences = A.B + A.B = 0.0 + 0.1 = 1. 1 + 0. 0 =1 _ O/P of Borrow = A.B. = 1.1 =1 A=1, B=0 _ _ O/P difference = A.B +A.B = 1.0 +1.0 = 0.0 +1.1 =1 Difference =1 O/P of Barrow = A.B. = 1.0 =0 Bo = 0 A=1, B=1 _ _ O/P difference = A.B + A.B = 1.0 + 1.0

=0 D=0 _ O/P of Borrow = A.B. = 1.1 =0 So, Bo is 0 FULL SUBTRACTOR Substractor is a Logic Circuit that performs the Subtraction of 3 bits, where A (minuend), B and Cn-1 (borrow from previous Stage) are the I/Ps and Difference (D) and Borrow (Bo) are Following Fig shows the block schematic of Full Substractor. A B Full Substractor (A-B-Cn-1) D Bo (Borrow)

Cn-1 (Borrow form Previous Stage)

Basic symbol of full subtractor Cn-1 0 0 0 0 1 1 1 1 Inputs B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 Output D 0 1 1 0 1 0 0 1 Bo 0 1 1 1 0 0 0 1

Procedure: 1) 2) 3) 4) Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table.

Observation Table: Half subtractor: A 0 0 1 1

Input

B 0 1 0 1

D 0 1 1 0

Output Bo 0 1 0 0

Full Subtractor: -

Inputs Cn-1 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

Output D

Bo

Simulation: -

Result: The circuit for half adder and full adder is studied and the truth table is verified

Viva Questions: 1) List the Standard Configuration of the gate as SSI/MSI/VLSI circuit? 2) What is the Karnaugh map?

Experiment no: - 16 Aim: - To study and verify the 4 Bit Adder. (IC-7483). Simulate using micro-cap. Apparatus: - Breadboard, connecting wires, power supply, IC 7483. Circuit Diagram:-

Theory:A full adder capable of adding two 1 bit binary nos. and carry in. When two n-bit binary numbers are to be added., the number of full adder required will be equal to the number of bits n in each number. The addition of LSB can be done by half adder or full adder (with making carry ground). A parallel adder is used to add to two numbers in parallel form and to produce the sum of bits as parallel output. A block diagram of 4 bit is shown above it is capable of adding of two 4 bit numbers designated as A3 A2A1A0 and B3B2B1B0. The resulting output sum bits are S3S2S1S0. A3 B3 Cin A2 B2 Cin A1 B1 Cin A0 B0 Cin

FA3

FA2

FA1

FA0

Cout Cout S3 S2

Cout S1

Cout S0

Procedure:1) 2) 3) 4) Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table.

Observation Table:Input A3A2A1A0

Input Output B3B2B1B0 S3S2S1S0

Result: Two 4 Bit numbers are added using 4 bit Adder and result is verified.

Viva Questions:1. What is Lock Free state in counter? 2. Explain BCD adder.

Experiment no: - 17 Aim: - To study and verify the 4 Bit comparator (IC-7485). Simulate using micro-cap. Apparatus: - Breadboard, connecting wires, power supply, IC 7485 Circuit Diagram:B2 A2 (A=B)OUT (A>B)IN (A<B)IN (A=B)IN A1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC A3 B3 (A>B)OUT (A<B)OUT B0 A0 B1

7485 Theory: Comparator is a logic circuit, used to compare the magnitudes of two binary numbers, depending on the design, it may either simply provide an output that is active when the two numbers are equal, or additionally provide outputs that signify which of the numbers is greater when equality does not hold X-NOR gate is a basic comparator, because its output is 1 only if its two input bits are equal, i.e. the output is a 1 if and only if the input bit coincides. Fig shows the operation of an X-NOR gate is a comparator. Two binary numbers are equal, if and only if all their corresponding bits coincide. For example, two 4-bit binary numbers A3A2A1Ao and B3B2B1Bo are equal, if and only if A3=B3, A2=B2, A1=B1 and A0=B0.Thus, equality holds when A3 coincides with B3, A2 coincides with B2, A1 coincides with B1, and Ao coincides with Bo. The implementation of this logic.

Procedure: 1) 2) 3) 4) Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table.

Observation Table: SR.NO. A3A2A1A0 1 2 3 4 B3B2B1B0 A<B A>B A=B

Result: The 4 Bit comparator. (IC-7485).is studied & verified

Viva Questions: 1.What is the Combinational Logic Design? 2.What is the difference between the Sequential & the combinational Logic circuit?

Experiment no: - 18 Aim: - To study and verify the Carry Loop Ahead adder. Simulate using micro-cap. Apparatus: - Bread board, connecting wires, power supply, IC 7486,7432,7408. Circuit Diagram: -

Theory: In case of the parallel adder, the speed with which an addition can be performed is governed by the time required for the carriers to propagate or ripple through all of the stages of the adder. The look-ahead carry adder speeds up the process by eliminating this ripple carry delay. It examines all the input bits simultaneously and also generates the carry-in bits for all the stages simultaneously. The method of speeding up the addition process is based on the two additional functions of the full-adder, called the carry generate and carry propagate functions. The carry generate (CG) functions indicates as to when a carryout would be generated by the full adder. A carry-out is generated only when both the input bits are one. This condition is expressed as the AND functions of the two input bits A and B. Thus, CG=A.B. A carry-in may be propagated by the full adder when either or both of the input bits are 1.This condition is expressed as the AND functions of the two inputs A and B. Thus CP=A+B

The Look Ahead Carry Adder: -

Procedure: 1) 2) 3) 4) Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table.

Observation Table: A B Cin C CG=A.B CP=A+B

Result: Carry lookahead adder is studied and verified

Viva Questions: 1) What is the UP counter? 2) What is the Down counter?

Experiment no: - 19 Aim: - To study and verify the Decade Counter (IC-7490). Simulate using micro-cap. Apparatus: - IC-7490, Digital Multimeter, Patch Chords Circuit Diagram:-

Theory: Sequential logic circuits are used for a variety of things, sequencing and storage functions. The O/P of sequential logic circuits is combined function of the various I/p states and the result of previous operation, which are stored in the circuit it self. The sequential operations are generally sequenced by a clock signal. A counter driven by clock can be used to count the number of clock cycles. A decade counter is sequential circuit that counts by tens. It has ten discrete states which represent decimal numbers from 0 to 9. The integrated circuit 7490 a decade counters using the standard 8421 binary code. But reset to 0000 on the tenth count. Following fig shows the pin configuration of IC 7490. IC 7490 internally consists of Mod-2 & Mod-5 Converters. It has two reset pins i.e.R1 & R2 pin no. 2 & 3 respectively. Both the pins to be connected to logic 1 for clearing o/p. The IC can be reset to 0000 by giving appropriate (high & low) input which are shown in truth table. For counting both inputs either R1 and S1 OR R2 and S2 must be low.

INPUT R1 H X L R2 H L X S1 L X L S2 X L X Q3 L

OUTPUT Q2 L Q1 L Q0 L

COUNT COUNT

Procedure: 1) Study the pin configuration of IC 7490. 2) Connect pin no 1 to pin no 12 using connecting wire and apply logic I/Ps to pin no. 2,3,6,7 using connecting wires. 3) Switch ON the power supply. 4) Reset the o/p to 0000 by applying logic 1 to R1 and R2 & logic 0 to S1 and S2. 5) Give logic to R2 & S2 and now apply the clock pulse to the pin no 14 and observe the o/p after each clock pulse.

Observation Table: I/P No. of clock pulses 0 1 2 3 4 5 6 7 8 9 10 O/P Q3 Q2 Q1 Q0

Simulation: -

Result: It is observed that the Decade counter counts from 0000 to 1001 and after 1001, it reset to 0000. Hence counts decade (i.e.) 10 clock pulses.

Viva Questions:1. What are the Different Types of the counter? 2. What is the Synchronous Counter?

Experiment no:- 20 Aim:- To study and verify the Synchronous And Asynchronous Counter (74163)
Simulate using micro-cap.

Apparatus: - Breadboard, connecting wires, power supply, IC 74163 . Circuit Diagram:-

SYNCHRONOUS COUNTER

D
CLR LOAD ENP ENT CLK

IC 74LS163A
Rco

Qa

Qb

Qc

Qd

Theory:Asynchronous counter are serial counter. They are slow because each FF can change state only if all the preceding FFs have changed their state. The propagation delay thus gets accumulated, and so causes problems. If the clock frequency is very high, the asynchronous counter may skip some the states and, therefore, malfunction. This problem is overcome in synchronous or parallel counters. Synchronous counters are counter are counters in which all the FFs are triggered simultaneously in synchronization with the clock pulses, the propagation delays of FFs do not add together (as in ripple counters) to produce the overall delay. In fact, the propagation delay of the gates involved. So, the synchronous counters can operate at much higher frequencies than those that can be used in asynchronous counters. To increase in counter speed can be achieved by synchronous counter. In this type of counter each flip flop is triggered by the clock. The clock is applied directly to flip flop. A since the J-K flip flop are used they responds to the negative going edge of clock pulse and toggles when both the J & K inputs are high. Flip flop A will change state with each negative clock transmission. Whenever A is high AND gate X is enable and a clock pulse is passed though the gate to the clock input of flip flop. Thus B changes states with every other ve clock transition. Since AND gate Y is enabled and with transmit the clock of flip flop C only when both A and B are high. Flip flop C changes state with every fourth negative clock transition. Similarly counting goes on.

Advantages: Synchronous counter have the advantage of high speed and less severe decoding problems.

Disadvantages: Synchronous counter having more circuitry than that of asynchronous counters.

Procedure:1) 2) 3) 4) Study the circuit diagram. Connect the circuit as shown in fig. by using connecting wires. Switch ON the power supply. Apply the corresponding inputs and verify the truth table.

Observation Table:Clock QA QB QC QD

Result:Thus Synchronous & Asynchronous Counter are studied and verified.

Viva Questions: 1. What is synchronous counter? 2. What is asynchronous counter?